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Blackfin
Embedded Processor
ADSP-BF512/BF514/BF514F16/BF516/BF518/BF518F16
Rev. D Document Feedback
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FEATURES
Up to 400 MHz high performance Blackfin processor
Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs,
40-bit shifter
RISC-like register and instruction model for ease of
programming and compiler-friendly support
Advanced debug, trace, and performance monitoring
Wide range of operating voltages. See Operating Conditions
on Page 22
Qualified for Automotive Applications. See Automotive
Products on Page 67
168-ball CSP_BGA or 176-lead LQFP_EP (with exposed pad)
MEMORY
116K bytes of on-chip memory
External memory controller with glueless support for SDRAM
and asynchronous 8-bit and 16-bit memories
Optional 16M bit SPI flash with boot option
Flexible booting options from internal SPI flash, OTP
memory, external SPI/parallel memories, or from SPI/UART
host devices
Code security with Lockbox secure technology
One-time-programmable (OTP) memory
Memory management unit providing memory protection
PERIPHERALS
IEEE 802.3-compliant 10/100 Ethernet MAC with IEEE 1588
support (ADSP-BF518/ADSP-BF518F16 only)
Parallel peripheral interface (PPI), supporting ITU-R 656
video data formats
2 dual-channel, full-duplex synchronous serial ports
(SPORTs), supporting 8 stereo I
2
S channels
12 peripheral DMAs, 2 mastered by the Ethernet MAC
2 memory-to-memory DMAs with external request lines
Event handler with 56 interrupt inputs
2 serial peripheral interfaces (SPI)
Removable storage interface (RSI) controller for MMC, SD,
SDIO, and CE-ATA
2 UARTs with IrDA support
2-wire interface (TWI) controller
Eight 32-bit timers/counters with PWM support
3-phase 16-bit center-based PWM unit
32-bit general-purpose counter
Real-time clock (RTC) and watchdog timer
32-bit core timer
40 general-purpose I/Os (GPIOs)
Debug/JTAG interface
On-chip PLL capable of frequency multiplication
Figure 1. Functional Block Diagram
JTAG TEST AND EMULATION
PERIPHERAL
ACCESS BUS
OTP
3-PHASE PWM
WATCHDOG TIMERRTC
TWI
SPORT1-0
RSI (SDIO)
PPI
UART1–0
SPI0
16M bit SPI Flash
(See Table 1)
SPI1
TIMER7–0
COUNTER
EMAC
BOOT
ROM
DMA
EXTERNAL
BUS
INTERRUPT
CONTROLLER
DMA
CONTROLLER
L1
DATA
MEMORY
L1
INSTRUCTION
MEMORY
16 DMA CORE BUS
EXTERNAL ACCESS BUS
EXTERNAL PORT
FLASH, SDRAM CONTROL
PORTS
B
Rev. D | Page 2 of 68 | April 2014
ADSP-BF512/BF514/BF514F16/BF516/BF518/BF518F16
TABLE OF CONTENTS
Features ................................................................. 1
Memory ................................................................ 1
Peripherals ............................................................. 1
General Description ................................................. 3
Portable Low Power Architecture ............................. 3
System Integration ................................................ 3
Blackfin Processor Core .......................................... 3
Memory Architecture ............................................ 5
Event Handling .................................................... 7
DMA Controllers .................................................. 8
Processor Peripherals ............................................. 8
Dynamic Power Management ................................ 12
Voltage Regulation Interface .................................. 14
Clock Signals ..................................................... 14
Booting Modes ................................................... 15
Instruction Set Description ................................... 16
Development Tools ............................................. 16
Additional Information ........................................ 18
Related Signal Chains .......................................... 18
Lockbox Secure Technology Disclaimer ................... 18
Signal Descriptions ................................................. 19
Specifications ........................................................ 22
Operating Conditions ........................................... 22
Electrical Characteristics ....................................... 24
Flash Memory Characteristics ................................ 26
Absolute Maximum Ratings ................................... 27
Package Information ............................................ 28
ESD Sensitivity ................................................... 28
Timing Specifications ........................................... 29
Output Drive Currents ......................................... 52
Test Conditions .................................................. 54
Thermal Characteristics ........................................ 58
176-Lead LQFP_EP Lead Assignment ......................... 59
168-Ball CSP_BGA Ball Assignment ........................... 62
Outline Dimensions ................................................ 65
Surface-Mount Design .......................................... 66
Automotive Products .............................................. 67
Ordering Guide ..................................................... 67
REVISION HISTORY
4/14—Rev. C to Rev. D
This Rev D product data sheet includes Flash memory specifica-
tions that differ from all previous data sheet versions (A, B, C).
The Flash memory specifications contained in the Rev D prod-
uct data sheet are appropriate only for those products that
include 16M bit SPI Flash memory.
These changes are reflected in the following sections:
Processor Comparison .............................................. 3
Flash Memory ......................................................... 5
Operating Conditions ............................................. 22
Electrical Characteristics .......................................... 24
Flash Memory Characteristics ................................... 26
Ordering Guide ..................................................... 67
ADSP-BF512/BF514/BF514F16/BF516/BF518/BF518F16
Rev. D | Page 3 of 68 | April 2014
GENERAL DESCRIPTION
The ADSP-BF512/ADSP-BF514/ADSP-BF514F16/ADSP-
BF516/ADSP-BF518/ADSP-BF518F16 processors are members
of the Blackfin
®
family of products, incorporating the Analog
Devices/Intel Micro Signal Architecture (MSA). Blackfin pro-
cessors combine a dual-MAC state-of-the-art signal processing
engine, the advantages of a clean, orthogonal RISC-like micro-
processor instruction set, and single-instruction, multiple-data
(SIMD) multimedia capabilities into a single instruction-set
architecture.
The processors are completely code compatible with other
Blackfin processors.
By integrating a rich set of industry-leading system peripherals
and memory, Blackfin processors are the platform of choice for
next-generation applications that require RISC-like program-
mability, multimedia support, and leading-edge signal
processing in one integrated package.
PORTABLE LOW POWER ARCHITECTURE
Blackfin processors provide world-class power management
and performance. They are produced with a low power and low
voltage design methodology and feature on-chip dynamic
power management, which is the ability to vary both the voltage
and frequency of operation to significantly lower overall power
consumption. This capability can result in a substantial reduc-
tion in power consumption, compared with just varying the
frequency of operation. This allows longer battery life for
portable appliances.
SYSTEM INTEGRATION
The ADSP-BF51x processors are highly integrated system-on-a-
chip solutions for the next generation of embedded network
connected applications. By combining industry-standard inter-
faces with a high performance signal processing core, cost-
effective applications can be developed quickly, without the
need for costly external components. The system peripherals
include an IEEE-compliant 802.3 10/100 Ethernet MAC with
IEEE-1588 support (ADSP-BF518/ADSP-BF518F16 only), an
RSI controller, a TWI controller, two UART ports, two SPI
ports, two serial ports (SPORTs), nine general-purpose 32-bit
timers (eight with PWM capability), 3-phase PWM for motor
control, a real-time clock, a watchdog timer, and a parallel
peripheral interface (PPI).
BLACKFIN PROCESSOR CORE
As shown in Figure 2, the Blackfin processor core contains two
16-bit multipliers, two 40-bit accumulators, two 40-bit ALUs,
four video ALUs, and a 40-bit shifter. The computation units
process 8-, 16-, or 32-bit data from the register file.
The compute register file contains eight 32-bit registers. When
performing compute operations on 16-bit operand data, the
register file operates as 16 independent 16-bit registers. All
operands for compute operations come from the multiported
register file and instruction constant fields.
Each MAC can perform a 16-bit by 16-bit multiply in each
cycle, accumulating the results into the 40-bit accumulators.
Signed and unsigned formats, rounding, and saturation
are supported.
The ALUs perform a traditional set of arithmetic and logical
operations on 16-bit or 32-bit data. In addition, many special
instructions are included to accelerate various signal processing
tasks. These include bit operations such as field extract and pop-
ulation count, modulo 2
32
multiply, divide primitives, saturation
and rounding, and sign/exponent detection. The set of video
instructions include byte alignment and packing operations,
16-bit and 8-bit adds with clipping, 8-bit average operations,
and 8-bit subtract/absolute value/accumulate (SAA) operations.
The compare/select and vector search instructions are also
provided.
Table 1. Processor Comparison
Feature
ADSP-BF512
ADSP-BF514
ADSP-BF514F16
ADSP-BF516
ADSP-BF518
ADSP-BF518F16
IEEE-1588 ––––11
Ethernet MAC – – – 1 1 1
RSI –11111
TWI 111111
SPORTs 222222
UARTs 222222
SPIs 222222
GP Timers 888888
Watchdog Timers 111111
RTC 111111
PPI 111111
Flash (M bit) – – 16 – – 16
Rotary Counter 1 1 1 1 1 1
3-Phase PWM Pairs 333333
GPIOs 40 40 40 40 40 40
Memory (bytes)
L1 Instruction SRAM 32K
L1 Instruction SRAM/Cache 16K
L1 Data SRAM 32K
L1 Data SRAM/Cache 32K
L1 Scratchpad 4K
L3 Boot ROM 32K
Maximum Speed Grade 400 MHz
Package Options 176-Lead LQFP_EP (with
Exposed Pad)
168-Ball CSP_BGA
Rev. D | Page 4 of 68 | April 2014
ADSP-BF512/BF514/BF514F16/BF516/BF518/BF518F16
For certain instructions, two 16-bit ALU operations can be per-
formed simultaneously on register pairs (a 16-bit high half and
16-bit low half of a compute register). If the second ALU is used,
quad 16-bit operations are possible.
The 40-bit shifter can perform shifts and rotates and is used to
support normalization, field extract, and field deposit
instructions.
The program sequencer controls the flow of instruction execu-
tion, including instruction alignment and decoding. For
program flow control, the sequencer supports PC relative and
indirect conditional jumps (with static branch prediction), and
subroutine calls. Hardware is provided to support zero-over-
head looping. The architecture is fully interlocked, meaning that
the programmer need not manage the pipeline when executing
instructions with data dependencies.
The address arithmetic unit provides two addresses for simulta-
neous dual fetches from memory. It contains a multiported
register file consisting of four sets of 32-bit index, modify,
length, and base registers (for circular buffering), and eight
additional 32-bit pointer registers (for C-style indexed stack
manipulation).
Blackfin processors support a modified Harvard architecture in
combination with a hierarchical memory structure. Level 1 (L1)
memories are those that typically operate at the full processor
speed with little or no latency. At the L1 level, the instruction
memory holds instructions only. The two data memories hold
data, and a dedicated scratchpad data memory stores stack and
local variable information.
In addition, multiple L1 memory blocks are provided, offering a
configurable mix of SRAM and cache. The memory manage-
ment unit (MMU) provides memory protection for individual
tasks that may be operating on the core and can protect system
registers from unintended access.
The architecture provides three modes of operation: user mode,
supervisor mode, and emulation mode. User mode has
restricted access to certain system resources, thus providing a
protected software environment, while supervisor mode has
unrestricted access to the system and core resources.
The Blackfin processor instruction set has been optimized so
that 16-bit opcodes represent the most frequently used instruc-
tions, resulting in excellent compiled code density. Complex
DSP instructions are encoded into 32-bit opcodes, representing
fully featured multifunction instructions. Blackfin processors
support a limited multi-issue capability, where a 32-bit
Figure 2. Blackfin Processor Core
SEQUENCER
ALIGN
DECODE
LOOP BUFFER
16 16
8888
40 40
A0 A1
BARREL
SHIFTER
DATA ARITHMETIC UNIT
CONTROL
UNIT
R7.H
R6.H
R5.H
R4.H
R3.H
R2.H
R1.H
R0.H
R7.L
R6.L
R5.L
R4.L
R3.L
R2.L
R1.L
R0.L
ASTAT
40 40
32 32
32
32
32
32
32LD0
LD1
SD
DAG0
DAG1
ADDRESS ARITHMETIC UNIT
I3
I2
I1
I0
L3
L2
L1
L0
B3
B2
B1
B0
M3
M2
M1
M0
SP
FP
P5
P4
P3
P2
P1
P0
DA1
DA0
32
32
32
PREG
RAB
32
TO MEMORY
ADSP-BF512/BF514/BF514F16/BF516/BF518/BF518F16
Rev. D | Page 5 of 68 | April 2014
instruction can be issued in parallel with two 16-bit instruc-
tions, allowing the programmer to use many of the core
resources in a single instruction cycle.
The Blackfin processor assembly language uses an algebraic syn-
tax for ease of coding and readability. The architecture has been
optimized for use in conjunction with the C/C++ compiler,
resulting in fast and efficient software implementations.
MEMORY ARCHITECTURE
The ADSP-BF51x processors view memory as a single unified
4G byte address space, using 32-bit addresses. All resources,
including internal memory, external memory, and I/O control
registers, occupy separate sections of this common address
space. The memory portions of this address space are arranged
in a hierarchical structure to provide a good cost/performance
balance of some very fast, low-latency on-chip memory as cache
or SRAM, and larger, lower-cost and performance off-chip
memory systems. The memory map for both internal and exter-
nal memory space is shown in Figure 3.
The on-chip L1 memory system is the highest-performance
memory available to the Blackfin processor. The off-chip mem-
ory system, accessed through the external bus interface unit
(EBIU), provides expansion with SDRAM, flash memory, and
SRAM, optionally accessing up to 132M bytes of
physical memory.
The memory DMA controller provides high bandwidth data-
movement capability. It can perform block transfers of code or
data between the internal memory and the external
memory spaces.
Internal (On-Chip) Memory
The ADSP-BF51x processors have three blocks of on-chip
memory that provide high bandwidth access to the core.
The first block is the L1 instruction memory, consisting of
48K bytes SRAM, of which 16K bytes can be configured as a
four-way set-associative cache. This memory is accessed at full
processor speed.
The second on-chip memory block is the L1 data memory, con-
sisting of up to two banks of up to 32K bytes each. Each memory
bank is configurable, offering both cache and SRAM functional-
ity. This memory block is accessed at full processor speed.
The third memory block is a 4K byte scratchpad SRAM which
runs at the same speed as the L1 memories, but is only accessible
as data SRAM and cannot be configured as cache memory.
External (Off-Chip) Memory
External memory is accessed via the EBIU. This 16-bit interface
provides a glueless connection to a bank of synchronous DRAM
(SDRAM) as well as up to four banks of asynchronous memory
devices including flash, EPROM, ROM, SRAM, and memory
mapped I/O devices.
The SDRAM controller can be programmed to interface to up
to 128M bytes of SDRAM. A separate row can be open for each
SDRAM internal bank, and the SDRAM controller supports up
to four internal SDRAM banks, improving overall performance.
The asynchronous memory controller can be programmed to
control up to four banks of devices with very flexible timing
parameters for a wide variety of devices. Each bank occupies a
1M byte segment regardless of the size of the devices used, so
that these banks are only contiguous if each is fully populated
with 1M byte of memory.
Flash Memory
The ADSP-BF51xF processors contain an SPI flash memory
within the package of the processor connected to SPI0
(Figure 4).
The SPI flash memory has a 16M bit capacity. Also included are
support for software write protection and for fast erase and
byte-program.
Figure 3. ADSP-BF51x Internal/External Memory Map
RESERVED
CORE MMR REGISTERS (2M BYTES)
RESERVED
SCRATCHPAD SRAM (4K BYTES)
INSTRUCTION BANK B SRAM (16K BYTES)
SYSTEM MMR REGISTERS (2M BYTES)
RESERVED
RESERVED
DATA BANK B SRAM / CACHE (16K BYTES)
DATA BANK B SRAM (16K BYTES)
DATA BANK A SRAM / CACHE (16K BYTES)
ASYNCMEMORYBANK3(1MBYTES)
ASYNCMEMORYBANK2(1MBYTES)
ASYNCMEMORYBANK1(1MBYTES)
ASYNCMEMORYBANK0(1MBYTES)
INSTRUCTION BANK C SRAM/CACHE (16K BYTES)
INTERNALMEMORYMAP
EXTERNALMEMORYMAP
0xFFFF FFFF
0xFFE0 0000
0xFFB0 0000
0xFFA1 4000
0xFFA1 0000
0xFF90 8000
0xFF90 4000
0xFF80 8000
0xFF80 4000
0x2040 0000
0x2030 0000
0x2020 0000
0x2010 0000
0x2000 0000
0xEF00 0000
0x0000 0000
0xFFC0 0000
0xFFB0 1000
0xFFA0 0000
DATA BANK A SRAM (16K BYTES)
0xFF90 0000
0xFF80 0000
RESERVED
RESERVED
0xFFA0 8000
INSTRUCTION BANK A SRAM (16K BYTES)
RESERVED
BOOT ROM (32K BYTES)
0xEF00 8000
RESERVED
0x08 00 0000
0xFFA0 4000
SDRAM MEMORY (16M BYTES
-
128M BYTES)
Rev. D | Page 6 of 68 | April 2014
ADSP-BF512/BF514/BF514F16/BF516/BF518/BF518F16
The processors internally connect to the flash memory die with
the SPI0SCK, SPI0SEL4 or PH8, SPI0MOSI, and SPI0MISO sig-
nals similar to an external SPI flash (for signal descriptions, see
Table 2). To further provide a secure processing environment,
these internally connected signals are not exposed outside of the
package. For this reason, programming the ADSP-BF51xF flash
memory is performed by running code on the processor and
cannot be programmed from external signals. Data transfers
between the SPI flash and the processor cannot be probed exter-
nally. The flash memory has the following additional features.
• Serial Interface Architecture—SPI compatible with Mode 0
and Mode 3
• Flexible Erase Capability—Uniform 4K Byte sectors and
uniform 64K Byte overlay blocks
• Fast Erase and Byte-Program—Chip-erase time = 11.2 s
(typical), Sector-/Block-Erase Time = 70/350 ms (typical)
Byte-Program Time = 15 μS (typical)
• Software Write Protection—Write protection through
block-protection bits in status register
Figure 4. Flash Memory Block Diagram
MISO_EXT
SPICLK_EXT
SEL4
Combinational Logic
SPICLK_INT
MOSI_INT
SPISS
MOSI_EXT
MISO_INT
SEL4
SPICLK
MOSI
MISO
M
U
X
L
O
G
I
C
SPISS
VDD
GND
RST
SPI Flash Die
SO
SCK
CE
SI
VDDFLASH
GND
RESET
PG13
-
SPI0MISO
PG12
-
SPI0SCK
PG14
-
SPI0MOSI
PG11
-
SPI0SS
SEL4 PH8
RESET
SEL4 or PH8 MISO_EXT, SPICLK_EXT, MOSI_EXT
0
1
Three-state
As programmed
Combinational Logic
Truth Table
ADSP-BF51xF
Package
Signals between the processor and the flash
operate at the VDDFLASH voltage level.
SPI0 signals external
to the processor
operate at the
VDDEXT voltage
level.
SPI0
ADSP-BF51x Die
ADSP-BF512/BF514/BF514F16/BF516/BF518/BF518F16
Rev. D | Page 7 of 68 | April 2014
One-Time Programmable Memory
The processors have 64K bits of one-time programmable non-
volatile memory that can be programmed by the developer only
once. It includes the array and logic to support read access and
programming. Additionally, its pages can be write protected.
The OTP memory allows both public and private data to be
stored on-chip. In addition to storing public and private key
data for applications requiring security, OTP allows developers
to store completely user-definable data such as customer ID,
product ID, and MAC address. Therefore, generic parts can be
supplied which are then programmed and protected by the
developer within this non-volatile memory.
I/O Memory Space
The processors do not define a separate I/O space. All resources
are mapped through the flat 32-bit address space. On-chip I/O
devices have their control registers mapped into memory-
mapped registers (MMRs) at addresses near the top of the
4G byte address space. These are separated into two smaller
blocks, one which contains the control MMRs for all core func-
tions, and the other which contains the registers needed for
setup and control of the on-chip peripherals outside of the core.
The MMRs are accessible only in supervisor mode and appear
as reserved space to on-chip peripherals.
Booting from ROM
The processors contain a small on-chip boot kernel, which con-
figures the appropriate peripheral for booting. If the processors
are configured to boot from boot ROM memory space, the pro-
cessor starts executing from the on-chip boot ROM. For more
information, see Booting Modes on Page 15.
EVENT HANDLING
The event controller handles all asynchronous and synchronous
events to the processor. The processors provide event handling
that supports both nesting and prioritization. Nesting allows
multiple event service routines to be active simultaneously.
Prioritization ensures that servicing of a higher priority event
takes precedence over servicing of a lower priority event.
The controller provides support for five different types of
events:
• Emulation—An emulation event causes the processor to
enter emulation mode, allowing command and control of
the processor through the JTAG interface.
• Reset—This event resets the processor.
• Nonmaskable Interrupt (NMI)—The NMI event can be
generated by the software watchdog timer or by the NMI
input signal to the processor. The NMI event is frequently
used as a power-down indicator to initiate an orderly shut-
down of the system.
• Exceptions—Events that occur synchronously to program
flow; that is, the exception is taken before the instruction is
allowed to complete. Conditions such as data alignment
violations and undefined instructions cause exceptions.
• Interrupts—Events that occur asynchronously to program
flow. They are caused by input signals, timers, and other
peripherals, as well as by an explicit software instruction.
Each event type has an associated register to hold the return
address and an associated return-from-event instruction. When
an event is triggered, the state of the processor is saved on the
supervisor stack.
The event controller consists of two stages, the core event con-
troller (CEC) and the system interrupt controller (SIC). The
core event controller works with the system interrupt controller
to prioritize and control all system events. Conceptually, inter-
rupts from the peripherals enter into the SIC, and are then
routed directly into the general-purpose interrupts of the CEC.
Core Event Controller (CEC)
The CEC supports nine general-purpose interrupts (IVG15–7),
in addition to the dedicated interrupt and exception events. Of
these general-purpose interrupts, the two lowest priority
interrupts (IVG15–14) are recommended to be reserved for
software interrupt handlers, leaving seven prioritized interrupt
inputs to support the peripherals of the processors. The inputs
to the CEC, identifies their names in the event vector table
Table 2. Internal Flash Memory Signal Descriptions
Symbol Pin Name Function
SCK Serial Clock Provides the timing of the serial interface.
Commands, addresses, or input data are latched on the rising edge of the clock input, while
output data is shifted out on the falling edge of the clock input.
SI Serial Data Input Transfers commands, addresses, or data serially into the device.
Inputs are latched on the rising edge of the serial clock.
SO Serial Data Output Transfers data serially out of the device.
Data is shifted out on the falling edge of the serial clock.
Flash busy status pin in AAI mode if SO is configured as a hardware RY/BY pin.
CE Chip Enable The device is enabled by a high to low transition on CE. CE must remain low for the duration
of any command sequence.
RST Reset Resets the operation of the device and the internal logic. This signal is tied to the ADSP-BF51x
RESET signal.
Rev. D | Page 8 of 68 | April 2014
ADSP-BF512/BF514/BF514F16/BF516/BF518/BF518F16
(EVT), and lists their priorities are described in the
ADSP-BF51x Blackfin Processor Hardware Reference Manual
“System Interrupts” chapter.
System Interrupt Controller (SIC)
The system interrupt controller provides the mapping and rout-
ing of events from the many peripheral interrupt sources to the
prioritized general-purpose interrupt inputs of the CEC.
Although the processors provide a default mapping, the user
can alter the mappings and priorities of interrupt events by
writing the appropriate values into the interrupt assignment
registers (SIC_IARx). See the ADSP-BF51x Blackfin Processor
Hardware Reference Manual “System Interrupts” chapter for the
inputs into the SIC and the default mappings into the CEC.
The SIC allows further control of event processing by providing
three pairs of 32-bit interrupt control and status registers. Each
register contains a bit corresponding to each of the peripheral
interrupt events. For more information, see the ADSP-BF51x
Blackfin Processor Hardware Reference Manual “System Inter-
rupts” chapter.
DMA CONTROLLERS
The ADSP-BF51x processors have multiple independent DMA
channels that support automated data transfers with minimal
overhead for the processor core. DMA transfers can occur
between the processor's internal memories and any of its DMA-
capable peripherals. Additionally, DMA transfers can be accom-
plished between any of the DMA-capable peripherals and
external devices connected to the external memory interfaces,
including the SDRAM controller and the asynchronous mem-
ory controller. DMA-capable peripherals include the Ethernet
MAC, RSI, SPORTs, SPIs, UARTs, and PPI. Each individual
DMA-capable peripheral has at least one dedicated DMA
channel.
The processors’ DMA controller supports both one-dimen-
sional (1-D) and two-dimensional (2-D) DMA transfers. DMA
transfer initialization can be implemented from registers or
from sets of parameters called descriptor blocks.
The 2-D DMA capability supports arbitrary row and column
sizes up to 64K elements by 64K elements, and arbitrary row
and column step sizes up to ±32K elements. Furthermore, the
column step size can be less than the row step size, allowing
implementation of interleaved data streams. This feature is
especially useful in video applications where data can be de-
interleaved on the fly.
Examples of DMA types supported by the DMA controller
include:
• A single, linear buffer that stops upon completion
• A circular, auto-refreshing buffer that interrupts on each
full or fractionally full buffer
• 1-D or 2-D DMA using a linked list of descriptors
• 2-D DMA using an array of descriptors, specifying only the
base DMA address within a common page
In addition to the dedicated peripheral DMA channels, there are
two memory DMA channels that transfer data between the vari-
ous memories of the processor system. This enables transfers of
blocks of data between any of the memories—including external
SDRAM, ROM, SRAM, and flash memory—with minimal
processor intervention. Memory DMA transfers can be con-
trolled by a very flexible descriptor-based methodology or by a
standard register-based autobuffer mechanism.
The processors also have an external DMA controller capability
via dual external DMA request signals when used in conjunc-
tion with the external bus interface unit (EBIU). This
functionality can be used when a high speed interface is
required for external FIFOs and high bandwidth communica-
tions peripherals. It allows control of the number of data
transfers for memory DMA. The number of transfers per edge is
programmable. This feature can be programmed to allow mem-
ory DMA to have an increased priority on the external bus
relative to the core.
PROCESSOR PERIPHERALS
The ADSP-BF51x processors contain a rich set of peripherals
connected to the core via several high bandwidth buses, provid-
ing flexibility in system configuration as well as excellent overall
system performance (see Figure 2). The processors contain ded-
icated network communication modules and high speed serial
and parallel ports, an interrupt controller for flexible manage-
ment of interrupts from the on-chip peripherals or external
sources, and power management control functions to tailor the
performance and power characteristics of the processor and sys-
tem to many application scenarios.
All of the peripherals, except for the general-purpose I/O, rotary
counter, TWI, three-phase PWM, real-time clock, and timers,
are supported by a flexible DMA structure. There are also sepa-
rate memory DMA channels dedicated to data transfers
between the processor's various memory spaces, including
external SDRAM and asynchronous memory. Multiple on-chip
buses provide enough bandwidth to keep the processor core
running along with activity on all of the on-chip and external
peripherals.
Real-Time Clock
The real-time clock (RTC) provides a robust set of digital watch
features, including current time, stopwatch, and alarm. The
RTC is clocked by a 32.768 kHz crystal external to the proces-
sors. The RTC peripheral has a dedicated power supply so that it
can remain powered up and clocked even when the rest of the
processor is in a low power state. The RTC provides several pro-
grammable interrupt options, including interrupt per second,
minute, hour, or day clock ticks, interrupt on programmable
stopwatch countdown, or interrupt at a programmed alarm
time.
The 32.768 kHz input clock frequency is divided down to a 1 Hz
signal by a prescaler. The counter function of the timer consists
of four counters: a 60-second counter, a 60-minute counter, a
24-hour counter, and an 32,768-day counter.
ADSP-BF512/BF514/BF514F16/BF516/BF518/BF518F16
Rev. D | Page 9 of 68 | April 2014
When enabled, the alarm function generates an interrupt when
the output of the timer matches the programmed value in the
alarm control register. There are two alarms: The first alarm is
for a time of day. The second alarm is for a day and time of
that day.
The stopwatch function counts down from a programmed
value, with one-second resolution. When the stopwatch is
enabled and the counter underflows, an interrupt is generated.
Like the other peripherals, the RTC can wake up the processor
from sleep mode upon generation of any RTC wakeup event.
Additionally, an RTC wakeup event can wake up the processor
from deep sleep mode or cause a transition from the hibernate
state.
Connect RTC signals RTXI and RTXO with external compo-
nents as shown in Figure 5.
Watchdog Timer
The ADSP-BF51x processors include a 32-bit timer that can be
used to implement a software watchdog function. A software
watchdog can improve system availability by forcing the proces-
sor to a known state through generation of a hardware reset,
nonmaskable interrupt (NMI), or general-purpose interrupt, if
the timer expires before being reset by software. The program-
mer initializes the count value of the timer, enables the
appropriate interrupt, then enables the timer. Thereafter, the
software must reload the counter before it counts to zero from
the programmed value. This protects the system from remain-
ing in an unknown state where software, which would normally
reset the timer, has stopped running due to an external noise
condition or software error.
If configured to generate a hardware reset, the watchdog timer
resets both the core and the processor peripherals. After a reset,
software can determine if the watchdog was the source of the
hardware reset by interrogating a status bit in the watchdog
timer control register.
The timer is clocked by the system clock (SCLK) at a maximum
frequency of f
SCLK
.
Timers
There are nine general-purpose programmable timer units in
the ADSP-BF51x processors. Eight timers have an external sig-
nal that can be configured either as a pulse width modulator
(PWM) or timer output, as an input to clock the timer, or as a
mechanism for measuring pulse widths and periods of external
events. These timers can be synchronized to an external clock
input to the several other associated PF signals, an external
clock input to the PPI_CLK input signal, or to the internal
SCLK.
The timer units can be used in conjunction with the two UARTs
to measure the width of the pulses in the data stream to provide
a software auto-baud detect function for the respective serial
channels.
The timers can generate interrupts to the processor core provid-
ing periodic events for synchronization, either to the system
clock or to a count of external signals.
In addition to the eight general-purpose programmable timers,
a ninth timer is also provided. This extra timer is clocked by the
internal processor clock and is typically used as a system tick
clock for generation of operating system periodic interrupts.
3-Phase PWM
The processors integrate a flexible and programmable 3-phase
PWM waveform generator that can be programmed to generate
the required switching patterns to drive a 3-phase voltage
source inverter for ac induction (ACIM) or permanent magnet
synchronous (PMSM) motor control. In addition, the PWM
block contains special functions that considerably simplify the
generation of the required PWM switching patterns for control
of the electronically commutated motor (ECM) or brushless dc
motor (BDCM). Software can enable a special mode for
switched reluctance motors (SRM).
Features of the 3-phase PWM generation unit are:
• 16-bit center-based PWM generation unit
• Programmable PWM pulse width
• Single/double update modes
• Programmable dead time and switching frequency
•Twos-complement implementation which permits smooth
transition to full ON and full OFF states
• Possibility to synchronize the PWM generation to an exter-
nal synchronization
• Special provisions for BDCM operation (crossover and
output enable functions)
• Wide variety of special switched reluctance (SR) operating
modes
• Output polarity and clock gating control
• Dedicated asynchronous PWM shutdown signal
General-Purpose (GP) Counter
A 32-bit GP counter is provided that can sense 2-bit quadrature
or binary codes as typically emitted by industrial drives or man-
ual thumb wheels. The counter can also operate in
Figure 5. External Components for RTC
RTXO
C1 C2
X1
SUGGESTED COMPONENTS:
X1 = ECLIPTEK EC38J (THROUGH-HOLE PACKAGE) OR
EPSON MC405 12 pF LOAD (SURFACE-MOUNT PACKAGE)
C1 = 22 pF
C2 = 22 pF
R1 = 10 M:
NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1.
CONTACT CRYSTAL MANUFACTURER FOR DETAILS. C1 AND C2
SPECIFICATIONS ASSUME BOARD TRACE CAPACITANCE OF 3 pF.
RTXI
R1
Rev. D | Page 10 of 68 | April 2014
ADSP-BF512/BF514/BF514F16/BF516/BF518/BF518F16
general-purpose up/down count modes. Then, count direction
is either controlled by a level-sensitive input signal or by two
edge detectors.
A third input can provide flexible zero marker support and can
alternatively be used to input the push-button signal of thumb
wheels. All three signals have a programmable debouncing
circuit.
An internal signal forwarded to the GP timer unit enables one
timer to measure the intervals between count events. Boundary
registers enable auto-zero operation or simple system warning
by interrupts when programmable count values are exceeded.
Serial Ports
The ADSP-BF51x processors incorporate two dual-channel syn-
chronous serial ports (SPORT0 and SPORT1) for serial and
multiprocessor communications. The SPORTs support the fol-
lowing features:
Serial port data can be automatically transferred to and from
on-chip memory/external memory via dedicated DMA chan-
nels. Each of the serial ports can work in conjunction with
another serial port to provide TDM support. In this configura-
tion, one SPORT provides two transmit signals while the other
SPORT provides the two receive signals. The frame sync and
clock are shared.
Serial ports operate in five modes:
• Standard DSP serial mode
• Multichannel (TDM) mode
•I
2
S mode
•Packed I
2
S mode
•Left-justified mode
Serial Peripheral Interface (SPI) Ports
The processors have two SPI-compatible ports (SPI0 and SPI1)
that enable the processor to communicate with multiple SPI-
compatible devices.
The SPI interface uses three signals for transferring data: two
data signals (master output-slave input–MOSI, and master
input-slave output–MISO) and a clock signal (serial
clock–SCK). An SPI chip select input signal (SPIxSS) lets other
SPI devices select the processor, and multiple SPI chip select
output signals let the processor select other SPI devices. The SPI
select signals are reconfigured general-purpose I/O signals.
Using these signals, the SPI port provides a full-duplex, syn-
chronous serial interface, which supports both master/slave
modes and multimaster environments.
The SPI port baud rate and clock phase/polarities are program-
mable, and it has an integrated DMA channel, configurable to
support transmit or receive data streams. The SPI’s DMA chan-
nel can only service unidirectional accesses at any given time.
UART Ports
The processors provide two full-duplex universal asynchronous
receiver/transmitter (UART) ports, which are fully compatible
with PC-standard UARTs. Each UART port provides a
simplified UART interface to other peripherals or hosts, sup-
porting full-duplex, DMA-supported, asynchronous transfers of
serial data. A UART port includes support for five to eight data
bits, and none, even, or odd parity. Optionally, an additional
address bit can be transferred to interrupt only addressed nodes
in multi-drop bus (MDB) systems. A frame is terminates by one,
one and a half, two or two and a half stop bits.
The UART ports support automatic hardware flow control
through the Clear To Send (CTS) input and Request To Send
(RTS) output with programmable assertion FIFO levels.
To help support the Local Interconnect Network (LIN) proto-
cols, a special command causes the transmitter to queue a break
command of programmable bit length into the transmit buffer.
Similarly, the number of stop bits can be extended by a pro-
grammable inter-frame space.
The capabilities of the UARTs are further extended with sup-
port for the Infrared Data Association (IrDA®) serial infrared
physical layer link specification (SIR) protocol.
2-Wire Interface (TWI)
The processors include a TWI module for providing a simple
exchange method of control data between multiple devices. The
TWI is compatible with the widely used I
2
C
®
bus standard. The
TWI module offers the capabilities of simultaneous master and
slave operation, support for both 7-bit addressing and multime-
dia data arbitration. The TWI interface utilizes two signals for
transferring clock (SCL) and data (SDA) and supports the pro-
tocol at speeds up to 400k bits/sec. The TWI interface signals
are compatible with 5 V logic levels.
Additionally, the processor’s TWI module is fully compatible
with serial camera control bus (SCCB) functionality for easier
control of various CMOS camera sensor devices.
Removable Storage Interface (RSI)
The RSI controller, available on the ADSP-BF514/ADSP-
BF514F16/ADSP-BF516/ADSP-BF518/ADSP-BF518F16 pro-
cessors, acts as the host interface for multi-media cards (MMC),
secure digital memory cards (SD Card), secure digital
input/output cards (SDIO), and CE-ATA hard disk drives. The
following list describes the main features of the RSI controller.
• Support for a single MMC, SD memory, SDIO card or CE-
ATA hard disk drive
• Support for 1-bit and 4-bit SD modes
• Support for 1-bit, 4-bit and 8-bit MMC modes
• Support for 4-bit and 8-bit CE-ATA hard disk drives
• A ten-signal external interface with clock, command, and
up to eight data lines
• Card detection using one of the data signals
• Card interface clock generation from SCLK
• SDIO interrupt and read wait features
• CE-ATA command completion signal recognition and
disable
ADSP-BF512/BF514/BF514F16/BF516/BF518/BF518F16
Rev. D | Page 11 of 68 | April 2014
10/100 Ethernet MAC
The ADSP-BF516 and ADSP-BF518/ADSP-BF518F16 proces-
sors offer the capability to directly connect to a network by way
of an embedded fast Ethernet media access controller (MAC)
that supports both 10-BaseT (10M bits/sec) and 100-BaseT
(100M bits/sec) operation. The 10/100 Ethernet MAC periph-
eral on the processor is fully compliant to the IEEE 802.3-2002
standard and it provides programmable features designed to
minimize supervision, bus use, or message processing by the
rest of the processor system.
Some standard features are:
• Support of MII and RMII protocols for external PHYs
• Full duplex and half duplex modes
• Data framing and encapsulation: generation and detection
of preamble, length padding, and FCS
• Media access management (in half-duplex operation): col-
lision and contention handling, including control of
retransmission of collision frames and of back-off timing
• Flow control (in full-duplex operation): generation and
detection of pause frames
• Station management: generation of MDC/MDIO frames
for read-write access to PHY registers
• Operating range for active and sleep operating modes, see
Table 43 on Page 47 and Table 44 on Page 48
• Internal loopback from transmit to receive
Some advanced features are:
• Buffered crystal output to external PHY for support of a
single crystal system
• Automatic checksum computation of IP header and IP
payload fields of Rx frames
• Independent 32-bit descriptor-driven receive and transmit
DMA channels
• Frame status delivery to memory through DMA, including
frame completion semaphores for efficient buffer queue
management in software
• Tx DMA support for separate descriptors for MAC header
and payload to eliminate buffer copy operations
• Convenient frame alignment modes support even 32-bit
alignment of encapsulated receive or transmit IP packet
data in memory after the 14-byte MAC header
• Programmable Ethernet event interrupt supports any com-
bination of:
• Selected receive or transmit frame status conditions
• PHY interrupt condition
• Wakeup frame detected
• Selected MAC management counter(s) at half-full
• DMA descriptor error
• 47 MAC management statistics counters with selectable
clear-on-read behavior and programmable interrupts on
half maximum value
• Programmable receive address filters, including a 64-bin
address hash table for multicast and/or unicast frames, and
programmable filter modes for broadcast, multicast, uni-
cast, control, and damaged frames
• Advanced power management supporting unattended
transfer of receive and transmit frames and status to/from
external memory via DMA during low power sleep mode
• System wakeup from sleep operating mode upon magic
packet or any of four user-definable wakeup frame filters
• Support for 802.3Q tagged VLAN frames
• Programmable MDC clock rate and preamble suppression
• In RMII operation, seven unused signals may be config-
ured as GPIO signals for other purposes
IEEE 1588 Support
The IEEE 1588 standard is a precision clock synchronization
protocol for networked measurement and control systems. The
ADSP-BF518/ADSP-BF518F16 processors include hardware
support for IEEE 1588 with an integrated precision time proto-
col synchronization engine (PTP_TSYNC). This engine
provides hardware assisted time stamping to improve the accu-
racy of clock synchronization between PTP nodes. The main
features of the PTP_SYNC engine are:
• Support for both IEEE 1588-2002 and IEEE 1588-2008 pro-
tocol standards
• Hardware assisted time stamping capable of up to 12.5 ns
resolution
•Lock adjustment
• Programmable PTM message support
• Dedicated interrupts
• Programmable alarm
• Multiple input clock sources (SCLK, MII clock, external
clock)
• Programmable pulse per second (PPS) output
• Auxiliary snapshot to time stamp external events
Ports
Because of the rich set of peripherals, the processors group the
many peripheral signals to four ports—port F, port G, port H,
and port J. Most of the associated pins/balls are shared by multi-
ple signals. The ports function as multiplexer controls.
General-Purpose I/O (GPIO)
The ADSP-BF51x processors have 40 bidirectional, general-
purpose I/O (GPIO) signals allocated across three separate
GPIO modules—PORTFIO, PORTGIO, and PORTHIO, associ-
ated with Port F, Port G, and Port H, respectively. Each
GPIO-capable signal shares functionality with other peripherals
via a multiplexing scheme; however, the GPIO functionality is
the default state of the device upon power-up. Neither GPIO
output nor input drivers are active by default. Each general-pur-
pose port signal can be individually controlled by manipulation
of the port control, status, and interrupt registers.
Rev. D | Page 12 of 68 | April 2014
ADSP-BF512/BF514/BF514F16/BF516/BF518/BF518F16
Parallel Peripheral Interface (PPI)
The ADSP-BF51x processors provide a parallel peripheral inter-
face (PPI) that can connect directly to parallel analog-to-digital
and digital-to-analog converters, ITU-R-601/656 video encod-
ers and decoders, and other general-purpose peripherals. The
PPI consists of a dedicated input clock signal, up to three frame
synchronization signals, and up to 16 data signals.
In ITU-R-656 modes, the PPI receives and parses a data stream
of 8-bit or 10-bit data elements. On-chip decode of embedded
preamble control and synchronization information
is supported.
Three distinct ITU-R-656 modes are supported:
• Active video only mode—The PPI does not read in any
data between the End of Active Video (EAV) and Start of
Active Video (SAV) preamble symbols, or any data present
during the vertical blanking intervals. In this mode, the
control byte sequences are not stored to memory; they are
filtered by the PPI.
• Vertical blanking only mode—The PPI only transfers verti-
cal blanking interval (VBI) data, as well as horizontal
blanking information and control byte sequences on
VBI lines.
• Entire field mode—The entire incoming bitstream is read
in through the PPI. This includes active video, control pre-
amble sequences, and ancillary data that may be embedded
in horizontal and vertical blanking intervals.
Though not explicitly supported, ITU-R-656 output functional-
ity can be achieved by setting up the entire frame structure
(including active video, blanking, and control information) in
memory and streaming the data out the PPI in a frame sync-less
mode. The processor’s 2-D DMA features facilitate this transfer
by allowing the static frame buffer (blanking and control codes)
to be placed in memory once, and simply updating the active
video information on a per-frame basis.
The general-purpose modes of the PPI are intended to suit a
wide variety of data capture and transmission applications. The
modes are divided into four main categories, each allowing up
to 16 bits of data transfer per PPI_CLK cycle:
• Data receive with internally generated frame syncs
• Data receive with externally generated frame syncs
• Data transmit with internally generated frame syncs
• Data transmit with externally generated frame syncs
These modes support ADC/DAC connections, as well as video
communication with hardware signalling. Many of the modes
support more than one level of frame synchronization. If
desired, a programmable delay can be inserted between asser-
tion of a frame sync and reception/transmission of data.
Code Security with Lockbox Secure Technology
A security system consisting of a blend of hardware and soft-
ware provides customers with a flexible and rich set of code
security features with Lockbox
®
secure technology. Key features
include:
• OTP memory
• Unique chip ID
• Code authentication
• Secure mode of operation
The security scheme is based upon the concept of authentica-
tion of digital signatures using standards-based algorithms and
provides a secure processing environment in which to execute
code and protect assets.
DYNAMIC POWER MANAGEMENT
The ADSP-BF51x processors provide four operating modes,
each with a different performance/power profile. In addition,
dynamic power management provides the control functions to
dynamically alter the processor core supply voltage, further
reducing power dissipation. When configured for a 0 V core
supply voltage, the processor enters the hibernate state. Control
of clocking to each of the processor peripherals also reduces
power consumption. See Table 3 for a summary of the power
settings for each mode.
Full-On Operating Mode—Maximum Performance
In the full-on mode, the PLL is enabled and is not bypassed,
providing capability for maximum operational frequency. This
is the power-up default execution state in which maximum per-
formance can be achieved. The processor core and all enabled
peripherals run at full speed.
Active Operating Mode—Moderate Power Savings
In the active mode, the PLL is enabled but bypassed. Because the
PLL is bypassed, the processor’s core clock (CCLK) and system
clock (SCLK) run at the input clock (CLKIN) frequency. In this
mode, the CLKIN to CCLK multiplier ratio can be changed,
although the changes are not realized until the full-on mode is
entered. DMA access is available to appropriately configured
L1 memories.
Table 3. Power Settings
Mode/State PLL
PLL
Bypassed
Core
Clock
(CCLK)
System
Clock
(SCLK)
Core
Power
Full On Enabled No Enabled Enabled On
Active Enabled/
Disabled
Yes Enabled Enabled On
Sleep Enabled — Disabled Enabled On
Deep Sleep Disabled — Disabled Disabled On
Hibernate Disabled — Disabled Disabled Off
ADSP-BF512/BF514/BF514F16/BF516/BF518/BF518F16
Rev. D | Page 13 of 68 | April 2014
In the active mode, it is possible to disable the PLL through the
PLL control register (PLL_CTL). If disabled, the PLL must be
re-enabled before transitioning to the full-on or sleep modes.
Sleep Operating Mode—High Dynamic Power Savings
The sleep mode reduces dynamic power dissipation by disabling
the clock to the processor core (CCLK). The PLL and system
clock (SCLK), however, continue to operate in this mode. Typi-
cally an external event or RTC activity wakes up the processor.
When in the sleep mode, asserting wakeup causes the processor
to sense the value of the BYPASS bit in the PLL control register
(PLL_CTL). If BYPASS is disabled, the processor transitions to
the full on mode. If BYPASS is enabled, the processor transi-
tions to the active mode.
System DMA access to L1 memory is not supported in
sleep mode.
Deep Sleep Operating Mode—Maximum Dynamic Power
Savings
The deep sleep mode maximizes dynamic power savings by dis-
abling the clocks to the processor core (CCLK) and to all
synchronous peripherals (SCLK). Asynchronous peripherals,
such as the RTC, may still be running but cannot access internal
resources or external memory. This powered-down mode can
only be exited by assertion of the reset interrupt (RESET) or by
an asynchronous interrupt generated by the RTC. When in deep
sleep mode, an RTC asynchronous interrupt causes the proces-
sor to transition to the Active mode. Assertion of RESET while
in deep sleep mode causes the processor to transition to the full
on mode.
Hibernate State—Maximum Static Power Savings
The hibernate state maximizes static power savings by disabling
the voltage and clocks to the processor core (CCLK) and system
blocks (SCLK). Any critical information stored internally (for
example memory contents, register contents) must be written to
a non-volatile storage device prior to removing power if the
processor state is to be preserved. Writing b#00 to the FREQ bits
in the VR_CTL register also causes the EXT_WAKE signal to
transition low, which can be used to signal an external voltage
regulator to shut down.
Since V
DDEXT
is still supplied in this mode, all of the external sig-
nals three-state, unless otherwise specified. This allows other
devices that may be connected to the processor to still have
power applied without drawing unwanted current.
The Ethernet module can signal an external regulator to wake
up using the EXT_WAKE signal. If PF15 does not connect as a
PHYINT signal to an external PHY device, it can be pulled low
by any other device to wake the processor up. The processor can
also be woken up by a real-time clock wakeup event or by assert-
ing the RESET pin. All hibernate wakeup events initiate the
hardware reset sequence. Individual sources are enabled by the
VR_CTL register. The EXT_WAKE signal is provided to indi-
cate the occurrence of wakeup events.
With the exception of the VR_CTL and the RTC registers, all
internal registers and memories lose their content in the hiber-
nate state. State variables may be held in external SRAM or
SDRAM. The SCKELOW bit in the VR_CTL register controls
whether or not SDRAM operates in self-refresh mode, which
allows it to retain its content while the processor is in hiberna-
tion and through the subsequent reset sequence.
Power Savings
As shown in Table 4, the processors support up to six different
power domains, which maximizes flexibility while maintaining
compliance with industry standards and conventions. By isolat-
ing the internal logic of the processor into its own power
domain, separate from the RTC and other I/O, the processor
can take advantage of dynamic power management without
affecting the RTC or other I/O devices. There are no sequencing
requirements for the various power domains, but all domains
must be powered according to the appropriate Specifications
table for processor Operating Conditions; even if the fea-
ture/peripheral is not used.
The dynamic power management feature of the processor
allows both the processor’s input voltage (V
DDINT
) and clock fre-
quency (f
CCLK
) to be dynamically controlled.
The power dissipated by a processor is largely a function of its
clock frequency and the square of the operating voltage. For
example, reducing the clock frequency by 25% results in a 25%
reduction in dynamic power dissipation, while reducing the
voltage by 25% reduces dynamic power dissipation by more
than 40%. Further, these power savings are additive, in that if
the clock frequency and supply voltage are both reduced, the
power savings can be dramatic, as shown in the following
equations.
where the variables in the equations are:
f
CCLKNOM
is the nominal core clock frequency
f
CCLKRED
is the reduced core clock frequency
V
DDINTNOM
is the nominal internal supply voltage
V
DDINTRED
is the reduced internal supply voltage
Table 4. Power Domains
Power Domain V
DD
Range
All internal logic, except RTC, Memory, OTP V
DDINT
RTC internal logic and crystal I/O V
DDRTC
Memory logic V
DDMEM
OTP logic V
DDOTP
Optional internal flash V
DDFLASH
All other I/O V
DDEXT
Power Savings Factor
fCCLKRED
fCCLKNOM
-------------------------- VDDINTRED
VDDINTNOM
--------------------------------


2
TRED
TNOM
---------------
=
% Power Savings 1 Power Savings Factor–100%=
Rev. D | Page 14 of 68 | April 2014
ADSP-BF512/BF514/BF514F16/BF516/BF518/BF518F16
T
NOM
is the duration running at f
CCLKNOM
T
RED
is the duration running at f
CCLKRED
VOLTAGE REGULATION INTERFACE
The ADSP-BF51x processors require an external voltage regula-
tor to power the V
DDINT
domain. To reduce standby power
consumption in the hibernate state, the external voltage regula-
tor can be signaled through EXT_WAKE to remove power from
the processor core. The EXT_WAKE signal is high-true for
power-up and may be connected directly to the low-true shut
down input of many common regulators.
The Power Good (PG) input signal allows the processor to start
only after the internal voltage has reached a chosen level. In this
way, the startup time of the external regulator is detected after
hibernation. For a complete description of the PG functionality,
refer to the ADSP-BF51x Blackfin Processor Hardware Reference.
CLOCK SIGNALS
The ADSP-BF51x processors can be clocked by an external crys-
tal, a sine wave input, or a buffered, shaped clock derived from
an external clock oscillator.
If an external clock is used, it should be a TTL compatible signal
and must not be halted, changed, or operated below the speci-
fied frequency during normal operation. This signal is
connected to the processor CLKIN signal. When an external
clock is used, the XTAL pin/ball must be left unconnected.
Alternatively, because the processor includes an on-chip oscilla-
tor circuit, an external crystal may be used. For fundamental
frequency operation, use the circuit shown in Figure 6. A paral-
lel-resonant, fundamental frequency, microprocessor-grade
crystal is connected across the CLKIN and XTAL pins/balls. The
on-chip resistance between the CLKIN pin/ball and the XTAL
pin/ball is in the 500 kΩ range. Further parallel resistors are typ-
ically not recommended. The two capacitors and the series
resistor shown in Figure 6 fine tune phase and amplitude of the
sine frequency.
The capacitor and resistor values shown in Figure 6 are typical
values only. The capacitor values are dependent upon the crystal
manufacturers’ load capacitance recommendations and the PCB
physical layout. The resistor value depends on the drive level
specified by the crystal manufacturer. The user should verify the
customized values based on careful investigations on multiple
devices over temperature range.
A third-overtone crystal can be used for frequencies above
25 MHz. The circuit is then modified to ensure crystal operation
only at the third overtone, by adding a tuned inductor circuit as
shown in Figure 6. A design procedure for third-overtone oper-
ation is discussed in detail in application note (EE-168) Using
Third Overtone Crystals with the ADSP-218x DSP on the Analog
Devices website (www.analog.com)—use site search on
“EE-168.”
The CLKBUF signal is an output signal, which is a buffered ver-
sion of the input clock. This signal is particularly useful in
Ethernet applications to limit the number of required clock
sources in the system. In this type of application, a single
25 MHz or 50 MHz crystal may be applied directly to the pro-
cessor. The 25 MHz or 50 MHz output of CLKBUF can then be
connected to an external Ethernet MII or RMII PHY device.
The Blackfin core runs at a different clock rate than the on-chip
peripherals. As shown in Figure 7, the core clock (CCLK) and
system peripheral clock (SCLK) are derived from the input
clock (CLKIN) signal. An on-chip PLL is capable of multiplying
the CLKIN signal by a programmable 5× to 64× multiplication
factor (bounded by specified minimum and maximum VCO
frequencies). The default multiplier is 6×, but it can be modified
by a software instruction sequence.
On-the-fly frequency changes can be done simply by writing to
the PLL_DIV register. The maximum allowed CCLK and SCLK
rates depend on the applied voltages V
DDINT
, V
DDEXT
, and
V
DDMEM
, and the VCO is always permitted to run up to the fre-
quency specified by the part’s speed grade. The CLKOUT signal
reflects the SCLK frequency to the off-chip world. It belongs to
the SDRAM interface, but it functions as a reference signal in
other timing specifications as well. While active by default, it
can be disabled using the EBIU_SDGCTL and EBIU_AMGCTL
registers.
Figure 6. External Crystal Connections
Figure 7. Frequency Modification Methods
CLKIN
CLKOUT
XTAL
EN
CLKBUF
TO PLL CIRCUITRY
FOR OVERTONE
OPERATION ONLY:
NOTE: VALUES MARKED WITH * MUST BE CUSTOMIZED, DEPENDING
ON THE CRYSTAL AND LAYOUT. PLEASE ANALYZE CAREFULLY. FOR
FREQUENCIES ABOVE 33 MHz, THE SUGGESTED CAPACITOR VALUE
OF 18 pF SHOULD BE TREATED AS A MAXIMUM, AND THE SUGGESTED
RESISTOR VALUE SHOULD BE REDUCED TO 0 ⍀.
18 pF *
EN
18 pF *
330 ⍀*
BLACKFIN
560 ⍀
ADSP-BF512/BF514/BF514F16/BF516/BF518/BF518F16
Rev. D | Page 15 of 68 | April 2014
All on-chip peripherals are clocked by the system clock (SCLK).
The system clock frequency is programmable by means of the
SSEL3–0 bits of the PLL_DIV register. The values programmed
into the SSEL fields define a divide ratio between the PLL output
(VCO) and the system clock. SCLK divider values are 1 through
15. Table 5 illustrates typical system clock ratios.
Note that the divisor ratio must be chosen to limit the system
clock frequency to its maximum of f
SCLK
. The SSEL value can be
changed dynamically without any PLL lock latencies by writing
the appropriate values to the PLL divisor register (PLL_DIV).
The core clock (CCLK) frequency can also be dynamically
changed by means of the CSEL1–0 bits of the PLL_DIV register.
Supported CCLK divider ratios are 1, 2, 4, and 8, as shown in
Table 6. This programmable core clock capability is useful for
fast core frequency modifications.
The maximum CCLK frequency not only depends on the part's
speed grade (see Page 67), it also depends on the applied V
DDINT
voltage. See Table 10 on Page 23 for details. The maximal sys-
tem clock rate (SCLK) depends on the chip package and the
applied V
DDINT
, V
DDEXT
, and V
DDMEM
voltages (see Table 12 on
Page 23).
BOOTING MODES
The processor has several mechanisms (listed in Table 7) for
automatically loading internal and external memory after a
reset. The boot mode is defined by three BMODE input bits
dedicated to this purpose. There are two categories of boot
modes. In master boot modes the processor actively loads data
from parallel or serial memories. In slave boot modes the pro-
cessor receives data from external host devices.
The boot modes listed in Table 7 provide a number of mecha-
nisms for automatically loading the processor’s internal and
external memories after a reset. By default, all boot modes use
the slowest meaningful configuration settings. Default settings
can be altered via the initialization code feature at boot time or
by proper OTP programming at pre-boot time. The BMODE
bits of the reset configuration register, sampled during power-
on resets and software-initiated resets, implement the modes
shown in Table 7.
• Idle/no boot mode (BMODE = 0x0)—In this mode, the
processor goes into idle. The idle boot mode helps recover
from illegal operating modes, such as when the user has
mis configured the OTP memory.
• Boot from 8-bit or 16-bit external flash memory
(BMODE = 0x1)—In this mode, the boot kernel loads the
first block header from address 0x2000 0000 and—depend-
ing on instructions containing in the header—the boot
kernel performs 8-bit or 16-bit boot or starts program exe-
cution at the address provided by the header. By default, all
configuration settings are set for the slowest device possible
(3-cycle hold time, 15-cycle R/W access times, 4-cycle
setup).
The ARDY is not enabled by default, but it can be enabled
by OTP programming. Similarly, all interface behavior and
timings can be customized by OTP programming. This
includes activation of burst-mode or page-mode operation.
In this mode, all signals belonging to the asynchronous
interface are enabled at the port muxing level.
• Boot from internal SPI memory (BMODE = 0x2)—The
processor uses the internal PH8 GPIO signal to load code
previously loaded to the 16M bit internal SPI flash con-
nected to SPI0. Only available on the ADSP-BF51xF
processors.
• Boot from external SPI EEPROM or flash
(BMODE = 0x3)—8-bit, 16-bit, 24-bit or 32-bit address-
able devices are supported. The processor uses the PG15
GPIO signal (at SPI0SEL2) to select a single SPI
EEPROM/flash device connected to the SPI0 interface;
then submits a read command and successive address bytes
(0x00) until a valid 8-, 16-, 24-, or 32-bit addressable device
is detected. Pull-up resistors are required on the SSEL and
MISO signals. By default, a value of 0x85 is written to the
SPI0_BAUD register.
Table 5. Example System Clock Ratios
Signal Name
SSEL3–0
Divider Ratio
VCO/SCLK
Example Frequency Ratios
(MHz)
VCO SCLK
0010 2:1 100 50
0110 6:1 300 50
1010 10:1 400 40
Table 6. Core Clock Ratios
Signal Name
CSEL1–0
Divider Ratio
VCO/CCLK
Example Frequency Ratios
(MHz)
VCO CCLK
00 1:1 300 300
01 2:1 300 150
10 4:1 400 100
11 8:1 200 25
Table 7. Booting Modes
BMODE2–0 Description
000 Idle - No boot
001 Boot from 8- or 16-bit external flash memory
010 Boot from internal SPI memory
011 Boot from external SPI memory (EEPROM or flash)
100 Boot from SPI0 host
101 Boot from OTP memory
110 Boot from SDRAM
111 Boot from UART0 Host
Rev. D | Page 16 of 68 | April 2014
ADSP-BF512/BF514/BF514F16/BF516/BF518/BF518F16
• Boot from SPI0 host device (BMODE = 0x4)—The proces-
sor operates in SPI slave mode and is configured to receive
the bytes of the LDR file from an SPI host (master) agent.
In the host, the HWAIT signal must be interrogated by the
host before every transmitted byte. A pull-up resistor is
required on the SPI0SS input. A pull-down on the serial
clock may improve signal quality and booting robustness.
• Boot from OTP memory (BMODE = 0x5)—This provides
a stand-alone booting method. The boot stream is loaded
from on-chip OTP memory. By default the boot stream is
expected to start from OTP page 0x40 on and can occupy
all public OTP memory up to page 0xDF. This is 2560
bytes. Since the start page is programmable the maximum
size of the boot stream can be extended to 3072 bytes.
• Boot from SDRAM (BMODE = 0x6)—This is a warm boot
scenario, where the boot kernel starts booting from address
0x0000 0010. The SDRAM is expected to contain a valid
boot stream and the SDRAM controller must be configured
by the OTP settings.
•Boot from UART0 host (BMODE = 0x7)—Using an auto-
baud handshake sequence, a boot-stream formatted
program is downloaded by the host. The host selects a bit
rate within the UART clocking capabilities.
When performing the autobaud, the UART expects a “@”
(0x40) character (eight bits data, one start bit, one stop bit,
no parity bit) on the RX0 signal to determine the bit rate.
The UART then replies with an acknowledgement com-
posed of 4 bytes (0xBF—the value of UART0_DLL and
0x00—the value of UART0_DLH). The host can then
download the boot stream. To hold off the host the Blackfin
processor signals the host with the boot host wait
(HWAIT) signal. Therefore, the host must monitor
HWAIT before every transmitted byte.
For each of the boot modes, a 16-byte header is first read from
an external memory device. The header specifies the number of
bytes to be transferred and the memory destination address.
Multiple memory blocks may be loaded by any boot sequence.
Once all blocks are loaded, program execution commences from
the address stored in the EVT1 register.
Prior to booting, the pre-boot routine interrogates the OTP
memory. Individual boot modes can be customized or even dis-
abled based on OTP programming. External hardware,
especially booting hosts may watch the HWAIT signal to deter-
mine when the pre-boot has finished and the boot kernel starts
the boot process. By programming OTP memory, the user can
instruct the preboot routine to also customize the PLL, the
SDRAM Controller, and the Asynchronous Interface.
The boot kernel differentiates between a regular hardware reset
and a wakeup-from-hibernate event to speed up booting in the
later case. Bits 6-4 in the system reset configuration (SYSCR)
register can be used to bypass pre-boot routine and/or boot ker-
nel in case of a software reset. They can also be used to simulate
a wakeup-from-hibernate boot in the software reset case.
The boot process can be further customized by “initialization
code.” This is a piece of code that is loaded and executed prior to
the regular application boot. Typically, this is used to configure
the SDRAM controller or to speed up booting by managing
PLL, clock frequencies, wait states, or serial bit rates.
The boot ROM also features C-callable function entries that can
be called by the user application at run time. This enables sec-
ond-stage boot or boot management schemes to be
implemented with ease.
INSTRUCTION SET DESCRIPTION
The Blackfin processor family assembly language instruction set
employs an algebraic syntax designed for ease of coding and
readability. The instructions have been specifically tuned to pro-
vide a flexible, densely encoded instruction set that compiles to
a very small final memory size. The instruction set also provides
fully featured multifunction instructions that allow the pro-
grammer to use many of the processor core resources in a single
instruction. Coupled with many features more often seen on
microcontrollers, this instruction set is very efficient when com-
piling C and C++ source code. In addition, the architecture
supports both user (algorithm/application code) and supervisor
(O/S kernel, device drivers, debuggers, ISRs) modes of opera-
tion, allowing multiple levels of access to core
processor resources.
The assembly language, which takes advantage of the proces-
sor’s unique architecture, offers the following advantages:
• Seamlessly integrated DSP/MCU features are optimized for
both 8-bit and 16-bit operations.
• A multi-issue load/store modified-harvard architecture,
which supports two 16-bit MACs or four 8-bit ALUs plus
two load/store plus two pointer updates per cycle.
• All registers, I/O, and memory are mapped into a unified
4G byte memory space, providing a simplified program-
ming model.
• Microcontroller features, such as arbitrary bit and bit-field
manipulation, insertion, and extraction; integer operations
on 8-, 16-, and 32-bit data-types; and separate user and
supervisor stack pointers.
• Code density enhancements, which include intermixing of
16-bit and 32-bit instructions (no mode switching, no code
segregation). Frequently used instructions are encoded
in 16 bits.
DEVELOPMENT TOOLS
Analog Devices supports its processors with a complete line of
software and hardware development tools, including integrated
development environments (which include CrossCore
®
Embed-
ded Studio and/or VisualDSP++
®
), evaluation products,
emulators, and a wide variety of software add-ins.
Integrated Development Environments (IDEs)
For C/C++ software writing and editing, code generation, and
debug support, Analog Devices offers two IDEs.
ADSP-BF512/BF514/BF514F16/BF516/BF518/BF518F16
Rev. D | Page 17 of 68 | April 2014
The newest IDE, CrossCore Embedded Studio, is based on the
Eclipse
TM
framework. Supporting most Analog Devices proces-
sor families, it is the IDE of choice for future processors,
including multicore devices. CrossCore Embedded Studio
seamlessly integrates available software add-ins to support real
time operating systems, file systems, TCP/IP stacks, USB stacks,
algorithmic software modules, and evaluation hardware board
support packages. For more information visit
www.analog.com/cces.
The other Analog Devices IDE, VisualDSP++, supports proces-
sor families introduced prior to the release of CrossCore
Embedded Studio. This IDE includes the Analog Devices VDK
real time operating system and an open source TCP/IP stack.
For more information visit www.analog.com/visualdsp. Note
that VisualDSP++ will not support future Analog Devices
processors.
EZ-KIT Lite Evaluation Board
For processor evaluation, Analog Devices provides wide range
of EZ-KIT Lite
®
evaluation boards. Including the processor and
key peripherals, the evaluation board also supports on-chip
emulation capabilities and other evaluation and development
features. Also available are various EZ-Extenders
®
, which are
daughter cards delivering additional specialized functionality,
including audio and video processing. For more information
visit www.analog.com and search on “ezkit” or “ezextender”.
EZ-KIT Lite Evaluation Kits
For a cost-effective way to learn more about developing with
Analog Devices processors, Analog Devices offer a range of EZ-
KIT Lite evaluation kits. Each evaluation kit includes an EZ-KIT
Lite evaluation board, directions for downloading an evaluation
version of the available IDE(s), a USB cable, and a power supply.
The USB controller on the EZ-KIT Lite board connects to the
USB port of the user’s PC, enabling the chosen IDE evaluation
suite to emulate the on-board processor in-circuit. This permits
the customer to download, execute, and debug programs for the
EZ-KIT Lite system. It also supports in-circuit programming of
the on-board Flash device to store user-specific boot code,
enabling standalone operation. With the full version of Cross-
Core Embedded Studio or VisualDSP++ installed (sold
separately), engineers can develop software for supported EZ-
KITs or any custom system utilizing supported Analog Devices
processors.
Software Add-Ins for CrossCore Embedded Studio
Analog Devices offers software add-ins which seamlessly inte-
grate with CrossCore Embedded Studio to extend its capabilities
and reduce development time. Add-ins include board support
packages for evaluation hardware, various middleware pack-
ages, and algorithmic modules. Documentation, help,
configuration dialogs, and coding examples present in these
add-ins are viewable through the CrossCore Embedded Studio
IDE once the add-in is installed.
Board Support Packages for Evaluation Hardware
Software support for the EZ-KIT Lite evaluation boards and EZ-
Extender daughter cards is provided by software add-ins called
Board Support Packages (BSPs). The BSPs contain the required
drivers, pertinent release notes, and select example code for the
given evaluation hardware. A download link for a specific BSP is
located on the web page for the associated EZ-KIT or EZ-
Extender product. The link is found in the Product Download
area of the product web page.
Middleware Packages
Analog Devices separately offers middleware add-ins such as
real time operating systems, file systems, USB stacks, and
TCP/IP stacks. For more information see the following web
pages:
•www.analog.com/ucos3
•www.analog.com/ucfs
•www.analog.com/ucusbd
•www.analog.com/lwip
Algorithmic Modules
To speed development, Analog Devices offers add-ins that per-
form popular audio and video processing algorithms. These are
available for use with both CrossCore Embedded Studio and
VisualDSP++. For more information visit www.analog.com and
search on “Blackfin software modules” or “SHARC software
modules”.
Designing an Emulator-Compatible DSP Board (Target)
For embedded system test and debug, Analog Devices provides
a family of emulators. On each JTAG DSP, Analog Devices sup-
plies an IEEE 1149.1 JTAG Test Access Port (TAP). In-circuit
emulation is facilitated by use of this JTAG interface. The emu-
lator accesses the processor’s internal features via the
processor’s TAP, allowing the developer to load code, set break-
points, and view variables, memory, and registers. The
processor must be halted to send data and commands, but once
an operation is completed by the emulator, the DSP system is set
to run at full speed with no impact on system timing. The emu-
lators require the target board to include a header that supports
connection of the DSP’s JTAG port to the emulator.
For details on target board design issues including mechanical
layout, single processor connections, signal buffering, signal ter-
mination, and emulator pod logic, see the EE-68: Analog Devices
JTAG Emulation Technical Reference on the Analog Devices
website (www.analog.com)—use site search on “EE-68.” This
document is updated regularly to keep pace with improvements
to emulator support.
Rev. D | Page 18 of 68 | April 2014
ADSP-BF512/BF514/BF514F16/BF516/BF518/BF518F16
ADDITIONAL INFORMATION
The following publications that describe ADSP-BF512/
ADSP-BF514/ADSP-BF516/ADSP-BF518 processors (and
related processors) can be accessed electronically on our
website:
•Getting Started With Blackfin Processors
•ADSP-BF51x Blackfin Processor Hardware Reference
•Blackfin Processor Programming Reference
•ADSP-BF512/BF514/BF514F16/BF516/BF518/BF518F16
Blackfin Processor Anomaly List
RELATED SIGNAL CHAINS
A signal chain is a series of signal-conditioning electronic com-
ponents that receive input (data acquired from sampling either
real-time phenomena or from stored data) in tandem, with the
output of one portion of the chain supplying input to the next.
Signal chains are often used in signal processing applications to
gather and process data or to apply system controls based on
analysis of real-time phenomena. For more information about
this term and related topics, see the "signal chain" entry in
Wikipedia or the Glossary of EE Terms on the Analog Devices
website.
Analog Devices eases signal processing system development by
providing signal processing components that are designed to
work together well. A tool for viewing relationships between
specific applications and related components is available on the
www.analog.com website.
The Application Signal Chains page in the Circuits from the
Lab
TM
site (http://www.analog.com/circuits) provides:
• Graphical circuit block diagram presentation of signal
chains for a variety of circuit types and applications
• Drill down links for components in each chain to selection
guides and application information
• Reference designs applying best practice design techniques
LOCKBOX SECURE TECHNOLOGY DISCLAIMER
Analog Devices products containing Lockbox Secure Technol-
ogy are warranted by Analog Devices as detailed in the Analog
Devices Standard Terms and Conditions of Sale. To our knowl-
edge, the Lockbox Secure Technology, when used in accordance
with the data sheet and hardware reference manual specifica-
tions, provides a secure method of implementing code and data
safeguards. However, Analog Devices does not guarantee that
this technology provides absolute security. ACCORDINGLY,
ANALOG DEVICES HEREBY DISCLAIMS ANY AND ALL
EXPRESS AND IMPLIED WARRANTIES THAT THE LOCK-
BOX SECURE TECHNOLOGY CANNOT BE BREACHED,
COMPROMISED, OR OTHERWISE CIRCUMVENTED AND
IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR
ANY LOSS, DAMAGE, DESTRUCTION, OR RELEASE OF
DATA, INFORMATION, PHYSICAL PROPERTY, OR INTEL-
LECTUAL PROPERTY.
ADSP-BF512/BF514/BF514F16/BF516/BF518/BF518F16
Rev. D | Page 19 of 68 | April 2014
SIGNAL DESCRIPTIONS
The processors’ signal definitions are listed in Table 8. In order
to maintain maximum function and reduce package size and
signal count, some signals have dual, multiplexed functions. In
cases where signal function is reconfigurable, the default state is
shown in plain text, while the alternate function is shown in
italics.
All pins are three-stated during and immediately after reset,
with the exception of the external memory interface, asynchro-
nous and synchronous memory control, and the buffered XTAL
output pin (CLKBUF). On the external memory interface, the
control and address lines are driven high, with the exception of
CLKOUT, which toggles at the system clock rate. During hiber-
nate all outputs are three-stated unless otherwise noted in
Table 8.
All I/O signals have their input buffers disabled with the excep-
tion of the signals noted in the data sheet that need pull-ups or
pull downs if unused.
The SDA (serial data) and SCL (serial clock) pins/balls are open
drain and therefore require a pullup resistor. Consult version
2.1 of the I
2
C specification for the proper resistor value.
It is strongly advised to use the available IBIS models to ensure
that a given board design meets overshoot/undershoot and sig-
nal integrity requirements. If no IBIS simulation is performed, it
is strongly recommended to add series resistor terminations for
all Driver Types A, C and D. The termination resistors should
be placed near the processor to reduce transients and improve
signal integrity. The resistance value, typically 33 Ω or 47 Ω,
should be chosen to match the average board trace impedance.
Additionally, adding a parallel termination to CLKOUT may
prove useful in further enhancing signal integrity. Be sure to
verify overshoot/undershoot and signal integrity specifications
on actual hardware.
Table 8. Signal Descriptions
Signal Name Type Function
Driver
Type
1
EBIU
ADDR19–1 O Address Bus A
DATA15–0 I/O Data Bus A
ABE1–0/SDQM1–0 O Byte Enable or Data Mask A
AMS1–0 O Asynchronous Memory Bank Selects (Require pull-ups if hibernate is used) A
ARE O Asynchronous Memory Read Enable A
AWE O Asynchronous Memory Write Enable A
SRAS O SDRAM Row Address Strobe A
SCAS O SDRAM Column Address Strobe A
SWE OSDRAM Write Enable A
SCKE O SDRAM Clock Enable (Requires a pull-down if hibernate with SDRAM self-refresh
is used)
A
CLKOUT O SDRAM Clock Output B
SA10 O SDRAM A10 Signal A
SMS O SDRAM Bank Select A
Port F: GPIO and Multiplexed Peripherals
PF0/ETxD2/PPI D0/SPI1SEL2/TACLK6 I/O GPIO/Ethernet MII Transmit D2/PPI Data 0/SPI1 Slave Select 2/Timer6 Alternate
Clock
C
PF1/ERxD2/PPI D1/PWM AH/TACLK7 I/O GPIO/Ethernet MII Receive D2/PPI Data 1/PWM AH Output/Timer7 Alternate Clock C
PF2/ETxD3/PPI D2/PWM AL I/O GPIO/Ethernet Transmit D3/PPI Data 2/PWM AL Output C
PF3/ERxD3/PPI D3/PWM BH/TACLK0 I/O GPIO/Ethernet MII Data Receive D3/PPI Data 3/PWM BH Output/Timer0 Alternate
Clock
C
PF4/ERxCLK/PPI D4/PWM BL/TACLK1 I/O GPIO/Ethernet MII Receive Clock/PPI Data 4/PWM BL Out/Timer1 Alternate CLK C
PF5/ERxDV/PPI D5/PWM CH/TACI0 I/O GPIO/Ethernet MII Receive Data Valid/PPI Data 5/PWM CH Out
/Timer0 Alternate Capture Input
C
PF6/COL/PPI D6/PWM CL/TACI1 I/O GPIO/Ethernet MII Collision/PPI Data 6/PWM CL Out/Timer1 Alternate Capture Input C
PF7/SPI0SEL1/PPI D7/PWMSYNC I/O GPIO/SPI0 Slave Select 1/PPI Data 7/PWM Sync C
Rev. D | Page 20 of 68 | April 2014
ADSP-BF512/BF514/BF514F16/BF516/BF518/BF518F16
PF8/MDC/PPI D8/SPI1SEL4 I/O GPIO/Ethernet Management Channel Clock/PPI Data 8/SPI1 Slave Select 4 C
PF9/MDIO/PPI D9/TMR2 I/O GPIO/Ethernet Management Channel Serial Data/PPI Data 9/Timer 2 C
PF10/ETxD0/PPI D10/TMR3 I/O GPIO/Ethernet MII or RMII Transmit D0/PPI Data 10/Timer 3 C
PF11/ERxD0/PPI D11/PWM AH/TACI3 I/O GPIO/Ethernet MII Receive D0/PPI Data 11/PWM AH output
/Timer3 Alternate Capture Input
C
PF12/ETxD1/PPI D12/PWM AL I/O GPIO/Ethernet MII Transmit D1/PPI Data 12/PWM AL Output C
PF13/ERxD1/PPI D13/PWM BH I/O GPIO/Ethernet MII or RMII Receive D1/PPI Data 13/PWM BH Output C
PF14/ETxEN/PPI D14/PWM BL I/O GPIO/Ethernet MII Transmit Enable/PPI Data 14/PWM BL Out C
PF15
2
/RMII PHYINT/PPI D15/PWM_SYNCA I/O GPIO/Ethernet MII PHY Interrupt/PPI Data 15/Alternate PWM Sync C
Port G: GPIO and Multiplexed Peripherals
PG0/MIICRS/RMIICRS/HWAIT
3
/SPI1SEL3 I/O GPIO/Ethernet MII or RMII Carrier Sense or RMII Data Valid/HWAIT/SPI1 Slave Select3 C
PG1/ERxER/DMAR1/PWM CH I/O GPIO/Ethernet MII or RMII Receive Error/DMA Req 1/PWM CH Out C
PG2/MIITxCLK/RMIIREF_CLK/DMAR0/PWM CL I/O GPIO/Ethernet MII or RMII Reference Clock/DMA Req 0/PWM CL Out C
PG3/DR0PRI/RSI_DATA0/SPI0SEL5/TACLK3 I/O GPIO/SPORT0 Primary Rx Data/RSI Data 0/SPI0 Slave Select 5/Timer3 Alternate CLK C
PG4/RSCLK0/RSI_DATA1/TMR5/TACI5 I/O GPIO/SPORT0 Rx Clock/RSI Data 1/Timer 5/Timer5 Alternate Capture Input D
PG5/RFS0/RSI_DATA2/PPICLK/TMRCLK I/O GPIO/SPORT0 Rx Frame Sync/RSI Data 2/PPI Clock/External Timer Reference C
PG6/TFS0/RSI_DATA3/TMR0/PPIFS1 I/O GPIO/SPORT0 Tx Frame Sync/RSI Data 3/Timer0/PPI Frame Sync1 C
PG7/DT0PRI/RSI_CMD/TMR1/PPIFS2 I/O GPIO/SPORT0 Tx Primary Data/RSI Command/Timer 1/PPI Frame Sync2 C
PG8/TSCLK0/RSI_CLK/TMR6/TACI6 I/O GPIO/SPORT0 Tx Clock/RSI Clock/Timer 6/Timer6 Alternate Capture Input D
PG9/DT0SEC/UART0TX/TMR4 I/O GPIO/SPORT0 Secondary Tx Data/UART0 Transmit/Timer 4 C
PG10/DR0SEC/UART0RX/TACI4 I/O GPIO/SPORT0 Secondary Rx Data/UART0 Receive/Timer4 Alternate Capture Input C
PG11/SPI0SS/AMS2/SPI1SEL5/TACLK2 I/O GPIO/SPI0 Slave Device Select/Asynchronous Memory Bank Select 2/SPI1 Slave
Select 5/Timer2 Alternate CLK
C
PG12/SPI0SCK/PPICLK/TMRCLK/PTP_PPS I/O GPIO/SPI0 Clock/PPI Clock/External Timer Reference/PTP Pulse Per Second Out D
PG13/SPI0MISO
4
/TMR0/PPIFS1/
PTP_CLKOUT
I/O GPIO/SPI0 Master In Slave Out/Timer0/PPI Frame Sync1/PTP Clock Out C
PG14/SPI0MOSI/TMR1/PPIFS2/PWM TRIP
/PTP_AUXIN
I/O GPIO/SPI0 Master Out Slave In/Timer 1/PPI Frame Sync2/PWM Trip/PTP Auxiliary
Snapshot Trigger Input
C
PG15/SPI0SEL2/PPIFS3/AMS3 I/O GPIO/SPI0 Slave Select 2/PPI Frame Sync3/Asynchronous Memory Bank Select 3 C
Port H: GPIO and Multiplexed Peripherals
PH0/DR1PRI/SPI1SS/RSI_DATA4 I/O GPIO/SPORT1 Primary Rx Data/SPI1 Device Select/RSI Data 4 C
PH1/RFS1/SPI1MISO/RSI_DATA5 I/O GPIO/SPORT1 Rx Frame Sync/SPI1 Master In Slave Out/RSI Data 5 C
PH2/RSCLK1/SPI1SCK/RSI DATA6 I/O GPIO/SPORT1 Rx Clock/SPI1 Clock/RSI Data 6 D
PH3/DT1PRI/SPI1MOSI/RSI DATA7 I/O GPIO/SPORT1 Primary Tx Data/SPI1 Master Out Slave In/RSI Data 7 C
PH4/TFS1/AOE/SPI0SEL3/CUD I/O GPIO/SPORT1 Tx Frame Sync/Asynchronous Memory Output Enable/SPI0 Slave
Select 3/Counter Up Direction
C
PH5/TSCLK1/ARDY/PTP_EXT_CLKIN/CDG I/O GPIO/SPORT1 Tx Clock/Asynchronous Memory Hardware Ready Control/
External Clock for PTP TSYNC/Counter Down Gate
D
PH6/DT1SEC/UART1TX/SPI1SEL1/CZM I/O GPIO/SPORT1 Secondary Tx Data/UART1 Transmit/SPI1 Slave Select 1
/Counter Zero Marker
C
PH7/DR1SEC/UART1RX/TMR7/TACI2 I/O GPIO/SPORT1 Secondary Rx Data/UART1 Receive/Timer 7/Timer2 Alternate Clock
Input
C
Table 8. Signal Descriptions (Continued)
Signal Name Type Function
Driver
Type
1
ADSP-BF512/BF514/BF514F16/BF516/BF518/BF518F16
Rev. D | Page 21 of 68 | April 2014
Port J
PJ0:SCL I/O 5V TWI Serial Clock (This signal is an open-drain output and requires a pull-up
resistor. Consult version 2.1 of the I
2
C specification for the proper resistor value.)
E
PJ1:SDA I/O 5V TWI Serial Data (This signal is an open-drain output and requires a pull-up
resistor. Consult version 2.1 of the I
2
C specification for the proper resistor value.)
E
Real Time Clock
RTXI I RTC Crystal Input (This ball should be pulled low when not used.)
RTXO O RTC Crystal Output (Does not three-state during hibernate)
JTAG Port
TCK I JTAG Clock
TDO O JTAG Serial Data Out C
TDI I JTAG Serial Data In
TMS I JTAG Mode Select
TRST I JTAG Reset (This signal should be pulled low if the JTAG port is not used.)
EMU O Emulation Output C
Clock
CLKIN I Clock/Crystal Input
XTAL O Crystal Output (If CLKBUF is enabled, does not three-state during hibernate)
CLKBUF O Buffered XTAL Output (If enabled, does not three-state during hibernate) C
Mode Controls
RESET I Reset
NMI I Non-maskable Interrupt (This signal should be pulled high when not used.)
BMODE2-0 I Boot Mode Strap 2-0
Voltage Regulation Interface
PG I Power Good (This signal should be pulled low when not used.)
EXT_WAKE O Wake up Indication (Does not three-state during hibernate) C
Power Supplies ALL SUPPLIES MUST BE POWERED See Operating Conditions on Page 22.
V
DDEXT
PI/O Power Supply
V
DDINT
P Internal Power Supply
V
DDRTC
P Real Time Clock Power Supply
V
DDFLASH
P Internal SPI Flash Power Supply
V
DDMEM
PMEM Power Supply
V
PPOTP
P OTP Programming Voltage
V
DDOTP
POTP Power Supply
GND G Ground for All Supplies
1
See Output Drive Currents on Page 52 for more information about each driver type.
2
When driven low, the PF15 signal can be used to wake up the processor from the hibernate state, either in normal GPIO mode or in Ethernet mode as PHYINT. If the pin/ball
is used for wake up, enable the feature with the PHYWE bit in the VR_CTL register, and pull-up the signal with a resistor.
3
Boot host wait is a GPIO signal toggled by the boot kernel. The mandatory external pull-up/pull-down resistor defines the signal polarity.
4
A pull-up resistor is required for the boot from external SPI EEPROM or flash (BMODE = 0x3).
Table 8. Signal Descriptions (Continued)
Signal Name Type Function
Driver
Type
1
Rev. D | Page 22 of 68 | April 2014
ADSP-BF512/BF514/BF514F16/BF516/BF518/BF518F16
SPECIFICATIONS
Note that component specifications are subject to change
without notice.
OPERATING CONDITIONS
Parameter Conditions Min Nominal Max Unit
V
DDINT
Internal Supply Voltage Industrial Models 1.14 1.47 V
Internal Supply Voltage Commercial Models 1.10 1.47 V
Internal Supply Voltage Automotive Models 1.33 1.47 V
V
DDEXT1,
2
1
Must remain powered (even if the associated function is not used).
2
V
DDEXT
is the supply to the GPIO.
External Supply Voltage 1.8 V I/O, Nonautomotive Models 1.7 1.8 1.9 V
External Supply Voltage 2.5 V I/O, Nonautomotive Models 2.25 2.5 2.75 V
External Supply Voltage 3.3 V I/O, All Models 3.0 3.3 3.6 V
V
DDMEM3
3
Pins/balls that use V
DDMEM
are DATA15–0, ADDR19–1, ABE1–0, ARE, AWE, AMS1–0, SA10, SWE, SCAS, CLKOUT, SRAS, SMS, SCKE. These pins/balls are not tolerant
to voltages higher than V
DDMEM
. When using any of the asynchronous memory signals AMS3–2, ARDY, or AOE V
DDMEM
and V
DDEXT
must be shorted externally.
MEM Supply Voltage 1.8 V I/O, Nonautomotive Models 1.7 1.8 1.9 V
MEM Supply Voltage 2.5 V I/O, Nonautomotive Models 2.25 2.5 2.75 V
MEM Supply Voltage 3.3 V I/O, All Models 3.0 3.3 3.6 V
V
DDRTC4
4
If not used, power with V
DDEXT
.
RTC Power Supply Voltage 2.25 3.6 V
V
DDFLASH4
Internal SPI Flash Supply
Voltage
2.7 3.3 3.6 V
V
DDOTP1
OTP Supply Voltage 2.25 2.5 2.75 V
V
PPOTP
OTP Programming Voltage
For Reads
1
2.25 2.5 2.75 V
For Writes
5
5
The V
PPOTP
voltage for writes must only be applied when programming OTP memory. There is a finite amount of cumulative time that this voltage may be applied (dependent
on voltage and junction temperature) over the lifetime of the part.
6.9 7.0 7.1 V
V
IH
High Level Input Voltage
6, 7
6
Parameter value applies to all input and bidirectional pins/balls except SDA and SCL.
7
Bidirectional balls (PF15–0, PG15–0, PH15–0) and input balls (RTXI, TCK, TDI, TMS, TRST, CLKIN, RESET, NMI, and BMODE3–0) of the ADSP-BF51x processors are
2.5 V tolerant (always accept up to 2.7 V maximum V
IH
). Voltage compliance (on outputs, V
OH
) is limited by the V
DDEXT
supply voltage.
V
DDEXT
/V
DDMEM
= 1.90 V 1.2 V
High Level Input Voltage
6, 8
8
Bidirectional pins/balls (PF15–0, PG15–0, PH7–0) and input pins/balls (RTXI, TCK, TDI, TMS, TRST, CLKIN, RESET, NMI, and BMODE2–0) of the ADSP-BF51x are
3.3 V tolerant (always accept up to 3.6 V maximum V
IH
). Voltage compliance (on outputs, V
OH
) is limited by the V
DDEXT
supply voltage.
V
DDEXT
/V
DDMEM
= 2.75 V 1.7 V
High Level Input Voltage
6, 8
V
DDEXT
/V
DDMEM
= 3.6 V 2 V
V
IHTWI
High Level Input Voltage V
DDEXT
= 1.90 V/2.75 V/3.6 V 0.7 × V
BUSTWI
V
BUSTWI9
9
The V
IHTWI
min and max value vary with the selection in the TWI_DT field of the NONGPIO_DRIVE register. See V
BUSTWI
min and max values in Table 9.
V
V
IL
Low Level Input Voltage
6, 7
V
DDEXT
/V
DDMEM
= 1.7 V 0.6 V
Low Level Input Voltage
6, 8
V
DDEXT
/V
DDMEM
= 2.25 V 0.7 V
Low Level Input Voltage
6, 8
V
DDEXT
/V
DDMEM
= 3.0 V 0.8 V
V
ILTWI
Low Level Input Voltage V
DDEXT
= Minimum 0.3 × V
BUSTWI10
10
SDA and SCL are pulled up to V
BUSTWI
. See Table 9.
V
Junction Temperature 168-Ball CSP_BGA @ T
AMBIENT
= 0°C to +70°C 0 +95 °C
Junction Temperature 168-Ball CSP_BGA @ T
AMBIENT
= –40°C to +85°C –40 +105 °C
Junction Temperature 176-Lead LQFP_EP @ T
AMBIENT
= 0°C to +70°C 0 +95 °C
Junction Temperature 176-Lead LQFP_EP @ T
AMBIENT
= –40°C to +85°C –40 +105 °C
ADSP-BF512/BF514/BF514F16/BF516/BF518/BF518F16
Rev. D | Page 23 of 68 | April 2014
Table 9 shows settings for TWI_DT in the NONGPIO_DRIVE
register. Set this register prior to using the TWI port.
Clock Related Operating Conditions
Table 10 describes the timing requirements for the processor
clocks. Take care in selecting MSEL, SSEL, and CSEL ratios so as
not to exceed the maximum core clock and system clock.
Table 11 describes phase-locked loop operating conditions.
Table 9. TWI_DT Field Selections and V
DDEXT
/V
BUSTWI
TWI_DT V
DDEXT
Nominal V
BUSTWI
Minimum V
BUSTWI
Nominal V
BUSTWI
Maximum Unit
000 (default) 3.3 2.97 3.3 3.63 V
001 1.8 1.7 1.8 1.98 V
010 2.5 2.97 3.3 3.63 V
011 1.8 2.97 3.3 3.63 V
100 3.3 4.5 5 5.5 V
101 1.8 2.25 2.5 2.75 V
110 2.5 2.25 2.5 2.75 V
111 (reserved)—————
Table 10. Core Clock (CCLK) Requirements
Parameter
Nominal
Voltage Setting Maximum Unit
f
CCLK
Core Clock Frequency (V
DDINT
=1.33 V Minimum, All Models) 1.400 V 400 MHz
Core Clock Frequency (V
DDINT
=1.23 V Minimum, Industrial/Commercial Models) 1.300 V 300 MHz
Core Clock Frequency (V
DDINT
= 1.14 V Minimum, Industrial Models Only) 1.200 V 200 MHz
Core Clock Frequency (V
DDINT
= 1.10 V Minimum, Commercial Models Only) 1.150 V 200 MHz
Table 11. Phase-Locked Loop Operating Conditions
Parameter Min Max Unit
f
VCO
Voltage Controlled Oscillator (VCO) Frequency
(Commercial/Industrial Models)
72 Instruction Rate
1
MHz
Voltage Controlled Oscillator (VCO) Frequency
(Automotive Models)
84 Instruction Rate
1
MHz
1
For more information, see Ordering Guide on Page 67.
Table 12. SCLK Conditions
V
DDEXT
/V
DDMEM
1.8 V Nominal
V
DDEXT
/V
DDMEM
2.5 V or 3.3 V Nominal
Parameter
1
Max Max Unit
f
SCLK
CLKOUT/SCLK Frequency (V
DDINT
≥ 1.230 V
Minimum)
80 100 MHz
f
SCLK
CLKOUT/SCLK Frequency (V
DDINT
< 1.230 V) 80 80 MHz
1
f
SCLK
must be less than or equal to f
CCLK
and is subject to additional restrictions for SDRAM interface operation. See Table 28 on Page 33.
Rev. D | Page 24 of 68 | April 2014
ADSP-BF512/BF514/BF514F16/BF516/BF518/BF518F16
ELECTRICAL CHARACTERISTICS
Parameter Test Conditions Min Typical Max Unit
V
OH
High Level Output Voltage V
DDEXT
/V
DDMEM
= 1.7 V,
I
OH
=–0.5mA
1.35 V
High Level Output Voltage V
DDEXT
/V
DDMEM
= 2.25 V,
I
OH
=–0.5mA
2V
High Level Output Voltage V
DDEXT
/V
DDMEM
= 3.0 V,
I
OH
=–0.5mA
2.4 V
V
OL
Low Level Output Voltage V
DDEXT
/V
DDMEM
= 1.7/2.25/3.0 V,
I
OL
=2.0mA
0.4 V
I
IH1
High Level Input Current V
DDEXT
/V
DDMEM
=3.6 V, V
IN
=3.6V 10 µA
I
IL1
Low Level Input Current V
DDEXT
/V
DDMEM
=3.6 V, V
IN
= 0 V 10 µA
I
IHP2
High Level Input Current JTAG V
DDEXT
= 3.6 V, V
IN
= 3.6 V 75 µA
I
OZH3
Three-State Leakage Current V
DDEXT
/V
DDMEM
= 3.6 V, V
IN
=3.6V 10 µA
I
OZHTWI4
Three-State Leakage Current V
DDEXT
=3.0 V, V
IN
= 5.5 V 10 µA
I
OZL3
Three-State Leakage Current V
DDEXT
/V
DDMEM
= 3.6 V, V
IN
= 0 V 10 µA
C
IN5, 6
Input Capacitance f
IN
= 1 MHz, T
AMBIENT
= 25°C,
V
IN
=2.5V
58 pF
C
INTWI4,
6
Input Capacitance f
IN
= 1 MHz, T
AMBIENT
= 25°C,
V
IN
=2.5V
15 pF
I
DDDEEPSLEEP7
V
DDINT
Current in Deep Sleep
Mode
V
DDINT
= 1.3 V, f
CCLK
= 0 MHz,
f
SCLK
=0MHz, T
J
= 25°C,
ASF = 0.00
2.1 mA
I
DDSLEEP
V
DDINT
Current in Sleep Mode V
DDINT
= 1.3 V, f
SCLK
= 25 MHz,
T
J
= 25°C
5.5 mA
I
DD-IDLE
V
DDINT
Current in Idle V
DDINT
= 1.3 V, f
CCLK
= 50 MHz,
f
SCLK
=25MHz, T
J
= 25°C,
ASF = 0.41
12 mA
I
DD-TYP
V
DDINT
Current V
DDINT
= 1.3 V, f
CCLK
= 300 MHz,
f
SCLK
=25MHz, T
J
= 25°C,
ASF = 1.00
77 mA
I
DD-TYP
V
DDINT
Current V
DDINT
= 1.4 V, f
CCLK
= 400 MHz,
f
SCLK
=25MHz, T
J
= 25°C,
ASF = 1.00
108 mA
I
DDHIBERNATE8
Hibernate State Current V
DDEXT
=V
DDMEM
=V
DDRTC
=3.3 V
V
DDOTP
=V
PPOTP
=2.5 V, T
J
=25°C,
CLKIN = 0 MHz
40 A
I
DDRTC
V
DDRTC
Current V
DDRTC
= 3.3 V, T
J
= 25°C 20 A
I
DDSLEEP8,
9
V
DDINT
Current in Sleep Mode f
CCLK
= 0 MHz, f
SCLK
> 0 MHz Table 14 +
(0.20 × V
DDINT
× f
SCLK
)
mA
10
I
DDDEEPSLEEP8,
10
V
DDINT
Current in Deep Sleep
Mode
f
CCLK
= 0 MHz, f
SCLK
= 0 MHz Table 14 mA
I
DDINT10,
11
V
DDINT
Current f
CCLK
> 0 MHz, f
SCLK
0 MHz Table 14 +
(Table 15 × ASF) +
(0.20 × V
DDINT
× f
SCLK
)
mA
ADSP-BF512/BF514/BF514F16/BF516/BF518/BF518F16
Rev. D | Page 25 of 68 | April 2014
Total Power Dissipation
Total power dissipation has two components:
1. Static, including leakage current
2. Dynamic, due to transistor switching characteristics
Many operating conditions can also affect power dissipation,
including temperature, voltage, operating frequency, and pro-
cessor activity. Electrical Characteristics on Page 24 shows the
current dissipation for internal circuitry (V
DDINT
). I
DDDEEPSLEEP
specifies static power dissipation as a function of voltage
(V
DDINT
) and temperature (see Table 14), and I
DDINT
specifies the
total power specification for the listed test conditions, including
the dynamic component as a function of voltage (V
DDINT
) and
frequency (Table 15).
There are two parts to the dynamic component. The first part is
due to transistor switching in the core clock (CCLK) domain.
This part is subject to an Activity Scaling Factor (ASF) which
represents application code running on the processor core and
L1 memories (Table 13).
The ASF is combined with the CCLK Frequency and V
DDINT
dependent data in Table 15 to calculate this part. The second
part is due to transistor switching in the system clock (SCLK)
domain, which is included in the I
DDINT
specification equation.
I
DDFLASH1
Flash Memory Supply Current 1
—Asynchronous Read
69 mA
I
DDFLASH2
Flash Memory Supply Current 2
—Standby
15 25 A
I
DDFLASH3
Flash Memory Supply Current 3
—Program and Erase
20 25 mA
I
DDOTP
V
DDOTP
Current V
DDOTP
= 2.5 V, T
J
= 25°C,
OTP Memory Read
2mA
I
DDOTP
V
DDOTP
Current V
DDOTP
= 2.5 V, T
J
= 25°C,
OTP Memory Write
2mA
I
PPOTP
V
PPOTP
Current V
PPOTP
= 2.5 V, T
J
= 25°C,
OTP Memory Read
100 A
I
PPOTP
V
PPOTP
Current V
PPOTP
= Table 20 V, T
J
= 25°C,
OTP Memory Write
3mA
1
Applies to input balls.
2
Applies to JTAG input balls (TCK, TDI, TMS, TRST).
3
Applies to three-statable balls.
4
Applies to bidirectional balls SCL and SDA.
5
Applies to all signal balls, except SCL and SDA.
6
Guaranteed, but not tested.
7
See the ADSP-BF51x Blackfin Processor Hardware Reference Manual for definition of sleep, deep sleep, and hibernate operating modes.
8
Includes current on V
DDEXT
, V
DDMEM
, V
DDOTP
, and V
PPOTP
supplies. Clock inputs are tied high or low.
9
Guaranteed maximum specifications.
10
Unit for V
DDINT
is V (Volts). Unit for f
SCLK
is MHz.
11
See Table 13 for the list of I
DDINT
power vectors covered.
Parameter Test Conditions Min Typical Max Unit
Table 13. Activity Scaling Factors (ASF)
1
1
See Estimating Power for ASDP-BF534/BF536/BF537 Blackfin Processors
(EE-297). The power vector information also applies to the ADSP-BF51x
processors.
I
DDINT
Power Vector Activity Scaling Factor (ASF)
I
DD-PEAK
1.29
I
DD-HIGH
1.25
I
DD-TYP
1.00
I
DD-APP
0.85
I
DD-NOP
0.70
I
DD-IDLE
0.41
Table 14. Static Current—I
DD-DEEPSLEEP
(mA)
T
J
(°C)
1
Voltage (V
DDINT
)
1
1.10 V 1.15 V 1.20 V 1.25 V 1.30 V 1.35 V 1.40 V 1.45 V 1.50 V
–40 0.9 1.0 1.0 1.1 1.1 1.2 1.3 1.7 1.9
–20 1.0 1.1 1.2 1.3 1.4 1.6 1.7 1.9 2.0
0 1.2 1.3 1.4 1.6 1.8 2.0 2.2 2.3 2.5
Rev. D | Page 26 of 68 | April 2014
ADSP-BF512/BF514/BF514F16/BF516/BF518/BF518F16
FLASH MEMORY CHARACTERISTICS
25 1.8 1.9 2.1 2.3 2.5 2.8 3.1 3.3 3.7
40 2.4 2.6 2.8 3.0 3.3 3.7 4.0 4.4 4.9
55 3.3 3.5 3.8 4.3 4.6 5.0 5.5 6.1 6.7
70 4.6 5.0 5.4 6.0 6.4 7.0 7.7 8.4 9.2
85 6.5 7.1 7.7 8.3 9.1 9.9 10.8 11.8 12.8
100 9.2 10.0 10.8 11.7 12.7 13.7 15.0 16.1 17.5
105 10.3 11.1 12.1 13.1 14.2 15.3 16.6 18.0 19.4
1
Valid frequency and voltage ranges are model-specific. See Operating Conditions on Page 22.
Table 15. Dynamic Current in CCLK Domain (mA, with ASF = 1.0)
1
f
CCLK
(MHz)
2
Voltage (V
DDINT
)
2
1.10 V 1.15 V 1.20 V 1.25 V 1.30 V 1.35 V 1.40 V 1.45 V 1.50 V
400 N/A N/A N/A N/A N/A N/A 102.1 106.5 111.0
350 N/A N/A N/A N/A N/A 86.2 90.1 94.0 98.0
300 N/A N/A N/A N/A 71.4 74.7 78.1 81.5 85.0
250 N/A N/A N/A 57.5 60.4 63.2 66.1 69.0 71.9
200 N/A 42.5 44.7 47.0 49.4 51.7 54.1 56.5 58.9
150 31.1 32.9 34.7 36.5 38.4 40.2 42.1 44.0 45.9
100 22.0 23.4 24.7 26.0 27.4 28.7 30.1 31.5 33.0
1
The values are not guaranteed as standalone maximum specifications. They must be combined with static current per the equations of Electrical Characteristics on Page 24.
2
Valid frequency and voltage ranges are model-specific. See Operating Conditions on Page 22.
Table 14. Static Current—I
DD-DEEPSLEEP
(mA) (Continued)
T
J
(°C)
1
Voltage (V
DDINT
)
1
1.10 V 1.15 V 1.20 V 1.25 V 1.30 V 1.35 V 1.40 V 1.45 V 1.50 V
Table 16. Reliability Characteristics
Parameter Min Unit Test Method
N
END
Endurance 100,000 Cycles JEDEC Standard A117
T
DR
Data Retention 20 Years JEDEC Standard A103
Table 17. AC Operating Characteristics
Parameter Min Max Unit
f
CLK
Serial Clock Frequency 0.25 × f
SCLK
MHz
T
SE
Sector-Erase 450 ms
T
BE
Block-Erase 2000 ms
T
SCE
Chip-Erase 64 s
T
BP1
Byte-Program 50 s
T
PWU2
Power-Up Time Delay Before Write Command 1 10 ms
1
For multiple bytes after first byte within a page, t
BP(MAX)
increments by 12 × N, where N = number of bytes programmed after the first byte.
2
Program, Erase, and Write instructions are ignored until T
PWU
ms after flash power-on.
ADSP-BF512/BF514/BF514F16/BF516/BF518/BF518F16
Rev. D | Page 27 of 68 | April 2014
ABSOLUTE MAXIMUM RATINGS
Stresses greater than those listed in Table 18 may cause perma-
nent damage to the device. These are stress ratings only.
Functional operation of the device at these or any other condi-
tions greater than those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
When programming OTP memory on the ADSP-BF51x proces-
sor, the V
PPOTP
pin/ball must be set to the write value specified in
the Operating Conditions on Page 22. There is a finite amount
of cumulative time that the write voltage may be applied
(dependent on voltage and junction temperature) to V
PPOTP
over
the lifetime of the part. Therefore, maximum OTP memory pro-
gramming time for the processor is shown in Table 20.
Table 21 and Table 22 specify the maximum total source/sink
(I
OH
/I
OL
) current for a group of pins. Permanent damage can
occur if this value is exceeded. To understand this specification,
if pins PF9, PF8, PF7, PF6, and PF5 from Group 1 in Table 22
table were sourcing or sinking 2 mA each, the total current for
those pins would be 10 mA. This would allow up to 70 mA total
that could be sourced or sunk by the remaining pins in the
group without damaging the device. Note that the V
OH
and V
OL
specifications have separate per-pin maximum current require-
ments as shown in the Electrical Characteristics table.
Table 18. Absolute Maximum Ratings
Parameter Rating
Internal Supply Voltage (V
DDINT
) –0.3 V to +1.50 V
External (I/O) Supply Voltage
(V
DDEXT
/V
DDMEM
)
–0.3 V to +3.8 V
Input Voltage
1, 2
1
Applies to 100% transient duty cycle. For other duty cycles see Table 19.
2
Applies only when V
DDEXT
is within specifications. When V
DDEXT
is outside speci-
fications, the range is V
DDEXT
± 0.2.
–0.5 V to +3.6 V
Input Voltage
1, 3
3
Applies to signals SCL, SDA.
–0.5 V to +5.5 V
Output Voltage Swing –0.5 V to
V
DDEXT
/V
DDMEM
+0.5 V
I
OH
/I
OL
Current per Pin Group
4
4
For more information, see the information preceding Table 21 and Table 22.
80 mA (max)
Storage Temperature Range –65°C to +150°C
Junction Temperature While biased +110°C
Table 19. Maximum Duty Cycle for Input Transient Voltage
1
1
Applies to all signal pins/balls with the exception of CLKIN, XTAL.
V
IN
Min (V)
2
2
The individual values cannot be combined for analysis of a single instance of
overshoot or undershoot. The worst case observed value must fall within one of
the voltages specified and the total duration of the overshoot or undershoot
(exceeding the 100% case) must be less than or equal to the corresponding duty
cycle.
V
IN
Max (V)
2
Maximum Duty Cycle
3
3
Duty cycle refers to the percentage of time the signal exceeds the value for the
100% case. It is equivalent to the measured duration of a single instance of
overshoot or undershoot as a percentage of the period of occurrence.
–0.50 +3.80 100%
–0.70 +4.00 40%
–0.80 +4.10 25%
–0.90 +4.20 15%
–1.00 +4.30 10%
Table 20. Maximum OTP Memory Programming Time
Temperature
VPPOTP
Voltage (V) 25°C 85°C 110°C
6.9 6000 sec 100 sec 25 sec
7.0 2400 sec 44 sec 12 sec
7.1 1000 sec 18 sec 4.5 sec
Table 21. Total Current Pin Groups–V
DDMEM
Groups
Group Pins in Group
1 DATA15, DATA14, DATA13, DATA12, DATA11, DATA10
2 DATA9, DATA8, DATA7, DATA6, DATA5, DATA4
3 DATA3, DATA2, DATA1, DATA0, ADDR19, ADDR18
4 ADDR17, ADDR16, ADDR15, ADDR14, ADDR13
5 ADDR12, ADDR11, ADDR10, ADDR9, ADDR8, ADDR7
6 ADDR6, ADDR5, ADDR4, ADDR3, ADDR2, ADDR1
7ABE1
, ABE0, SA10, SWE, SCAS, SRAS
8SMS, SCKE, AMS1, ARE, AWE, AMS0, CLKOUT
Table 22. Total Current Pin Groups–V
DDEXT
Groups
Group Pins in Group
1 PF9, PF8, PF7, PF6, PF5, PF4, PF3, PF2
2 PF1, PF0, PG15, PG14, PG13, PG12, PG11, PG10
3 PG9, PG8, PG7, PG6, PG5, PG4, PG3, PG2, BMODE0,
BMODE1, BMODE2
4PG1, PG0, TDO, EMU
, TDI, TCK, TRST, TMS
5RESET
, NMI, CLKBUF
6 PH7, PH6, PH5, PH4, PH3, PH2, PH1, PH0
7 PF15, PF14, PF13, PF12, PF11, SDA, SCL, PF10
Rev. D | Page 28 of 68 | April 2014
ADSP-BF512/BF514/BF514F16/BF516/BF518/BF518F16
PACKAGE INFORMATION
The information presented in Figure 8 and Table 23 provides
details about the package branding for the processor. For a com-
plete listing of product availability, see Ordering Guide on
Page 67.
ESD SENSITIVITY
Figure 8. Product Information on Package
Table 23. Package Brand Information
Brand Key Field Description
ADSP-BF51x Product Name
t Temperature Range
pp Package Type
Z Lead Free Option
ccc See Ordering Guide
vvvvvv.x Assembly Lot Code
n.n Silicon Revision
# RoHS Compliance Designator
yyww Date Code
vvvvvv.x n.n
tppZccc
ADSP-BF51x
a
B
#yyww country_of_origin
ESD (electrostatic discharge) sensitive device.
Charged devices and circuit boards can discharge
without detection. Although this product features
patented or proprietary protection circuitry, damage
may occur on devices subjected to high energy ESD.
Therefore, proper ESD precautions should be taken to
avoid
performance degradation or loss of functionality.
ADSP-BF512/BF514/BF514F16/BF516/BF518/BF518F16
Rev. D | Page 29 of 68 | April 2014
TIMING SPECIFICATIONS
Clock and Reset Timing
Table 24 and Figure 9 describe clock and reset operations. Per
the CCLK and SCLK timing specifications in Table 10, Table 11,
and Table 12 on Page 23, combinations of CLKIN and clock
multipliers must not select core/peripheral clocks in excess of
the processor’s speed grade.
Table 24. Clock and Reset Timing
Parameter Min Max Unit
Timing Requirements
f
CKIN
CLKIN Frequency (Commercial/Industrial Models
1, 2,
3,
4
12 50 MHz
f
CKIN
CLKIN Frequency (Automotive Models)
1,
2,
3,
4
14 50 MHz
t
CKINL
CLKIN Low Pulse
1
10 ns
t
CKINH
CLKIN High Pulse
1
10 ns
t
WRST
RESET Asserted Pulse Width Low
5
11 × t
CKIN
ns
Switching Characteristic
t
BUFDLAY
CLKIN to CLKBUF Delay 11 ns
1
Applies to PLL bypass mode and PLL nonbypass mode.
2
Combinations of the CLKIN frequency and the PLL clock multiplier must not exceed the allowed f
VCO
, f
CCLK
, and f
SCLK
settings discussed in Table 10 through Table 12 on Page 23.
3
The t
CKIN
period (see Figure 9) equals 1/f
CKIN
.
4
If the DF bit in the PLL_CTL register is set, the minimum f
CKIN
specification is 24 MHz for commercial/industrial models and 28 MHz for automotive models.
5
Applies after power-up sequence is complete. See Table 25 and Figure 10 for power-up reset timing.
Figure 9. Clock and Reset Timing
CLKIN
tWRST
tCKIN
tCKINL tCKINH
tBUFDLAY
tBUFDLAY
RESET
CLKBUF
Rev. D | Page 30 of 68 | April 2014
ADSP-BF512/BF514/BF514F16/BF516/BF518/BF518F16
Table 25. Power-Up Reset Timing
Parameter Min Max Unit
Timing Requirements
t
RST_IN_PWR
RESET Deasserted after the V
DDINT
, V
DDEXT
, V
DDRTC
, V
DDMEM
, V
DDOTP
, and CLKIN Pins are
Stable and Within Specification
3500 × t
CKIN
ns
Figure 10. Power-Up Reset Timing
RESET
tRST_IN_PWR
CLKIN
VDD_SUPPLIES
ADSP-BF512/BF514/BF514F16/BF516/BF518/BF518F16
Rev. D | Page 31 of 68 | April 2014
Asynchronous Memory Read Cycle Timing
Table 26. Asynchronous Memory Read Cycle Timing
V
DDMEM
1.8V Nominal
V
DDMEM
2.5 V/3.3V Nominal
Parameter Min Max Min Max Unit
Timing Requirements
t
SDAT
DATA15–0 Setup Before CLKOUT 2.1 2.1 ns
t
HDAT
DATA15–0 Hold After CLKOUT 1.2 0.8 ns
t
SARDY
ARDY Setup Before CLKOUT 4 4 ns
t
HARDY
ARDY Hold After CLKOUT 0.2 0.2 ns
Switching Characteristics
t
DO
Output Delay After CLKOUT
1
1
Output pins/balls include AMS3–0, ABE1– 0, ADDR19–1, AOE, ARE.
66ns
t
HO
Output Hold After CLKOUT
1
0.8 0.8 ns
Figure 11. Asynchronous Memory Read Cycle Timing
tHARDY
SETUP
2 CYCLES
PROGRAMMED READ
ACCESS 4 CYCLES
ACCESS EXTENDED
3 CYCLES
HOLD
1 CYCLE
tDO tHO
tDO
tHARDY
tSARDY
tSDAT
tHDAT
tSARDY
CLKOUT
AMSx
ABE1–0
ADDR19–1
AOE
ARE
ARDY
DATA 15–0
tHO
Rev. D | Page 32 of 68 | April 2014
ADSP-BF512/BF514/BF514F16/BF516/BF518/BF518F16
Asynchronous Memory Write Cycle Timing
Table 27. Asynchronous Memory Write Cycle Timing
Parameter Min Max Unit
Timing Requirements
t
SARDY
ARDY Setup Before CLKOUT 4 ns
t
HARDY
ARDY Hold After CLKOUT 0.2 ns
Switching Characteristics
t
DDAT
DATA15–0 Disable After CLKOUT 6 ns
t
ENDAT
DATA15–0 Enable After CLKOUT 0 ns
t
DO
Output Delay After CLKOUT
1
1
Output pins/balls include AMS3–0, ABE1–0, ADDR19–1, DATA15–0, AOE, AWE.
6ns
t
HO
Output Hold After CLKOUT
1
0.8 ns
Figure 12. Asynchronous Memory Write Cycle Timing
SETUP
2 CYCLES
PROGRAMMED
WRITE
ACCESS
2 CYCLES
ACCESS
EXTEND
1 CYCLE
HOLD
1 CYCLE
tDO tHO
CLKOUT
AMSx
ABE1–0
ADDR19–1
AWE
ARDY
DATA 15–0
tSARDY
tSARDY
tDDAT
tENDAT tHARDY
tHO
tDO
tHARDY
ADSP-BF512/BF514/BF514F16/BF516/BF518/BF518F16
Rev. D | Page 33 of 68 | April 2014
SDRAM Interface Timing
Table 28. SDRAM Interface Timing
V
DDMEM
1.8V Nominal
V
DDMEM
2.5 V/3.3V Nominal
Parameter Min Max Min Max Unit
Timing Requirements
t
SSDAT
Data Setup Before CLKOUT 1.5 1.5 ns
t
HSDAT
Data Hold After CLKOUT 1.3 0.8 ns
Switching Characteristics
t
SCLK
CLKOUT Period
1
1
The t
SCLK
value is the inverse of the f
SCLK
specification discussed in Table 12 on Page 23. Package type and reduced supply voltages affect the best-case value listed here.
12.5 10 ns
t
SCLKH
CLKOUT Width High 54ns
t
SCLKL
CLKOUT Width Low 54ns
t
DCAD
Command, Address, Data Delay After CLKOUT
2
2
Command pins/balls include: SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE.
54ns
t
HCAD
Command, Address, Data Hold After CLKOUT
2
11ns
t
DSDAT
Data Disable After CLKOUT 5.5 5 ns
t
ENSDAT
Data Enable After CLKOUT 0 0 ns
Figure 13. SDRAM Interface Timing
tSCLK
CLKOUT
tSCLKL tSCLKH
tSSDAT tHSDAT
tENSDAT
tDCAD tDSDAT
tHCAD
tDCAD tHCAD
DATA (IN)
DATA (OUT)
COMMAND,
ADDRESS
(OUT)
NOTE: COMMAND = SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE.
Rev. D | Page 34 of 68 | April 2014
ADSP-BF512/BF514/BF514F16/BF516/BF518/BF518F16
External DMA Request Timing
Table 29 and Figure 14 describe the External DMA Request
operations.
Table 29. External DMA Request Timing
1
V
DDMEM
/V
DDEXT
1.8 V Nominal
V
DDMEM
/V
DDEXT
2.5 V/3.3 V Nominal
Parameter Min Max Min Max Unit
Timing Requirements
t
DS
DMARx Asserted to CLKOUT High Setup 9 7.2 ns
t
DH
CLKOUT High to DMARx Deasserted Hold Time 0 0 ns
t
DMARACT
DMARx Active Pulse Width t
SCLK
+ 1 t
SCLK
+ 1 ns
t
DMARINACT
DMARx Inactive Pulse Width 1.75 × t
SCLK
1.75 × t
SCLK
ns
1
Because the external DMA control pins are part of the V
DDEXT
power domain and the CLKOUT signal is part of the V
DDMEM
power domain, systems in which V
DDEXT
and
V
DDMEM
are NOT equal may require level shifting logic for correct operation.
Figure 14. External DMA Request Timing
CLKOUT
tDS
DMAR0/1
(ACTIVE LOW)
DMAR0/1
(ACTIVE HIGH)
tDMARACT tDMARINACT
tDH
ADSP-BF512/BF514/BF514F16/BF516/BF518/BF518F16
Rev. D | Page 35 of 68 | April 2014
Parallel Peripheral Interface Timing
Table 30 and Figure 16 on Page 35, Figure 22 on Page 40, and
Figure 25 on Page 42 describe parallel peripheral interface
operations.
Table 30. Parallel Peripheral Interface Timing
V
DDEXT
1.8 V Nominal
V
DDEXT
2.5 V/3.3 V Nominal
Parameter Min Max Min Max Unit
Timing Requirements
t
PCLKW
PPI_CLK Width t
SCLK
– 1.5 t
SCLK
– 1.5 ns
t
PCLK
PPI_CLK Period 2 × t
SCLK
– 1.5 2 × t
SCLK
– 1.5 ns
Timing Requirements - GP Input and Frame Capture Modes
t
PSUD
External Frame Sync Startup Delay
1
4 × t
PCLK
4 × t
PCLK
ns
t
SFSPE
External Frame Sync Setup Before PPI_CLK
(Nonsampling Edge for Rx, Sampling Edge for Tx)
6.7 6.7 ns
t
HFSPE
External Frame Sync Hold After PPI_CLK 1.75 1.75 ns
t
SDRPE
Receive Data Setup Before PPI_CLK 4.1 3.5 ns
t
HDRPE
Receive Data Hold After PPI_CLK 2 1.6 ns
Switching Characteristics - GP Output and Frame Capture Modes
t
DFSPE
Internal Frame Sync Delay After PPI_CLK 8 8 ns
t
HOFSPE
Internal Frame Sync Hold After PPI_CLK 1.7 1.7 ns
t
DDTPE
Transmit Data Delay After PPI_CLK 8.2 8 ns
t
HDTPE
Transmit Data Hold After PPI_CLK 2.3 1.9 ns
1
The PPI port is fully enabled 4 PPI clock cycles after the PAB write to the PPI port enable bit. Only after the PPI port is fully enabled are external frame syncs and data words
guaranteed to be received correctly by the PPI peripheral.
Figure 15. PPI with External Frame Sync Timing
Figure 16. PPI GP Rx Mode with External Frame Sync Timing
PPI_CLK
PPI_FS1/2
tPSUD
tPCLK
tSFSPE
DATA SAMPLED /
FRAME SYNC SAMPLED
DATA SAMPLED /
FRAME SYNC SAMPLED
PPI_DATA
PPI_CLK
PPI_FS1/2
tHFSPE
tHDRPE
tSDRPE
tPCLKW
Rev. D | Page 36 of 68 | April 2014
ADSP-BF512/BF514/BF514F16/BF516/BF518/BF518F16
Figure 17. PPI GP Tx Mode with External Frame Sync Timing
Figure 18. PPI GP Rx Mode with Internal Frame Sync Timing
Figure 19. PPI GP Tx Mode with Internal Frame Sync Timing
tHDTPE
tSFSPE
DATA DRIVEN /
FRAME SYNC SAMPLED
PPI_DATA
PPI_CLK
PPI_FS1/2
tHFSPE
tDDTPE
tPCLK
tPCLKW
tHDRPE
tSDRPE
tHOFSPE
FRAME SYNC
DRIVEN
DATA
SAMPLED
PPI_DATA
PPI_CLK
PPI_FS1/2
tDFSPE
tPCLK
tPCLKW
tHOFSPE
FRAME SYNC
DRIVEN
DATA
DRIVEN
PPI_DATA
PPI_CLK
PPI_FS1/2
tDFSPE
tDDTPE tHDTPE
tPCLK
tPCLKW
DATA
DRIVEN
ADSP-BF512/BF514/BF514F16/BF516/BF518/BF518F16
Rev. D | Page 37 of 68 | April 2014
RSI Controller Timing
Table 31 and Figure 20 describe RSI controller timing. Table 32
and Figure 21 describe RSI controller (high speed) timing.
Table 31. RSI Controller Timing
Parameter Min Max Unit
Timing Requirements
t
ISU
Input Setup Time 5.6 ns
t
IH
Input Hold Time 2 ns
Switching Characteristics
f
PP1
Clock Frequency Data Transfer Mode 0 25 MHz
f
OD
Clock Frequency Identification Mode 100
2
400 kHz
t
WL
Clock Low Time 10 ns
t
WH
Clock High Time 10 ns
t
TLH
Clock Rise Time 10 ns
t
THL
Clock Fall Time 10 ns
t
ODLY
Output Delay Time During Data Transfer Mode 14 ns
t
ODLY
Output Delay Time During Identification Mode 50 ns
1
t
PP
= 1/f
PP
2
Specification can be 0 kHz, which means to stop the clock. The given minimum frequency range is for cases where a continuous clock is required.
Figure 20. RSI Controller Timing
SD_CLK
INPUT
OUTPUT
tISU
NOTES:
1 INPUT INCLUDES SD_Dx AND SD_CMD SIGNALS.
2 OUTPUT INCLUDES SD_Dx AND SD_CMD SIGNALS.
tTHL tTLH
tWL tWH
tPP
tIH
tODLY
VOH (MIN)
VOL (MAX)
Rev. D | Page 38 of 68 | April 2014
ADSP-BF512/BF514/BF514F16/BF516/BF518/BF518F16
Table 32. RSI Controller Timing (High Speed Mode)
Parameter Min Max Unit
Timing Requirements
t
ISU
Input Setup Time 5.6 ns
t
IH
Input Hold Time 2 ns
Switching Characteristics
f
PP1
Clock Frequency Data Transfer Mode 0 50 MHz
t
WL
Clock Low Time 7 ns
t
WH
Clock High Time 7 ns
t
TLH
Clock Rise Time 3ns
t
THL
Clock Fall Time 3ns
t
ODLY
Output Delay Time During Data Transfer Mode 4 ns
t
OH
Output Hold Time 2.75 ns
1
t
PP
= 1/f
PP
Figure 21. RSI Controller Timing (High Speed Mode)
SD_CLK
INPUT
OUTPUT
tISU
NOTES:
1 INPUT INCLUDES SD_Dx AND SD_CMD SIGNALS.
2 OUTPUT INCLUDES SD_Dx AND SD_CMD SIGNALS.
tTHL tTLH
tWL tWH
tPP
tIH
tODLY tOH
VOH (MIN)
VOL (MAX)
ADSP-BF512/BF514/BF514F16/BF516/BF518/BF518F16
Rev. D | Page 39 of 68 | April 2014
Serial Ports
Table 33 through Table 36 on Page 42 and Figure 22 on Page 40
through Figure 25 on Page 42 describe serial port operations.
Table 33. Serial Ports—External Clock
V
DDEXT
1.8V Nominal
V
DDEXT
2.5 V/3.3V Nominal
Parameter Min Max Min Max Unit
Timing Requirements
t
SFSE1
TFSx/RFSx Setup Before TSCLKx/RSCLKx 3 3 ns
t
HFSE1
TFSx/RFSx Hold After TSCLKx/RSCLKx 3 3 ns
t
SDRE1
Receive Data Setup Before RSCLKx 3 3 ns
t
HDRE1
Receive Data Hold After RSCLKx 3.5 3 ns
t
SCLKEW
TSCLKx/RSCLKx Width 7 4.5 ns
t
SCLKE
TSCLKx/RSCLKx Period 2 × t
SCLK
2 × t
SCLK
ns
t
SUDTE2
Start-Up Delay From SPORT Enable To First External TFSx 4 × t
SCLKE
4 × t
SCLKE
ns
t
SUDRE2
Start-Up Delay From SPORT Enable To First External RFSx 4 × t
SCLKE
4 × t
SCLKE
ns
Switching Characteristics
t
DFSE3
TFSx/RFSx Delay After TSCLKx/RSCLKx (Internally Generated
TFSx/RFSx)
10 10 ns
t
HOFSE3
TFSx/RFSx Hold After TSCLKx/RSCLKx (Internally Generated
TFSx/RFSx)
00ns
t
DDTE3
Transmit Data Delay After TSCLKx 10 10 ns
t
HDTE3
Transmit Data Hold After TSCLKx 0 0 ns
1
Referenced to sample edge.
2
Verified in design but untested.
3
Referenced to drive edge.
Table 34. Serial Ports—Internal Clock
V
DDEXT
1.8V Nominal
V
DDEXT
2.5 V/3.3V Nominal
Parameter Min Max Min Max Unit
Timing Requirements
t
SFSI1
TFSx/RFSx Setup Before TSCLKx/RSCLKx 11 9.6 ns
t
HFSI1
TFSx/RFSx Hold After TSCLKx/RSCLKx –1.5 –1.5 ns
t
SDRI1
Receive Data Setup Before RSCLKx 11 9.6 ns
t
HDRI1
Receive Data Hold After RSCLKx –1.5 –1.5 ns
Switching Characteristics
t
DFSI2
TFSx/RFSx Delay After TSCLKx/RSCLKx (Internally Generated
TFSx/RFSx)
33ns
t
HOFSI2
TFSx/RFSx Hold After TSCLKx/RSCLKx (Internally Generated
TFSx/RFSx)
21ns
t
DDTI2
Transmit Data Delay After TSCLKx 3 3 ns
t
HDTI2
Transmit Data Hold After TSCLKx 1.8 1.5 ns
t
SCLKIW
TSCLKx/RSCLKx Width 10 8 ns
1
Referenced to sample edge.
2
Referenced to drive edge.
Rev. D | Page 40 of 68 | April 2014
ADSP-BF512/BF514/BF514F16/BF516/BF518/BF518F16
Figure 22. Serial Ports
Figure 23. Serial Port Start Up with External Clock and Frame Sync
t
SDRI
RSCLKx
DRx
DRIVE EDGE
t
HDRI
t
SFSI
t
HFSI
t
DFSI
t
HOFSI
t
SCLKIW
DATA RECEIVE—INTERNAL CLOCK
t
SDRE
DATA RECEIVE—EXTERNAL CLOCK
RSCLKx
DRx
t
HDRE
t
SFSE
t
HFSE
t
DFSE
t
SCLKEW
t
HOFSE
t
DDTI
t
HDTI
TSCLKx
TFSx
(INPUT)
DTx
t
SFSI
t
HFSI
t
SCLKIW
t
DFSI
t
HOFSI
DATA TRANSMIT—INTERNAL CLOCK
t
DDTE
t
HDTE
TSCLKx
DTx
t
SFSE
t
DFSE
t
SCLKEW
t
HOFSE
DATA TRANSMIT—EXTERNAL CLOCK
SAMPLE EDGE
DRIVE EDGE SAMPLE EDGE DRIVE EDGE SAMPLE EDGE
DRIVE EDGE SAMPLE EDGE
t
SCLKE
t
SCLKE
t
HFSE
TFSx
(OUTPUT)
TFSx
(INPUT)
TFSx
(OUTPUT)
RFSx
(INPUT)
RFSx
(OUTPUT)
RFSx
(INPUT)
RFSx
(OUTPUT)
TSCLKx
(INPUT)
TFSx
(INPUT)
RFSx
(INPUT)
RSCLKx
(INPUT)
tSUDTE
tSUDRE
FIRST
ADSP-BF512/BF514/BF514F16/BF516/BF518/BF518F16
Rev. D | Page 41 of 68 | April 2014
Table 35. Serial Ports—Enable and Three-State
1
Parameter Min Max Unit
Switching Characteristics
t
DTENE
Data Enable Delay from External TSCLKx 0 ns
t
DDTTE
Data Disable Delay from External TSCLKx t
SCLK
+ 1 ns
t
DTENI
Data Enable Delay from Internal TSCLKx –2.0 ns
t
DDTTI
Data Disable Delay from Internal TSCLKx t
SCLK
+ 1 ns
1
Referenced to drive edge.
Figure 24. Enable and Three-State
TSCLKx
DTx
DRIVE EDGE
tDDTTE/I
tDTENE/I
DRIVE EDGE
Rev. D | Page 42 of 68 | April 2014
ADSP-BF512/BF514/BF514F16/BF516/BF518/BF518F16
Table 36. External Late Frame Sync
V
DDEXT
1.8V Nominal
V
DDEXT
2.5 V/3.3V Nominal
Parameter Min Max Min Max Unit
Switching Characteristics
t
DDTLFSE1, 2
Data Delay from Late External TFSx or External RFSx with
MCE = 1, MFD = 0
12 10 ns
t
DTENLFSE1, 2
Data Enable from Late FS or MCE = 1, MFD = 0 0 0 ns
1
MCE = 1, TFSx enable and TFSx valid follow t
DDTENFS
and t
DDTLFSE
.
2
If external RFSx/TFSx setup to RSCLKx/TSCLKx > t
SCLKE
/2 then t
DDTTE/I
and t
DTENE/I
apply, otherwise t
DDTLFSE
and t
DTENLFS
apply.
Figure 25. External Late Frame Sync
RSCLKx
RFSx
DTx
DRIVE
EDGE
DRIVE
EDGE
SAMPLE
EDGE
EXTERNAL RFSx IN MULTI-CHANNEL MODE
1ST BIT
tDTENLFSE
tDDTLFSE
TSCLKx
TFSx
DTx
DRIVE
EDGE
DRIVE
EDGE
SAMPLE
EDGE
LATE EXTERNAL TFSx
1ST BIT
tDDTLFSE
ADSP-BF512/BF514/BF514F16/BF516/BF518/BF518F16
Rev. D | Page 43 of 68 | April 2014
Serial Peripheral Interface (SPI) Port—Master Timing
Table 37 and Figure 26 describe SPI port master operations.
Table 37. Serial Peripheral Interface (SPI) Port—Master Timing
V
DDEXT
1.8V Nominal
V
DDEXT
2.5 V/3.3V Nominal
Parameter Min Max Min Max Unit
Timing Requirements
t
SSPIDM
Data Input Valid to SCK Edge (Data Input Setup) 11.6 9.6 ns
t
HSPIDM
SCK Sampling Edge to Data Input Invalid –1.5 –1.5 ns
Switching Characteristics
t
SDSCIM
SPISELx low to First SCK Edge 2 × t
SCLK
–1.5 2 × t
SCLK
–1.5 ns
t
SPICHM
Serial Clock High Period 2 × t
SCLK
–1.5 2 × t
SCLK
–1.5 ns
t
SPICLM
Serial Clock Low Period 2 × t
SCLK
–1.5 2 × t
SCLK
–1.5 ns
t
SPICLK
Serial Clock Period 4 × t
SCLK
4 × t
SCLK
ns
t
HDSM
Last SCK Edge to SPISELx High 2 × t
SCLK
–1.5 2 × t
SCLK
–1.5 ns
t
SPITDM
Sequential Transfer Delay 2 × t
SCLK
–1.5 2 × t
SCLK
–1.5 ns
t
DDSPIDM
SCK Edge to Data Out Valid (Data Out Delay) 6 6 ns
t
HDSPIDM
SCK Edge to Data Out Invalid (Data Out Hold) –1 –1 ns
Figure 26. Serial Peripheral Interface (SPI) Port—Master Timing
tSDSCIM tSPICLK tHDSM tSPITDM
tSPICLM tSPICHM
tHDSPIDM
tHSPIDM
tSSPIDM
SPIxSELy
(OUTPUT)
SPIxSCK
(OUTPUT)
SPIxMOSI
(OUTPUT)
SPIxMISO
(INPUT)
SPIxMOSI
(OUTPUT)
SPIxMISO
(INPUT)
CPHA = 1
CPHA = 0
tDDSPIDM
tHSPIDM
tSSPIDM
tHDSPIDM
tDDSPIDM
Rev. D | Page 44 of 68 | April 2014
ADSP-BF512/BF514/BF514F16/BF516/BF518/BF518F16
Serial Peripheral Interface (SPI) Port—Slave Timing
Table 38 and Figure 27 describe SPI port slave operations.
Universal Asynchronous Receiver-Transmitter
(UART) Ports—Receive and Transmit Timing
The UART ports receive and transmit operations are described
in the ADSP-BF51x Hardware Reference Manual.
Table 38. Serial Peripheral Interface (SPI) Port—Slave Timing
V
DDEXT
1.8V Nominal
V
DDEXT
2.5 V/3.3V Nominal
Parameter Min Max Min Max Unit
Timing Requirements
t
SPICHS
Serial Clock High Period 2 × t
SCLK
–1.5 2 × t
SCLK
–1.5 ns
t
SPICLS
Serial Clock Low Period 2 × t
SCLK
–1.5 2 × t
SCLK
–1.5 ns
t
SPICLK
Serial Clock Period 4 × t
SCLK
–1.5 4 × t
SCLK
–1.5 ns
t
HDS
Last SCK Edge to SPISS Not Asserted 2 × t
SCLK
–1.5 2 × t
SCLK
–1.5 ns
t
SPITDS
Sequential Transfer Delay 2 × t
SCLK
–1.5 2 × t
SCLK
–1.5 ns
t
SDSCI
SPISS Assertion to First SCK Edge 2 × t
SCLK
–1.5 2 × t
SCLK
–1.5 ns
t
SSPID
Data Input Valid to SCK Edge (Data Input Setup) 1.6 1.6 ns
t
HSPID
SCK Sampling Edge to Data Input Invalid 2 1.6 ns
Switching Characteristics
t
DSOE
SPISS Assertion to Data Out Active 0 12 0 10.3 ns
t
DSDHI
SPISS Deassertion to Data High Impedance 0 11 0 9 ns
t
DDSPID
SCK Edge to Data Out Valid (Data Out Delay) 10 10 ns
t
HDSPID
SCK Edge to Data Out Invalid (Data Out Hold) 0 0 ns
Figure 27. Serial Peripheral Interface (SPI) Port—Slave Timing
tSPICLK tHDS tSPITDS
tSDSCI tSPICLS tSPICHS
tDSOE tDDSPID
tDDSPID tDSDHI
tHDSPID
tSSPID
tDSDHI
tHDSPID
tDSOE
tHSPID
tSSPID
tDDSPID
SPIxSS
(INPUT)
SPIxSCK
(INPUT)
SPIxMISO
(OUTPUT)
SPIxMOSI
(INPUT)
SPIxMISO
(OUTPUT)
SPIxMOSI
(INPUT)
CPHA = 1
CPHA = 0
tHSPID
ADSP-BF512/BF514/BF514F16/BF516/BF518/BF518F16
Rev. D | Page 45 of 68 | April 2014
General-Purpose Port Timing
Table 39 and Figure 28 describe general-purpose
port operations.
Timer Clock Timing
Table 40 and Figure 29 describe timer clock timing.
Table 39. General-Purpose Port Timing
V
DDEXT
1.8V Nominal
V
DDEXT
2.5 V/3.3V Nominal
Parameter Min Max Min Max Unit
Timing Requirement
t
WFI
General-Purpose Port Signal Input Pulse Width t
SCLK
+ 1 t
SCLK
+ 1 ns
Switching Characteristic
t
GPOD
General-Purpose Port Signal Output Delay from CLKOUT Low 0 11 0 8.5 ns
Figure 28. General-Purpose Port Timing
CLKOUT
GPIO OUTPUT
GPIO INPUT
tWFI
tGPOD
Table 40. Timer Clock Timing
Parameter Min Max Unit
Switching Characteristic
t
TODP
Timer Output Update Delay After PPICLK High 12 ns
Figure 29. Timer Clock Timing
PPI_CLK
TMRx OUTPUT
tTODP
Rev. D | Page 46 of 68 | April 2014
ADSP-BF512/BF514/BF514F16/BF516/BF518/BF518F16
Timer Cycle Timing
Table 41 and Figure 30 describe timer expired operations. The
input signal is asynchronous in “width capture mode” and
“external clock mode” and has an absolute maximum input fre-
quency of (f
SCLK
/2) MHz.
Table 41. Timer Cycle Timing
V
DDEXT
1.8V Nominal
V
DDEXT
2.5 V/3.3V Nominal
Parameter Min Max Min Max Unit
Timing Characteristics
t
WL1
Timer Pulse Width Input Low (Measured In SCLK Cycles) t
SCLK
t
SCLK
ns
t
WH1
Timer Pulse Width Input High (Measured In SCLK Cycles) t
SCLK
t
SCLK
ns
t
TIS2
Timer Input Setup Time Before CLKOUT Low 10 7 ns
t
TIH2
Timer Input Hold Time After CLKOUT Low –2 –2 ns
Switching Characteristics
t
HTO
Timer Pulse Width Output (Measured In SCLK Cycles) t
SCLK
– 1.5 (2
32
–1)t
SCLK
t
SCLK
– 1 (2
32
–1)t
SCLK
ns
t
TOD
Timer Output Update Delay After CLKOUT High 6 6 ns
1
The minimum pulse widths apply for TMRx signals in width capture and external clock modes. They also apply to the PF15 or PPI_CLK signals in PWM output mode.
2
Either a valid setup and hold time or a valid pulse width is sufficient. There is no need to resynchronize programmable flag inputs.
Figure 30. Timer Cycle Timing
CLKOUT
TMRx OUTPUT
TMRx INPUT
tTIS tTIH
tWH,tWL
tTOD
tHTO
ADSP-BF512/BF514/BF514F16/BF516/BF518/BF518F16
Rev. D | Page 47 of 68 | April 2014
Up/Down Counter/Rotary Encoder Timing
10/100 Ethernet MAC Controller Timing
Table 43 through Table 48 and Figure 32 through Figure 37
describe the 10/100 Ethernet MAC Controller operations.
Table 42. Up/Down Counter/Rotary Encoder Timing
Parameter
V
DDEXT
1.8V Nominal
V
DDEXT
2.5 V/3.3V Nominal
Min Max Min Max Unit
Timing Requirements
t
WCOUNT
Up/Down Counter/Rotary Encoder Input Pulse Width t
SCLK
+ 1 t
SCLK
+ 1 ns
t
CIS
Counter Input Setup Time Before CLKOUT Low
1
1
Either a valid setup and hold time or a valid pulse width is sufficient. There is no need to resynchronize counter inputs.
97 ns
t
CIH
Counter Input Hold Time After CLKOUT Low
1
00 ns
Figure 31. Up/Down Counter/Rotary Encoder Timing
CLKOUT
CUD/CDG/CZM
tCIS
tCIH
tWCOUNT
Table 43. 10/100 Ethernet MAC Controller Timing: MII Receive Signal
V
DDEXT
1.8V Nominal
V
DDEXT
2.5 V/3.3V Nominal
Parameter
1
Min Max Min Max Unit
Timing Requirements
t
ERXCLKF
ERxCLK Frequency (f
SCLK
= SCLK Frequency) None 25 + 1% None 25 + 1% MHz
t
ERXCLKW
ERxCLK Width (t
ERxCLK
= ERxCLK Period) t
ERxCLK
× 40% t
ERxCLK
× 60% t
ERxCLK
× 35% t
ERxCLK
× 65% ns
t
ERXCLKIS
Rx Input Valid to ERxCLK Rising Edge (Data In Setup) 7.5 7.5 ns
t
ERXCLKIH
ERxCLK Rising Edge to Rx Input Invalid (Data In Hold) 7.5 7.5 ns
1
MII inputs synchronous to ERxCLK are ERxD3–0, ERxDV, and ERxER.
Figure 32. 10/100 Ethernet MAC Controller Timing: MII Receive Signal
tERXCLKIS tERXCLKIH
ERxD3–0
ERxDV
ERxER
ERx_CLK
tERXCLKW
tERXCLK
Rev. D | Page 48 of 68 | April 2014
ADSP-BF512/BF514/BF514F16/BF516/BF518/BF518F16
Table 44. 10/100 Ethernet MAC Controller Timing: MII Transmit Signal
V
DDEXT
1.8V Nominal
V
DDEXT
2.5 V/3.3V Nominal
Parameter
1
Min Max Min Max Unit
Switching Characteristics
t
ETF
ETxCLK Frequency (f
SCLK
= SCLK Frequency) None 25 + 1% None 25 + 1% MHz
t
ETXCLKW
ETxCLK Width (t
ETxCLK
= ETxCLK Period) t
ETxCLK
× 40% t
ETxCLK
× 60% t
ETxCLK
× 35% t
ETxCLK
× 65% ns
t
ETXCLKOV
ETxCLK Rising Edge to Tx Output Valid (Data Out Valid) 20 20 ns
t
ETXCLKOH
ETxCLK Rising Edge to Tx Output Invalid (Data Out Hold) 0 0 ns
1
MII outputs synchronous to ETxCLK are ETxD3–0.
Figure 33. 10/100 Ethernet MAC Controller Timing: MII Transmit Signal
Table 45. 10/100 Ethernet MAC Controller Timing: RMII Receive Signal
V
DDEXT
1.8V Nominal
V
DDEXT
2.5 V/3.3V Nominal
Parameter
1
MinMax MinMax Unit
Timing Requirements
t
EREFCLKF
REF_CLK Frequency (f
SCLK
= SCLK Frequency) None 50 + 1% None 50 + 1% MHz
t
EREFCLKW
EREF_CLK Width (t
EREFCLK
= EREFCLK Period) t
EREFCLK
× 40% t
EREFCLK
× 60% t
EREFCLK
× 35% t
EREFCLK
× 65% ns
t
EREFCLKIS
Rx Input Valid to RMII REF_CLK Rising Edge (Data In
Setup)
44ns
t
EREFCLKIH
RMII REF_CLK Rising Edge to Rx Input Invalid (Data In
Hold)
22ns
1
RMII inputs synchronous to RMII REF_CLK are ERxD1–0, RMII CRS_DV, and ERxER.
Figure 34. 10/100 Ethernet MAC Controller Timing: RMII Receive Signal
tETXCLKOH
ETxD3–0
ETxEN
MIITxCLK
tETXCLK
tETXCLKOV
tETXCLKW
tREFCLKIS tREFCLKIH
ERxD1–0
ERxDV
ERxER
RMII_REF_CLK
tREFCLKW
tREFCLK
ADSP-BF512/BF514/BF514F16/BF516/BF518/BF518F16
Rev. D | Page 49 of 68 | April 2014
Table 46. 10/100 Ethernet MAC Controller Timing: RMII Transmit Signal
Parameter
1
Min Max Unit
Switching Characteristics
t
EREFCLKOV
RMII REF_CLK Rising Edge to Tx Output Valid (Data Out Valid) 8.1 ns
t
EREFCLKOH
RMII REF_CLK Rising Edge to Tx Output Invalid (Data Out Hold) 2 ns
1
RMII outputs synchronous to RMII REF_CLK are ETxD1–0.
Figure 35. 10/100 Ethernet MAC Controller Timing: RMII Transmit Signal
tREFCLKOV
tREFCLKOH
RMII_REF_CLK
ETxD1–0
ETxEN
tREFCLK
Rev. D | Page 50 of 68 | April 2014
ADSP-BF512/BF514/BF514F16/BF516/BF518/BF518F16
Table 47. 10/100 Ethernet MAC Controller Timing: MII/RMII Asynchronous Signal
Parameter Min Max Unit
Timing Requirements
t
ECOLH
COL Pulse Width High
1
t
ETxCLK
× 1.5
t
ERxCLK
× 1.5
ns
ns
t
ECOLL
COL Pulse Width Low
1
t
ETxCLK
× 1.5
t
ERxCLK
× 1.5
ns
ns
t
ECRSH
CRS Pulse Width High
2
t
ETxCLK
× 1.5 ns
t
ECRSL
CRS Pulse Width Low
2
t
ETxCLK
× 1.5 ns
1
MII/RMII asynchronous signals are COL, CRS. These signals are applicable in both MII and RMII modes. The asynchronous COL input is synchronized separately to both
the ETxCLK and the ERxCLK, and must have a minimum pulse width high or low at least 1.5 times the period of the slower of the two clocks.
2
The asynchronous CRS input is synchronized to the ETxCLK, and must have a minimum pulse width high or low at least 1.5 times the period of ETxCLK.
Figure 36. 10/100 Ethernet MAC Controller Timing: Asynchronous Signal
Table 48. 10/100 Ethernet MAC Controller Timing: MII Station Management
Parameter
1
Min Max Unit
Timing Requirements
t
MDIOS
MDIO Input Valid to MDC Rising Edge (Setup) 11.5 ns
t
MDCIH
MDC Rising Edge to MDIO Input Invalid (Hold) 0 ns
Switching Characteristics
t
MDCOV
MDC Falling Edge to MDIO Output Valid 25 ns
t
MDCOH
MDC Falling Edge to MDIO Output Invalid (Hold) –1.25 ns
1
MDC/MDIO is a 2-wire serial bidirectional port for controlling one or more external PHYs. MDC is an output clock whose minimum period is programmable as a multiple
of the system clock SCLK. MDIO is a bidirectional data line.
Figure 37. 10/100 Ethernet MAC Controller Timing: MII Station Management
MIICRS, COL
tECRSH
tECOLH
tECRSL
tECOLL
MDIO (INPUT)
MDIO (OUTPUT)
MDC (OUTPUT)
tMDIOS
tMDCOH
tMDCIH
tMDCOV
ADSP-BF512/BF514/BF514F16/BF516/BF518/BF518F16
Rev. D | Page 51 of 68 | April 2014
JTAG Test And Emulation Port Timing
Table 49 and Figure 38 describe JTAG port operations.
Table 49. JTAG Port Timing
Parameter Min Max Unit
Timing Requirements
t
TCK
TCK Period 20 ns
t
STAP
TDI, TMS Setup Before TCK High 4 ns
t
HTAP
TDI, TMS Hold After TCK High 4 ns
t
SSYS1
System Inputs Setup Before TCK High 4 ns
t
HSYS1
System Inputs Hold After TCK High 5 ns
t
TRSTW
TRST Pulse Width
2
(measured in TCK cycles) 4 TCK
Switching Characteristics
t
DTDO
TDO Delay from TCK Low 10 ns
t
DSYS3
System Outputs Delay After TCK Low 0 13 ns
1
System Inputs = DATA15–0, SCL, SDA, TFS0, TSCLK0, RSCLK0, RFS0, DR0PRI, DR0SEC, PF15–0, PG15–0, PH7–0, MDIO, TD1, TMS, RESET, NMI, BMODE2–0.
2
50 MHz Maximum.
3
System Outputs = DATA15–0, ADDR19–1, ABE1–0, ARE, AWE, AMS1–0, SRAS, SCAS, SWE, SCKE, CLKOUT, SA10, SMS, SCL, SDA, TSCLK0, TFS0, RFS0, RSCLK0,
DT0PRI, DT0SEC, PF15–0, PG15–0, PH7–0, MDC, MDIO.
Figure 38. JTAG Port Timing
TCK
TMS
TDI
TDO
SYSTEM
INPUTS
SYSTEM
OUTPUTS
tTCK
tSTAP tHTAP
tDTDO
tSSYS tHSYS
tDSYS
Rev. D | Page 52 of 68 | April 2014
ADSP-BF512/BF514/BF514F16/BF516/BF518/BF518F16
OUTPUT DRIVE CURRENTS
Figure 39 through Figure 53 show typical current-voltage char-
acteristics for the output drivers of the ADSP-BF51xF
processors.
The curves represent the current drive capability of the output
drivers. See Table 8 on Page 19 for information about which
driver type corresponds to a particular ball.
Figure 39. Driver Type A Current (3.3V V
DDEXT
/V
DDMEM
)
Figure 40. Driver Type A Current (2.5V V
DDEXT
/V
DDMEM
)
Figure 41. Driver Type A Current (1.8V V
DDEXT
/V
DDMEM
)
0
SOURCE CURRENT (mA)
SOURCE VOLTAGE (V)
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
200
120
80
–200
–120
–40
VOL
VOH
VDDEXT = 3.6V @ – 40
°
C
VDDEXT = 3.3V @ 25
°
C
–80
–160
40
160
VDDEXT = 3.0V @ 105
°
C
0
SOURCE CURRENT (mA)
SOURCE VOLTAGE (V)
0 0.5 1.0 1.5 2.0 2.5
160
120
40
–160
–120
–40
VOL
VOH
VDDEXT = 2.75V @ – 40
°
C
VDDEXT = 2.5V @ 25
°
C
80
–80
VDDEXT = 2.25V @ 105
°
C
0
SOURCE CURRENT (mA)
SOURCE VOLTAGE (V)
0 0.5 1.0 1.5
80
60
40
–80
–60
–20
VOL
VOH
VDDEXT = 1.9V @ – 40
°
C
VDDEXT = 1.8V @ 25
°
C
–40
20
VDDEXT = 1.7V @ 105
°
C
Figure 42. Driver Type B Current (3.3V V
DDEXT
/V
DDMEM
)
Figure 43. Driver Type B Current (2.5V V
DDEXT
/V
DDMEM
)
Figure 44. Driver Type B Current (1.8V V
DDEXT
/V
DDMEM
)
0
SOURCE CURRENT (mA)
SOURCE VOLTAGE (V)
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
240
120
80
–240
–120
–40
VOL
VOH
VDDEXT = 3.6V @ – 40
°
C
VDDEXT = 3.3V @ 25
°
C
–80
–200
40
160 VDDEXT = 3.0V @ 105
°
C
–160
200
0
SOURCE CURRENT (mA)
SOURCE VOLTAGE (V)
0 0.5 1.0 1.5 2.0 2.5
160
120
40
–200
–160
–40
VOL
VOH
VDDEXT = 2.75V @ – 40
°
C
VDDEXT = 2.5V @ 25
°
C
80
–80
VDDEXT = 2.25V @ 105
°
C
–120
0
SOURCE CURRENT (mA)
SOURCE VOLTAGE (V)
00.5 1.0 1.5
80
60
40
–100
–60
–20
VOL
VOH
VDDEXT = 1.9V @ – 40
°
C
VDDEXT = 1.8V @ 25
°
C
–40
20
VDDEXT = 1.7V @ 105
°
C
–80
ADSP-BF512/BF514/BF514F16/BF516/BF518/BF518F16
Rev. D | Page 53 of 68 | April 2014
Figure 45. Driver Type C Current (3.3V V
DDEXT
/V
DDMEM
)
Figure 46. Drive Type C Current (2.5V V
DDEXT
/V
DDMEM
)
Figure 47. Driver Type C Current (1.8V V
DDEXT
/V
DDMEM
)
0
SOURCE CURRENT (mA)
SOURCE VOLTAGE (V)
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
100
60
40
–100
–60
–20
VOL
VOH
VDDEXT = 3.6V @ – 40
°
C
VDDEXT = 3.3V @ 25
°
C
–40
–80
20
80
VDDEXT = 3.0V @ 105
°
C
0
SOURCE CURRENT (mA)
SOURCE VOLTAGE (V)
0 0.5 1.0 1.5 2.0 2.5
80
60
20
–80
–60
–20
VOL
VOH
VDDEXT = 2.75V @ – 40
°
C
VDDEXT = 2.5V @ 25
°
C
40
–40
VDDEXT = 2.25V @ 105
°
C
0
SOURCE CURRENT (mA)
SOURCE VOLTAGE (V)
0 0.5 1.0 1.5
40
30
20
–40
–30
–10
VOL
VOH
VDDEXT = 1.9V @ – 40
°
C
VDDEXT = 1.8V @ 25
°
C
–20
10
VDDEXT = 1.7V @ 105
°
C
Figure 48. Driver Type D Current (3.3V V
DDEXT
/V
DDMEM
)
Figure 49. Driver Type D Current (2.5V V
DDEXT
/V
DDMEM
)
Figure 50. Driver Type D Current (1.8V V
DDEXT
/V
DDMEM
)
0
SOURCE CURRENT (mA)
SOURCE VOLTAGE (V)
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
160
120
80
–160
–40
VOL
VOH
VDDEXT = 3.6V @ – 40
°
C
VDDEXT = 3.3V @ 25
°
C
–80
–120
40
VDDEXT = 3.0V @ 105
°
C
0
SOURCE CURRENT (mA)
SOURCE VOLTAGE (V)
0 0.5 1.0 1.5 2.0 2.5
120
100
40
–120
–100
–40
VOL
VOH
VDDEXT = 2.75V @ – 40
°
C
VDDEXT = 2.5V @ 25
°
C
80
–60
VDDEXT = 2.25V @ 105
°
C
–80
–20
20
60
0
SOURCE CURRENT (mA)
SOURCE VOLTAGE (V)
0 0.5 1.0 1.5 2
60
40
–60
–20
VOL
VOH
VDDEXT = 1.9V @ – 40
°
C
VDDEXT = 1.8V @ 25
°
C
–40
20
VDDEXT = 1.7V @ 105
°
C
Rev. D | Page 54 of 68 | April 2014
ADSP-BF512/BF514/BF514F16/BF516/BF518/BF518F16
TEST CONDITIONS
All timing parameters appearing in this data sheet were mea-
sured under the conditions described in this section. Figure 54
shows the measurement point for ac measurements (except out-
put enable/disable). The measurement point V
MEAS
is V
DDEXT
/2
or V
DDMEM
/2 for V
DDEXT
/V
DDMEM
(nominal) = 1.8 V/2.5 V/3.3 V.
Output Enable Time Measurement
Output signals are considered to be enabled when they have
made a transition from a high impedance state to the point
when they start driving.
The output enable time t
ENA
is the interval from the point when
a reference signal reaches a high or low voltage level to the point
when the output starts driving as shown on the right side of
Figure 55.
The time t
ENA_MEASURED
is the interval from when the reference
signal switches to when the output voltage reaches V
TRIP
(high)
or V
TRIP
(low). For V
DDEXT
(nominal) = 1.8 V, V
TRIP
(high) is
0.95 V, and V
TRIP
(low) is 0.85 V. For V
DDEXT
(nominal) = 2.5 V,
V
TRIP
(high) is 1.3 V and V
TRIP
(low) is 1.2 V. For V
DDEXT
(nomi-
nal) = 3.3 V, V
TRIP
(high) is 1.7 V, and V
TRIP
(low) is 1.6 V. Time
t
TRIP
is the interval from when the output starts driving to when
the output reaches the V
TRIP
(high) or V
TRIP
(low) trip voltage.
Time t
ENA
is calculated as shown in the equation:
If multiple signals (such as the data bus) are enabled, the mea-
surement value is that of the first signal to start driving.
Figure 51. Driver Type E Current (3.3V V
DDEXT
/V
DDMEM
)
Figure 52. Driver Type E Current (2.5V V
DDEXT
/V
DDMEM
)
Figure 53. Driver Type E Current (1.8V V
DDEXT
/V
DDMEM
)
0
SOURCE CURRENT (mA)
SOURCE VOLTAGE (V)
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
60
30
20
–60
–30
–10
VOL
VDDEXT = 3.6V @ – 40
°
C
VDDEXT = 3.3V @ 25
°
C
–20
–40
10
40 VDDEXT = 3.0V @ 105
°
C
50
–50
3.0 3.5
0
SOURCE CURRENT (mA)
SOURCE VOLTAGE (V)
0 0.5 1.0 1.5 2.0 2.5
40
30
10
–40
–30
–10
VOL
VDDEXT = 2.75V @ – 40
°
C
VDDEXT = 2.5V @ 25
°
C
20
–20
VDDEXT = 2.25V @ 105
°
C
3.5
0
SOURCE CURRENT (mA)
SOURCE VOLTAGE (V)
0 0.5 1.0 1.5
20
15
10
–20
–15
–5
VOL
VDDEXT = 1.9V @ – 40
°
C
VDDEXT = 1.8V @ 25
°
C
–10
5
VDDEXT = 1.7V @ 105
°
C
3.02.52.0
Figure 54. Voltage Reference Levels for AC
Measurements (Except Output Enable/Disable)
Figure 55. Output Enable/Disable
INPUT
OR
OUTPUT
V
MEAS
V
MEAS
REFERENCE
SIGNAL
tDIS
OUTPUT STARTS DRIVING
VOH (MEASURED)
-
ΔV
VOL (MEASURED) + ΔV
tDIS_MEASURED
VOH
(MEASURED)
VOL
(MEASURED)
VTRIP(HIGH)
VOH(MEASURED
)
VOL(MEASURED)
HIGH IMPEDANCE STATE
OUTPUT STOPS DRIVING
tENA
tDECAY
tENA_MEASURED
tTRIP
VTRIP(LOW)
tENA tENA_MEASURED tTRIP
–=
ADSP-BF512/BF514/BF514F16/BF516/BF518/BF518F16
Rev. D | Page 55 of 68 | April 2014
Output Disable Time Measurement
Output signals are considered to be disabled when they stop
driving, go into a high impedance state, and start to decay from
their output high or low voltage. The output disable time t
DIS
is
the difference between t
DIS_MEASURED
and t
DECAY
as shown on the
left side of Figure 55.
The time for the voltage on the bus to decay by V is dependent
on the capacitive load C
L
and the load current I
L
. This decay
time can be approximated by the equation:
The time t
DECAY
is calculated with test loads C
L
and I
L
and with
V equal to 0.25 V for V
DDEXT
/V
DDMEM
(nominal) = 2.5 V/3.3 V
and 0.15 V for V
DDEXT
/
VDDMEM
(nominal) = 1.8 V.
The time t
DIS_MEASURED
is the interval from when the reference
signal switches to when the output voltage decays V from the
measured output high or output low voltage.
Example System Hold Time Calculation
To determine the data output hold time in a particular system,
first calculate t
DECAY
using the equation given above. Choose V
to be the difference between the ADSP-BF51x processor’s out-
put voltage and the input threshold for the device requiring the
hold time. C
L
is the total bus capacitance (per data line), and I
L
is
the total leakage or three-state current (per data line). The hold
time is t
DECAY
plus the various output disable times as specified
in the Timing Specifications on Page 29 (for example t
DSDAT
for
an SDRAM write cycle as shown in SDRAM Interface Timing
on Page 33).
Capacitive Loading
Output delays and holds are based on standard capacitive loads
of an average of 6 pF on all balls (see Figure 56). V
LOAD
is equal
to (V
DDEXT
/V
DDMEM
)/2. The graphs of Figure 57 through
Figure 68 show how output rise time varies with capacitance.
The delay and hold specifications given should be derated by a
factor derived from these figures. The graphs in these figures
may not be linear outside the ranges shown.
tDIS tDIS_MEASURED tDECAY
–=
tDECAY CLVIL
=
Figure 56. Equivalent Device Loading for AC Measurements
(Includes All Fixtures)
Figure 57. Driver Type A Typical Rise and Fall Times (10%–90%) vs.
Load Capacitance (1.8V V
DDEXT
/V
DDMEM
)
T1
ZO = 50:(impedance)
TD = 4.04 ± 1.18 ns
2pF
TESTER PIN ELECTRONICS
50:
0.5pF
70:
400:
45:
4pF
NOTES:
THE WORST CASE TRANSMISSION LINE DELAY IS SHOWN AND CAN BE USED
FOR THE OUTPUT TIMING ANALYSIS TO REFLECT THE TRANSMISSION LINE
EFFECT AND MUST BE CONSIDERED. THE TRANSMISSION LINE (TD) IS FOR
LOAD ONLY AND DOES NOT AFFECT THE DATA SHEET TIMING SPECIFICATIONS.
ANALOG DEVICES RECOMMENDS USING THE IBIS MODEL TIMING FOR A GIVEN
SYSTEM REQUIREMENT. IF NECESSARY, A SYSTEM MAY INCORPORATE
EXTERNAL DRIVERS TO COMPENSATE FOR ANY TIMING DIFFERENCES.
V
LOAD
DUT
OUTPUT
50:
6
RISE AND FALL TIME (ns)
LOAD CAPACITANCE (pF)
0 50 100 150 250
12
10
0
2
4
8
200
tRISE
tFALL
tRISE = 1.8V @ 25
°
C
tFALL = 1.8V @ 25
°
C
Rev. D | Page 56 of 68 | April 2014
ADSP-BF512/BF514/BF514F16/BF516/BF518/BF518F16
Figure 58. Driver Type A Typical Rise and Fall Times (10%–90%) vs.
Load Capacitance (2.5V V
DDEXT
/V
DDMEM
)
Figure 59. Driver Type A Typical Rise and Fall Times (10%–90%) vs.
Load Capacitance (3.3V V
DDEXT
/V
DDMEM
)
Figure 60. Driver Type B Typical Rise and Fall Times (10%–90%) vs.
Load Capacitance (1.8V V
DDEXT
/V
DDMEM
)
4
RISE AND FALL TIME (ns)
LOAD CAPACITANCE (pF)
0 50 100 150 250
8
6
0
1
2
5
200
tRISE
tFALL
3
7
tRISE = 2.5V @ 25
°
C
tFALL = 2.5V @ 25
°
C
3
RISE AND FALL TIME (ns)
LOAD CAPACITANCE (pF)
0 50 100 150 250
6
5
0
1
2
4
200
tRISE
tFALL
tRISE = 3.3V @ 25
°
C
tFALL = 3.3V @ 25
°
C
4
RISE AND FALL TIME (ns)
LOAD CAPACITANCE (pF)
0 50 100 150 250
9
7
0
1
3
6
200
tRISE
tFALL
tRISE = 1.8V @ 25
°
C
tFALL = 1.8V @ 25
°
C
2
5
8
Figure 61. Driver Type B Typical Rise and Fall Times (10%–90%) vs.
Load Capacitance (2.5V V
DDEXT
/V
DDMEM
)
Figure 62. Driver Type B Typical Rise and Fall Times (10%–90%) vs.
Load Capacitance (3.3V V
DDEXT
/V
DDMEM
)
Figure 63. Driver Type C Typical Rise and Fall Times (10%–90%) vs.
Load Capacitance (1.8V V
DDEXT
/V
DDMEM
)
4
RISE AND FALL TIME (ns)
LOAD CAPACITANCE (pF)
0 50 100 150 250
7
6
0
1
2
5
200
tRISE
tFALL
3
tRISE = 2.5V @ 25
°
C
tFALL = 2.5V @ 25
°
C
3
RISE AND FALL TIME (ns)
LOAD CAPACITANCE (pF)
0 50 100 150 250
6
5
0
1
2
4
200
tRISE
tFALL
tRISE = 3.3V @ 25
°
C
tFALL = 3.3V @ 25
°
C
15
RISE AND FALL TIME (ns)
LOAD CAPACITANCE (pF)
0 50 100 150 250
25
20
0
5
10
200
tRISE
tFALL
tRISE = 1.8V @ 25
°
C
tFALL = 1.8V @ 25
°
C
ADSP-BF512/BF514/BF514F16/BF516/BF518/BF518F16
Rev. D | Page 57 of 68 | April 2014
Figure 64. Driver Type C Typical Rise and Fall Times (10%–90%) vs.
Load Capacitance (2.5V V
DDEXT
/V
DDMEM
)
Figure 65. Driver Type C Typical Rise and Fall Times (10%–90%) vs.
Load Capacitance (3.3V V
DDEXT
/V
DDMEM
)
Figure 66. Driver Type D Typical Rise and Fall Times (10%–90%) vs.
Load Capacitance (1.8V V
DDEXT
/V
DDMEM
)
8
RISE AND FALL TIME (ns)
LOAD CAPACITANCE (pF)
0 50 100 150 250
16
12
0
2
4
10
200
t
RISE
t
FALL
6
14
t
RISE
= 2.5V @ 25
°
C
t
FALL
= 2.5V @ 25
°
C
6
RISE AND FALL TIME (ns)
LOAD CAPACITANCE (pF)
0 50 100 150 250
14
12
0
2
4
8
200
tRISE
tFALL
tRISE = 3.3V @ 25
°
C
tFALL = 3.3V @ 25
°
C
10
6
RISE AND FALL TIME (ns)
LOAD CAPACITANCE (pF)
0 50 100 150 250
14
10
0
2
4
8
200
tRISE
tFALL
tRISE = 1.8V @ 25
°
C
tFALL = 1.8V @ 25
°
C
12
Figure 67. Driver Type D Typical Rise and Fall Times (10%–90%) vs.
Load Capacitance (2.5V V
DDEXT
/V
DDMEM
)
Figure 68. Driver Type D Typical Rise and Fall Times (10%–90%) vs.
Load Capacitance (3.3V V
DDEXT
/V
DDMEM
)
4
RISE AND FALL TIME (ns)
LOAD CAPACITANCE (pF)
0 50 100 150 250
10
6
0
1
2
5
200
tRISE
tFALL
3
7
tRISE = 2.5V @ 25
°
C
tFALL = 2.5V @ 25
°
C
8
9
3
RISE AND FALL TIME (ns)
LOAD CAPACITANCE (pF)
0 50 100 150 250
8
5
0
1
2
4
200
t
RISE
t
FALL
t
RISE
= 3.3V @ 25
°
C
t
FALL
= 3.3V @ 25
°
C
6
7
Rev. D | Page 58 of 68 | April 2014
ADSP-BF512/BF514/BF514F16/BF516/BF518/BF518F16
THERMAL CHARACTERISTICS
To determine the junction temperature on the application
printed circuit board use:
where:
T
J
= Junction temperature (°C)
T
CASE
= Case temperature (°C) measured by customer at top
center of package.
Ψ
JT
= From Table 51
P
D
= Power dissipation (see Total Power Dissipation on Page 25
for the method to calculate P
D
)
Values of θ
JA
are provided for package comparison and printed
circuit board design considerations.
JA
can be used for a first
order approximation of T
J
by the equation:
where:
T
A
= Ambient temperature (°C)
Values of θ
JC
are provided for package comparison and printed
circuit board design considerations when an external heat sink
is required.
Values of θ
JB
are provided for package comparison and printed
circuit board design considerations.
In Table 51, airflow measurements comply with JEDEC stan-
dards JESD51-2 and JESD51-6, and the junction-to-board
measurement complies with JESD51-8. The junction-to-case
measurement complies with MIL-STD-883 (Method 1012.1).
All measurements use a 2S2P JEDEC test board.
The LQFP_EP package requires thermal trace squares and ther-
mal vias to an embedded ground plane in the PCB. The paddle
must be connected to ground for proper operation to data sheet
specifications. Refer to JEDEC standard JESD51-5 for more
information.
TJTCASE JT PD
+=
TJTAJA PD
+=
Table 50. Thermal Characteristics for SQ-176-2 Package
Parameter Condition Typical Unit
θ
JA
0 Linear m/s Airflow 17.4 °C/W
θ
JMA
1 Linear m/s Airflow 14.8 °C/W
θ
JMA
2 Linear m/s Airflow 14.0 °C/W
θ
JC
Not Applicable 7.8 °C/W
Ψ
JT
0 Linear m/s Airflow 0.28 °C/W
Ψ
JT
1 Linear m/s Airflow 0.39 °C/W
Ψ
JT
2 Linear m/s Airflow 0.48 °C/W
Table 51. Thermal Characteristics for BC-168-1 Package
Parameter Condition Typical Unit
θ
JA
0 Linear m/s Airflow 30.5 °C/W
θ
JMA
1 Linear m/s Airflow 27.6 °C/W
θ
JMA
2 Linear m/s Airflow 26.3 °C/W
θ
JC
Not Applicable 11.1 °C/W
Ψ
JT
0 Linear m/s Airflow 0.20 °C/W
Ψ
JT
1 Linear m/s Airflow 0.35 °C/W
Ψ
JT
2 Linear m/s Airflow 0.45 °C/W
ADSP-BF512/BF514/BF514F16/BF516/BF518/BF518F16
Rev. D | Page 59 of 68 | April 2014
176-LEAD LQFP_EP LEAD ASSIGNMENT
Table 52 lists the LQFP_EP leads by lead number. Table 53 on Page 60 lists the LQFP_EP by signal mnemonic.
Table 52. 176-Lead LQFP_EP Pin Assignment (Numerical by Lead Number)
Lead No. Signal Lead No. Signal Lead No. Signal Lead No. Signal
1 GND 45 GND 89 GND 133 GND
2 GND 46 GND 90 GND 134 GND
3 PF9 47 PG1 91 A12 135 PG
4 PF8 48 PG0 92 A11 136 V
DDEXT
5PF749V
DDEXT
93 A10 137 GND
6PF650TDO94A9138V
DDINT
7V
DDEXT
51 EMU 95 V
DDMEM
139 GND
8V
PPOTP
52 TDI 96 A8 140 RTXO
9V
DDOTP
53 TCK 97 A7 141 RTXI
10 PF5 54 TRST 98 V
DDINT
142 V
DDRTC
11 PF4 55 TMS 99 GND 143 CLKIN
12 PF3 56 D15 100 V
DDINT
144 XTAL
13 PF2 57 D14 101 A6 145 V
DDEXT
14 V
DDINT
58 D13 102 A5 146 RESET
15 GND 59 V
DDMEM
103 A4 147 NMI
16 V
DDFLASH
60 D12 104 V
DDMEM
148 V
DDEXT
17 V
DDFLASH
61 D11 105 A3 149 GND
18 PF1 62 D10 106 A2 150 CLKBUF
19 PF0 63 V
DDINT
107 A1 151 GND
20 PG15 64 D9 108 ABE1152 V
DDINT
21 PG14 65 D8 109 ABE0153 PH7
22 GND 66 D7 110 SA10 154 PH6
23 V
DDINT
67 GND 111 GND 155 PH5
24 V
DDEXT
68 V
DDMEM
112 V
DDMEM
156 PH4
25 PG13 69 D6 113 SWE 157 GND
26 PG12 70 D5 114 SCAS 158 V
DDEXT
27 PG11 71 D4 115 SRAS 159 PH3
28 PG10 72 D3 116 V
DDINT
160 PH2
29 V
DDFLASH
73 D2 117 GND 161 PH1
30 V
DDINT
74 D1 118 SMS 162 PH0
31 PG9 75 V
DDMEM
119 SCKE 163 GND
32 PG8 76 D0 120 AMS1164 V
DDINT
33 PG7 77 A19 121 ARE 165 PF15
34 PG6 78 A18 122 AWE 166 PF14
35 V
DDEXT
79 V
DDINT
123 AMS0167 PF13
36 PG5 80 A17 124 V
DDMEM
168 PF12
37 PG4 81 A16 125 CLKOUT 169 GND
38 PG3 82 V
DDMEM
126 V
DDFLASH
170 V
DDEXT
39 PG2 83 GND 127 NC
1
171 PF11
40 BMODE2 84 A15 128 V
DDEXT
172 SDA
41 BMODE1 85 A14 129 V
DDEXT
173 SCL
42 BMODE0 86 A13 130 EXT_WAKE 174 PF10
43 GND 87 GND 131 GND 175 GND
44 GND 88 GND 132 GND 176 GND
GND 177
*
* Pin no. 177 is the GND supply (see Figure 70) for the processor; this pad must be robustly connected to GND.
1
This pin must not be connected.
Rev. D | Page 60 of 68 | April 2014
ADSP-BF512/BF514/BF514F16/BF516/BF518/BF518F16
Table 53. 176-Lead LQFP_EP Pin Assignment (Alphabetical by Signal Mnemonic)
Lead No. Signal Lead No. Signal Lead No. Signal Lead No. Signal
107 A1 58 D13 5 PF7 113 SWE
106 A2 57 D14 4 PF8 53 TCK
105 A3 56 D15 3 PF9 52 TDI
103 A4 51 EMU 174 PF10 50 TDO
102 A5 130 EXT_WAKE 171 PF11 55 TMS
101 A6 1 GND 168 PF12 54 TRST
97 A7 2 GND 167 PF13 7 V
DDEXT
96 A8 15 GND 166 PF14 24 V
DDEXT
94 A9 22 GND 165 PF15 35 V
DDEXT
93 A10 43 GND 135 PG 49 V
DDEXT
92 A11 44 GND 48 PG0 128 V
DDEXT
91 A12 45 GND 47 PG1 129 V
DDEXT
86 A13 46 GND 39 PG2 136 V
DDEXT
85 A14 67 GND 38 PG3 145 V
DDEXT
84 A15 83 GND 37 PG4 148 V
DDEXT
81 A16 87 GND 36 PG5 158 V
DDEXT
80 A17 88 GND 34 PG6 170 V
DDEXT
78 A18 89 GND 33 PG7 16 V
DDFLASH
77 A19 90 GND 32 PG8 17 V
DDFLASH
109 ABE099GND31PG929V
DDFLASH
108 ABE1 111 GND 28 PG10 126 V
DDFLASH
123 AMS0131GND27PG1114V
DDINT
120 AMS1132GND26PG1223V
DDINT
121 ARE 133 GND 25 PG13 30 V
DDINT
122 AWE 134 GND 21 PG14 63 V
DDINT
42 BMODE0 137 GND 20 PG15 79 V
DDINT
41 BMODE1 139 GND 162 PH0 98 V
DDINT
40 BMODE2 149 GND 161 PH1 100 V
DDINT
150 CLKBUF 151 GND 160 PH2 116 V
DDINT
143 CLKIN 157 GND 159 PH3 138 V
DDINT
125 CLKOUT 163 GND 156 PH4 152 V
DDINT
76 D0 169 GND 155 PH5 164 V
DDINT
74 D1 175 GND 154 PH6 59 V
DDMEM
73 D2 176 GND 153 PH7 68 V
DDMEM
72 D3 117 GND 146 RESET 75 V
DDMEM
71 D4 127 NC
1
141 RTXI 82 V
DDMEM
70 D5 147 NMI 140 RTXO 95 V
DDMEM
69 D6 19 PF0 110 SA10 104 V
DDMEM
66 D7 18 PF1 114 SCAS 112 V
DDMEM
65 D8 13 PF2 119 SCKE 124 V
DDMEM
64 D9 12 PF3 173 SCL 9 V
DDOTP
62 D10 11 PF4 172 SDA 142 V
DDRTC
61 D11 10 PF5 118 SMS 8V
PPOTP
60 D12 6 PF6 115 SRAS 144 XTAL
GND 177
*
* Pin no. 177 is the GND supply (see Figure 70) for the processor; this pad must be robustly connected to GND.
1
This pin must not be connected.
ADSP-BF512/BF514/BF514F16/BF516/BF518/BF518F16
Rev. D | Page 61 of 68 | April 2014
Figure 69 shows the top view of the LQFP_EP lead configura-
tion. Figure 70 shows the bottom view of the LQFP_EP lead
configuration.
Figure 69. 176-Lead LQFP_EP Lead Configuration (Top View)
PIN 1
PIN 44
PIN 132
PIN 89
PIN 176 PIN 133
PIN 45 PIN 88
PIN 1 INDICATOR
ADSP-BF51X
176-LEAD LQFP_EP
TOP VIEW
Figure 70. 176-Lead LQFP_EP Lead Configuration (Bottom View)
PIN 132
PIN 89
PIN 1
PIN 44
PIN 133 PIN 176
PIN 88 PIN 45
PIN 1 INDICATOR
ADSP-BF51X
176-LEAD
LQFP_EP
BOTTOM VIEW
GND PAD
(PIN 177)
Rev. D | Page 62 of 68 | April 2014
ADSP-BF512/BF514/BF514F16/BF516/BF518/BF518F16
168-BALL CSP_BGA BALL ASSIGNMENT
Table 54 lists the CSP_BGA by ball number. Table 55 on
Page 63 lists the CSP_BGA balls by signal mnemonic.
Table 54. 168-Ball CSP_BGA Ball Assignment (Numerical by Ball Number)
Ball No. Signal Name Ball No. Signal Name Ball No. Signal Name Ball No. Signal Name Ball No. Signal Name Ball No. Signal Name
A1 GND C1 PF4 E10 V
DDINT
H1 PG12 K6 V
DDMEM
N1 BMODE1
A2 SCL C2 PF7 E12 V
DDMEM
H2 PG13 K7 V
DDMEM
N2 PG1
A3 SDA C3 PF8 E13 ARE H3 PG11 K8 V
DDMEM
N3 TDO
A4 PF13 C4 PF10 E14 AWE H5 V
DDEXT
K9 V
DDMEM
N4 TRST
A5 PF15 C5 V
DDEXT
F1 PF0 H6 GND K10 V
DDMEM
N5 TMS
A6 PH2 C6 V
DDEXT
F2 PF1 H7 GND K12 A8 N6 D13
A7 PH1 C7 PF11 F3 V
DDINT
H8 GND K13 A2 N7 D9
A8 PH5 C8 V
DDEXT
F5 V
DDEXT
H9 GND K14 A1 N8 D5
A9 PH6 C9 V
DDINT
F6 GND H10 V
DDINT
L1 PG5 N9 D1
A10 PH7 C10 V
DDEXT
F7 GND H12 A3 L2 PG3 N10 A18
A11 CLKBUF C11 RTXI F8 GND H13 ABE0L3PG2 N11A16
A12 XTAL C12 RTXO F9 GND H14 SCAS L12 A9 N12 A14
A13 CLKIN C13 PG F10 V
DDINT
J1 PG10 L13 A6 N13 A11
A14 GND C14 NC
1
F12 SMS J2 V
DDFLASH
L14 A4 N14 A7
B1 V
DDOTP
D1 PF3 F13 SCKE J3 PG9 M1 PG4 P1 GND
B2 GND D2 PF5 F14 AMS1J5V
DDMEM
M2 BMODE2 P2 TDI
B3 PF9 D3 VPPOTP G1 PG15 J6 GND M3 BMODE0 P3 TCK
B4 PF12 D12 V
DDFLASH
G2 PG14 J7 GND M4 PG0 P4 D15
B5 PF14 D13 CLKOUT G3 V
DDINT
J8 GND M5 EMU P5 D14
B6 PH0 D14 AMS0G5V
DDEXT
J9 GND M6 D12 P6 D11
B7 PH3 E1 V
DDFLASH
G6 GND J10 V
DDINT
M7 D10 P7 D8
B8 PH4 E2 PF2 G7 GND J12 A15 M8 D2 P8 D7
B9 V
DDEXT
E3 PF6 G8 GND J13 ABE1M9D0 P9D6
B10 RESET E5 V
DDEXT
G9 GND J14 SA10 M10 A17 P10 D4
B11 NMI E6 V
DDEXT
G10 V
DDINT
K1 PG6 M11 A13 P11 D3
B12 V
DDRTC
E7 V
DDINT
G12 SWE K2 PG8 M12 A12 P12 A19
B13 V
DDEXT
E8 V
DDINT
G13 SRAS K3 PG7 M13 A10 P13 GND
B14 EXT_WAKE E9 V
DDINT
G14 GND K5 V
DDMEM
M14 A5 P14 GND
1
This pin must not be connected.
ADSP-BF512/BF514/BF514F16/BF516/BF518/BF518F16
Rev. D | Page 63 of 68 | April 2014
Table 55. 168-Ball CSP_BGA Ball Assignment (Alphabetical by Signal Mnemonic)
Ball No. Signal Name Ball No. Signal Name Ball No. Signal Name Ball No. Signal Name Ball No. Signal Name Ball No. Signal Name
K14 A1 A11 CLKBUF G6 GND C4 PF10 A8 PH5 G5 V
DDEXT
K13 A2 A13 CLKIN G7 GND C7 PF11 A9 PH6 H5 V
DDEXT
H12 A3 D13 CLKOUT G8 GND B4 PF12 A10 PH7 D12 V
DDFLASH
L14 A4 M9 D0 G9 GND A4 PF13 B10 RESET E1 V
DDFLASH
M14 A5 N9 D1 H6 GND B5 PF14 C11 RTXI J2 V
DDFLASH
L13 A6 M8 D2 H7 GND A5 PF15 C12 RTXO C9 V
DDINT
N14 A7 P11 D3 H8 GND C13 PG J14 SA10 E7 V
DDINT
K12 A8 P10 D4 H9 GND M4 PG0 H14 SCAS E8 V
DDINT
L12 A9 N8 D5 J6 GND N2 PG1 F13 SCKE E9 V
DDINT
M13 A10 P9 D6 J7 GND L3 PG2 A2 SCL E10 V
DDINT
N13 A11 P8 D7 J8 GND L2 PG3 A3 SDA F3 V
DDINT
M12 A12 P7 D8 J9 GND M1 PG4 F12 SMS F10 V
DDINT
M11 A13 N7 D9 P1 GND L1 PG5 G13 SRAS G3 V
DDINT
N12 A14 M7 D10 P13 GND K1 PG6 G12 SWE G10 V
DDINT
J12 A15 P6 D11 P14 GND K3 PG7 P3 TCK H10 V
DDINT
N11 A16 M6 D12 G14 GND K2 PG8 P2 TDI J10 V
DDINT
M10 A17 N6 D13 C14 NC
1
J3 PG9 N3 TDO E12 V
DDMEM
N10 A18 P5 D14 B11 NMI J1 PG10 N5 TMS J5 V
DDMEM
P12 A19 P4 D15 F1 PF0 H3 PG11 N4 TRST K5 V
DDMEM
H13 ABE0M5EMU F2 PF1 H1 PG12 B9 V
DDEXT
K6 V
DDMEM
J13 ABE1 B14 EXT_WAKE E2 PF2 H2 PG13 B13 V
DDEXT
K7 V
DDMEM
D14 AMS0A1GND D1PF3 G2PG14 C5V
DDEXT
K8 V
DDMEM
F14 AMS1 A14 GND C1 PF4 G1 PG15 C6 V
DDEXT
K9 V
DDMEM
E13 ARE B2 GND D2 PF5 B6 PH0 C8 V
DDEXT
K10 V
DDMEM
E14 AWE F6 GND E3 PF6 A7 PH1 C10 V
DDEXT
B1 V
DDOTP
M3 BMODE0 F7 GND C2 PF7 A6 PH2 E5 V
DDEXT
B12 V
DDRTC
N1 BMODE1 F8 GND C3 PF8 B7 PH3 E6 V
DDEXT
D3 V
PPOTP
M2 BMODE2 F9 GND B3 PF9 B8 PH4 F5 V
DDEXT
A12 XTAL
1
This pin must not be connected.
Rev. D | Page 64 of 68 | April 2014
ADSP-BF512/BF514/BF514F16/BF516/BF518/BF518F16
Figure 71 shows the top view of the CSP_BGA ball configura-
tion. Figure 72 shows the bottom view of the CSP_BGA
ball configuration.
Figure 71. 168-Ball CSP_BGA Ball Configuration (Top View)
Figure 72. 168-Ball CSP_BGA Ball Configuration (Bottom View)
A1 BALL PAD CORNER
TOP VIEW
A
B
C
D
E
F
G
H
J
K
L
M
N
P
1 2 3 4 5 6 7 8 9 10 11121314
VDDINT
VDDEXT
GND
I/O
KEY
VDDRTC
VDDMEM
VDDFLASH
NC
A1 BALL PAD CORNER
BOTTOM VIEW
A
B
C
D
E
F
G
H
J
K
L
M
N
P
1413121110987654321
VDDINT
VDDEXT
GND
I/O
KEY
VDDRTC
VDDMEM
VDDFLASH
NC
ADSP-BF512/BF514/BF514F16/BF516/BF518/BF518F16
Rev. D | Page 65 of 68 | April 2014
OUTLINE DIMENSIONS
Dimensions in Figure 73 are shown in millimeters.
Figure 73. 176-Lead Low Profile Quad Flat Package [LQFP_EP]
(SQ-176-2)
Dimensions shown in millimeters
COMPLIANT TO JEDEC STANDARDS MS-026-BGA-HD
1.45
1.40
1.35
0.15
0.10
0.05
TOP VIEW
(PINS DOWN)
133
1132
45
44
88
89
176
0.27
0.22
0.17
0.50
BSC
LEAD PITCH
1.60
MAX
26.20
26.00 SQ
25.80 24.10
24.00 SQ
23.90
VIEW A
PIN 1
0.08 MAX
COPLANARITY
VIEW A
ROTATED 90
°
CCW
SEATING
PLANE
12°
7°
0°
0.20
0.15
0.09
0.75
0.60
0.45
1.00 REF
BOTTOM VIEW
(PINS UP)
133
1
132
45
44
88
89
176
EXPOSED
PAD
EXPOSED PAD IS CENTERED ON
THE PACKAGE.
5.80 REF
SQ
NOTE: THE EXPOSED PAD IS REQUIRED TO BE ELECTRICALLY AND
THERMALLY CONNECTED TO GND. IMPLEMENT THIS BY
SOLDERING THE EXPOSED PAD TO A GND PCB LAND THAT IS
THE SAME SIZE AS THE EXPOSED PAD. THE GND PCB LAND
SHOULD BE ROBUSTLY CONNECTED TO THE GND PLANE IN
THE PCB WITH AN ARRAY OF THERMAL VIAS FOR BEST
PERFORMANCE.
Rev. D | Page 66 of 68 | April 2014
ADSP-BF512/BF514/BF514F16/BF516/BF518/BF518F16
SURFACE-MOUNT DESIGN
Table 56 is provided as an aid to PCB design. For industry
standard design recommendations, refer to IPC-7351, Generic
Requirements for Surface Mount Design and Land Pattern
Standard.
Figure 74. 168-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
(BC-168-1)
Dimensions shown in millimeters
0.80
BSC
10.40
BSC SQ
12.10
12.00 SQ
11.90
COMPLIANT TO JEDEC STANDARDS MO-275-GGAB-1.
0.80
REF
0.70
REF
0.36
REF
A
B
C
D
E
F
G
910 81112 7 564231
BOTTOM VIEW
H
J
K
L
M
DETAIL A
TOP VIEW
DETAIL A
COPLANARITY
0.20
0.50
0.45
0.40
BALL DIAMETER
SEATING
PLANE
A1 BALL
CORNER
A1 BALL
CORNER
0.34 NOM
0.29 MIN
1.50
1.40
1.30
1.12
1.06
1.00
14 13
N
P
Table 56. BGA Data for Use with Surface-Mount Design
Package Package Ball Attach Type
Package Solder Mask
Opening Package Ball Pad Size
168-Ball CSP_BGA Solder Mask Defined 0.35 mm diameter 0.48 mm diameter
ADSP-BF512/BF514/BF514F16/BF516/BF518/BF518F16
Rev. D | Page 67 of 68 | April 2014
AUTOMOTIVE PRODUCTS
The ADBF512W and ADBF518 models are available with con-
trolled manufacturing to support the quality and reliability
requirements of automotive applications. Note that these auto-
motive models may have specifications that differ from the
commercial models and designers should review the product
Specifications section of this data sheet carefully. Only the auto-
motive grade products shown in Table 57 are available for use in
automotive applications. Contact your local ADI account repre-
sentative for specific product ordering information and to
obtain the specific Automotive Reliability reports for these
models.
ORDERING GUIDE
Table 57. Automotive Products
Automotive Models
1,2
Temperature
Range
3
Instruction
Rate (Max) Package Description
Package
Option
ADBF512WBBCZ4xx –40ºC to +85ºC 400 MHz 168-Ball CSP_BGA BC-168-1
ADBF518WBBCZ4xx –40ºC to +85ºC 400 MHz 168-Ball CSP_BGA BC-168-1
ADBF512WBSWZ4xx –40ºC to +85ºC 400 MHz 176-Lead LQFP_EP SQ-176-2
ADBF518WBSWZ4xx –40ºC to +85ºC 400 MHz 176-Lead LQFP_EP SQ-176-2
1
Z = RoHS Compliant Part.
2
The use of xx designates silicon revision.
3
Referenced temperature is ambient temperature. The ambient temperature is not a specification. Please see Operating Conditions on Page 22 for junction temperature (T
J
)
specification which is the only temperature specification.
Model
1
Temperature
Range
2
Processor Instruction
Rate (Max)
Flash
Memory Package Description
Package
Option
ADSP-BF512BBCZ-3 –40ºC to +85ºC 300 MHz N/A 168-Ball CSP_BGA BC-168-1
ADSP-BF512BBCZ-4 –40ºC to +85ºC 400 MHz N/A 168-Ball CSP_BGA BC-168-1
ADSP-BF512BSWZ-3 –40ºC to +85ºC 300 MHz N/A 176-Lead LQFP_EP SQ-176-2
ADSP-BF512BSWZ-4 –40ºC to +85ºC 400 MHz N/A 176-Lead LQFP_EP SQ-176-2
ADSP-BF512KBCZ-3 0ºC to +70ºC 300 MHz N/A 168-Ball CSP_BGA BC-168-1
ADSP-BF512KBCZ-4 0ºC to +70ºC 400 MHz N/A 168-Ball CSP_BGA BC-168-1
ADSP-BF512KSWZ-3 0ºC to +70ºC 300 MHz N/A 176-Lead LQFP_EP SQ-176-2
ADSP-BF512KSWZ-4 0ºC to +70ºC 400 MHz N/A 176-Lead LQFP_EP SQ-176-2
ADSP-BF514BBCZ-3 –40ºC to +85ºC 300 MHz N/A 168-Ball CSP_BGA BC-168-1
ADSP-BF514BBCZ-4 –40ºC to +85ºC 400 MHz N/A 168-Ball CSP_BGA BC-168-1
ADSP-BF514BBCZ4F16 –40ºC to +85ºC 400 MHz 16M bit 168-Ball CSP_BGA BC-168-1
ADSP-BF514BSWZ-3 –40ºC to +85ºC 300 MHz N/A 176-Lead LQFP_EP SQ-176-2
ADSP-BF514BSWZ-4 –40ºC to +85ºC 400 MHz N/A 176-Lead LQFP_EP SQ-176-2
ADSP-BF514BSWZ4F16 –40ºC to +85ºC 400 MHz 16M bit 176-Lead LQFP_EP SQ-176-2
ADSP-BF514KBCZ-3 0ºC to +70ºC 300 MHz N/A 168-Ball CSP_BGA BC-168-1
ADSP-BF514KBCZ-4 0ºC to +70ºC 400 MHz N/A 168-Ball CSP_BGA BC-168-1
ADSP-BF514KSWZ-3 0ºC to +70ºC 300 MHz N/A 176-Lead LQFP_EP SQ-176-2
ADSP-BF514KSWZ-4 0ºC to +70ºC 400 MHz N/A 176-Lead LQFP_EP SQ-176-2
ADSP-BF516KSWZ-3 0ºC to +70ºC 300 MHz N/A 176-Lead LQFP_EP SQ-176-2
ADSP-BF516KBCZ-3 0ºC to +70ºC 300 MHz N/A 168-Ball CSP_BGA BC-168-1
ADSP-BF516KSWZ-4 0ºC to +70ºC 400 MHz N/A 176-Lead LQFP_EP SQ-176-2
ADSP-BF516KBCZ-4 0ºC to +70ºC 400 MHz N/A 168-Ball CSP_BGA BC-168-1
Rev. D | Page 68 of 68 | April 2014
ADSP-BF512/BF514/BF514F16/BF516/BF518/BF518F16
©2014 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08574-0-4/14(D)
ADSP-BF516BBCZ-3 –40ºC to +85ºC 300 MHz N/A 168-Ball CSP_BGA BC-168-1
ADSP-BF516BBCZ-4 –40ºC to +85ºC 400 MHz N/A 168-Ball CSP_BGA BC-168-1
ADSP-BF516BSWZ-3 –40ºC to +85ºC 300 MHz N/A 176-Lead LQFP_EP SQ-176-2
ADSP-BF516BSWZ-4 –40ºC to +85ºC 400 MHz N/A 176-Lead LQFP_EP SQ-176-2
ADSP-BF518BBCZ-4 –40ºC to +85ºC 400 MHz N/A 168-Ball CSP_BGA BC-168-1
ADSP-BF518BBCZ4F16 –40ºC to +85ºC 400 MHz 16M bit 168-Ball CSP_BGA BC-168-1
ADSP-BF518BSWZ-4 –40ºC to +85ºC 400 MHz N/A 176-Lead LQFP_EP SQ-176-2
ADSP-BF518BSWZ4F16 –40ºC to +85ºC 400 MHz 16M bit 176-Lead LQFP_EP SQ-176-2
1
Z = RoHS compliant part.
2
Referenced temperature is ambient temperature. The ambient temperature is not a specification. Please see Operating Conditions on Page 22 for junction temperature (T
J
)
specification which is the only temperature specification.
Model
1
Temperature
Range
2
Processor Instruction
Rate (Max)
Flash
Memory Package Description
Package
Option