Advanced v0.3 ProASICPLUSTM APA Family Fe a t ur es an d B e ne f i ts I/O High C apaci t y * Mixed 2.5V/3.3V Support with Individually-Selectable Voltage and Slew Rate * Bidirectional Global I/Os * PCI Compliance with PCI Revision 2.2 Including 3.3V, 64-bit PCI * Boundary-scan Test IEEE Std. 1149.1 (JTAG) Compliant * 150,000 to 1 million System Gates * 36k to 198kbits of Two-Port SRAM * 232 to 712 User I/Os P erf orm a nce * 50 MHz PCI * Internal System Performance up to 350 MHz * External System Performance up to 150 MHz Uni que Cl ock Con dit io ning C ir cui tr y * Two Integrated PLLs (1.5 to 240 MHz Input and Output Ranges) * PLL with Flexible Phase, Multiply/Divide and Delay Capabilities * Internal and/or External Dynamic PLL Configuration * Two LVPECL Differential Pairs for Clock or Data Inputs Low P ower * Low Impedance Flash Switches * Segmented Hierarchical Routing Structure * Small, Efficient, Configurable (Combinatorial or Sequential) Logic Cells S ta ndar d FP GA and AS IC De si gn F low H ig h P er f o r m ance R out ing H i era rc hy * * * * * Flexibility with Choice of Industry-Standard Front-End Tools * Efficient Design Through Front-End Timing and Gate Optimization Ultra Fast Local and Long Line Network High Speed Very Long Line Network High Performance, Low Skew, Splitable Global Network 100% Routability and Utilization IS P S uppo rt * In-System Programming (ISP) with on-board P Rep ro gra m m able Fl as h T ech nol ogy * * * * 0.22 4LM Flash-based CMOS Process Live at Power Up, Single-Chip Solution No Configuration Device Required Retains Programmed Design During Power-Down/ Power-Up Cycles E m bedde d M em or y Net li st Ge ner at or for S RA Ms and FIFO s * Ensures Optimal Usage of Embedded Memory Blocks * Up to 150 MHz Synchronous and Asynchronous Operation of 24 RAM and FIFO Configurations S ecur e Pr og ram m i ng * The Industry's Most Effective Security Key Prevents Read Back of Programming Bit Stream Pr oA S I C PL U S P r o du ct Pr o f i l e Device Maximum System Gates Maximum Registers Embedded RAM Bits Embedded RAM Blocks (256 X 9) PLL Global Networks Maximum Clocks Maximum User I/Os JTAG PCI User I/Os (by Package Pin Count) PQFP 208-pin PBGA 456-pin FBGA 144-pin FBGA 256-pin FBGA 676-pin FBGA 896-pin FBGA 1152-pin D e ce m b e r 2 0 0 1 (c) 2001 Actel Corporation APA150 150,000 6,144 36k 16 2 4 32 232 Yes Yes APA300 300,000 8,192 72k 32 2 4 32 280 Yes Yes APA450 450,000 12,288 108k 48 2 4 48 332 Yes Yes APA600 600,000 21,504 126k 56 2 4 56 472 Yes Yes APA750 750,000 32,768 144k 64 2 4 64 562 Yes Yes APA1000 1,000,000 56,320 198k 88 2 4 88 712 Yes Yes 164 232 106 188 164 280 106 188 164 332 106 188 164 362 164 362 164 362 188 468 468 562 566 712 1 P r o A SI C P L U S A P A F a m ily G en er al D e sc r i p t i on The ProASICPLUS family enhance upon the performance and reputation of Actel's ProASIC 500K family. It combines the advantages of ASICs with the benefits of programmable devices through nonvolatile Flash technology, thus enabling engineers to create high-density systems using existing ASIC or FPGA design flows and tools. In addition, the ProASICPLUS family offers a unique clock conditioning circuits based on two on-board phase lock loops (PLLs). The family offers up to 1 million system gates, supported with up to 198kbits of 2-port SRAM and up to 712 user I/Os, all providing 50MHz PCI performance. The advantages to the designer extend beyond performance. Four levels of routing hierarchy simplify routing, while the use of Flash technology allows all functionality to be available at power up. No external Boot PROM is required to support device programming. While on-board security mechanisms prevent all access to the program information, reprogramming (even in-system) is still easy enough to support future design iterations and field upgrades. The device's architecture mitigates the complexity of ASIC migration at higher user volume, making ProASICPLUS a cost-effective solution for applications in the networking, communications, computing and avionics markets. The ProASICPLUS family achieves its nonvolatility and reprogrammability through an advanced Flash-based 0.22 LVCMOS process with four-layer metal. Standard CMOS design techniques are used to implement logic and control functions, including the PLLs and LVPECL inputs. The result is predictable performance fully compatible with gate arrays. PLUS architecture provides a The proprietary ProASIC granularity comparable to gate arrays. The device core consists of a Sea-of-TilesTM. Each tile can be configured as a flip-flop, latch, or any 3-input/1-output logic function (except a 3-input XOR), by programming the appropriate Flash switches. The combination of fine granularity, flexible routing resources, and abundant Flash switches allow 100% utilization and over 95% routability for highly congested designs. Gates and larger functions are interconnected through a 4-level routing hierarchy. Embedded 2-port SRAM blocks with built-in FIFO/RAM control logic can user-defined depth and width. Users can also select programmed for synchronous or asynchronous operation, as well as parity generations or checking. frequency dividers which allow the incoming clock signal to be divided by a wide range of factors of up to 64. The clock conditioning circuit will also delay or advance the up to 4 ns (in increments of 0.25 ns) relative to the positive edge of the incoming reference clock. The PLL can be configured internally or externally during operation without redesigning or reprograming the part. In addition to the PLL there are two LVPECL differential input pairs to accommodate high speed clock and data inputs. To support customers' needs for more comprehensive, lower cost board-level testing, Actel's ProASICPLUS devices are fully compatible with IEEE Standard 1149.1 for test access port and boundary-scan test architecture. For more details on the Flash FPGA implementation please refer to the ProASICPLUS APA Family data sheet. ProASICPLUS devices are available in a variety of high-performance plastic packages. Those packages, and the performance features discussed above are described in more detail in the following sections of this document: * "Features and Benefits" on page 1 * "ProASICPLUS APA Architecture" on page 4 * "Routing Resources" on page 5 * "Clock Trees" on page 8 * "Input/Output Blocks" on page 9 * "LVPECL Input Pads" on page 9 * "Boundary Scan" on page 10 * "User Security" on page 13 * "Embedded Memory Floorplan" on page 13 * "Design Environment" on page 16 * "Package Thermal Characteristics" on page 18 * "Operating Conditions" on page 19 * In-system programming (TBD) * "DC Electrical Specifications (VDDP = 2.5V)" on page 20 - page 22 * "AC Specifications (3.3V PCI Operation)" on page 23 * "Clock Conditioning Circuit" on page 24 * "Embedded Memory Specifications" on page 34 * "Package Pin Assignments" on page 54 - page 76 The clock conditioning circuitry is unique. Each chip contains two clock conditioning blocks, each with a PLL core, delay lines, phase shifts (90, 180, 270), and clock multipliers/dividers. In short, this is all the circuitry needed to provide bidirectional access to the PLL, and operation up to 240 MHz. The PLL block contains four programmable 2 Advanced v0.3 Pr o A SI C P L U S A PA F a m ily O r d e r i n g I nf o r m a t i o n _ APA1000 1 FG 1152 ES Application (Ambient Temperature Range) Blank = Commercial (0 to +70 C) I = Industrial (-40 to +85 C) PP = Pre-production ES = Engineering Silicon (Room Temperature Only) Package Lead Count Package Type PQ = Plastic Quad Flat Pack FG = FineBall Grid Array PB = Plastic Ball Grid Array Speed Grade Blank = Standard Speed _1 = TBD Part Number APA150 = APA300 = APA450 = APA600 = APA750 = APA1000 = 150,000 Equivalent System Gates 300,000 Equivalent System Gates 450,000 Equivalent System Gates 600,000 Equivalent System Gates 750,000 Equivalent System Gates 1,000,000 Equivalent System Gates Pr od uc t P l a n Speed Grade APA150 Device 208-Pin Plastic Quad Flat Pack (PQFP) 456-Pin Plastic Ball Grid Array (PBGA) 144-Pin Fine Ball Grid Array (FBGA) 256-Pin Fine Ball Grid Array (FBGA) APA300 Device 208-Pin Plastic Quad Flat Pack (PQFP) 456-Pin Plastic Ball Grid Array (PBGA) 144-Pin Fine Ball Grid Array (FBGA) 256-Pin Fine Ball Grid Array (FBGA) APA450 Device 208-Pin Plastic Quad Flat Pack (PQFP) 456-Pin Plastic Ball Grid Array (PBGA) 144-Pin Fine Ball Grid Array (FBGA) 256-Pin Fine Ball Grid Array (FBGA) APA600 Device 208-Pin Plastic Quad Flat Pack (PQFP) 456-Pin Plastic Ball Grid Array (PBGA) 256-Pin Fine Ball Grid Array (FBGA) 676-Pin Fine Ball Grid Array (FBGA) APA750 Device 208-Pin Plastic Quad Flat Pack (PQFP) 456-Pin Fine Ball Grid Array (PBGA) 676-Pin Fine Ball Grid Array (FBGA) 896-Pin Plastic Ball Grid Array (FBGA) APA1000 Device 208-Pin Plastic Quad Flat Pack (PQFP) 456-Pin Plastic Ball Grid Array (PBGA) 896-Pin Plastic Ball Grid Array (FBGA) 1152-Pin Plastic Ball Grid Array (FBGA) Application Std -1* C I P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P Contact your Actel sales representative for product availability. *Speed Grade: -1 = TBD Applications: C = Commercial Availability: P = Planned I = Industrial = Limited Availability - Contact your Actel Sales representative for the latest availability information. Advanced v0.3 3 P r o A SI C P L U S A P A F a m ily P r oA S I C PL U S A P A A r c hi t ec t u r e The proprietary ProASICPLUS architecture provides granularity comparable to gate arrays. Unlike SRAM- based FPGAs, which utilize look-up tables or architectural mapping during design, ProASIC device designs are directly synthesized to gates. That streamlines the design flow, increases design productivity, and eliminates dependencies on vendor-specific design tools. The ProASICPLUS device core (Figure 1) consists of a Sea-of-TilesTM, each of which (Figure 3 on page 5) can be configured as a 3-input logic function (e.g., NAND gate, D-Flip-Flop, etc.) by programming the appropriate Flash switches interconnections (Figure 2 on page 5). Gates and larger functions are connected with the four levels of routing hierarchy. Flash cells are distributed throughout the device to provide nonvolatile, reconfigurable interconnect programming. Flash switches are programmed to connect signal lines to the appropriate logic cell inputs and outputs. Dedicated high-performance lines are connected as needed for fast, low-skew global signal distribution throughout the core. Maximum core utilization is possible for virtually any design. operation, two-port RAM configurations, user defined depth and width, and parity generation or checking. Table 3 on page 13 lists the 24 basic memory configurations. Fl as h S wi t ch PLUS In the ProASIC Flash switch (Figure 2 on page 5), two transistors (the Flash transistor in which programming and erasing is performed, and a second transistor connecting or separating routing elements or configuration signal lines) share the floating gate in which the Flash transistor stores the programming information. Lo gic T il e The logic tile cell (Figure 3 on page 5) has three inputs (any or all of which can be inverted) and one output (which can connect to both ultra fast local and efficient long line routing resources). Any three-input one-output logic function, except a three input XOR, can be configured as one tile. Two multiplexers with feedback paths through the NAND gates allow the tile to be configured as a latch with clear or set, or as a flip-flop with clear or set. Thus the tiles can flexibly map logic and sequential gates of a design. ProASICPLUS devices also contain embedded two-port SRAM blocks with built-in FIFO/RAM control logic. Programming options include synchronous or asynchronous 256x9 Two-Port SRAM or FIFO Block Logic Tile Figure 1 * The ProASICPLUS Device Architecture 4 Advanced v0.3 Pr o A SI C P L U S A PA F a m ily Sel 1 Sel 2 Floating Gate Switch In Word Switch Out Figure 2 * Flash Switch Local Routing In 1 Efficient Long Line Routing In 2 (CLK) In 3 (Reset) Figure 3 * Core Logic Tile Rou ti ng Res our ces ProASICPLUS The routing structure of the devices is designed to provide high performance through a flexible four-level hierarchy of routing resources: ultra fast local resources, efficient long line resources, high speed very long line resources, and high performance global networks. The ultra fast local resources are dedicated lines that allow the output of each tile to connect directly to every input of the eight surrounding tiles (Figure 4 on page 6). The efficient long line resources provide routing for longer distances and higher fanout connections. These resources vary in length (spanning 1, 2, or 4 tiles), run both vertically and horizontally, and cover the entire ProASICPLUS device (Figure 5 on page 6). Each tile can drive signals onto the efficient long line resources, which can, in turn, access every input of every tile. Active buffers are inserted automatically by routing software to limit the loading effects due to distance and fanout. The high speed very long line resources which span the entire device with minimal delay, are used to route very long or very high fanout nets. The routing software automatically inserts active buffers to limit loading effects due to distance and fanout. (Figure 6 on page 7). The high performance global networks are low skew, high fanout nets that are accessible from external pins or from internal logic (Figure 7 on page 8). These nets are typically used to distribute clocks, resets, and other high fanout nets requiring a minimum skew. The global networks are implemented as clock trees, and signals can be introduced at any junction. These can be employed hierarchically, with signals accessing every input on all tiles. Advanced v0.3 5 P r o A SI C P L U S A P A F a m ily L Inputs L L L Ultra Fast Local Lines (connects a tile to the adjacent tile, I/O buffer, or memory block) Output L L L L L Figure 4 * Ultra Fast Local Resources Spans 4 Tile Spans 1 Tile Spans 2 Tiles Logic Tile L L L L L L L L L L L L L L L L L L L L L L L L Spans 1 Tile Spans 2 Tiles Spans 4 Tile Logic Cell L L L L Figure 5 * Efficient Long Line Resources 6 Advanced v0.3 L L Pr o A SI C P L U S A PA F a m ily High Speed Very Long Line Resouces I/O RING I/O RING PAD RING PAD RING PAD RING Figure 6 * High Speed Very Long Line Resources Advanced v0.3 7 P r o A SI C P L U S A P A F a m ily Cl ock Res our ce s PLUS The ProASIC family offers powerful and flexible control of circuit timing through the use of analog circuitry. Each chip has two clock conditioning blocks, each containing a 240 MHz phase lock loop (PLL) core, delay lines, (0, 90, 180, 270), clock multiplier/dividers and all the circuitry needed for the selection and interconnection of inputs to the global network (thus providing bidirectional access to the PLL). This permits the PLL block to drive inputs and/or outputs via the two global lines on each side of the chip (four total lines). This circuitry is discussed in more detail later in the data sheet. C lock T r ees One of the main architectural benefits of ProASICPLUS is the power and delay friendly clock tree (Global Networks). Each device of the ProASICPLUS FPGA family offers 4 global trees. Each of these trees is based on a network of spines and ribs that reach all the tiles in their regions (Figure 7). This flexible clock tree architecture allows users to map up to 56 different internal/external clocks in an A500K270 device (Table 1 on page 9). The flexible use of the ProASICPLUS clock spine allows the designer to cope with several design requirements. Users implementing clock resource intensive applications can easily route external or gated internal clocks using global routing spines. Users can also drastically reduce delay penalties and save buffering resources by mapping critical high-fanout nets to spines. For design hints on using these features, refer to the Efficient Use of ProASIC Clock Trees application note. High Performace Global Network I/O RING PAD RING PAD RING Low Skew Global Networks Global Pads Global Pads Global Spine I/O RING Global Ribs Scope of Spine PAD RING Figure 7 * High Performance Global Network 8 Advanced v0.3 Pr o A SI C P L U S A PA F a m ily Table 1 * Number of Clock Spines APA150 APA300 APA450 APA600 APA750 APA1000 Global Clock Networks (Trees) 4 4 4 4 4 4 Clock Spines/Tree 8 8 12 14 16 22 Total Spines 32 32 48 56 64 88 Top Spine Height 24 32 32 48 64 80 Bottom Spine Height 24 32 32 48 64 80 Tiles in Top Spine 768 1,024 1,024 1,536 2,048 2,560 Tiles in Bottom Spine 768 1,024 1,024 1,536 2,048 2,560 6,144 8,192 12,288 21,504 32,768 56,320 Total Tiles Inpu t/ Out put Blo cks * 3.3V PCI compliant To meet complex system demands, the ProASICPLUS family offers devices with a large number of user I/O pins, up to 712 on the APA1000. If the I/O pad is powered at 3.3V, each I/O can be selectively configured at 2.5V and 3.3V threshold levels. Table 2 shows the available supply voltage configurations (the PLL block uses an independent 2.5V supply). Figure 8 on page 10 illustrates I/O interfaces with other devices. All I/Os include ESD protection circuits. Each I/O has been tested to 2000V to the human body model (per MIL-STD-883, Method 3015) and 200V to the machine model. * Ability to drive LVTTL and LVCMOS levels * Selectable drive strengths * Selectable slew rates * Three-state I/O pads configured as bidirectional buffers have the following features: * Individually selectable 2.5V or 3.3V output signals and threshold levels1 Six or seven standard I/O pads are grouped with a GND pad and either a VDD or VDDP pad. Two reference bias signals ring the chip. One protects the cascaded output drivers while the other creates a virtual VDD supply for the I/O ring. * 3.3V PCI compliant Table 2 * ProASICPLUS Power Supply Voltages * Three-state * Optional pull-up resistor * Selectable drive strengths * Selectable slew rates LV PE C L In put P ads VDDP 2.5V 3.3V Input Tolerance 2.5V 3.3V, 2.5V Output Drive Note: VDD is always 2.5V. 2.5V 3.3V, 2.5V I/O pads are fully configurable to provide the maximum flexibility and speed. Each pad can be configured as an input, an output, a tristate driver, or a bidirectional buffer (Figure 9 on page 10). I/O pads configured as inputs have the following features: * Individually selectable 2.5V or 3.3V threshold levels1 * Optional pull-up resistor I/O pads configured as outputs have the following features: * Individually selectable 2.5V or 3.3V compliant output signals1 1. If pads are configured for 2.5V operation, they are compliant with 2.5V level signals as defined by JEDEC JESD 8-5. If pads are configured for 3.3V operation, they are compliant with the standard as defined by JEDEC JESD 8-A (LVTTL and LVCMOS). In addition to standard I/O pads and power pads, ProASICPLUS devices have a PECL input pad at each end of each of the global MUX lines, along with AVDD and AGND pins to power the PLL block. The PECL input pad cell differs from the standard I/O cell. It is operated from VDD only. Since it is exclusively an input, it requires no output signal, output enable signal or output configuration bits. As a special high-speed differential input, it also requires no pull ups. The PECL pad cell (Figure 10 on page 10) consists of an inbuffer (containing a low voltage differential amplifier, whose power is enabled by the PC<0> and CL<1> signals, and a cascaded buffer), a signal pad (sigpad) and a reference pad (refpad). The PECL pad cell compares voltages on the sigpad and the refpad and send the results to the global mux over the P<0> wire. This high speed, low skew output essentially controls the clock conditioning circuit. Advanced v0.3 9 P r o A SI C P L U S A P A F a m ily Bou ndar y S can PLUS ProASIC devices are compatible with IEEE Standard 1149.1, which defines a set of hardware architecture and mechanisms for cost-effective board-level testing. The basic ProASICPLUS boundary-scan logic circuit is composed of the TAP (test access port), TAP controller, test data registers and instruction register (Figure 11 on page 11). This circuit supports all mandatory IEEE 1149.1 instructions (EXTEST, SAMPLE/PRELOAD and BYPASS), the optional IDCODE instructions and private instructions used for device programming and factory testing. (test data input and output), TMS (test mode selector) and TRST (test reset input). TMS, TDI and TRST are equipped with pull-up resistors to ensure proper operation when no input data is supplied to them. These pins are dedicated for boundary-scan test usage. The TAP controller is a four-bit state machine (16 states) that operates as shown in Figure 12 on page 12. The 1s and 0s represent the values that must be present at TMS at a rising edge of TCK for the given state transition to occur. IR and DR indicate that the instruction register or the data register is operating in that state. Each test section is accessed through the TAP, which has five associated pins: TCK (test clock input), TDI and TDO STDIO PAD Standard I/O Pad Cell Global MUX Driver PC<0:4> P<1,2> P<0> I/O Tile X PC<0:4> P<1,2> P<0> I/O Tile A HC<A> GLOB<A> PAD Standard I/O Pad Cell GLOB<B> PAD Standard I/O Pad Cell PC<0:4> P<1,2> P<0> PC<0:4> P<1,2> P<0> Global MUX Driver PC<0:4> P<1,2> P<0> I/O Tile GA I/O Tile GB I/O Tile B HC<B> GLOB<B> PAD PECLIN GLOB<B> PAD PECLREF PECL Input Pad Cell Figure 8 * ProASICPLUS Global I/O Scheme with Multiplexed Global Pads 3.3V/2.5V Signal Control Pull-up Control Y EN A Pad CORE & GLOBAL MUX CL<1> 3.3V/2.5V Signal Control Drive Strength and Slew Rate Control Figure 9 * I/O Block Schematic Representation 10 SIG PAD P<0> PC<0> inbuffer REF PAD sigpad + ESD protection + clamp refpad + ESD protection + clamp Figure 10 * High Speed Global Pad Cell Block Diagram Advanced v0.3 Pr o A SI C P L U S A PA F a m ily I/O I/O I/O I/O I/O TDI Test Data Registers TAP Controller Instruction Register Device Logic I/O TDO (Optional) TRST I/O TMS I/O TCK I/O Bypass Register I/O I/O I/O I/O I/O Figure 11 * ProASICPLUS JTAG Boundary Scan Test Logic Circuit Advanced v0.3 11 P r o A SI C P L U S A P A F a m ily The TAP controller receives two control inputs (TMS and TCK) and generates control and clock signals for the rest of the test logic architecture. On power up, the TAP controller enters the Test-Logic-Reset state. To guarantee a reset of the controller from any of the possible states, TMS must remain high for five TCK cycles. The optional TRST pin may also be used to asynchronously place the TAP controller in the Test-Logic-Reset state. ProASICPLUS devices support three types of test data registers: bypass, device identification, and boundary scan. The bypass register is selected when no other register needs to be accessed in a device; this speeds up test data transfer to other devices in a test data path. The 32-bit device identification register is a shift register with four fields (LSB, ID number, part number and version). The 1 Test-Logic Reset 0 0 Run-Test/ Idle 1 boundary-scan register observes and controls the state of each I/O pin. Each I/O cell has three boundary-scan register cells, each with a serial-in, serial-out, parallel-in and parallel-out pin. The serial pins are used to serially connect all the boundary-scan register cells in a device into a boundary scan register chain which starts at the TDI pin and ends at the TDO pin. The parallel ports are connected to the internal core logic tile and the input, output and control ports of an I/O buffer to capture and load data into the register to control or observe the logic state of each I/O. Details on the implementation of boundary-scan testing on ProASICPLUS devices can be found in the Actel application note, Using JTAG Boundary-Scan with ProASIC Devices. 1 Select-DRScan 0 Scan 0 Capture-DR 1 Capture-IR 1 0 0 0 Shift-DR 0 0 1 1 0 0 Pause-IR 1 1 Exit2-DR 0 Exit2-IR 1 Update-DR 0 1 Figure 12 * TAP Controller State Diagram 12 Advanced v0.3 1 Exit-IR Pause-DR 0 0 Shift-IR 1 Exit-DR 1 Select-IR- 1 Update-IR 1 0 Pr o A SI C P L U S A PA F a m ily U se r S e c u r it y PLUS The ProASIC devices have read-protect bits that, once programmed, block the entire programmed contents from being read externally. This security key can only be cleared by erasing the entire device. This protects it from being read back and duplicated. Since programmed data is stored in nonvolatile memory cells (which are actually very small capacitors), rather than in the wiring, physical deconstruction cannot be used to compromise data. That approach would be further hampered by the placement of the memory cells, beneath the four metal layers (whose removal could not be accomplished without disturbing the charge in the capacitor). This is the highest security provided in the industry. For more information, request our Design Security in Nonvolatile Flash and Antifuse FPGAs technical report. E m bedde d M em or y Flo orp lan The embedded memory is located across the top of the device (see Figure 1 on page 4) in 256x9 blocks. Depending upon the device, up to 88 blocks are available to support a variety of memory configurations. Each block can be programmed as an independent memory or combined (using dedicated memory routing resources) to form larger, more complex memories. A single memory configuration cannot include blocks from both the top and bottom memory locations. E m bedde d M em or y Con f igu rat i ons PLUS The embedded memory in the ProASIC family provides great configuration flexibility. While other programmable vendors typically use single port memories that can only be transformed into two-port memories by sacrificing half the memory, each ProASIC block is designed and optimized as a two-port memory (1r, 1w). This provides 198k bits of total memory for two-port and single port usage in the APA1000 device. Each memory can be configured as a FIFO or an SRAM, with independent selection of synchronous or asynchronous read and write ports (Table 3). Multiple write ports are not supported. Additional characteristics include programmable flags as well as parity check and generation. Figure 13 on page 14 and Figure 14 on page 15 show the block diagram of the basic SRAM and FIFO blocks. These memories are designed to operate at up to 150 MHz when operated individually. Each block contains a 256 word deep by 9-bit wide (1r, 1w) memory. The memory blocks may be combined in parallel to form wider memories or stacked to form deeper memories (Figure 15 on page 15). This provides optimal bit widths of 9 (1 block), 18, 36, and 72, and optimal depths of 256, 512, 768, and 1024. Refer to the Macro Library Guide for ProASIC FPGA Devices for more information. Figure 16 on page 16 gives an example of optimal memory usage. 10 blocks with 23,040 bits have been used to generate three memories of various widths and depths. Figure 17 on page 16 shows how memory can be doubled up to create extra read ports. In this example, using only 10 of the 88 available blocks of the APA1000 yields an effective 6,912 bits of multiple port memories. The ACTgen software facilitates easily building wider and deeper memories for optimal memory usage. Table 3 * Basic Memory Configurations Type Write Access Read Access Parity Library Cell Name RAM Asynchronous Asynchronous Checked RAM256x9AA RAM Asynchronous Asynchronous Generated RAM256x9AAP RAM Asynchronous Synchronous Transparent Checked RAM256xAST RAM Asynchronous Synchronous Transparent Generated RAM256xASTP RAM Asynchronous Synchronous Pipelined Checked RAM256x9ASR RAM Asynchronous Synchronous Pipelined Generated RAM256x9ASRP RAM Synchronous Asynchronous Checked RAM256x9SA RAM Synchronous Asynchronous Generated RAM256xSAP RAM Synchronous Synchronous Transparent Checked RAM256x9SST RAM Synchronous Synchronous Transparent Generated RAM256x9SSTP RAM Synchronous Synchronous Pipelined Checked RAM256x9SSR RAM Synchronous Synchronous Pipelined Generated RAM256x9SSRP FIFO Asynchronous Asynchronous Checked FIFO256xAA FIFO Asynchronous Asynchronous Generated FIFO256x9AAP Advanced v0.3 13 P r o A SI C P L U S A P A F a m ily Table 3 * Basic Memory Configurations Type Write Access Read Access Parity Library Cell Name FIFO Asynchronous Synchronous Transparent Checked FIFO256xAST FIFO Asynchronous Synchronous Transparent Generated FIFO256x9ASTP FIFO Asynchronous Synchronous Pipelined Checked FIFO256x9ASR FIFO Asynchronous Synchronous Pipelined Generated FIFO256x9ASRP FIFO Synchronous Asynchronous Checked FIFO256x9SA FIFO Synchronous Asynchronous Generated FIFO256xSAP FIFO Synchronous Synchronous Transparent Checked FIFO256x9SST FIFO Synchronous Synchronous Transparent Generated FIFO256x9SSTP FIFO Synchronous Synchronous Pipelined Checked FIFO256x9SSR FIFO Synchronous Synchronous Pipelined Generated FIFO256x9SSRP WDATA <0:8> WADDR <0:7> WRB WBLKB WCLK SRAM (256 X 9) Sync Write & Sync Read Ports RDATA <0:8> RADDR <0:7> WRB RDB RBLKB RCLK WBLKB PARODD WDATA <0:8> WADDR <0:7> WRB WBLKB WCLK Sync Write & Async Read Ports RADDR <0:7> RDB RBLKB WDATA <0:8> WADDR <0:7> WRB WBLKB RPE WPE RDB RBLKB RPE SRAM (256 X 9) Async Write & Sync Read Ports PARODD Figure 13 * Example SRAM Block Diagrams Advanced v0.3 RDATA <0:8> RADDR <0:7> RDB RBLKB RCLK RPE WPE PARODD 14 RADDR <0:7> PARODD RDATA <0:8> SRAM (256 X 9) RDATA <0:8> SRAM (256 X 9) Async Write & Async Read Ports WPE RPE WPE WDATA <0:8> WADDR <0:7> Pr o A SI C P L U S A PA F a m ily WDATA<0:8> LEVEL<0:7> RDATA <0:8> LGDEP<0:2> RDB RPE FULL RBLKB EQTH PARODD WPE FIFO (256 X 9) Sync Write & Async Read Ports RDB EMPTY RBLKB RDATA <0:8> WRB WBLKB WPE FIFO (256 X 9) Sync Write & Sync Read Ports WRB WBLKB WDATA <0:8> LEVEL <0:7> LGDEP<0:2> RPE FULL EMPTY EQTH PARODD GEQTH GEQTH WCLK WCLK RCLK RDATA <0:8> WDATA <0:8> LEVEL <0:7> LGDEP<0:2> WRB WBLKB RDB RBLKB RDATA <0:8> WRB WBLKB WPE FIFO (256 X 9) Async Write & Sync Read Ports WDATA <0:8> LEVEL <0:7> LGDEP<0:2> EMPTY RDB EQTH WPE FIFO (256 X 9) Async Write & Async.Read Ports RPE FULL RPE FULL EMPTY EQTH RBLKB PARODD GEQTH GEQTH PARODD RCLK Figure 14 * Basic FIFO Block Diagrams Word Width 9 Word Depth 256 9 256 9 256 9 256 9 ... 256 9 256 9 256 9 256 9 256 88 blocks Figure 15 * APA1000 Memory Block Architecture Advanced v0.3 15 P r o A SI C P L U S A P A F a m ily Word Width 9 9 Word 256 Depth 256 256 256 9 9 9 256 18 bit x 256 word 1r1w 18 bit x 512 word 1r1w 256 256 9 bit x 1,024 word 1r1w Total Memory Blocks Used = 10 Total Memory Bits = 23,040 Figure 16 * Example Showing Memories with Different Width and Depth Word Width 9 Write Port 9 9 Word Depth 9 Write Port 256 256 Read Ports 9 bit x 256 word, 2r1w Read Ports 9 bit x 512 word, 4r1w Total Memory Blocks Used = 10 Total Memory Bits = 6,912 Figure 17 * Multiport Memory Usage D es i gn E nv i r on m e nt ProASICPLUS devices are supported by Designer (an Actel software package that includes the ASICmaster and MEMORYmaster software previously available in standalone form), as well as third party CAE tools. Unlike some FPGA vendors, no special HDL design techniques are needed when using the standard VHDL or Verilog HDL descriptions. As a result, designers may utilize the technology independent of HDL code for ProASICPLUS devices. This and the ProASICPLUS design flow ensure a seamless transition to an ASIC should production volumes warrant a migration to a gate array or a standard cell product (Figure 18 on page 17). Designer automatically generates memories from the designer's inputs with ACTgen. The design engineer can 16 select the depth and width, usage of parity generation or check, and synchronous or asynchronous functionality of the ports. For a synchronous read port, the designer can choose whether the output is pipelined or transparent. Designer allows any bit width up to 252. However, when an intermediate bit width, such as 16 bits, is chosen, the remaining two bits are not accessible for other memories. Designer also enables optimal memory stacking in 256 word increments. However, any word depth may be combined for up to 22,528 words. Place-and-route is also performed by Actel's Designer software. Available for Solaris(R), HP(R), and Windows NT(R), Designer accepts standard netlists in Verilog, VHDL, and in EDIF 2.0.0 format, performs place and route of the design into the selected device, and provides postlayout delay Advanced v0.3 Pr o A SI C P L U S A PA F a m ily Designer can also generate the BSDL (boundary-scan description language) files required for documenting the IEEE 1149.1 components which can be used by automatic test equipment software. information for back-annotation simulation or static timing analysis. The Designer software also contains very powerful interactive layout capabilities for the experienced user. Designer also incorporates Actel's proprietary macro generator, ACTgen, which provides all the software needed for configuration of the PLL clock conditioning circuit. While the PLL has no placement mobility, ACTgen allows users to use placement and routing floorplan constraints hierarchically in order to more easily and efficiently explore floorplan alternatives. This allows the power of the PLL circuitry to be utilized with minimal top level timing loop iterations. Design Creation/Verification Designer also contains the necessary information for the placing, routing and configuration of the clock conditioning circuit. Once the design is finalized, the programming bitstream is downloaded into the device programmer for ProASIC part programming. ProASICPLUS devices can be programmed with the Silicon Sculptor programmer, also in-system programming is available. For details on ProASICPLUS programming, refer to the programming application note. High-Level Design (Verilog or VHDL) ModelSim Synplify Tool Synthesis Library Forward Constraints Simulation Library Structural Netlist Design Implementation P&R User Constraints Designer (P&R Tool) ACTgen Backannotation Programming Programming Data SDF Timing Timing and Simulation File Timing Silicon Sculptor Libraries Simulation Library ModelSim Timing Analyzer Figure 18 * Design Flow Advanced v0.3 17 P r o A SI C P L U S A P A F a m ily Pa c ka ge T he r m a l C ha r a ct e r i s t i c s The ProASICPLUS family is available in several package types with a range of pin-counts. Actel has selected packages based on high pin count, reliability factors, and superior thermal characteristics. Thermal resistance defines the ability of a package to conduct heat away from the silicon, through the package, to the surrounding air. Junction-to-ambient thermal resistance is measured in degrees Celsius/Watt and is represented as Theta ja (ja). The lower thermal resistance, the more efficiently a package will dissipate heat. A package's maximum allowed power (P) is a function of maximum junction temperature (TJ), maximum ambient operating temperature (TA), and junction-to-ambient thermal resistance ja. Maximum junction temperature is the maximum allowable temperature on the active surface of the IC and is 110 C. P is defined as: TJ - TA P = ---------------- ja ja is a function of the rate (in linear feet per minute - lfpm) of airflow in contact with the package,. When the estimated power consumption exceeds the maximum allowed power, other means of cooling, such as increasing the airflow rate, must be used. Pin Count jc ja Still Air ja 300 ft./min Units Plastic Ball Grid Array (PBGA) 456 3 18 14.5 C/W Fine Ball Grid Array (FBGA) 676 3 18 14.5 C/W Fine Ball Grid Array (FBGA) 896 3 18 14.5 C/W Fine Ball Grid Array (FBGA) 1152 3 18 14.5 C/W Package Type 18 Advanced v0.3 Pr o A SI C P L U S A PA F a m ily O pe r a t i ng C on d i t i on s Abs ol ut e M axim u m Ra ti ngs Parameter Condition Minimum Maximum Units Supply Voltage (VDD) -0.3 3.0 V Supply Voltage I/O Ring (VDDP) -0.3 4.0 V DC Input Voltage -0.3 VDDP + 0.3 V PCI DC Input Voltage -0.5 VDDP + 0.5 V -10 +10 mA 0 2.5 V DC Input Clamp Current (IIK) VIN < 0 or > VDDP PECL Input Voltage P rog ra m mi ng Lim i t s and Rec om m ende d Ope ra ti ng Cond it io ns Parameter Min. Max. Units Program Retention1 Storage Temperature -55 +150 C N/A Storage Temperature--Programmed -55 +110 C 20 years Note: 1. Available after full qualification and characterization. T em per at ur e M axi mu m s Junction Temperature Programming Cycles1 Program Retention2 Min. Max. Commercial 100 20 years 0C 110C Industrial 100 20 years -40C 110C Product Grade Notes: 1. 500 cycles available after completion of full qualification and characterization. 2. Available after full qualification and characterization. S uppl y Vol t ages Mode VDD VDDP VPP VPN Single Voltage 2.5V 2.5V 2.5V Vpp 16.5 -12V VPN 0V Mixed Voltage 2.5V 3.3V 3.3V Vpp 16.5 -12V VPN 0V Rec om m ende d Op era ti ng Con dit io ns Parameter Symbol Limits VDD & VDDP VDDP VDD TA TJ fCLOCK fRAM 2.3V to 2.7V 3.0V to 3.6V 2.3V to 2.7V 0C to 70C 110C 250 MHz 150 MHz VDD & VDDP VDDP VDD TA TJ fCLOCK fRAM 2.3V to 2.7V 3.0V to 3.6V 2.3V to 2.7V -40C to 85C 110C 250 MHz 150 MHz Commercial DC Supply Voltage (2.5V I/Os) DC Supply Voltage (2.5V, 3.3V I/Os) Operation Ambient Temperature Range Operation Junction Temperature (maximum) Maximum Clock Frequency Maximum RAM Frequency Industrial DC Supply Voltage (2.5V I/Os) DC Supply Voltage (2.5V, 3.3V I/Os) Operation Ambient Temperature Range Operation Junction Temperature (maximum) Maximum Clock Frequency Maximum RAM Frequency Advanced v0.3 19 P r o A SI C P L U S A P A F a m ily DC E le ct ri cal S peci fic at ions ( V D D P = 2. 5V) Symbol Parameter VDDP, VDD Supply Voltage Output High Voltage Conditions Min. 2.3 High Drive (OB25LPH) IOH = -2.0 mA IOH = -4.0 mA IOH = -8.0 mA 2.1 2.0 1.7 Low Drive (OB25LPL) IOH = -1.0 mA IOH = -2.0 mA IOH = -4.0 mA 2.1 2.0 1.7 VOH Typ. Max. Units 2.7 V V Output Low Voltage High Drive (OB25LPH) VOL Low Drive (OB25LPL) IOL = 5.0 mA IOL = 10.0 mA IOL = 15.0 mA 0.2 0.4 0.7 IOL = 2.0 mA IOL = 3.5 mA IOL = 5.0 mA 0.2 0.4 0.7 V VIH Input High Voltage 1.7 VDDP + 0.3 V VIL Input Low Voltage -0.3 .7 V Input Current with pull up -25 -250 A Input Current without pull up -10 10 A IDDQ Quiescent Supply Current VIN = VSS or VDD 10 mA IOZ 3-State Output Leakage Current VOH = VSS or VDD -10 +10 A High Drive (OB25LPH) VIN = VSS -120 Low Drive (OB25LPL) VIN = VSS -100 IIN 5.0 Output Short Circuit Current High IOSH mA Output Short Circuit Current Low IOSL High Drive (OB25LPH) VIN = VDDP 100 Low Drive (OB25LPL) VIN = VDDP 30 mA CI/O I/O Pad Capacitance 10 pF CCLK Clock Input Pad Capacitance 10 pF Notes: All process conditions. Junction Temperature: -40 to +110C. No pull-up resistor. 20 Advanced v0.3 Pr o A SI C P L U S A PA F a m ily DC E le ct ri cal S peci fic at ions ( V D D P = 3. 3V) Symbol Parameter VDDP VDD Supply Voltage Supply Voltage, Logic Array Output High Voltage 3.3V I/O, High Drive (OB33P) Conditions Min. Typ. 3.0 2.3 IOH = -5.0 mA IOH = -10.0 mA 0.9VDDP 2.4 IOH = -2.5 mA IOH = -5.0 mA 0.9VDDP 2.4 IOH = -200A IOH = -10.0 mA IOH = -2.0 mA 2.1 2.0 1.7 IOH = -100A IOH = -1.0 mA IOH = -2.0 mA 2.1 2.0 1.7 Max. Units 3.6 2.7 V V V 3.3V I/O, Low Drive (OB33L) VOH Output High Voltage 2.5V I/O, High Drive (OB25H) V 2.5V I/O, Low Drive (OB25L) Output High Voltage 3.3V I/O, High Drive (OB33P) IOL = 7.5 mA IOL = 12.0 mA 0.1VDDP 0.4 IOL = 4.0 mA IOL = 5.0 mA 0.1VDDP 0.4 IOL = 5.0 mA IOL = 12.0 mA IOL = 16.0 mA 0.2 0.4 0.7 IOL = 2.5 mA IOL = 5.0 mA IOL = 8.0 mA 0.2 0.4 0.7 V 3.3V I/O, Low Drive (OB33L) VOL Output High Voltage 2.5V I/O, High Drive (OB25H) V 2.5V I/O, Low Drive (OB25L) VIH VIL IIN IDDQ IOZ IOSH IOSL Input High Voltage 3.3V LVTTL/CMOS 2.5V Mode Input Low Voltage 3.3V LVTTL/CMOS 2.5V Mode Input Current LVTTL/CMOS LVTTL/CMOS Quiescent Supply Current 3-State Output Leakage Current Output Short Circuit Current High 3.3V High Drive 3.3 Low Drive with pull up without pull up VIN = VSS or VDD VOH = VSS or VDD 2 1.7 VDDP + 0.3 VDDP + 0.3 -0.3 -0.3 0.8 0.7 V -30 -10 -300 10 10 +10 A A mA A 5.0 -10 V -200 -140 mA 2.5V High Drive 2.5 Low Drive Output Short Circuit Current Low 3.3V High Drive 3.3 Low Drive -120 -100 160 150 mA 2.5V High Drive 2.5 Low Drive CI/O I/O Pad Capacitance CCLK Clock Input Pad Capacitance Notes: All process conditions. Junction Temperature: -40 to +110C. No pull-up resistor. Advanced v0.3 160 50 10 10 pF pF 21 P r o A SI C P L U S A P A F a m ily DC S pec if i cat ion s (3.3 V P C I Op era ti on) Symbol Parameter VDD Min. Max. Units Supply Voltage for Core 2.3 2.7 V VDDP Supply Voltage for I/O Ring 3.0 3.6 V VIH Input High Voltage 0.5VDPP VDPP + 0.5 V VIL Input Low Voltage -0.5 0.3VDDP V IIPU Condition 1 Input Pull-up Voltage 0.7VDDP 2 IIL Input Leakage Current 0 < VIN < VCCI -10 VOH Output High Voltage IOUT = -500 A 0.9VDPP VOL Output Low Voltage IOUT = 1500 A 3 CIN Input Pin Capacitance CCLK CLK Pin Capacitance 5 V +10 A V 0.1VDPP V 10 pF 12 pF Notes: 1. This specification should be guaranteed by design. It is the minimum voltage to which pull-up resistors are calculated to pull a floated network. Applications sensitive to static power utilization should assure that the input buffer is conducting minimum current at this input voltage. 2. Input leakage currents include hi-Z output leakage for all bidirectional buffers with tristate outputs. 3. Absolute maximum pin capacitance for a PCI input is 10 pF (except for CLK). 22 Advanced v0.3 Pr o A SI C P L U S A PA F a m ily AC S pec if i cat ion s (3.3 V P C I Op era ti on) Symbol Parameter Condition Min. 0 < VOUT 0.3VCCI 1 Switching Current High IOH(AC) 0.3VCCI VOUT < 0.9VCCI 0.7VCCI < VOUT < VCCI (Test Point) Switching Current Low mA (-17.1 + (VDDP - VOUT)) mA 1, 2 -32VCCI 1 0.6VCCI > VOUT > 0.1VCCI 1 VOUT = 0.18VCC 2 ICL Low Clamp Current -3 < VIN -1 ICH High Clamp Current slewR slewF mA 16VDDP mA (26.7VOUT) mA Equation B on Page 21 0.18VCCI > VOUT > 0 1, 2 (Test Point) Units -12VCCI VOUT = 0.7VCC 2 VCCI > VOUT 0.6VCCI IOL(AC) 1 Max. 38VCCI mA -25 + (VIN + 1)/0.015 mA VCCI + 4 > VIN VCCI + 1 25 + (VIN - VDDP - 1)/0.015 mA Output Rise Slew Rate 0.2VCCI to 0.6VCCI load 3 1 4 V/ns Output Fall Slew Rate 0.6VCCI to 0.2VCCI load 3 1 4 V/ns Notes: 1. Refer to the V/I curves in Figure 16 on Page 21. Switching current characteristics for REQ# and GNT# are permitted to be one half of that specified here; i.e., half size output drivers may be used on these signals. This specification does not apply to CLK and RST#, which are system outputs. "Switching Current High" specifications are not relevant to SERR#, INTA#, INTB#, INTC#, and INTD#, which are open drain outputs. 2. Maximum current requirements must be met as drivers pull beyond the last step voltage. Equations defining these maximums (A and B) are provided with the respective diagrams in Figure 16 on Page 21. The equation defined maxima should be met by design. In order to facilitate component testing, a maximum current test point is defined for each side of the output driver. 3. This parameter is to be interpreted as the cumulative edge rate across the specified range, rather than the instantaneous rate at any point within the transition range. The specified load (diagram below) is optional; i.e., the designer may elect to meet this parameter with an unloaded output per the latest revision of the PCI Local Bus Specification. However, adherence to both maximum and minimum parameters is required (the maximum is no longer simply a guideline). Rise slew rate does not apply to open drain outputs. pin 1/2 in. max. output buffer 10 pF 1k pin output buffer 1k 10 pF Advanced v0.3 23 P r o A SI C P L U S A P A F a m ily T i m i ng C on t r o l an d Ch a r ac t e r i s t i cs Cl ock Con dit io nin g C ir cui t PLUS ProASIC devices provide designers with the most flexible clocking capabilities available. Each side of the chip contains a clock conditioning circuit based upon a 240-MHz phase-locked loop (PLL) core (Figure 19). Two global multiplexed lines extend along each side of the chip to provide bidirectional access to the PLL on that side (neither MUX can be connected to the opposite side's PLL). Each global line has an optional PECL input pads (described below). The global lines may be driven by either the PECL global input pad or the outputs from the PLL block (or both). Each can be driven by a different output from the PLL. Thus global A could be driven from a phase output, multiplied or divided version of the frequency driving global B. See Table 4 on page 25. Each PLL block contains four programmable dividers. The first (n) provides all integer division factors from 1 to 16 inclusive. The second and third (u and v) permit the signal applied to the global network to be further divided by factors of 2, 3 or 4. The fourth divider (m, located in the direct feedback path) is controlled by 6 bits, allowing the incoming clock signal to be multiplied by factors of up to 64. The implementations m/(n*u) and m/(n*v) enable to user to define a wide range of multiplication and division factors. The clock conditioning circuit can advance or delay the clock up to 4ns (in increments of 0.25ns) relative to the AVDD positive edge of the incoming reference clock. The system also allows for the selection of output frequency clock phases of 90, 180, and 270 degrees. A "lock" signal is provided to indicate that the PLL has locked to the incoming signal, and a "standby" signal switches the PLL block off when it is not locked to a signal. That allows pre-selected signals to be passed directly through, at least to the corresponding rib drivers. Prior to the application of signals to the rib drivers, they pass through programmable delay units, one per global network. These units permit the delaying of global signals relative to other signals to assist in the control of input set-up times. Not all possible combinations of input and output mode can be used. The degrees of freedom available in the bidirectional global pad system and in the clock conditioning circuit have been restricted to avoid unnecessary and unwieldy design kit and software work. Table 5 on page 25 shows the allowable clock conditioning circuit connections. The PLL can be configured internally during design (via flash configuration bits set in the programming bitstream) or externally during operation (through a simple dynamically accessible asynchronous interface - a dedicated register file - that allows user signals to initiate parameter changes, such as PLL divide/multiply ratios). See Table 6 on page 26 and Table 7 on page 27. AGND VDD GND External Feedback Signal Output to Global Rib Driver (A) Global Input MUX A OUT PLL Bypass (A) VDD-Off PLL Core Output to Global RIb Driver (B) Input Clock Signal PLL Bypass (B) (Global Input MUX B Out) 8 4 Dynamic Configuration Bits 24 To/From Mask Programmable Delay Flash Configuration Bits Dynamic Configuration Bit Inputs Dynamic Configuration Bit Outputs Stand-by mode of Core Data In Shift Clock Shift Enable Update NVM/Register Mode (Other three bits used for flash configuration) Lock Detect Data Out GND ( Spare 1) GND (Spare 2) Figure 19 * Top-Level View of the PLL Core 24 Advanced v0.3 Pr o A SI C P L U S A PA F a m ily Table 4 * Signals Available for Global Networks Global HC<A> Global HC<B> Output from global mux A. Output from global mux B. fOUT with 0, 90, 180 or 270 degrees shift. fOUT with 0 degrees shift. Time delayed or advanced version of fOUT Time delayed or advanced version of fOUTt Time advanced version of 90, 180 or 270 degrees shifted fOUT Any of the above further divided. Any of the above further divided. Any of the above with a 0.25ns, 0.50ns or Any of the above with a 0.25ns, 0.50ns or 4.00ns delay.* 4.00ns delay.* Note: * This mode is available through the delay feature of the Global Mux driver. Table 5 * Connections and Restrictions to/from the CCC Type PECL inputs Connections * Connect only to (one) HC line (B) per side. Restrictions * Dedicated pads. Not routable to core logic. * Generic IO with access to one HC line (B) per side. IO Pad B * Use as input signal to the CCC Use either the PECL inputs or pad B for a PCI clock. * If the CCC is being used, HC(B) will be driven from one of the 2 available outputs. See section 3 for more information on precise output options. * The input muxes allow the dynamic selection of (Pad B, PB<2>) or (PECL, PB<2>) to the HC(B) global. * If the CCC is being used, HC(A) will be driven from one of the 2 available outputs. See section 3 for more Both can be used as generic IO pads. information on precise output Use these for PCI IRDY and TRDY sigoptions. nals * If the external feedback mode is Pad A1 used for (optional) ex being used, the external feedback The input muxes allow the dynamic signal must be applied to pad A1. selection of (Pad A1, Pad A0) or (Pad * The combination of PCI and external A0, PA<2>) to the HC(A) global.ternal feedback option is not therefore feedback signal for the CCC. accommodated. * Either can connect to one HC line (A) per side. * * IO pads A0 and A1 * * Analog power pads * Two pads will be used for analog power * As with all power pads, these will be supplies to the CCC only dedicated pads. Advanced v0.3 25 P r o A SI C P L U S A P A F a m ily Table 6 * Global Mux "B" Outputs vs. Selector States T5 PC<4:2> T3 PC<2:0> T3 P<1> GMUXBOUT to PLL HC<B> 0 0 0 T0, P<0> (I/O pad B input to I/O tile B) T0, P<0> w/ no delay 0 0 1 T3, P<2> (core "D" output from I/O tile B) T3, P<2> w/ no delay 0 1 0 PECLIN (PECL pad input) PECLIN w/ no delay 0 1 1 T3, P<2> (core "D" output from I/O tile B) T3, P<2> w/ no delay 0 2 0 T0, P<0> (I/O pad B input to I/O tile B) T0, P<0> w/ 250ps delay 0 2 1 T3, P<2> (core "D" output from I/O tile B) T3, P<2> w/ 250ps delay 0 3 0 PECLIN (PECL pad input) PECLIN w/ 250ps delay 0 3 1 T3, P<2> (core "D" output from I/O tile B) T3, P<2> w/ 250ps delay 0 4 0 T0, P<0> (I/O pad B input to I/O tile B) T0, P<0> w/ 500ps delay 0 4 1 T3, P<2> (core "D" output from I/O tile B) T3, P<2> w/ 500ps delay 0 5 0 PECLIN (PECL pad input) PECLIN w/ 500ps delay 0 5 1 T3, P<2> (core "D" output from I/O tile B) T3, P<2> w/ 500ps delay 0 6 0 T0, P<0> (I/O pad B input to I/O tile B) T0, P<0> w/ 4000ps delay 0 6 1 T3, P<2> (core "D" output from I/O tile B) T3, P<2> w/ 4000ps delay 0 7 0 PECLIN (PECL pad input) PECLIN w/ 4000ps delay 0 7 1 T3, P<2> (core "D" output from I/O tile B) T3, P<2> w/ 4000ps delay Not 0 0 0 T0, P<0> (I/O pad B input to I/O tile B) PLLBOUT w/ no delay Not 0 0 1 T3, P<2> (core "D" output from I/O tile B) PLLBOUT w/ no delay Not 0 1 0 PECLIN (PECL pad input) PLLBOUT w/ no delay Not 0 1 1 T3, P<2> (core "D" output from I/O tile B) PLLBOUT w/ no delay Not 0 2 0 T0, P<0> (I/O pad B input to I/O tile B) PLLBOUT w/ 250ps delay Not 0 2 1 T3, P<2> (core "D" output from I/O tile B) PLLBOUT w/ 250ps delay Not 0 3 0 PECLIN (PECL pad input) PLLBOUT w/ 250ps delay Not 0 3 1 T3, P<2> (core "D" output from I/O tile B) PLLBOUT w/ 250ps delay Not 0 4 0 T0, P<0> (I/O pad B input to I/O tile B) PLLBOUT w/ 500ps delay Not 0 4 1 T3, P<2> (core "D" output from I/O tile B) PLLBOUT w/ 500ps delay Not 0 5 0 PECLIN (PECL pad input) PLLBOUT w/ 500ps delay Not 0 5 1 T3, P<2> (core "D" output from I/O tile B) PLLBOUT w/ 500ps delay Not 0 6 0 T0, P<0> (I/O pad B input to I/O tile B) PLLBOUT w/ 4000ps delay Not 0 6 1 T3, P<2> (core "D" output from I/O tile B) PLLBOUT w/ 4000ps delay Not 0 7 0 PECLIN (PECL pad input) PLLBOUT w/ 4000ps delay Not 0 7 1 T3, P<2> (core "D" output from I/O tile B) PLLBOUT w/ 4000ps delay Note: 26 T0 through T8 represent I/O tile row positions, in sequence. T0 is south-most and T8 is north-most. In the UV7x12M3A device T0 is tile row 53 and T8 is tile row 61. Tile row positions in other products are to be determined. Advanced v0.3 Pr o A SI C P L U S A PA F a m ily Table 7 * Global Mux "A" Outputs vs. Selector States T5 PC<1:0> T4 PC<2:0> T4 P<1> GMUXAOUT to PLL HC<A> 0 0 0 T4, P<2> (core "D" output from I/O tile A0) T4, P<2> w/ no delay 0 0 1 T7, P<0> (I/O pad A0 input to I/O tile A0) T7, P<0> w/ no delay 0 1 0 T8, P<0> (I/O pad A1 input to I/O tile A1) T8, P<0> w/ no delay 0 1 1 T7, P<0> (I/O pad A0 input to I/O tile A0) T7, P<0> w/ no delay 0 2 0 T4, P<2> (core "D" output from I/O tile A0) T4, P<2> w/ 250ps delay 0 2 1 T7, P<0> (I/O pad A0 input to I/O tile A0) T7, P<0> w/ 250ps delay 0 3 0 T8, P<0> (I/O pad A1 input to I/O tile A1) T8, P<0> w/ 250ps delay 0 3 1 T7, P<0> (I/O pad A0 input to I/O tile A0) T7, P<0> w/ 250ps delay 0 4 0 T4, P<2> (core "D" output from I/O tile A0) T4, P<2> w/ 500ps delay 0 4 1 T7, P<0> (I/O pad A0 input to I/O tile A0) T7, P<0> w/ 500ps delay 0 5 0 T8, P<0> (I/O pad A1 input to I/O tile A1) T8, P<0> w/ 500ps delay 0 5 1 T7, P<0> (I/O pad A0 input to I/O tile A0) T7, P<0> w/ 500ps delay 0 6 0 T4, P<2> (core "D" output from I/O tile A0) T4, P<2> w/ 4000ps delay 0 6 1 T7, P<0> (I/O pad A0 input to I/O tile A0) T7, P<0> w/ 4000ps delay 0 7 0 T8, P<0> (I/O pad A1 input to I/O tile A1) T8, P<0> w/ 4000ps delay 0 7 1 T7, P<0> (I/O pad A0 input to I/O tile A0) T7, P<0> w/ 4000ps delay Not 0 0 0 T4, P<2> (core "D" output from I/O tile A0) PLLAOUT w/ no delay Not 0 0 1 T7, P<0> (I/O pad A0 input to I/O tile A0) PLLAOUT w/ no delay Not 0 1 0 T8, P<0> (I/O pad A1 input to I/O tile A1) PLLAOUT w/ no delay Not 0 1 1 T7, P<0> (I/O pad A0 input to I/O tile A0) PLLAOUT w/ no delay Not 0 2 0 T4, P<2> (core "D" output from I/O tile A0) PLLAOUT w/ 250ps delay Not 0 2 1 T7, P<0> (I/O pad A0 input to I/O tile A0) PLLAOUT w/ 250ps delay Not 0 3 0 T8, P<0> (I/O pad A1 input to I/O tile A1) PLLAOUT w/ 250ps delay Not 0 3 1 T7, P<0> (I/O pad A0 input to I/O tile A0) PLLAOUT w/ 250ps delay Not 0 4 0 T4, P<2> (core "D" output from I/O tile A0) PLLAOUT w/ 500ps delay Not 0 4 1 T7, P<0> (I/O pad A0 input to I/O tile A0) PLLAOUT w/ 500ps delay Not 0 5 0 T8, P<0> (I/O pad A1 input to I/O tile A1) PLLAOUT w/ 500ps delay Not 0 5 1 T7, P<0> (I/O pad A0 input to I/O tile A0) PLLAOUT w/ 500ps delay Not 0 6 0 T4, P<2> (core "D" output from I/O tile A0) PLLAOUT w/ 4000ps delay Not 0 6 1 T7, P<0> (I/O pad A0 input to I/O tile A0) PLLAOUT w/ 4000ps delay Not 0 7 0 T8, P<0> (I/O pad A1 input to I/O tile A1) PLLAOUT w/ 4000ps delay Not 0 7 1 T7, P<0> (I/O pad A0 input to I/O tile A0) PLLAOUT w/ 4000ps delay Note: T0 through T8 represent I/O tile row positions, in sequence. T0 is south-most and T8 is north-most. In the UV7x12M3A device T0 is tile row 53 and T8 is tile row 61. Tile row positions in other products are to be determined. Logi c T i le T im i ng C har act er is t ics Timing characteristics for ProASICPLUS devices fall into three categories: family dependent, device dependent, and design dependent. The input and out buffer characteristics are common to all ProASICPLUS family members. Internal routing delays are device dependent. Design dependency means that actual delays are not determined until after placement and routing of the user's design are complete. Delay values may then be determined by using the Timer utility or performing simulation with post-layout delays. Advanced v0.3 27 P r o A SI C P L U S A P A F a m ily Cr it ic al Net s and T ypi cal Ne ts Propagation delays are expressed only for typical nets, which are used for initial design performance evaluation. Critical net delays can then be applied to the most timing critical paths. Critical nets are determined by net property assignment prior to placement and routing. Up to 6 percent of the nets in a design may be designated as critical, while 90% of the nets in a design are typical. High S pee d V er y Long Li nes Some nets in the design are very long lines, which are special routing resources that span multiple rows, columns or modules. This increases capacitance and resistance, resulting in longer net delays for macros connected to long tracks. Typically, up to 6 percent of nets in a fully utilized device require very long lines. Very long lines contribute approximately 4 to 8.4ns delay. This additional delay is represented statistically in higher fanout routing delays. T im i ng Der at in g PLUS Since ProASIC devices are manufactured with a CMOS process, device performance will vary with temperature, voltage and process. Minimum timing parameters reflect maximum operating voltage, minimum operating temperature, and optimal process variations. Maximum timing parameters reflect minimum operating voltage, maximum operating temperature, and worst-case process variations (within process specifications). EN A PAD OTBx A 50% PAD VOL 50% VOH EN 50% 50% 50% VCC 50% PAD VOL tDLH tDHL tENZL Figure 20 * Tristate Buffer Delays 28 EN 50% Advanced v0.3 10% 50% PAD GND 50% VOH 50% tENZH 90% Pr o A SI C P L U S A PA F a m ily Table 8 * Tristate Buffer Delays (Worst-Case Commercial Conditions, VDDP = 3.0V, VDD = 2.3V, 35 pF load, TJ = 70C) Max tDLH Max tDHL Max tENZH Max tENZL Units 3.3V, PCI Output Current, High Slew Rate 4.4 4.3 4.4 3.7 ns OTB33PN 3.3V, PCI Output Current, Nominal Slew Rate 4.9 6.1 5.0 5.5 ns OTB33PL 3.3V, PCI Output Current, Low Slew Rate 5.5 7.4 5.5 6.9 ns OTB33LH 3.3V, Low Output Current, High Slew Rate 6.2 6.9 6.2 6.1 ns OTB33LN 3.3V, Low Output Current, Nominal Slew Rate 7.0 9.6 7.0 9.3 ns OTB33LL 3.3V, Low Output Current, Low Slew Rate 7.8 12.6 7.8 12.3 ns OTB25HH 2.5V, High Output Current, High Slew Rate 7.2 3.7 7.2 3.5 ns OTB25HN 2.5V, High Output Current, Nominal Slew Rate 7.5 5.4 7.5 5.1 ns OTB25HL 2.5V, High Output Current, Low Slew Rate 8.5 6.7 8.5 6.4 ns OTB25LH 2.5V, Low Output Current, High Slew Rate 10.8 5.7 10.8 5.4 ns OTB25LN 2.5V, Low Output Current, Nominal Slew Rate 11.5 8.6 11.5 8.4 ns OTB25LL 2.5V, Low Output Current, Low Slew Rate 12.4 11.4 12.4 11.1 ns OTB25LPHH 2.5V, Low Power, High Output Current, High Slew Rate 5.3 5.3 5.3 4.6 ns OTB25LPHN 2.5V, Low Power, High Output Current, Nominal Slew Rate 6.3 8.0 6.2 7.7 ns OTB25LPHL 2.5V, Low Power, High Output Current, Low Slew Rate 7.2 10.2 7.1 9.7 ns OTB25LPLH 2.5V, Low Power, Low Output Current, High Slew Rate 7.7 9.0 7.7 8.1 ns OTB25LPLN 2.5V, Low Power, Low Output Current, Nominal Slew Rate 9.0 13.1 8.9 12.8 ns OTB25LPLL 2.5V, Low Power, Low Output Current, Low Slew Rate 10.2 17.7 10.2 17.4 ns Macro Type Description OTB33PH Notes: 1. tDLH = Data-to-Pad HIGH 2. tDHL = Data-to-Pad LOW 3. tENZH = Enable-to-Pad, Z to HIGH 4. tENZL = Enable-to-Pad, Z to LOW A A PAD OBx 50% PAD VOL 50% VOH 50% 50% tDLH tDHL Figure 21 * Output Buffer Delays Advanced v0.3 29 P r o A SI C P L U S A P A F a m ily Table 9 * Output Buffer Delays (Worst-Case Commercial Conditions, VDDP = 3.0V, VDD = 2.3V, 35 pF load, TJ = 70C) Macro Type Description Max. tDLH Max. tDHL Units OB33PH 3.3V, PCI Output Current, High Slew Rate 4.4 4.3 ns OB33PN 3.3V, PCI Output Current, Nominal Slew Rate 4.9 6.1 ns OB33PL 3.3V, PCI Output Current, Low Slew Rate 5.5 7.4 ns OB33LH 3.3V, Low Output Current, High Slew Rate 6.2 6.9 ns OB33LN 3.3V, Low Output Current, Nominal Slew Rate 7.0 9.6 ns OB33LL 3.3V, Low Output Current, Low Slew Rate 7.8 12.6 ns OB25HH 2.5V, High Output Current, High Slew Rate 7.2 3.7 ns OB25HN 2.5V, High Output Current, Nominal Slew Rate 7.5 5.4 ns OB25HL 2.5V, High Output Current, Low Slew Rate 8.5 6.7 ns OB25LH 2.5V, Low Output Current, High Slew Rate 10.8 5.7 ns OB25LN 2.5V, Low Output Current, Nominal Slew Rate 11.5 8.6 ns OB25LL 2.5V, Low Output Current, Low Slew Rate 12.4 11.4 ns OB25LPHH 2.5V, Low Power, High Output Current, High Slew Rate 5.3 5.3 ns OB25LPHN 2.5V, Low Power, High Output Current, Nominal Slew Rate 6.3 8.0 ns OB25LPHL 2.5V, Low Power, High Output Current, Low Slew Rate 7.2 10.2 ns OB25LPLH 2.5V, Low Power, Low Output Current, High Slew Rate 7.7 9.0 ns OB25LPLN 2.5V, Low Power, Low Output Current, Nominal Slew Rate 9.0 13.1 ns OB25LPLL 2.5V, Low Power, Low Output Current, Low Slew Rate 10.2 17.7 ns Notes: 1. tDLH = Data-to-Pad HIGH 2. tDHL = Data-to-Pad LOW 30 Advanced v0.3 Pr o A SI C P L U S A PA F a m ily VCC PAD Y PAD Y GND IBx 0V 50% 50% VCC 50% 50% tINYH tINYL Figure 22 * Input Buffer Delays Table 10 * Input Buffer Delays (Worst-Case Commercial Conditions, VDDP = 3.0V, VDD = 2.3V, TJ = 70C, fCLOCK = 250 MHz) Max. tINYH Max. tINYL Units 2.5V, CMOS Input Levels, No Pull-up Resistor 2.3 0.7 ns IB25LP 2.5V, CMOS Input Levels, Low Power 2.3 1.5 ns IB33 3.3V, CMOS Input Levels, No Pull-up Resistor 2.0 1.0 ns Max. tINYH Max. tINYL Units Macro Type Description IB25 Notes: 1. tINYH = Input Pad-to-Y HIGH 2. tINYL = Input Pad-to-Y LOW Table 11 * Global Input Buffer Delays (Worst-Case Commercial Conditions, VDDP = 3.0V, VDD = 2.3V, TJ = 70, fCLOCK = 250 MHz) Macro Type Description GL25 2.5V, CMOS Input Levels 2.2 1.7 ns GL25LP 2.5V, CMOS Input Levels 2.4 2.4 ns GL33 3.3V, CMOS Input Levels 4.0 1.2 ns GL25U 2.5V, CMOS Input Levels, with Pull-up Resistor 2.2 1.7 ns GL25LPU 2.5V, CMOS Input Levels, Low Power, with Pull-up Resistor 2.4 2.4 ns GL33U 3.3V, CMOS Input Levels, with Pull-up Resistor 4.0 1.2 ns Table 12 * Predicted Global Routing Delay* (Worst-Case Commercial Conditions, VDDP = 3.0V, VDD = 2.3V, TJ = 70C, fCLOCK = 250 MHz) Parameter Description Max. Units tRCKH Input Low to High (fully loaded row--32 inputs) 1.2 ns tRCKL Input High to Low (fully loaded row--32 inputs) 1.1 ns tRCKH Input Low to High (minimally loaded row--1 input) 0.9 ns tRCKL Input High to Low (minimally loaded row--1 input) 0.9 ns * The timing delay difference between tile locations is less than 15ps. Table 13 * Global Routing Skew (Worst-Case Commercial Conditions, VDDP = 3.0V, VDD = 2.3V, TJ = 70C, fCLOCK = 250 MHz) Parameter Description Max. Units tRCKSWH Maximum Skew Low to High 0.3 ns tRCKSHH Maximum Skew High to Low 0.3 ns Advanced v0.3 31 P r o A SI C P L U S A P A F a m ily A B C A Y 50% 50% B 50% 50% C 50% 50% Y 50% 50% tDCLH tDBLH tDALH 50% 50% 50% 50% tDCHL tDBHL tDAHL Figure 23 * Module Delays Table 14 * Sample Macrocell Library Listing (Worst-Case Commercial Conditions, VDD = 2.3V, TJ = 70 C) Maximum Intrinsic Delay Minimum Setup/Hold Cell Name Description NAND2 2-Input NAND 0.4 ns AND2 2-Input AND 0.4 ns NOR3 3-Input NOR 0.4 ns MUX2L 2-1 Mux with Active Low Select 0.4 ns OA21 2-Input OR into a 2-Input AND 0.4 ns XOR2 2-Input Exclusive OR 0.3 ns LDL Active Low Latch (LH/HL) DFFL Negative Edge-Triggered D-type Flip-Flop (LH/HL) Note: 32 Assumes fanout of two. Advanced v0.3 Units D: 0.3/0.2 tsetup 0.5 thold 0.2 ns CLK-Q: 0.4/0.4 tsetup 0.4 thold 0.2 ns Pr o A SI C P L U S A PA F a m ily Table 15 * Slew Rates measured at C = 10pF, nominal power supplies and 25C Type Trig. Lev. Rising Edge Slew Rate Falling Edge Slew Rate pS V/nS pS V/nS OB33PH 20%-60% 397 3.33 390 -3.38 OB33PN 20%-60% 463 2.85 450 -2.93 OB33PL 20%-60% 567 2.33 527 -2.51 OB33LH 20%-60% 467 2.83 700 -1.89 OB33LN 20%-60% 620 2.13 767 -1.72 OB33LL 20%-60% 813 1.62 1100 -1.20 OB25HH 20%-60% 750 1.33 310 -3.23 OB25HN 20%-60% 850 1.18 390 -2.56 OB25HL 20%-60% 1310 0.76 510 -1.96 OB25LH 20%-60% 793 1.26 430 -2.33 OB25LN 20%-60% 870 1.15 730 -1.37 OB25LL 20%-60% 1287 0.78 1037 -0.96 OB25LPHH 20%-60% 470 2.13 433 -2.31 OB25LPHN 20%-60% 533 1.81 527 -1.90 OB25LPHL 20%-60% 770 1.30 753 -1.33 OB25LPLH 20%-60% 597 1.68 707 -1.42 OB25LPLN 20%-60% 873 1.15 760 -1.32 OB25LPLL 20%-60% 1153 0.87 1563 -0.54 Advanced v0.3 33 P r o A SI C P L U S A P A F a m ily Em b e dd ed M e m or y S pe ci f i ca t i o ns This section discusses ProASICPLUS embedded memory and SRAM and FIFO interface signals, including timing diagrams that show the relationships of signals as they pertain to single embedded memory blocks (Table 16). Table 3 on page 13 shows basic RAM configurations. Simultaneous Read and Write to the same location is not supported. Note: Enclosed Timing Diagrams--SRAM Mode: * Synchronous RAM Read, Access Timed Output Strobe (Synchronous Transparent) * Synchronous RAM Read, Pipeline Mode Outputs (Synchronous Pipelined) * Asynchronous RAM Write * Asynchronous RAM Read, Address Controlled, RDB=0 * Asynchronous RAM Read, RDB Controlled * Synchronous RAM Write Embedded Memory Specifications The difference between synchronous transparent and pipeline modes is the timing of all the output signals from the memory. In transparent mode, the outputs will change within the same clock cycle to reflect the data requested by the currently valid access to the memory. If clock cycles are short (high clock speed), the data requires most of the clock cycle to change to valid values (stable signals). Processing of this data in the same clock cycle is thus nearly impossible. Most designers add registers at all outputs of the memory to push the data processing into the next clock cycle. An entire clock cycle can then be used to process the data. To simplify use of this memory setup, suitable registers have been implemented as part of the memory primitive and are available to the user in the synchronous pipeline mode. In this mode, the output signals will change shortly after the second rising edge following the initiation of the read access. Table 16 * Memory Block SRAM Interface Signals SRAM Signal Bits In/Out WCLKS 1 IN Write clock used on synchronization on write side RCLKS 1 IN Read clock used on synchronization on read side RADDR<0:7> 8 IN Read address RBLKB 1 IN Negative true read block select RDB 1 IN Negative true read pulse WADDR<0:7> 8 IN Write address WBLKB 1 IN Negative true write block select DI<0:8> 9 IN Input data bits <0:8>, <8> will be generated if PARGEN is true WRB 1 IN Negative true write pulse DO<0:8> 9 OUT Output data bits <0:8> RPE 1 OUT Read parity error WPE 1 OUT Write parity error 1 IN PARODD Note: 34 Description Selects odd parity generation/detect when high, even when low Not all signals shown are used in all modes. Advanced v0.3 Pr o A SI C P L U S A PA F a m ily Synchronous RAM Read, Access Timed Output Strobe (Synchronous Transparent) RCLK Cycle Start RB=(RBD+RBLKB) New Valid Address RADDR Old Data Out RDATA New Valid Data Out RPE tRACS tRDCS tRDCH tRACH tOCH tRPCH tCMH tCML tOCA tRPCA tCCYC T J = 0 C t o 11 0 C; V D D = 2 .3V t o 2.7V Symbol txxx Description Min. Max. CCYC Cycle time 7.5 ns CMH Clock high phase 3.0 ns CML Clock low phase 3.0 ns OCA New RDATA access from RCLK 7.5 ns OCH Old RDATA valid from RCLK RACH RADDR hold from RCLK 0.5 ns RACS RADDR setup to RCLK 1.0 ns RDCH RDB hold from RCLK 0.5 ns RDCS RDB setup to RCLK 1.0 ns RPCA New RPE access from RCLK 9.5 ns RPCH Old RPE valid from RCLK 3.0 3.0 Advanced v0.3 Units Notes ns ns 35 P r o A SI C P L U S A P A F a m ily Synchronous RAM Read, Pipeline Mode Outputs (Synchronous Pipelined) RCLK Cycle Start RB=(RDB+RBLKB) RADDR New Valid Address RDATA New Valid Data Out Old Data Out RPE Old RPE Out New RPE Out tRACS tOCA tRACH tRPCH tRDCH tOCH tRDCS tRPCA tCMH tCML tCCYC T J = 0 C t o 11 0 C; V D D = 2 .3V t o 2.7V Symbol txxx Description Min. CCYC Cycle time 7.5 ns CMH Clock high phase 3.0 ns CML Clock low phase 3.0 ns OCA New RDATA access from RCLK 2.0 ns OCH Old RDATA valid from RCLK RACH RADDR hold from RCLK 0.5 ns RACS RADDR setup to RCLK 1.0 ns RDCH RDB hold from RCLK 0.5 ns RDCS RDB setup to RCLK 1.0 ns RPCA New RPE access from RCLK 4.0 ns RPCH Old RPE valid from RCLK 36 Max. .75 1.0 Advanced v0.3 Units ns ns Notes Pr o A SI C P L U S A PA F a m ily Asynchronous RAM Write WADDR WB=(WRB+WBLKB) WDATA WPE tAWRS tAWRH tDWRH tWPDA tWPDH tDWRS tWRML tWRMH tWRCYC T J = 0 C t o 11 0 C; V D D = 2 .3V t o 2.7V Symbol txxx Description Min. Max. AWRH WADDR hold from WB 1.0 ns AWRS WADDR setup to WB 0.5 ns DWRH WDATA hold from WB 1.5 ns DWRS WDATA setup to WB 0.5 ns PARGEN is inactive DWRS WDATA setup to WB 2.5 ns PARGEN is active WPDA WPE access from WDATA 3.0 ns WPE is invalid while WPDH WPE hold from WDATA ns PARGEN is active WRCYC Cycle time 7.5 ns WRMH WB high phase 3.0 ns Inactive WRML WB low phase 3.0 ns Active 1.0 Advanced v0.3 Units Notes 37 P r o A SI C P L U S A P A F a m ily Asynchronous RAM Read, Address Controlled, RDB=0 RADDR RDATA RPE tOAH tRPAH tOAA tRPAA tACYC T J = 0 C t o 11 0 C; V D D = 2 .3V t o 2.7V Symbol txxx Description ACYC 38 Min. Max. Units Read cycle time 7.5 ns OAA New RDATA access from RADDR stable 7.5 ns OAH Old RDATA hold from RADDR stable RPAA New RPE access from RADDR stable RPAH Old RPE hold from RADDR stable 3.0 10.0 ns 3.0 Advanced v0.3 ns ns Notes Pr o A SI C P L U S A PA F a m ily Asynchronous RAM Read, RDB Controlled RB=(RDB+RBLKB) RDATA RPE tORDH tRPRDH tORDA tRPRDA tRDML tRDMH tRDCYC T J = 0 C t o 1 10 C; V D D = 2 .3V t o 2.7 V Symbol txxx Description Min. Max. ORDA New RDATA access from RB 7.5 ORDH Old RDATA valid from RB Notes RDCYC Read cycle time 7.5 ns RDMH RB high phase 3.0 ns Inactive setup to new cycle RDML RB low phase 3.0 ns Active RPRDA New RPE access from RB 9.5 ns RPRDH Old RPE valid from RB ns 3.0 3.0 Advanced v0.3 Units ns ns 39 P r o A SI C P L U S A P A F a m ily Synchronous RAM Write WCLK Cycle Start WRB, WBLKB WADDR, WDATA WPE tWRCH, tWBCH tWRCS, tWBCS tDCS, tWDCS tWPCH tDCH, tWACH tWPCA tCMH tCML tCCYC T J = 0 C t o 11 0 C; V D D = 2 .3V t o 2.7V Symbol txxx Description Min. CCYC Cycle time 7.5 ns CMH Clock high phase 3.0 ns CML Clock low phase 3.0 ns DCH WDATA hold from WCLK 0.5 ns DCS WDATA setup to WCLK 1.0 ns WACH WADDR hold from WCLK 0.5 ns WDCS WADDR setup to WCLK 1.0 ns WPCA New WPE access from WCLK 3.0 ns WPE is invalid while WPCH Old WPE valid from WCLK ns PARGEN is active WRCH, WBCH WRB & WBLKB hold from WCLK 0.5 ns WRCS, WBCS WRB & WBLKB setup to WCLK 1.0 ns Note: 40 Max. Units 0.5 On simultaneous read and write accesses to the same location WDATA is output to RDATA. Advanced v0.3 Notes Pr o A SI C P L U S A PA F a m ily Synchronous Write and Read to the Same Location RCLK RDATA New Data* Last Cycle Data WCLK t WCLKRCLKH t WCLKRCLKS t OCH t OCA * New data is read if WCLK occurs before setup time. The data stored is read if WCLK occurs after hold time. T J = 0 C t o 11 0 C; V D D = 2 .3V t o 2.7V Symbol txxx Description Min. CCYC Cycle time 7.5 ns CMH Clock high phase 3.0 ns CML Clock low phase 3.0 ns WCLKRCLKS WCLK to RCLK setup time - 0.1 ns WCLKRCLKH WCLK to RCLK hold time 7.0 ns OCH Old RDATA valid from RCLK 3.0 ns OCA New RDATA valid from RCLK 7.5 Max. Units ns Notes OCA/OCH displayed for Access Timed Output Notes: 1. This behavior is valid for Access Timed Output and Pipelined Mode Output. Shown are the timings of an access timed output. 2. During synchronous write and synchronous read access to the same location, the new write data will be read out if the active write clock edge occurs before or at the same time as the active read clock edge. The negative setup time insures this behavior for WCLK and RCLK driven by the same design signal. 3. If WCLK changes after the hold time, the data will be read. 4. A setup or hold time violation will result in unknown output data. Advanced v0.3 41 P r o A SI C P L U S A P A F a m ily Asynchronous Write and Synchronous Read to the Same Location RCLK New Data* RDATA Last Cycle Data WB = {WRB + WBLKB} WDATA t WCLKRCLKS t WCLKRCLKH t OCH t OCA t DWRRCLKS t DWRH * New data is read if WB occurs before setup time. The stored data is read if WB occurs after hold time. T J = 0 C t o 11 0 C; V D D = 2 .3V t o 2.7V Symbol txxx Description Min. Max. Units CCYC Cycle time 7.5 ns CMH Clock high phase 3.0 ns CML Clock low phase 3.0 ns WBRCLKS WB to RCLK setup time -0.1 ns WBRCLKH WB to RCLK hold time 7.0 ns OCH Old RDATA valid from RCLK 3.0 ns OCA New RDATA valid from RCLK DWRRCLKS WDATA to RCLK setup time DWRH WDATA to WB hold time 7.5 ns 0 ns 1.5 Notes OCA/OCH displayed for Access Timed Output ns Notes: 1. This behavior is valid for Access Timed Output and Pipelined Mode Output. Shown are the timings of an access timed output. 2. In asynchronous write and synchronous read access to the same location, the new write data will be read out if the active write signal edge occurs before or at the same time as the active read clock edge. If WB changes to low after hold time, the data will be read. 3. A setup or hold time violation will result in unknown output data. 42 Advanced v0.3 Pr o A SI C P L U S A PA F a m ily Asynchronous Write and Read to the Same Location RB, RADDR RDATA NEW OLD NEWER WB = {WRB+WBLKB} t ORDA t RAWRH t ORDH t RAWRS t OWRA t OWRH T J = 0 C t o 11 0 C ; V D D = 2. 3V t o 2 .7V Symbol txxx Description Min. Max. ORDA New RDATA access from RB ORDH Old RDATA valid from RB OWRA New RDATA access from WB OWRH Old RDATA valid from WB RAWRS RB or RADDR from WB 5.0 ns RAWRH RB or RADDR from WB 5.0 ns 7.5 Units Notes ns 3.0 3.0 ns ns 0.5 ns Notes: 1. During an asynchronous read cycle, each write operation (sync. or async.) to the same location will automatically trigger a read operation which updates the read data. 2. Violation or RAWRS will disturb access to the OLD data. 3. Violation of RAWRH will disturb access to the NEWER data. Advanced v0.3 43 P r o A SI C P L U S A P A F a m ily Synchronous Write and Asynchronous Read to the Same Location RB, RADDR RDATA NEW OLD NEWER WCLK t ORDA t RAWCLKH t ORDH t OWRA t OWRH t RAWCLKS T J = 0 C t o 11 0 C; V D D = 2 .3V t o 2.7V Symbol txxx Description Min. Max. ORDA New RDATA access from RB ORDH Old RDATA valid from RB OWRA New RDATA access from WCLK OWRH Old RDATA valid from WCLK RAWCLKS RB or RADDR from WCLK 5.0 ns RAWCLKH RB or RADDR from WCLK 5.0 ns 7.5 Units Notes ns 3.0 3.0 ns ns 0.5 ns Notes: 1. During an asynchronous read cycle, each write operation (sync. or async.) to the same location will automatically trigger a read operation which updates the read data. 2. Violation of RAWCLKS will disturb access to OLD data. 3. Violation of RAWCLKH will disturb access to NEWER data. 44 Advanced v0.3 Pr o A SI C P L U S A PA F a m ily Asynchronous FIFO Full and Empty Transitions The asynchronous FIFO accepts writes and reads while not full or not empty. When the FIFO is full, all writes are inhibited. Conversely, when the FIFO is empty, all reads are inhibited. A problem is created if the FIFO is written during the transition out of full to not full or read during the transition out of empty to not empty. The exact time at which the write (read) operation changes from inhibited to accepted after the read (write) signal which causes the transition from full (empty) to not full (empty) is indeterminate. This indeterminate period starts 1 ns after the RB (WB) transition which deactivates full (not empty) and ends 3 ns after the RB (WB) transition, for slow cycles. For fast cycles, the indeterminate period ends 3 ns (7.5 ns - RDL (WRL)) after the RB (WB) transition, whichever is later. The timing diagram for write is shown in Figure 24 on page 46. The timing diagram for read is shown in Figure 25 on page 46. For basic RAM configurations, see Table 3 on page 13. Enclosed Timing Diagrams--FIFO Mode: * Asynchronous FIFO Read * Asynchronous FIFO Write * Synchronous FIFO Read, Access Timed Output Strobe (Synchronous Transparent) * Synchronous FIFO Read, Pipeline Mode Outputs (Synchronous Pipelined) * Synchronous FIFO Write * FIFO Reset Table 17 * Memory Block FIFO Interface Signals FIFO Signal Bits In/Out Description WCLK 1 IN Write clock used on synchronization on write side RCLK 1 IN Read clock used on synchronization on read side LEVEL <0:7> 8 IN Direct configuration implements static flag logic RBLKB 1 IN Negative true read block select RDB 1 IN Negative true read pulse RESET 1 IN Negative true reset for FIFO pointers WBLKB 1 IN Negative true write block select DI<0:8> 9 IN Input data bits <0:8>, <8> will be generated if PARGEN is true WRB 1 IN Negative true write pulse FULL, EMPTY 2 OUT FIFO flags. FULL prevents write and EMPTY prevents read EQTH, GEQTH 2 OUT EQTH is true when the FIFO holds (LEVEL) words. GEQTH is true when the FIFO holds (LEVEL) words or more DO<0:8> 9 OUT Output data bits <0:8> RPE 1 OUT Read parity error WPE 1 OUT Write parity error LGDEP <0:2> 3 IN Configures DEPTH of the FIFO to 2 (LGDEP+1) PARODD 1 IN Selects odd parity generation/detect when high, even when low Advanced v0.3 45 P r o A SI C P L U S A P A F a m ily FULL RB Write cycle Write inhibited Write accepted 1ns 3ns WB Figure 24 * Write Timing Diagram EMPTY WB Read cycle Read inhibited Read accepted 1ns 3ns RB Figure 25 * Read Timing Diagram 46 Advanced v0.3 Pr o A SI C P L U S A PA F a m ily Asynchronous FIFO Read Cycle Start RB=(RDB+RBLKB) (Empty inhibits read) RDATA RPE WB EMPTY FULL EQTH, GETH tRDWRS tERDH, tFRDH tORDH tERDA, tFRDA tRPRDH tTHRDH tORDA tTHRDA T J = 0C to 110C; V DD = 2.3V to 2.7V Symbol txxx Description Min. Max. Units ERDH, FRDH, THRDH Old EMPTY, FULL, EQTH, & GETH valid hold time from RB 0.5 ns ERDA New EMPTY access from RB 3.01 ns FRDA FULL access from RB 3.01 ns ORDA New RDATA access from RB 7.5 ns ORDH Old RDATA valid from RB 3.0 Read cycle time 7.5 ns RDWRS WB , clearing EMPTY, setup to 3.02 ns 1.0 Empty/full/thresh are invalid from the end of hold until the new access is complete ns RDCYC RB Notes Enabling the read operation ns Inhibiting the read operation RDH RB high phase 3.0 ns Inactive RDL RB low phase 3.0 ns Active RPRDA New RPE access from RB 9.5 RPRDH Old RPE valid from RB ns 4.0 THRDA EQTH or GETH access from RB 4.5 Notes: 1. At fast cycles, ERDA & FRDA = MAX (7.5 ns - RDL), 3.0 ns 2. At fast cycles, RDWRS (for enabling read) = MAX (7.5 ns - WRL), 3.0 ns Advanced v0.3 ns ns 47 P r o A SI C P L U S A P A F a m ily Asynchronous FIFO Write Cycle Start WB=(WRB+WBLKB) WDATA (Full inhibits write) WPE RB FULL EMPTY EQTH, GETH tWRRDS tDWRH tWPDH tWPDA tDWRS tEWRH, tFWRH tEWRA, tFWRA T J = 0C to 110C; V DD = 2.3V to 2.7V Symbol txxx Description Min. DWRH WDATA hold from WB 1.5 ns DWRS WDATA setup to WB 0.5 ns PARGEN is inactive DWRS WDATA setup to WB 2.5 ns PARGEN is active EWRH, FWRH, THWRH Old EMPTY, FULL, EQTH, & GETH valid hold time after WB ns Empty/full/thresh are invalid from the end of hold until the new access is complete EWRA EMPTY access from WB 3.01 ns FWRA New FULL access from WB 3.01 ns THWRA EQTH or GETH access from WB 4.5 ns WPDA WPE access from WDATA 3.0 ns WPDH WPE hold from WDATA WRCYC Cycle time WRRDS RB , clearing FULL, setup to 0.5 1.0 WB high phase ns Notes WPE is invalid while PARGEN is active ns 2 ns Enabling the write operation ns Inactive ns Active 3.0 1.0 3.0 WRL WB low phase 3.0 Notes: 1. At fast cycles, EWRA, FWRA = MAX (7.5 ns - WRL), 3.0 ns 2. At fast cycles, WRRDS (for enabling write) = MAX (7.5 ns - RDL), 3.0 ns 48 Units 7.5 WB WRH Max. Advanced v0.3 Inhibiting the write operation Pr o A SI C P L U S A PA F a m ily Synchronous FIFO Read, Access Timed Output Strobe (Synchronous Transparent) RCLK Cycle Start RDB RDATA Old Data Out New Valid Data Out (Empty Inhibits Read) RPE EMPTY FULL EQTH, GETH tRDCH tECBH, tFCBH tECBA, tFCBA tRDCS tTHCBH tOCH tRPCH tHCBA tOCA T J = 0C to 110C; V DD = 2.3V to 2.7V Symbol txxx Description Min. Max. CCYC Cycle time 7.5 ns CMH Clock high phase 3.0 ns CML Clock low phase 3.0 ns ECBA New EMPTY access from RCLK 3.01 ns FCBA FULL access from RCLK 3.01 ns ECBH, FCBH, THCBH Old EMPTY, FULL, EQTH, & GETH valid hold time from RCLK 1.0 Units ns OCA New RDATA access from RCLK OCH Old RDATA valid from RCLK RDCH RDB hold from RCLK 0.5 ns RDCS RDB setup to RCLK 1.0 ns RPCA New RPE access from RCLK 9.5 ns RPCH Old RPE valid from RCLK 7.5 3.0 4.5 Advanced v0.3 Empty/full/thresh are invalid from the end of hold until the new access is complete ns 3.0 HCBA EQTH or GETH access from RCLK Note: 1. At fast cycles, ECBA & FCBA = MAX (7.5 ns - CMH), 3.0 ns Notes ns ns ns 49 P r o A SI C P L U S A P A F a m ily Synchronous FIFO Read, Pipeline Mode Outputs (Synchronous Pipelined) RCLK Cycle Start RDB RDATA Old Data Out RPE New Valid Data Out Old RPE Out New RPE Out EMPTY FULL EQTH, GETH tECBH, tFCBH tOCA tRDCH tECBA, tFCBA tTHCBH tRDCS tRPCH tOCH tHCBA tRPCA tCMH tCML tCCYC T J = 0C to 110C; V DD = 2.3V to 2.7V Symbol txxx Description Min. CCYC CMH CML ECBA FCBA Cycle time Clock high phase Clock low phase New EMPTY access from RCLK FULL access from RCLK 7.5 3.0 3.0 3.01 3.01 ECBH, FCBH, Old EMPTY, FULL, EQTH, & GETH valid THCBH hold time from RCLK OCA New RDATA access from RCLK OCH Old RDATA valid from RCLK RDCH RDB hold from RCLK RDCS RDB setup to RCLK RPCA New RPE access from RCLK RPCH Old RPE valid from RCLK HCBA EQTH or GETH access from RCLK Note: 1. At fast cycles, ECBA & FCBA = MAX (7.5 ns - CMS), 3.0 ns 50 Max. 2.0 0.75 0.5 1.0 4.0 1.0 Advanced v0.3 Notes ns ns ns ns ns 1.0 4.5 Units ns ns ns ns ns ns ns ns Empty/full/thresh are invalid from the end of hold until the new access is complete Pr o A SI C P L U S A PA F a m ily Synchronous FIFO Write WCLK Cycle Start WRB, WBLKB (Full Inhibits Write) WDATA WPE FULL EMPTY EQTH, GETH tWRCH, tWBCH tECBH, tFCBH tWRCS, tWBCS tECBA, tFCBA tDCS tHCBH tHCBA tWPCH tDCH tWPCA tCMH tCML tCCYC T J = 0C to 110C; V DD = 2.3V to 2.7V Symbol txxx Description Min. CCYC Cycle time CMH Clock high phase CML Clock low phase DCH WDATA hold from WCLK DCS WDATA setup to WCLK FCBA New FULL access from WCLK ECBA EMPTY access from WCLK ECBH, Old EMPTY, FULL, EQTH, & GETH valid FCBH, hold time from WCLK THCBH HCBA EQTH or GETH access from WCLK WPCA New WPE access from WCLK WPCH Old WPE valid from WCLK WRCH, WRB & WBLKB hold from WCLK WBCH WRCS, WRB & WBLKB setup to WCLK WBCS Note: 1. At fast cycles, ECBA & FCBA = MAX (7.5 ns - CMH), 3.0 ns Max. Units 1.0 ns ns ns ns ns ns ns ns 7.5 3.0 3.0 0.5 1.0 3.01 3.01 4.5 3.0 0.5 ns ns ns ns 1.0 ns 0.5 Advanced v0.3 Notes Empty/full/thresh are invalid from the end of hold until the new access is complete WPE is invalid while PARGEN is active 51 P r o A SI C P L U S A P A F a m ily FIFO Reset RESETB Cycle Start WB* WCLK, RCLK Cycle Start FULL EMPTY EQTH, GETH tCBRSS tERSA, tFRSA tCBRSH tTHRSA tWBRSH *WB =t WRB + WBLRB RSL tWBRSS T J = 0 C t o 11 0 C; V D D = 2 .3V t o 2.7V Symbol txxx Description Units Notes CBRSH WCLK or RCLK hold from RESETB 1.5 ns Synchronous mode only CBRSS WCLK or RCLK setup to RESETB 1.5 ns Synchronous mode only ERSA New EMPTY access from RESETB 3.0 ns FRSA FULL access from RESETB 3.0 ns RSL RESETB low phase 7.5 ns THRSA EQTH or GETH access from RESETB 4.5 ns WBRSH WB hold from RESETB 1.5 ns Asynchronous mode only WBRSS WB setup to RESETB 1.5 ns Asynchronous mode only 52 Min. Advanced v0.3 Max. Pr o A SI C P L U S A PA F a m ily Pi n D es c r i pt i on I/O User Input/Output V PN The I/O pin functions as an input, output, tristate, or bidirectional buffer. Input and output signal levels are compatible with standard LVTTL and LVCMOS specifications. Unused I/O pins are configured as inputs with pull-up resistor. NC No Connect To maintain compatibility with other Actel ProASIC products it is recommended that this pin is not connected to the circuitry on the board. GL Programming Supply Pin This pin must be connected to GND during normal operation, or it can remain at -14V in an ISP application. This pin must not float. TMS Test Mode Select The TMS pin controls the use of Boundary-scan circuitry. TCK Test Clock Clock input pin for Boundary-scan. TDI Test Data In Serial input for Boundary-scan. Global Input Pin Low skew input pin for clock or other global signals. Input only. This pin can be configured with a pull-up resistor. TDO GND TRST Ground Test Data Out Serial output for Boundary-scan. Test Reset Input Common ground supply voltage. An optimal Boundary-scan reset pin. V DD RCK Logic Array Power Supply Pin A free running clock is needed during programming if the programmer cannot guarantee that TCK will be uninterrupted. 2.5V supply voltage. V DDP I/O Pad Power Supply Pin 2.5V or 3.3V supply voltage. V PP Running Clock NPECL Programming Supply Pin This pin must be connected to VDDP during normal operation, or it can remain at 16.5V in an ISP application. This pin must not float. PECL Negative Input Provides high speed clock or data signals to the PLL block. PPECL PECL Positive input Provides high speed clock or data signals to the PLL block. AVDD PLL Power Supply AGND PLL Power Ground Advanced v0.3 53 P r o A SI C P L U S A P A F a m ily Pa c ka ge P i n A s si g nm e n t s 208- P in P Q FP 208 1 208-Pin PQFP 54 Advanced v0.3 Pr o A SI C P L U S A PA F a m ily 208- P in P Q FP Pin Number APA750 Function APA1000 Function Pin Number APA750 Function APA1000 Function 1 GND GND 53 VDDP VDDP 2 3 I/O I/O I/O I/O 54 55 I/O I/O I/O I/O 4 I/O I/O 56 I/O I/O 5 6 I/O I/O I/O I/O 57 58 I/O I/O I/O I/O 7 I/O I/O 59 I/O I/O 8 9 I/O I/O I/O I/O 60 61 I/O I/O I/O I/O 10 I/O I/O 62 I/O I/O 11 12 I/O I/O I/O I/O 63 64 I/O I/O I/O I/O 13 I/O I/O 65 GND GND 14 15 I/O I/O I/O I/O 66 67 I/O I/O I/O I/O 16 VDD VDD 68 I/O I/O 17 18 GND I/O GND I/O 69 70 I/O I/O I/O I/O 19 I/O I/O 71 VDD VDD 20 21 I/O I/O I/O I/O 72 73 VDDP I/O VDDP I/O 22 VDDP VDDP 74 I/O I/O 23 I/O I/O 75 I/O I/O 24 25 GL AGND GL AGND 76 77 I/O I/O I/O I/O 26 NPECL NPECL 78 I/O I/O 27 28 AVDD PPECL AVDD PPECL 79 80 I/O I/O I/O I/O 29 GND GND 81 GND GND 30 31 GL I/O GL I/O 82 83 I/O I/O I/O I/O 32 I/O I/O 84 I/O I/O 33 34 I/O I/O I/O I/O 85 86 I/O I/O I/O I/O 35 I/O I/O 87 I/O I/O 36 VDD 37 I/O VDD I/O 88 89 VDD VDDP VDD VDDP 38 I/O I/O 90 I/O I/O 39 40 I/O VDDP I/O 91 I/O I/O VDDP 92 I/O I/O 41 GND GND 93 I/O I/O 42 43 I/O I/O I/O I/O 94 95 I/O I/O I/O I/O 44 I/O I/O 96 I/O I/O 45 46 I/O I/O I/O I/O 97 98 GND I/O GND I/O 47 I/O I/O 99 I/O I/O 48 49 I/O I/O I/O I/O 100 101 I/O TCK I/O TCK 50 I/O I/O 102 TDI TDI 51 52 I/O GND I/O GND 103 104 TMS VDDP TMS Advanced v0.3 VDDP 55 P r o A SI C P L U S A P A F a m ily 208- P in P Q FP (C ont inu ed) Pin Number APA750 Function APA1000 Function Pin Number APA750 Function APA1000 Function 105 GND GND 157 VDDP VDDP 106 107 VPP VPN VPP VPN 158 159 I/O I/O I/O I/O 56 108 TDO TDO 160 I/O I/O 109 110 TRST RCK TRST RCK 161 162 I/O GND I/O GND 111 I/O I/O 163 I/O I/O 112 113 I/O I/O I/O I/O 164 165 I/O I/O I/O I/O 114 I/O I/O 166 I/O I/O 115 116 I/O I/O I/O I/O 167 168 I/O I/O I/O I/O 117 I/O I/O 169 I/O I/O 118 I/O I/O 170 VDDP 119 I/O I/O 171 VDD VDDP VDD 120 I/O I/O 172 I/O I/O 121 122 I/O GND I/O GND 173 174 I/O I/O I/O I/O 123 VDDP VDDP 175 I/O I/O 124 125 I/O I/O I/O I/O 176 177 I/O I/O I/O I/O 126 VDD VDD 178 GND GND 127 I/O I/O 179 I/O I/O 128 129 GL PPECL GL PPECL 180 181 I/O I/O I/O I/O 130 GND GND 182 I/O I/O 131 132 AVDD NPECL AVDD NPECL 183 184 I/O I/O I/O I/O 133 AGND AGND 185 I/O I/O 134 GL GL 186 VDDP 135 I/O I/O 187 VDD VDDP VDD 136 I/O I/O 188 I/O I/O 137 138 I/O VDDP I/O 189 I/O I/O VDDP 190 I/O I/O 139 I/O I/O 191 I/O I/O 140 141 I/O GND I/O GND 192 193 I/O I/O I/O I/O 142 VDD VDD 194 I/O I/O 143 144 I/O I/O I/O I/O 195 196 GND I/O GND I/O 145 I/O I/O 197 I/O I/O 146 147 I/O I/O I/O I/O 198 199 I/O I/O I/O I/O 148 I/O I/O 200 I/O I/O 149 150 I/O I/O I/O I/O 201 202 I/O I/O I/O I/O 151 I/O I/O 203 I/O I/O 152 153 I/O I/O I/O I/O 204 205 I/O I/O I/O I/O 154 I/O I/O 206 I/O I/O 155 156 I/O GND I/O GND 207 208 I/O VDDP VDDP Advanced v0.3 I/O Pr o A SI C P L U S A PA F a m ily P a c ka ge P i n A s si g nm e n t s (Continued) 456- P in P BGA (B ott om Vi ew) 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF Advanced v0.3 57 P r o A SI C P L U S A P A F a m ily 4 5 6 - P in P BG A Pin Number APA750 Function APA1000 Function Pin Number APA750 Function APA1000 Function Pin Number APA750 Function APA1000 Function A1 VDDP VDDP AB10 I/O I/O AD3 VDDP VDDP A2 VDDP VDDP AB11 I/O I/O AD4 I/O I/O A3 I/O I/O AB12 I/O I/O AD5 I/O I/O A4 I/O I/O AB13 I/O I/O AD6 I/O I/O A5 I/O I/O AB14 I/O I/O AD7 I/O I/O A6 I/O I/O AB15 I/O I/O AD8 I/O I/O A7 I/O I/O AB16 I/O I/O AD9 I/O I/O A8 I/O I/O AB17 I/O I/O AD10 I/O I/O A9 I/O I/O AB18 I/O I/O AD11 I/O I/O A10 I/O I/O AB19 I/O I/O AD12 I/O I/O A11 I/O I/O AB20 VDD VDD AD13 I/O I/O A12 I/O I/O AB21 VDD VDD AD14 I/O I/O A13 I/O I/O AB22 VDD VDD AD15 I/O I/O A14 I/O I/O AB23 I/O I/O AD16 I/O I/O A15 I/O I/O AB24 I/O I/O AD17 I/O I/O A16 I/O I/O AB25 I/O I/O AD18 I/O I/O A17 I/O I/O AB26 I/O I/O AD19 I/O I/O A18 I/O I/O AC1 I/O I/O AD20 I/O I/O A19 I/O I/O AC2 I/O I/O AD21 TCK TCK A20 I/O I/O AC3 I/O I/O AD22 VPP VPP A21 I/O I/O AC4 VDDP VDDP AD23 I/O I/O A22 I/O I/O AC5 I/O I/O AD24 VDDP VDDP A23 I/O I/O AC6 I/O I/O AD25 I/O I/O 58 A24 I/O I/O AC7 I/O I/O AD26 I/O I/O A25 VDDP VDDP AC8 I/O I/O AE1 VDDP VDDP A26 VDDP VDDP AC9 I/O I/O AE2 VDDP VDDP AA1 I/O I/O AC10 I/O I/O AE3 I/O I/O AA2 I/O I/O AC11 I/O I/O AE4 I/O I/O AA3 I/O I/O AC12 I/O I/O AE5 I/O I/O AA4 I/O I/O AC13 I/O I/O AE6 I/O I/O AA5 VDD VDD AC14 I/O I/O AE7 I/O I/O AA22 VDD VDD AC15 I/O I/O AE8 I/O I/O AA23 I/O I/O AC16 I/O I/O AE9 I/O I/O AA24 I/O I/O AC17 I/O I/O AE10 I/O I/O AA25 I/O I/O AC18 I/O I/O AE11 I/O I/O AA26 I/O I/O AC19 I/O I/O AE12 I/O I/O AB1 I/O I/O AC20 I/O I/O AE13 I/O I/O AB2 I/O I/O AC21 TMS TMS AE14 I/O I/O AB3 I/O I/O AC22 TDO TDO AE15 I/O I/O AB4 I/O I/O AC23 VDDP VDDP AE16 I/O I/O AB5 VDD VDD AC24 RCK RCK AE17 I/O I/O AB6 VDD VDD AC25 I/O I/O AE18 I/O I/O AB7 VDD VDD AC26 I/O I/O AE19 I/O I/O AB8 I/O I/O AD1 I/O I/O AE20 I/O I/O AB9 I/O I/O AD2 I/O I/O AE21 I/O I/O Advanced v0.3 Pr o A SI C P L U S A PA F a m ily 4 5 6 - P in P BG A Pin Number APA750 Function APA1000 Function Pin Number APA750 Function APA1000 Function Pin Number APA750 Function APA1000 Function AE22 I/O I/O B15 I/O I/O D8 I/O I/O AE23 VPN VPN B16 I/O I/O D9 I/O I/O AE24 TRST TRST B17 I/O I/O D10 I/O I/O AE25 VDDP VDDP B18 I/O I/O D11 I/O I/O AE26 VDDP VDDP B19 I/O I/O D12 I/O I/O AF1 VDDP VDDP B20 I/O I/O D13 I/O I/O AF2 VDDP VDDP B21 I/O I/O D14 I/O I/O AF3 I/O I/O B22 I/O I/O D15 I/O I/O AF4 I/O I/O B23 I/O I/O D16 I/O I/O AF5 I/O I/O B24 I/O I/O D17 I/O I/O AF6 I/O I/O B25 VDDP VDDP D18 I/O I/O AF7 I/O I/O B26 VDDP VDDP D19 I/O I/O AF8 I/O I/O C1 VDDP VDDP D20 I/O I/O AF9 I/O I/O C2 I/O I/O D21 I/O I/O AF10 I/O I/O C3 VDDP VDDP D22 I/O I/O AF11 I/O I/O C4 I/O I/O D23 VDDP VDDP AF12 I/O I/O C5 I/O I/O D24 I/O I/O AF13 I/O I/O C6 I/O I/O D25 I/O I/O AF14 I/O I/O C7 I/O I/O D26 I/O I/O AF15 I/O I/O C8 I/O I/O E1 I/O I/O AF16 I/O I/O C9 I/O I/O E2 I/O I/O AF17 I/O I/O C10 I/O I/O E3 I/O I/O AF18 I/O I/O C11 I/O I/O E4 I/O I/O AF19 I/O I/O C12 I/O I/O E5 VDD VDD AF20 I/O I/O C13 I/O I/O E6 VDD VDD AF21 I/O I/O C14 I/O I/O E7 VDD VDD AF22 I/O I/O C15 I/O I/O E8 VDD VDD AF23 TDI TDI C16 I/O I/O E9 I/O I/O AF24 I/O I/O C17 I/O I/O E10 I/O I/O AF25 VDDP VDDP C18 I/O I/O E11 I/O I/O AF26 VDDP VDDP C19 I/O I/O E12 I/O I/O B1 VDDP VDDP C20 I/O I/O E13 I/O I/O B2 VDDP VDDP C21 I/O I/O E14 I/O I/O B3 I/O I/O C22 I/O I/O E15 I/O I/O B4 I/O I/O C23 I/O I/O E16 I/O I/O B5 I/O I/O C24 VDDP VDDP E17 I/O I/O B6 I/O I/O C25 I/O I/O E18 I/O I/O B7 I/O I/O C26 I/O I/O E19 I/O I/O B8 I/O I/O D1 I/O I/O E20 VDD VDD B9 I/O I/O D2 I/O I/O E21 VDD VDD B10 I/O I/O D3 I/O I/O E22 VDD VDD B11 I/O I/O D4 VDDP VDDP E23 I/O I/O B12 I/O I/O D5 I/O I/O E24 I/O I/O B13 I/O I/O D6 I/O I/O E25 I/O I/O B14 I/O I/O D7 I/O I/O E26 I/O I/O Advanced v0.3 59 P r o A SI C P L U S A P A F a m ily 4 5 6 - P in P BG A Pin Number APA750 Function APA1000 Function Pin Number APA750 Function APA1000 Function Pin Number APA750 Function APA1000 Function F1 I/O I/O K22 I/O I/O N14 GND GND F2 I/O I/O K23 I/O I/O N15 GND GND F3 I/O I/O K24 I/O I/O N16 GND GND 60 F4 I/O I/O K25 I/O I/O N22 PPECL PPECL F5 VDD VDD K26 I/O I/O N23 GL GL F22 VDD VDD L1 I/O I/O N24 AVDD AVDD F23 I/O I/O L2 I/O I/O N25 I/O I/O F24 I/O I/O L3 I/O I/O N26 AGND AGND F25 I/O I/O L4 I/O I/O P1 I/O I/O F26 I/O I/O L5 I/O I/O P2 I/O I/O G1 I/O I/O L11 GND GND P3 I/O I/O G2 I/O I/O L12 GND GND P4 I/O I/O G3 I/O I/O L13 GND GND P5 PPECL PPECL G4 I/O I/O L14 GND GND P11 GND GND G5 VDD VDD L15 GND GND P12 GND GND G22 VDD VDD L16 GND GND P13 GND GND G23 I/O I/O L22 I/O I/O P14 GND GND G24 I/O I/O L23 I/O I/O P15 GND GND G25 I/O I/O L24 I/O I/O P16 GND GND G26 I/O I/O L25 I/O I/O P22 I/O I/O H1 I/O I/O L26 I/O I/O P23 I/O I/O H2 I/O I/O M1 GL GL P24 I/O I/O H3 I/O I/O M2 GL GL P25 I/O I/O H4 I/O I/O M3 I/O I/O P26 NPECL NPECL H5 VDD VDD M4 I/O I/O R1 I/O I/O H22 VDD VDD M5 I/O I/O R2 I/O I/O H23 I/O I/O M11 GND GND R3 I/O I/O H24 I/O I/O M12 GND GND R4 I/O I/O H25 I/O I/O M13 GND GND R5 I/O I/O H26 I/O I/O M14 GND GND R11 GND GND J1 I/O I/O M15 GND GND R12 GND GND J2 I/O I/O M16 GND GND R13 GND GND J3 I/O I/O M22 GL GL R14 GND GND J4 I/O I/O M23 I/O I/O R15 GND GND J5 I/O I/O M24 I/O I/O R16 GND GND J22 I/O I/O M25 I/O I/O R22 I/O I/O J23 I/O I/O M26 I/O I/O R23 I/O I/O J24 I/O I/O N1 I/O I/O R24 I/O I/O J25 I/O I/O N2 I/O I/O R25 I/O I/O J26 I/O I/O N3 AGND AGND R26 I/O I/O K1 I/O I/O N4 NPECL NPECL T1 I/O I/O K2 I/O I/O N5 AVDD AVDD T2 I/O I/O K3 I/O I/O N11 GND GND T3 I/O I/O K4 I/O I/O N12 GND GND T4 I/O I/O K5 I/O I/O N13 GND GND T5 I/O I/O Advanced v0.3 Pr o A SI C P L U S A PA F a m ily 4 5 6 - P in P BG A Pin Number APA750 Function APA1000 Function Pin Number APA750 Function APA1000 Function Pin Number APA750 Function APA1000 Function T11 GND GND U24 I/O I/O W22 VDD VDD T12 GND GND U25 I/O I/O W23 I/O I/O T13 GND GND U26 I/O I/O W24 I/O I/O T14 GND GND V1 I/O I/O W25 I/O I/O T15 GND GND V2 I/O I/O W26 I/O I/O T16 GND GND V3 I/O I/O Y1 I/O I/O T22 I/O I/O V4 I/O I/O Y2 I/O I/O T23 I/O I/O V5 I/O I/O Y3 I/O I/O T24 I/O I/O V22 I/O I/O Y4 I/O I/O T25 I/O I/O V23 I/O I/O Y5 VDD VDD T26 I/O I/O V24 I/O I/O Y22 VDD VDD U1 I/O I/O V25 I/O I/O Y23 I/O I/O U2 I/O I/O V26 I/O I/O Y24 I/O I/O U3 I/O I/O W1 I/O I/O Y25 I/O I/O U4 I/O I/O W2 I/O I/O Y26 I/O I/O U5 I/O I/O W3 I/O I/O U22 I/O I/O W4 I/O I/O U23 I/O I/O W5 VDD VDD Advanced v0.3 61 P r o A SI C P L U S A P A F a m ily Pa c ka ge P i n A s si g nm e n t s (Continued) 676- P in FBG A ( Bot t om V iew ) 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF 62 Advanced v0.3 8 7 6 5 4 3 2 1 Pr o A SI C P L U S A PA F a m ily 676- P in FBG A Pin Number APA750 Function Pin Number APA750 Function Pin Number APA750 Function A1 GND AA14 I/O AC1 I/O A2 GND AA15 I/O AC2 I/O A3 I/O AA16 I/O AC3 I/O A4 I/O AA17 I/O AC4 I/O A5 I/O AA18 I/O AC5 GND A6 I/O AA19 I/O AC6 I/O A7 I/O AA20 I/O AC7 I/O A8 I/O AA21 TDO AC8 I/O A9 I/O AA22 GND AC9 GND A10 I/O AA23 GND AC10 I/O A11 I/O AA24 I/O AC11 I/O A12 I/O AA25 I/O AC12 I/O A13 I/O AA26 I/O AC13 I/O A14 I/O AB1 I/O AC14 I/O A15 I/O AB2 I/O AC15 I/O A16 I/O AB3 I/O AC16 I/O A17 I/O AB4 I/O AC17 I/O A18 I/O AB5 I/O AC18 I/O A19 I/O AB6 GND AC19 I/O A20 I/O AB7 GND AC20 I/O A21 I/O AB8 I/O AC21 I/O A22 I/O AB9 I/O AC22 TMS A23 I/O AB10 I/O AC23 RCK A24 I/O AB11 I/O AC24 I/O A25 GND AB12 I/O AC25 I/O A26 GND AB13 I/O AC26 I/O AA1 I/O AB14 I/O AD1 I/O AA2 I/O AB15 I/O AD2 I/O AA3 I/O AB16 I/O AD3 I/O AA4 I/O AB17 I/O AD4 I/O AA5 I/O AB18 I/O AD5 I/O AA6 GND AB19 I/O AD6 I/O AA7 I/O AB20 I/O AD7 I/O AA8 I/O AB21 TCK AD8 I/O AA9 I/O AB22 TRST AD9 I/O AA10 I/O AB23 I/O AD10 I/O AA11 I/O AB24 I/O AD11 I/O AA12 I/O AB25 I/O AD12 I/O AA13 I/O AB26 I/O AD13 I/O Advanced v0.3 63 P r o A SI C P L U S A P A F a m ily 676- P in FBG A 64 Pin Number APA750 Function Pin Number APA750 Function Pin Number APA750 Function AD14 I/O AF1 GND B14 I/O AD15 I/O AF2 GND B15 I/O AD16 I/O AF3 GND B16 I/O AD17 I/O AF4 GND B17 I/O AD18 I/O AF5 I/O B18 I/O AD19 I/O AF6 I/O B19 I/O AD20 I/O AF7 I/O B20 I/O AD21 I/O AF8 I/O B21 I/O AD22 I/O AF9 I/O B22 I/O AD23 TDI AF10 I/O B23 I/O AD24 VPN AF11 I/O B24 I/O AD25 I/O AF12 I/O B25 GND AD26 I/O AF13 I/O B26 GND AE1 GND AF14 I/O C1 GND AE2 GND AF15 I/O C2 GND AE3 GND AF16 I/O C3 GND AE4 I/O AF17 I/O C4 GND AE5 I/O AF18 I/O C5 I/O AE6 I/O AF19 I/O C6 I/O AE7 I/O AF20 I/O C7 I/O AE8 I/O AF21 I/O C8 I/O AE9 I/O AF22 I/O C9 I/O AE10 I/O AF23 I/O C10 I/O AE11 I/O AF24 I/O C11 I/O AE12 I/O AF25 GND C12 I/O AE13 I/O AF26 GND C13 I/O AE14 I/O B1 GND C14 I/O AE15 I/O B2 GND C15 I/O AE16 I/O B3 GND C16 I/O AE17 I/O B4 GND C17 I/O AE18 I/O B5 I/O C18 I/O AE19 I/O B6 I/O C19 I/O AE20 I/O B7 I/O C20 I/O AE21 I/O B8 I/O C21 I/O AE22 I/O B9 I/O C22 I/O AE23 I/O B10 I/O C23 I/O AE24 I/O B11 I/O C24 I/O AE25 GND B12 I/O C25 I/O AE26 GND B13 I/O C26 I/O Advanced v0.3 Pr o A SI C P L U S A PA F a m ily 676- P in FBG A Pin Number APA750 Function Pin Number APA750 Function Pin Number APA750 Function D1 I/O E14 I/O G1 I/O D2 I/O E15 I/O G2 I/O D3 GND E16 I/O G3 I/O D4 I/O E17 I/O G4 I/O D5 I/O E18 I/O G5 I/O D6 I/O E19 I/O G6 I/O D7 I/O E20 I/O G7 I/O D8 I/O E21 I/O G8 VDD D9 I/O E22 I/O G9 NC D10 I/O E23 I/O G10 I/O D11 I/O E24 I/O G11 NC D12 I/O E25 I/O G12 I/O D13 I/O E26 I/O G13 NC D14 I/O F1 I/O G14 I/O D15 I/O F2 I/O G15 NC D16 I/O F3 I/O G16 I/O D17 I/O F4 I/O G17 NC D18 I/O F5 GND G18 I/O D19 I/O F6 I/O G19 VDDP D20 I/O F7 NC G20 NC D21 I/O F8 I/O G21 I/O D22 I/O F9 I/O G22 I/O D23 I/O F10 I/O G23 I/O D24 I/O F11 I/O G24 I/O D25 I/O F12 I/O G25 I/O D26 I/O F13 I/O G26 I/O E1 I/O F14 I/O H1 I/O E2 I/O F15 I/O H2 I/O E3 I/O F16 I/O H3 I/O E4 I/O F17 I/O H4 I/O E5 I/O F18 I/O H5 I/O E6 I/O F19 I/O H6 I/O E7 I/O F20 I/O H7 VDDP E8 I/O F21 I/O H8 VDD E9 I/O F22 I/O H9 VDDP E10 I/O F23 I/O H10 VDDP E11 I/O F24 I/O H11 VDDP E12 I/O F25 I/O H12 VDDP E13 I/O F26 I/O H13 VDDP Advanced v0.3 65 P r o A SI C P L U S A P A F a m ily 676- P in FBG A 66 Pin Number APA750 Function Pin Number APA750 Function Pin Number APA750 Function H14 VDDP K1 I/O L14 GND H15 VDDP K2 I/O L15 GND H16 VDDP K3 I/O L16 GND H17 VDDP K4 I/O L17 GND H18 VDDP K5 I/O L18 VDD H19 VDD K6 I/O L19 VDDP H20 VDD K7 I/O L20 NC H21 I/O K8 VDDP L21 I/O H22 I/O K9 VDD L22 I/O H23 I/O K10 GND L23 I/O H24 I/O K11 GND L24 I/O H25 I/O K12 GND L25 I/O H26 I/O K13 GND L26 I/O J1 I/O K14 GND M1 I/O J2 I/O K15 GND M2 I/O J3 I/O K16 GND M3 I/O J4 I/O K17 GND M4 I/O J5 I/O K18 VDD M5 I/O J6 I/O K19 VDDP M6 I/O J7 NC K20 I/O M7 I/O J8 VDDP K21 I/O M8 VDDP J9 VDD K22 I/O M9 VDD J10 VDD K23 I/O M10 GND J11 VDD K24 I/O M11 GND J12 VDD K25 I/O M12 GND J13 VDD K26 I/O M13 GND J14 VDD L1 I/O M14 GND J15 VDD L2 I/O M15 GND J16 VDD L3 I/O M16 GND J17 VDD L4 I/O M17 GND J18 VDD L5 I/O M18 VDD J19 VDDP L6 I/O M19 VDDP J20 NC L7 NC M20 I/O J21 I/O L8 VDDP M21 I/O J22 I/O L9 VDD M22 I/O J23 I/O L10 GND M23 I/O J24 I/O L11 GND M24 I/O J25 I/O L12 GND M25 I/O J26 I/O L13 GND M26 I/O Advanced v0.3 Pr o A SI C P L U S A PA F a m ily 676- P in FBG A Pin Number APA750 Function Pin Number APA750 Function Pin Number APA750 Function N1 GL P14 GND T1 I/O N2 AGND P15 GND T2 I/O N3 I/O P16 GND T3 I/O N4 I/O P17 GND T4 I/O N5 NPECL P18 VDD T5 I/O N6 I/O P19 VDDP T6 I/O N7 NC P20 I/O T7 I/O N8 VDDP P21 I/O T8 VDDP N9 VDD P22 I/O T9 VDD N10 GND P23 I/O T10 GND N11 GND P24 PPECL T11 GND N12 GND P25 AVDD T12 GND N13 GND P26 AGND T13 GND N14 GND R1 I/O T14 GND N15 GND R2 I/O T15 GND N16 GND R3 I/O T16 GND N17 GND R4 I/O T17 GND N18 VDD R5 I/O T18 VDD N19 VDDP R6 I/O T19 VDDP N20 NC R7 NC T20 I/O N21 I/O R8 VDDP T21 I/O N22 GL R9 VDD T22 I/O N23 I/O R10 GND T23 I/O N24 NPECL R11 GND T24 I/O N25 GL R12 GND T25 I/O N26 I/O R13 GND T26 I/O P1 GL R14 GND U1 I/O P2 AVDD R15 GND U2 I/O P3 I/O R16 GND U3 I/O P4 I/O R17 GND U4 I/O P5 PPECL R18 VDD U5 I/O P6 I/O R19 VDDP U6 I/O P7 I/O R20 NC U7 NC P8 VDDP R21 I/O U8 VDDP P9 VDD R22 I/O U9 VDD P10 GND R23 I/O U10 GND P11 GND R24 I/O U11 GND P12 GND R25 I/O U12 GND P13 GND R26 I/O U13 GND Advanced v0.3 67 P r o A SI C P L U S A P A F a m ily 676- P in FBG A 68 Pin Number APA750 Function Pin Number APA750 Function Pin Number APA750 Function U14 GND V17 VDD W20 VDDP U15 GND V18 VDD W21 I/O U16 GND V19 VDDP W22 I/O U17 GND V20 I/O W23 I/O U18 VDD V21 I/O W24 I/O U19 VDDP V22 I/O W25 I/O U20 NC V23 I/O W26 I/O U21 I/O V24 I/O Y1 I/O U22 I/O V25 I/O Y2 I/O U23 I/O V26 I/O Y3 I/O U24 I/O W1 I/O Y4 I/O U25 I/O W2 I/O Y5 I/O U26 I/O W3 I/O Y6 I/O V1 I/O W4 I/O Y7 I/O V2 I/O W5 I/O Y8 VDDP V3 I/O W6 I/O Y9 NC V4 I/O W7 VDD Y10 I/O V5 I/O W8 VDD Y11 NC V6 I/O W9 VDDP Y12 I/O V7 I/O W10 VDDP Y13 NC V8 VDDP W11 VDDP Y14 I/O V9 VDD W12 VDDP Y15 NC V10 VDD W13 VDDP Y16 I/O V11 VDD W14 VDDP Y17 NC V12 VDD W15 VDDP Y18 I/O V13 VDD W16 VDDP Y19 VDD V14 VDD W17 VDDP Y20 VPP V15 VDD W18 VDDP Y21 I/O V16 VDD W19 VDD Y22 I/O Y23 I/O Y24 I/O Y25 I/O Y26 I/O Advanced v0.3 Pr o A SI C P L U S A PA F a m ily P a c ka ge P i n A s si g nm e n t s (Continued) 896- P in FBG A ( Bot t om V iew ) 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK Advanced v0.3 69 P r o A SI C P L U S A P A F a m ily 896- P in FBG A Pin Number APA750 Function APA1000 Function Pin Number APA750 Function APA1000 Function Pin Number APA750 Function APA1000 Function A2 GND GND AA18 VDDP VDDP AC3 I/O I/O A3 GND GND AA19 VDDP VDDP AC4 I/O I/O A4 I/O I/O AA20 I/O I/O AC5 I/O I/O A5 GND GND AA21 VDD VDD AC6 I/O I/O A6 I/O I/O AA22 I/O I/O AC7 I/O I/O A7 GND GND AA23 I/O I/O AC8 GND GND A8 I/O I/O AA24 I/O I/O AC9 I/O I/O A9 I/O I/O AA25 I/O I/O AC10 I/O I/O A10 I/O I/O AA26 I/O I/O AC11 I/O I/O 70 A11 I/O I/O AA27 I/O I/O AC12 I/O I/O A12 I/O I/O AA28 I/O I/O AC13 I/O I/O A13 I/O I/O AA29 I/O I/O AC14 I/O I/O A14 I/O I/O AA30 I/O I/O AC15 I/O I/O A15 I/O I/O AB1 I/O I/O AC16 I/O I/O A16 I/O I/O AB2 I/O I/O AC17 I/O I/O A17 I/O I/O AB3 I/O I/O AC18 I/O I/O A18 I/O I/O AB4 I/O I/O AC19 I/O I/O A19 I/O I/O AB5 I/O I/O AC20 I/O I/O A20 I/O I/O AB6 I/O I/O AC21 I/O I/O A21 I/O I/O AB7 VDDP VDDP AC22 I/O I/O A22 I/O I/O AB8 I/O I/O AC23 GND GND A23 I/O I/O AB9 VDD VDD AC24 I/O I/O A24 GND GND AB10 I/O I/O AC25 I/O I/O A25 I/O I/O AB11 I/O I/O AC26 I/O I/O A26 GND GND AB12 I/O I/O AC27 I/O I/O A27 I/O I/O AB13 I/O I/O AC28 I/O I/O A28 GND GND AB14 I/O I/O AC29 I/O I/O A29 GND GND AB15 I/O I/O AC30 I/O I/O AA1 I/O I/O AB16 I/O I/O AD1 GND GND AA2 I/O I/O AB17 I/O I/O AD2 I/O I/O AA3 I/O I/O AB18 I/O I/O AD3 I/O I/O AA4 I/O I/O AB19 I/O I/O AD4 I/O I/O AA5 I/O I/O AB20 I/O I/O AD5 VDDP VDDP AA6 I/O I/O AB21 I/O I/O AD6 I/O I/O AA7 I/O I/O AB22 VDD VDD AD7 VDD VDD AA8 I/O I/O AB23 I/O I/O AD8 I/O I/O AA9 I/O I/O AB24 VDDP VDDP AD9 VDDP VDDP AA10 VDD VDD AB25 I/O I/O AD10 I/O I/O AA11 I/O I/O AB26 I/O I/O AD11 I/O I/O AA12 VDDP VDDP AB27 I/O I/O AD12 I/O I/O AA13 VDDP VDDP AB28 I/O I/O AD13 I/O I/O AA14 VDDP VDDP AB29 I/O I/O AD14 I/O I/O AA15 VDDP VDDP AB30 I/O I/O AD15 I/O I/O AA16 VDDP VDDP AC1 I/O I/O AD16 I/O I/O AA17 VDDP VDDP AC2 I/O I/O AD17 I/O I/O Advanced v0.3 Pr o A SI C P L U S A PA F a m ily 896- P in FBG A ( Cont i nued) Pin Number APA750 Function APA1000 Function Pin Number APA750 Function APA1000 Function Pin Number APA750 Function APA1000 Function AD18 I/O I/O AF3 VDDP VDDP AG18 I/O I/O AD19 I/O I/O AF4 I/O I/O AG19 I/O I/O AD20 I/O I/O AF5 VDD VDD AG20 I/O I/O AD21 I/O I/O AF6 I/O I/O AG21 I/O I/O AD22 VDDP VDDP AF7 VDDP VDDP AG22 I/O I/O AD23 TCK TCK AF8 I/O I/O AG23 I/O I/O AD24 VDD VDD AF9 I/O I/O AG24 I/O I/O AD25 TRST TRST AF10 I/O I/O AG25 I/O I/O AD26 VDDP VDDP AF11 I/O I/O AG26 I/O I/O AD27 I/O I/O AF12 I/O I/O AG27 GND GND AD28 I/O I/O AF13 I/O I/O AG28 RCK RCK AD29 I/O I/O AF14 I/O I/O AG29 VDD VDD AD30 GND GND AF15 I/O I/O AG30 I/O I/O AE1 I/O I/O AF16 I/O I/O AH1 GND GND AE2 VDD VDD AF17 I/O I/O AH2 I/O I/O AE3 I/O I/O AF18 I/O I/O AH3 VDD VDD AE4 I/O I/O AF19 I/O I/O AH4 I/O I/O AE5 I/O I/O AF20 I/O I/O AH5 VDDP VDDP AE6 GND GND AF21 I/O I/O AH6 I/O I/O AE7 I/O I/O AF22 I/O I/O AH7 I/O I/O AE8 I/O I/O AF23 I/O I/O AH8 I/O I/O AE9 I/O I/O AF24 VDD VDD AH9 I/O I/O AE10 I/O I/O AF25 I/O I/O AH10 I/O I/O AE11 I/O I/O AF26 VDDP VDDP AH11 I/O I/O AE12 I/O I/O AF27 TDO TDO AH12 I/O I/O AE13 I/O I/O AF28 VDDP VDDP AH13 I/O I/O AE14 I/O I/O AF29 VPN VPN AH14 I/O I/O AE15 I/O I/O AF30 GND GND AH15 I/O I/O AE16 I/O I/O AG1 I/O I/O AH16 I/O I/O AE17 I/O I/O AG2 VDD VDD AH17 I/O I/O AE18 I/O I/O AG3 I/O I/O AH18 I/O I/O AE19 I/O I/O AG4 GND GND AH19 I/O I/O AE20 I/O I/O AG5 I/O I/O AH20 I/O I/O AE21 I/O I/O AG6 I/O I/O AH21 I/O I/O AE22 I/O I/O AG7 I/O I/O AH22 I/O I/O AE23 I/O I/O AG8 I/O I/O AH23 I/O I/O AE24 I/O I/O AG9 I/O I/O AH24 I/O I/O AE25 GND GND AG10 I/O I/O AH25 I/O I/O AE26 I/O I/O AG11 I/O I/O AH26 VDDP VDDP AE27 I/O I/O AG12 I/O I/O AH27 TDI TDI AE28 I/O I/O AG13 I/O I/O AH28 VDD VDD AE29 VDD VDD AG14 I/O I/O AH29 VPP VPP AE30 I/O I/O AG15 I/O I/O AH30 GND GND AF1 GND GND AG16 I/O I/O AJ1 GND GND AF2 I/O I/O AG17 I/O I/O AJ2 GND GND Advanced v0.3 71 P r o A SI C P L U S A P A F a m ily 896- P in FBG A ( Cont i nued) Pin Number APA750 Function APA1000 Function Pin Number APA750 Function APA1000 Function Pin Number APA750 Function APA1000 Function AK19 I/O I/O C5 VDDP VDDP D20 I/O I/O AK20 I/O I/O C6 I/O I/O D21 I/O I/O AK21 I/O I/O C7 I/O I/O D22 I/O I/O AK22 I/O I/O C8 I/O I/O D23 I/O I/O AK23 I/O I/O C9 I/O I/O D24 I/O I/O AK24 GND GND C10 I/O I/O D25 I/O I/O AK25 I/O I/O C11 I/O I/O D26 I/O I/O AK26 GND GND C12 I/O I/O D27 GND GND AK27 I/O I/O C13 I/O I/O D28 I/O I/O 72 AK28 GND GND C14 I/O I/O D29 VDD VDD AK29 GND GND C15 I/O I/O D30 I/O I/O B1 GND GND C16 I/O I/O E1 GND GND B2 GND GND C17 I/O I/O E2 I/O I/O B4 VDD VDD C18 I/O I/O E3 VDDP VDDP B5 I/O I/O C19 I/O I/O E4 I/O I/O B6 VDD VDD C20 I/O I/O E5 VDD VDD B7 I/O I/O C21 I/O I/O E6 I/O I/O B8 I/O I/O C22 I/O I/O E7 VDDP VDDP B9 I/O I/O C23 I/O I/O E8 I/O I/O B3 I/O I/O C24 I/O I/O E9 I/O I/O B10 I/O I/O C25 I/O I/O E10 I/O I/O B11 I/O I/O C26 VDDP VDDP E11 I/O I/O B12 I/O I/O C27 I/O I/O E12 I/O I/O B13 I/O I/O C28 VDD VDD E13 I/O I/O B14 I/O I/O C29 I/O I/O E14 I/O I/O B15 I/O I/O C30 GND GND E15 I/O I/O B16 I/O I/O D1 I/O I/O E16 I/O I/O B17 I/O I/O D2 VDD VDD E17 I/O I/O B18 I/O I/O D3 I/O I/O E18 I/O I/O B19 I/O I/O D4 GND GND E19 I/O I/O B20 I/O I/O D5 I/O I/O E20 I/O I/O B21 I/O I/O D6 I/O I/O E21 I/O I/O B22 I/O I/O D7 I/O I/O E22 I/O I/O B23 I/O I/O D8 I/O I/O E23 I/O I/O B24 I/O I/O D9 I/O I/O E24 VDDP VDDP B25 VDD VDD D10 I/O I/O E25 I/O I/O B26 I/O I/O D11 I/O I/O E26 VDD VDD B27 VDD VDD D12 I/O I/O E27 I/O I/O B28 I/O I/O D13 I/O I/O E28 VDDP VDDP B29 GND GND D14 I/O I/O E29 I/O I/O B30 GND GND D15 I/O I/O E30 GND GND C1 GND GND D16 I/O I/O F1 I/O I/O C2 I/O I/O D17 I/O I/O F2 VDD VDD C3 VDD VDD D18 I/O I/O F3 I/O I/O C4 I/O I/O D19 I/O I/O F4 I/O I/O Advanced v0.3 Pr o A SI C P L U S A PA F a m ily 896- P in FBG A ( Cont i nued) Pin Number APA750 Function APA1000 Function Pin Number APA750 Function APA1000 Function Pin Number APA750 Function APA1000 Function F5 I/O I/O G20 I/O I/O J5 I/O I/O F6 GND GND G21 I/O I/O J6 I/O I/O F7 I/O I/O G22 VDDP VDDP J7 VDDP VDDP F8 I/O I/O G23 I/O I/O J8 I/O I/O F9 I/O I/O G24 VDD VDD J9 VDD VDD F10 I/O I/O G25 I/O I/O J10 I/O I/O F11 I/O I/O G26 VDDP VDDP J11 I/O I/O F12 I/O I/O G27 I/O I/O J12 I/O I/O F13 I/O I/O G28 I/O I/O J13 I/O I/O F14 I/O I/O G29 I/O I/O J14 I/O I/O F15 I/O I/O G30 GND GND J15 I/O I/O F16 I/O I/O H1 I/O I/O J16 I/O I/O F17 I/O I/O H2 I/O I/O J17 I/O I/O F18 I/O I/O H3 I/O I/O J18 I/O I/O F19 I/O I/O H4 I/O I/O J19 I/O I/O F20 I/O I/O H5 I/O I/O J20 I/O I/O F21 I/O I/O H6 I/O I/O J21 I/O I/O F22 I/O I/O H7 I/O I/O J22 VDD VDD F23 I/O I/O H8 GND GND J23 I/O I/O F24 I/O I/O H9 I/O I/O J24 VDDP VDDP F25 GND GND H10 I/O I/O J25 I/O I/O F26 I/O I/O H11 I/O I/O J26 I/O I/O F27 I/O I/O H12 I/O I/O J27 I/O I/O F28 I/O I/O H13 I/O I/O J28 I/O I/O F29 VDD VDD H14 I/O I/O J29 I/O I/O F30 I/O I/O H15 I/O I/O J30 I/O I/O G1 GND GND H16 I/O I/O K1 I/O I/O G2 I/O I/O H17 I/O I/O K2 I/O I/O G3 I/O I/O H18 I/O I/O K3 I/O I/O G4 I/O I/O H19 I/O I/O K4 I/O I/O G5 VDDP VDDP H20 I/O I/O K5 I/O I/O G6 I/O I/O H21 I/O I/O K6 I/O I/O G7 VDD VDD H22 I/O I/O K7 I/O I/O G8 I/O I/O H23 GND GND K8 I/O I/O G9 VDDP VDDP H24 I/O I/O K9 I/O I/O G10 I/O I/O H25 I/O I/O K10 VDD VDD G11 I/O I/O H26 I/O I/O K11 I/O I/O G12 I/O I/O H27 I/O I/O K12 VDDP VDDP G13 I/O I/O H28 I/O I/O K13 VDDP VDDP G14 I/O I/O H29 I/O I/O K14 VDDP VDDP G15 I/O I/O H30 I/O I/O K15 VDDP VDDP G16 I/O I/O J1 I/O I/O K16 VDDP VDDP G17 I/O I/O J2 I/O I/O K17 VDDP VDDP G18 I/O I/O J3 I/O I/O K18 VDDP VDDP G19 I/O I/O J4 I/O I/O K19 VDDP VDDP Advanced v0.3 73 P r o A SI C P L U S A P A F a m ily 896- P in FBG A ( Cont i nued) Pin Number APA750 Function APA1000 Function Pin Number APA750 Function APA1000 Function Pin Number APA750 Function APA1000 Function K20 I/O I/O M5 I/O I/O N20 VDD VDD K21 VDD VDD M6 I/O I/O N21 VDDP VDDP K22 I/O I/O M7 I/O I/O N22 I/O I/O K23 I/O I/O M8 I/O I/O N23 I/O I/O K24 I/O I/O M9 I/O I/O N24 I/O I/O 74 K25 I/O I/O M10 VDDP VDDP N25 I/O I/O K26 I/O I/O M11 VDD VDD N26 I/O I/O K27 I/O I/O M12 GND GND N27 I/O I/O K28 I/O I/O M13 GND GND N28 I/O I/O K29 I/O I/O M14 GND GND N29 I/O I/O K30 I/O I/O M15 GND GND N30 I/O I/O L1 I/O I/O M16 GND GND P1 I/O I/O L2 I/O I/O M17 GND GND P2 I/O I/O L3 I/O I/O M18 GND GND P3 I/O I/O L4 I/O I/O M19 GND GND P4 I/O I/O L5 I/O I/O M20 VDD VDD P5 I/O I/O L6 I/O I/O M21 VDDP VDDP P6 I/O I/O L7 I/O I/O M22 I/O I/O P7 I/O I/O L8 I/O I/O M23 I/O I/O P8 I/O I/O L9 I/O I/O M24 I/O I/O P9 I/O I/O L10 I/O I/O M25 I/O I/O P10 VDDP VDDP L11 VDD VDD M26 I/O I/O P11 VDD VDD L12 VDD VDD M27 I/O I/O P12 GND GND L13 VDD VDD M28 I/O I/O P13 GND GND L14 VDD VDD M29 I/O I/O P14 GND GND L15 VDD VDD M30 I/O I/O P15 GND GND L16 VDD VDD N1 I/O I/O P16 GND GND L17 VDD VDD N2 I/O I/O P17 GND GND L18 VDD VDD N3 I/O I/O P18 GND GND L19 VDD VDD N4 I/O I/O P19 GND GND L20 VDD VDD N5 I/O I/O P20 VDDP VDDP L21 I/O I/O N6 I/O I/O P21 VDD VDD L22 I/O I/O N7 I/O I/O P22 I/O I/O L23 I/O I/O N8 I/O I/O P23 I/O I/O L24 I/O I/O N9 I/O I/O P24 I/O I/O L25 I/O I/O N10 VDDP VDDP P25 I/O I/O L26 I/O I/O N11 VDD VDD P26 I/O I/O L27 I/O I/O N12 GND GND P27 I/O I/O L28 I/O I/O N13 GND GND P28 I/O I/O L29 I/O I/O N14 GND GND P29 I/O I/O L30 I/O I/O N15 GND GND P30 I/O I/O M1 I/O I/O N16 GND GND R1 I/O I/O M2 I/O I/O N17 GND GND R2 I/O I/O M3 I/O I/O N18 GND GND R3 AGND AGND M4 I/O I/O N19 GND GND R4 NPECL NPECL Advanced v0.3 Pr o A SI C P L U S A PA F a m ily 896- P in FBG A ( Cont i nued) Pin Number APA750 Function APA1000 Function Pin Number APA750 Function APA1000 Function Pin Number APA750 Function APA1000 Function R5 GL GL T13 GND GND U22 I/O I/O R6 I/O I/O T14 GND GND U23 I/O I/O R7 I/O I/O T15 GND GND U24 I/O I/O R8 I/O I/O T16 GND GND U25 I/O I/O R9 I/O I/O T17 GND GND U26 I/O I/O R10 VDDP VDDP T18 GND GND U27 I/O I/O R11 VDD VDD T20 VDD VDD U28 I/O I/O R12 GND GND T21 VDDP VDDP U29 I/O I/O R13 GND GND T22 I/O I/O U30 I/O I/O R14 GND GND T23 I/O I/O V1 I/O I/O R15 GND GND T24 I/O I/O V2 I/O I/O R16 GND GND T25 I/O I/O V3 I/O I/O R17 GND GND T26 PPECL PPECL V4 I/O I/O R18 GND GND T27 GL GL V5 I/O I/O R19 GND GND T28 GL GL V6 I/O I/O R20 VDD VDD T29 AVDD AVDD V7 I/O I/O R21 VDDP VDDP T30 I/O I/O V8 I/O I/O R22 I/O I/O U1 I/O I/O V9 I/O I/O R23 I/O I/O U2 I/O I/O V10 VDDP VDDP R24 I/O I/O U3 I/O I/O V11 VDD VDD R25 I/O I/O U4 I/O I/O V12 GND GND R26 I/O I/O U5 I/O I/O V13 GND GND R27 NPECL NPECL U6 I/O I/O V14 GND GND R28 AGND AGND U7 I/O I/O V15 GND GND R29 I/O I/O U8 I/O I/O V16 GND GND R30 I/O I/O U9 I/O I/O V17 GND GND T1 I/O I/O U10 VDDP VDDP V18 GND GND T2 AVDD AVDD U11 VDD VDD V19 GND GND T3 GL GL U12 GND GND V20 VDD VDD T4 PPECL PPECL U13 GND GND V21 VDDP VDDP T5 I/O I/O U14 GND GND V22 I/O I/O T6 I/O I/O U15 GND GND V23 I/O I/O T7 I/O I/O U16 GND GND V24 I/O I/O T8 I/O I/O U17 GND GND V25 I/O I/O T9 I/O I/O U18 GND GND V26 I/O I/O T10 VDDP VDDP U19 GND GND V27 I/O I/O T11 VDD VDD U20 VDD VDD V28 I/O I/O T12 GND GND U21 VDDP VDDP V29 I/O I/O V30 I/O I/O Advanced v0.3 75 P r o A SI C P L U S A P A F a m ily Pa c ka ge P i n A s si g nm e n t s (Continued) 1152 -P in FB GA (Bot t om V ie w) 34 33 32 31 30 2928 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM AN AO AP 76 Advanced v0.3 Pr o A SI C P L U S A PA F a m ily 1 1 5 2 -P in F B G A Pin Number APA1000 Function Pin Number APA1000 Function Pin Number APA1000 Function Pin Number APA1000 Function A2 NC AA14 GND AB25 I/O AD2 I/O A3 GND AA15 GND AB26 I/O AD3 I/O A4 GND AA16 GND AB27 I/O AD4 I/O A5 GND AA17 GND AB28 I/O AD5 I/O A6 I/O AA18 GND AB29 I/O AD6 I/O A7 VDD AA19 GND AB30 I/O AD7 I/O A8 VDD AA20 GND AB31 I/O AD8 I/O A9 VDD AA21 GND AB32 I/O AD9 VDDP A10 VDD AA22 VDD AB33 I/O AD10 I/O A11 I/O AA23 VDDP AB34 I/O AD11 VDD A12 GND AA24 I/O AC1 GND AD12 I/O A13 I/O AA25 I/O AC2 GND AD13 I/O A14 VDDP AA26 I/O AC3 I/O AD14 I/O A15 VDDP AA27 I/O AC4 I/O AD15 I/O A16 I/O AA28 I/O AC5 I/O AD16 I/O A17 GND AA29 I/O AC6 I/O AD17 I/O A18 GND AA30 I/O AC7 I/O AD18 I/O A19 I/O AA31 I/O AC8 I/O AD19 I/O A20 VDDP AA32 I/O AC9 I/O AD20 I/O A21 VDDP AA33 VDDP AC10 I/O AD21 I/O A22 I/O AA34 VDDP AC11 I/O AD22 I/O A23 GND AB1 I/O AC12 VDD AD23 I/O A24 I/O AB2 I/O AC13 I/O AD24 VDD A25 VDD AB3 I/O AC14 VDDP AD25 I/O A26 VDD AB4 I/O AC15 VDDP AD26 VDDP A27 VDD AB5 I/O AC16 VDDP AD27 I/O A28 VDD AB6 I/O AC17 VDDP AD28 I/O A29 I/O AB7 I/O AC18 VDDP AD29 I/O A30 GND AB8 I/O AC19 VDDP AD30 I/O A31 GND AB9 I/O AC20 VDDP AD31 I/O A32 GND AB10 I/O AC21 VDDP AD32 I/O A33 I/O AB11 I/O AC22 I/O AD33 I/O AA1 VDDP AB12 I/O AC23 VDD AD34 I/O AA2 VDDP AB13 VDD AC24 I/O AE1 VDD AA3 I/O AB14 VDD AC25 I/O AE2 NC AA4 I/O AB15 VDD AC26 I/O AE3 I/O AA5 I/O AB16 VDD AC27 I/O AE4 I/O AA6 I/O AB17 VDD AC28 I/O AE5 I/O AA7 I/O AB18 VDD AC29 I/O AE6 I/O AA8 I/O AB19 VDD AC30 I/O AE7 I/O AA9 I/O AB20 VDD AC31 I/O AE8 I/O AA10 I/O AB21 VDD AC32 I/O AE9 I/O AA11 I/O AB22 VDD AC33 GND AE10 GND AA12 VDDP AB23 I/O AC34 GND AE11 I/O AA13 VDD AB24 I/O AD1 I/O AE12 I/O Advanced v0.3 77 P r o A SI C P L U S A P A F a m ily 1 1 5 2 -P in F B G A 78 Pin Number APA1000 Function Pin Number APA1000 Function Pin Number APA1000 Function Pin Number APA1000 Function AE13 I/O AF24 VDDP AH1 VDD AJ12 I/O AE14 I/O AF25 TCK AH2 I/O AJ13 I/O AE15 I/O AF26 VDD AH3 GND AJ14 I/O AE16 I/O AF27 TRST AH4 I/O AJ15 I/O AE17 I/O AF28 VDDP AH5 VDDP AJ16 I/O AE18 I/O AF29 I/O AH6 I/O AJ17 I/O AE19 I/O AF30 I/O AH7 VDD AJ18 I/O AE20 I/O AF31 I/O AH8 I/O AJ19 I/O AE21 I/O AF32 GND AH9 VDDP AJ20 I/O AE22 I/O AF33 I/O AH10 I/O AJ21 I/O AE23 I/O AF34 VDD AH11 I/O AJ22 I/O AE24 I/O AG1 VDD AH12 I/O AJ23 I/O AE25 GND AG2 NC AH13 I/O AJ24 I/O AE26 I/O AG3 I/O AH14 I/O AJ25 I/O AE27 I/O AG4 VDD AH15 I/O AJ26 I/O AE28 I/O AG5 I/O AH16 I/O AJ27 I/O AE29 I/O AG6 I/O AH17 I/O AJ28 I/O AE30 I/O AG7 I/O AH18 I/O AJ29 GND AE31 I/O AG8 GND AH19 I/O AJ30 RCK AE32 I/O AG9 I/O AH20 I/O AJ31 VDD AE33 NC AG10 I/O AH21 I/O AJ32 I/O AE34 VDD AG11 I/O AH22 I/O AJ33 NC AF1 VDD AG12 I/O AH23 I/O AJ34 NC AF2 I/O AG13 I/O AH24 I/O AK1 GND AF3 GND AG14 I/O AH25 I/O AK2 GND AF4 I/O AG15 I/O AH26 VDDP AK3 GND AF5 I/O AG16 I/O AH27 I/O AK4 I/O AF6 I/O AG17 I/O AH28 VDD AK5 VDD AF7 VDDP AG18 I/O AH29 TDO AK6 I/O AF8 I/O AG19 I/O AH30 VDDP AK7 VDDP AF9 VDD AG20 I/O AH31 VPN AK8 I/O AF10 I/O AG21 I/O AH32 GND AK9 I/O AF11 VDDP AG22 I/O AH33 I/O AK10 I/O AF12 I/O AG23 I/O AH34 VDD AK11 I/O AF13 I/O AG24 I/O AJ1 I/O AK12 I/O AF14 I/O AG25 I/O AJ2 NC AK13 I/O AF15 I/O AG26 I/O AJ3 I/O AK14 I/O AF16 I/O AG27 GND AJ4 VDD AK15 I/O AF17 I/O AG28 I/O AJ5 I/O AK16 I/O AF18 I/O AG29 I/O AJ6 GND AK17 I/O AF19 I/O AG30 I/O AJ7 I/O AK18 I/O AF20 I/O AG31 VDD AJ8 I/O AK19 I/O AF21 I/O AG32 I/O AJ9 I/O AK20 I/O AF22 I/O AG33 NC AJ10 I/O AK21 I/O AF23 I/O AG34 VDD AJ11 I/O AK22 I/O Advanced v0.3 Pr o A SI C P L U S A PA F a m ily 1 1 5 2 -P in F B G A Pin Number APA1000 Function Pin Number APA1000 Function Pin Number APA1000 Function Pin Number APA1000 Function AK23 I/O AL34 GND AN11 I/O AP23 GND AK24 I/O AM1 GND AN12 GND AP24 I/O AK25 I/O AM2 GND AN13 I/O AP25 VDD AK26 I/O AM3 NC AN14 VDDP AP26 VDD AK27 I/O AM4 GND AN15 VDDP AP27 VDD AK28 VDDP AM5 GND AN16 I/O AP28 VDD AK29 TDI AM6 I/O AN17 GND AP29 I/O AK30 VDD AM7 GND AN18 GND AP30 GND AK31 VPP AM8 I/O AN19 I/O AP31 GND AK32 GND AM9 GND AN20 VDD AP32 GND AK33 GND AM10 I/O AN21 VDD AP33 NC AK34 GND AM11 I/O AN22 I/O B1 NC AL1 GND AM12 I/O AN23 GND B2 NC AL2 GND AM13 I/O AN24 I/O B3 GND AL3 GND AM14 I/O AN25 NC B4 GND AL4 GND AM15 I/O AN26 I/O B5 GND AL5 I/O AM16 I/O AN27 NC B6 NC AL6 VDD AM17 I/O AN28 I/O B7 I/O AL7 I/O AM18 I/O AN29 NC B8 NC AL8 VDD AM19 I/O AN30 GND B9 I/O AL9 I/O AM20 I/O AN31 GND B10 NC AL10 I/O AM21 I/O AN32 GND B11 I/O AL11 I/O AM22 I/O AN33 NC B12 GND AL12 I/O AM23 I/O AN34 NC B13 I/O AL13 I/O AM24 I/O AP2 NC B14 VDDP AL14 I/O AM25 I/O AP3 GND B15 VDDP AL15 I/O AM26 GND AP4 GND B16 I/O AL16 I/O AM27 I/O AP5 GND B17 GND AL17 I/O AM28 GND AP6 I/O B18 GND AL18 I/O AM29 I/O AP7 VDD B19 I/O AL19 I/O AM30 GND AP8 VDD B20 VDDP AL20 I/O AM31 GND AP9 VDD B21 VDDP AL21 I/O AM32 NC AP10 VDD B22 I/O AL22 I/O AM33 GND AP11 I/O B23 GND AL23 I/O AM34 GND AP12 GND B24 I/O AL24 I/O AN1 NC AP13 I/O B25 NC AL25 I/O AN2 NC AP14 VDDP B26 I/O AL26 I/O AN3 GND AP15 VDDP B27 NC AL27 VDD AN4 GND AP16 I/O B28 I/O AL28 I/O AN5 GND AP17 GND B29 NC AL29 VDD AN6 NC AP18 GND B30 GND AL30 TMS AN7 I/O AP19 I/O B31 GND AL31 GND AN8 NC AP20 VDDP B32 GND AL32 GND AN9 I/O AP21 VDDP B33 NC AL33 GND AN10 NC AP22 I/O B34 NC Advanced v0.3 79 P r o A SI C P L U S A P A F a m ily 1 1 5 2 -P in F B G A 80 Pin Number APA1000 Function Pin Number APA1000 Function Pin Number APA1000 Function Pin Number APA1000 Function C1 GND D12 I/O E23 I/O F34 NC C2 GND D13 I/O E24 I/O G1 VDD C3 NC D14 I/O E25 I/O G2 I/O C4 GND D15 I/O E26 I/O G3 GND C5 GND D16 I/O E27 I/O G4 I/O C6 I/O D17 I/O E28 VDDP G5 VDDP C7 GND D18 I/O E29 I/O G6 I/O C8 I/O D19 I/O E30 VDD G7 VDD C9 GND D20 I/O E31 I/O G8 I/O C10 I/O D21 I/O E32 GND G9 VDDP C11 I/O D22 I/O E33 GND G10 I/O C12 I/O D23 I/O E34 GND G11 I/O C13 I/O D24 I/O F1 I/O G12 I/O C14 I/O D25 I/O F2 NC G13 I/O C15 I/O D26 I/O F3 I/O G14 I/O C16 I/O D27 VDD F4 VDD G15 I/O C17 I/O D28 I/O F5 I/O G16 I/O C18 I/O D29 VDD F6 GND G17 I/O C19 I/O D30 I/O F7 I/O G18 I/O C20 I/O D31 GND F8 I/O G19 I/O C21 I/O D32 GND F9 I/O G20 I/O C22 I/O D33 GND F10 I/O G21 I/O C23 I/O D34 GND F11 I/O G22 I/O C24 I/O E1 GND F12 I/O G23 I/O C25 I/O E2 GND F13 I/O G24 I/O C26 GND E3 GND F14 I/O G25 I/O C27 I/O E4 I/O F15 I/O G26 VDDP C28 GND E5 VDD F16 I/O G27 I/O C29 I/O E6 I/O F17 I/O G28 VDD C30 GND E7 VDDP F18 I/O G29 I/O C31 GND E8 I/O F19 I/O G30 VDDP C32 NC E9 I/O F20 I/O G31 I/O C33 GND E10 I/O F21 I/O G32 GND C34 GND E11 I/O F22 I/O G33 I/O D1 GND E12 I/O F23 I/O G34 VDD D2 GND E13 I/O F24 I/O H1 VDD D3 GND E14 I/O F25 I/O H2 NC D4 GND E15 I/O F26 I/O H3 I/O D5 I/O E16 I/O F27 I/O H4 VDD D6 VDD E17 I/O F28 I/O H5 I/O D7 I/O E18 I/O F29 GND H6 I/O D8 VDD E19 I/O F30 I/O H7 I/O D9 I/O E20 I/O F31 VDD H8 GND D10 I/O E21 I/O F32 I/O H9 I/O D11 I/O E22 I/O F33 NC H10 I/O Advanced v0.3 Pr o A SI C P L U S A PA F a m ily 1 1 5 2 -P in F B G A Pin Number APA1000 Function Pin Number APA1000 Function Pin Number APA1000 Function Pin Number APA1000 Function H11 I/O J22 I/O K33 NC M10 I/O H12 I/O J23 I/O K34 VDD M11 I/O H13 I/O J24 VDDP L1 I/O M12 VDD H14 I/O J25 I/O L2 I/O M13 I/O H15 I/O J26 VDD L3 I/O M14 VDDP H16 I/O J27 I/O L4 I/O M15 VDDP H17 I/O J28 VDDP L5 I/O M16 VDDP H18 I/O J29 I/O L6 I/O M17 VDDP H19 I/O J30 I/O L7 I/O M18 VDDP H20 I/O J31 I/O L8 I/O M19 VDDP H21 I/O J32 GND L9 VDDP M20 VDDP H22 I/O J33 I/O L10 I/O M21 VDDP H23 I/O J34 VDD L11 VDD M22 I/O H24 I/O K1 VDD L12 I/O M23 VDD H25 I/O K2 NC L13 I/O M24 I/O H26 I/O K3 I/O L14 I/O M25 I/O H27 GND K4 I/O L15 I/O M26 I/O H28 I/O K5 I/O L16 I/O M27 I/O H29 I/O K6 I/O L17 I/O M28 I/O H30 I/O K7 I/O L18 I/O M29 I/O H31 VDD K8 I/O L19 I/O M30 I/O H32 I/O K9 I/O L20 I/O M31 I/O H33 NC K10 GND L21 I/O M32 I/O H34 VDD K11 I/O L22 I/O M33 GND J1 VDD K12 I/O L23 I/O M34 GND J2 I/O K13 I/O L24 VDD N1 I/O J3 GND K14 I/O L25 I/O N2 I/O J4 I/O K15 I/O L26 VDDP N3 I/O J5 I/O K16 I/O L27 I/O N4 I/O J6 I/O K17 I/O L28 I/O N5 I/O J7 VDDP K18 I/O L29 I/O N6 I/O J8 I/O K19 I/O L30 I/O N7 I/O J9 VDD K20 I/O L31 I/O N8 I/O J10 I/O K21 I/O L32 I/O N9 I/O J11 VDDP K22 I/O L33 I/O N10 I/O J12 I/O K23 I/O L34 I/O N11 I/O J13 I/O K24 I/O M1 GND N12 I/O J14 I/O K25 GND M2 GND N13 VDD J15 I/O K26 I/O M3 I/O N14 VDD J16 I/O K27 I/O M4 I/O N15 VDD J17 I/O K28 I/O M5 I/O N16 VDD J18 I/O K29 I/O M6 I/O N17 VDD J19 I/O K30 I/O M7 I/O N18 VDD J20 I/O K31 I/O M8 I/O N19 VDD J21 I/O K32 I/O M9 I/O N20 VDD Advanced v0.3 81 P r o A SI C P L U S A P A F a m ily 1 1 5 2 -P in F B G A 82 Pin Number APA1000 Function Pin Number APA1000 Function Pin Number APA1000 Function Pin Number APA1000 Function N21 VDD P32 I/O T9 I/O U20 GND N22 VDD P33 VDDP T10 I/O U21 GND N23 I/O P34 VDDP T11 I/O U22 VDD N24 I/O R1 VDDP T12 VDDP U23 VDDP N25 I/O R2 VDDP T13 VDD U24 I/O N26 I/O R3 I/O T14 GND U25 I/O N27 I/O R4 I/O T15 GND U26 I/O N28 I/O R5 I/O T16 GND U27 I/O N29 I/O R6 I/O T17 GND U28 I/O N30 I/O R7 I/O T18 GND U29 NPECL N31 I/O R8 I/O T19 GND U30 AGND N32 I/O R9 I/O T20 GND U31 I/O N33 I/O R10 I/O T21 GND U32 I/O N34 I/O R11 I/O T22 VDD U33 GND P1 VDDP R12 VDDP T23 VDDP U34 GND P2 VDDP R13 VDD T24 I/O V1 GND P3 I/O R14 GND T25 I/O V2 GND P4 I/O R15 GND T26 I/O V3 I/O P5 I/O R16 GND T27 I/O V4 AVDD P6 I/O R17 GND T28 I/O V5 GL P7 I/O R18 GND T29 I/O V6 PPECL P8 I/O R19 GND T30 I/O V7 I/O P9 I/O R20 GND T31 I/O V8 I/O P10 I/O R21 GND T32 I/O V9 I/O P11 I/O R22 VDD T33 I/O V10 I/O P12 VDDP R23 VDDP T34 I/O V11 I/O P13 VDD R24 I/O U1 GND V12 VDDP P14 GND R25 I/O U2 GND V13 VDD P15 GND R26 I/O U3 I/O V14 GND P16 GND R27 I/O U4 I/O V15 GND P17 GND R28 I/O U5 AGND V16 GND P18 GND R29 I/O U6 NPECL V17 GND P19 GND R30 I/O U7 GL V18 GND P20 GND R31 I/O U8 I/O V19 GND P21 GND R32 I/O U9 I/O V20 GND P22 VDD R33 VDDP U10 I/O V21 GND P23 VDDP R34 VDDP U11 I/O V22 VDD P24 I/O T1 I/O U12 VDDP V23 VDDP P25 I/O T2 I/O U13 VDD V24 I/O P26 I/O T3 I/O U14 GND V25 I/O P27 I/O T4 I/O U15 GND V26 I/O P28 I/O T5 I/O U16 GND V27 I/O P29 I/O T6 I/O U17 GND V28 PPECL P30 I/O T7 I/O U18 GND V29 GL P31 I/O T8 I/O U19 GND V30 GL Advanced v0.3 Pr o A SI C P L U S A PA F a m ily 1 1 5 2 -P in F B G A Pin Number APA1000 Function Pin Number APA1000 Function Pin Number APA1000 Function Pin Number APA1000 Function V31 AVDD W15 GND W33 I/O Y17 GND V32 I/O W16 GND W34 I/O Y18 GND V33 GND W17 GND Y1 VDDP Y19 GND V34 GND W18 GND Y2 VDDP Y20 GND W1 I/O W19 GND Y3 I/O Y21 GND W2 I/O W20 GND Y4 I/O Y22 VDD W3 I/O W21 GND Y5 I/O Y23 VDDP W4 I/O W22 VDD Y6 I/O Y24 I/O W5 I/O W23 VDDP Y7 I/O Y25 I/O W6 I/O W24 I/O Y8 I/O Y26 I/O W7 I/O W25 I/O Y9 I/O Y27 I/O W8 I/O W26 I/O Y10 I/O Y28 I/O W9 I/O W27 I/O Y11 I/O Y29 I/O W10 I/O W28 I/O Y12 VDDP Y30 I/O W11 I/O W29 I/O Y13 VDD Y31 I/O W12 VDDP W30 I/O Y14 GND Y32 I/O W13 VDD W31 I/O Y15 GND Y33 VDDP W14 GND W32 I/O Y16 GND Y34 VDD Advanced v0.3 83 P r o A SI C P L U S A P A F a m ily Li s t o f C ha ng e s The following table lists critical changes that were made in the current version of the document. Previous version Advanced v0.1 Changes in current version (Advanced v0.1) Figure 15 on page 15 has been updated Page page 15 D at a S he et Ca t e g o r i e s In order to provide the latest information to designers, some data sheets are published before data has been fully characterized. Product Briefs are modified versions of data sheets. Data sheets are marked as "Advanced," "Preliminary," and "Web-only." The definition of these categories are as follows: P rod uct B ri ef The product brief is a modified version of an Advanced data sheet containing general product information. This brief summarizes specific device and family information for non-release products. Adv anc ed The data sheet contains initial estimated information based on simulation, other products, devices, or speed grades. This information can be used as estimates, but not for production. P rel im i nar y The data sheet contains information based on simulation and/or initial characterization. The information is believed to be correct, but changes are possible. Unm ar ked (pr odu ct ion) The data sheet contains information that is considered to be final. W eb- only V er si ons Web-only versions have three numbers in the version number (example: v2.0.1). A web-only version means Actel is posting the data sheet so customers have the latest information, but we are not printing the version because some information is going to change shortly after posting. 84 Advanced v0.3 Pr o A SI C P L U S A PA F a m ily Advanced v0.3 85 P r o A SI C P L U S A P A F a m ily 86 Advanced v0.3 Pr o A SI C P L U S A PA F a m ily Advanced v0.3 87 Actel and the Actel logo are registered trademarks of Actel Corporation. All other trademarks are the property of their owners. http://www.actel.com Actel Europe Ltd. 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