3.3 V, 200 Mbps, Half- and Full-Duplex,
High Speed M-LVDS Transceivers
Data Sheet
ADN4691E/ADN4693E/ADN4696E/ADN4697E
Rev. B Document Feedback
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FEATURES
Multipoint LVDS transceivers (low voltage differential
signaling driver and receiver pairs)
Switching rate: 200 Mbps (100 MHz)
Supported bus loads: 30 Ω to 55 Ω
Choice of 2 receiver types
Type 1 (ADN4691E/ADN4693E): hysteresis of 25 mV
Type 2 (ADN4696E/ADN4697E): threshold offset of 100 mV
for open-circuit and bus-idle fail-safe
Conforms to TIA/EIA-899 standard for M-LVDS
Glitch free power-up/power-down on M-LVDS bus
Controlled transition times on driver output
Common-mode range: −1 V to +3.4 V, allowing
communication with 2 V of ground noise
Driver outputs high-Z when disabled or powered off
Enhanced ESD protection on bus pins
±15 kV HBM (human body model), air discharge
±8 kV HBM (human body model), contact discharge
±10 kV IEC 61000-4-2, air discharge
±8 kV IEC 61000-4-2, contact discharge
Operating temperature range: −40°C to +85°C
Available in 8-lead (ADN4691E/ADN4696E) and 14-lead
(ADN4693E/ADN4697E) SOIC packages
APPLICATIONS
Backplane and cable multipoint data transmission
Multipoint clock distribution
Low power, high speed alternative to shorter RS-485 links
Networking and wireless base station infrastructure
FUNCTIONAL BLOCK DIAGRAMS
ADN4691E/
ADN4696E
V
CC
GND
RO R
D
RE
DE
A
B
DI
10355-001
Figure 1.
ADN4693E/
ADN4697E
V
CC
GND
RO R
D
RE
DE
DI
10355-002
A
B
Z
Y
Figure 2.
GENERAL DESCRIPTION
The ADN4691E/ADN4693E/ADN4696E/ADN4697E are
multipoint, low voltage differential signaling (M-LVDS)
transceivers (driver and receiver pairs) that can operate at up to
200 Mbps (100 MHz). The receivers detect the bus state with a
differential input of as little as 50 mV over a common-mode
voltage range of −1 V to +3.4 V. ESD protection of up to ±15 kV
is implemented on the bus pins. The devices adhere to the
TIA/EIA-899 standard for M-LVDS and complement TIA/EIA-
644 LVDS devices with additional multipoint capabilities.
The ADN4691E/ADN4693E are Type 1 receivers with 25 mV of
hysteresis so that slow-changing signals or loss of input does not
lead to output oscillations. The ADN4696E/ADN4697E are
Type 2 receivers exhibiting an offset threshold, guaranteeing the
output state when the bus is idle (bus-idle fail-safe) or the inputs are
open (open-circuit fail-safe).
The devices are available as half-duplex in an 8-lead SOIC package
(the ADN4691E/ADN4696E) or as full-duplex in a 14-lead
SOIC package (the ADN4693E/ADN4697E). A selection table
for the ADN4690E to ADN4697E devices is shown in Table 1.
Table 1. ADN4690E to ADN4697E Selection Table
Part No. Receiver Data Rate SOIC Duplex
ADN4690E Type 1 100 Mbps 8-lead Half
ADN4691E Type 1 200 Mbps 8-lead Half
ADN4692E Type 1 100 Mbps 14-lead Full
ADN4693E Type 1 200 Mbps 14-lead Full
ADN4694E Type 2 100 Mbps 8-lead Half
ADN4695E Type 2 100 Mbps 14-lead Full
ADN4696E Type 2 200 Mbps 8-lead Half
ADN4697E Type 2 200 Mbps 14-lead Full
ADN4691E/ADN4693E/ADN4696E/ADN4697E Data Sheet
Rev. B | Page 2 of 20
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagrams ............................................................. 1
General Description ......................................................................... 1
Revision History ........................................................................... 2
Specifications ..................................................................................... 3
Receiver Input Threshold Test Voltages .................................... 4
Timing Specifications .................................................................. 5
Absolute Maximum Ratings ............................................................ 6
Thermal Resistance ...................................................................... 6
ESD Caution .................................................................................. 6
Pin Configurations and Function Descriptions ........................... 7
Typical Performance Characteristics ............................................. 8
Test Circuits and Switching Characteristics ................................ 11
Driver Voltage and Current Measurements ............................ 11
Driver Timing Measurements .................................................. 12
Receiver Timing Measurements ............................................... 13
Theory of Operation ...................................................................... 14
Half-Duplex/Full-Duplex Operation ....................................... 14
Three-State Bus Connection ..................................................... 14
Truth Tables................................................................................. 14
Glitch-Free Power-Up/Power-Down ....................................... 15
Fault Conditions ......................................................................... 15
Receiver Input Thresholds/Fail-Safe ........................................ 15
Applications Information .............................................................. 16
Outline Dimensions ....................................................................... 17
Ordering Guide .......................................................................... 17
REVISION HISTORY
1/16—Rev. A to Rev. B
Change to Table 6 ............................................................................. 6
3/12—Rev. 0 to Rev. A
Added ADN4691E and ADN4693E ................................. Universal
Changes to Features Section, General Description Section,
and Table 1 ......................................................................................... 1
Added Type 1 Receiver Parameters, Table 2 ................................. 3
Added Table 3, Renumbered Sequentially .................................... 4
Added Type 1 Receiver Parameters, Table 5 ................................. 5
Added Table 7 .................................................................................... 6
Changes to Table 8 ............................................................................. 7
Changes to Figure 33 ...................................................................... 13
Added Table 12 ............................................................................... 14
Changes to Receiver Input Thresholds/Fail-Safe Section
and Figure 36 ................................................................................... 15
Changes to Ordering Guide .......................................................... 17
12/11—Revision 0: Initial Version
Data Sheet ADN4691E/ADN4693E/ADN4696E/ADN4697E
Rev. B | Page 3 of 20
SPECIFICATIONS
VCC = 3.0 V to 3.6 V; RL = 50 Ω; TA = TMIN to TMAX, unless otherwise noted. 1
Table 2.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
DRIVER
Differential Outputs
Differential Output Voltage Magnitude |VOD| 480 650 mV See Figure 19
∆|VOD| for Complementary Output States ∆|VOD| −50 +50 mV See Figure 19
Common-Mode Output Voltage (Steady State) VOC(SS) 0.8 1.2 V See Figure 20, Figure 23
ΔVOC(SS) for Complementary Output States ΔVOC(SS) −50 +50 mV See Figure 20, Figure 23
Peak-to-Peak VOC VOC(PP) 150 mV See Figure 20, Figure 23
Maximum Steady-State Open-Circuit Output
Voltage
VA(O), VB(O),
VY(O), or VZ(O)
0 2.4 V See Figure 21
Voltage Overshoot
Low to High VPH 1.2 VSS V See Figure 24, Figure 27
High to Low VPL −0.2 VSS V See Figure 24, Figure 27
Output Current
Short Circuit |IOS| 24 mA See Figure 22
High Impedance State, Driver Only IOZ −15 +10 µA –1.4 V ≤ (VY or VZ) ≤ 3.8 V,
other output = 1.2 V
Power Off IO(OFF) −10 +10 µA –1.4 V ≤ (VY or VZ) ≤ 3.8 V,
other output = 1.2 V, 0 V ≤ VCC ≤ 1.5 V
Output Capacitance CY or CZ 3 pF VI = 0.4 sin(30e6πt) V + 0.5 V,2
other output = 1.2 V, DE = 0 V
Differential Output Capacitance CYZ 2.5 pF VAB = 0.4 sin(30e6πt) V,2 DE = 0 V
Output Capacitance Balance (CY/CZ) CY/Z 0.99 1.01
Logic Inputs (DI, DE)
Input High Voltage
V
IH
2
V
CC
V
Input Low Voltage VIL GND 0.8 V
Input High Current IIH 0 10 µA VIH = 2 V
Input Low Current IIL 0 10 µA VIL = 0.8 V
RECEIVER
Differential Inputs
Differential Input Threshold Voltage
Type 1 Receiver (ADN4691E, ADN4693E) VTH −50 +50 mV See Table 3, Figure 36
Type 2 Receiver (ADN4696E, ADN4697E) VTH 50 150 mV See Table 4, Figure 36
Input Hysteresis
Type 1 Receiver (ADN4691E, ADN4693E) VHYS 25 mV
Type 2 Receiver (ADN4696E, ADN4697E) VHYS 0 mV
Differential Input Voltage Magnitude |VID| 0.05 VCC V
Input Capacitance CA or CB 3 pF VI = 0.4 sin(30e6πt) V + 0.5 V,2
other input = 1.2 V
Differential Input Capacitance CAB 2.5 pF VAB = 0.4 sin(30e6πt) V2
Input Capacitance Balance (CA/CB) CA/B 0.99 1.01
Logic Output RO
Output High Voltage VOH 2.4 V IOH = –8 mA
Output Low Voltage VOL 0.4 V IOL = 8 mA
High Impedance Output Current IOZ −10 +15 µA VO = 0 V or 3.6 V
Logic Input RE
Input High Voltage VIH 2 VCC V
Input Low Voltage VIL GND 0.8 V
Input High Current
I
IH
−10
0
µA
V
IH
= 2 V
Input Low Current IIL −10 0 µA VIL = 0.8 V
ADN4691E/ADN4693E/ADN4696E/ADN4697E Data Sheet
Rev. B | Page 4 of 20
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
BUS INPUT/OUTPUT
Input Current
A (Receiver or Transceiver with Driver Disabled) IA 0 32 µA VB = 1.2 V, VA = 3.8 V
−20 +20 µA VB = 1.2 V, VA = 0 V or 2.4 V
−32
0
µA
V
B
= 1.2 V, V
A
= −1.4 V
B (Receiver or Transceiver with Driver Disabled) IB 0 32 µA VA = 1.2 V, VB = 3.8 V
−20 +20 µA VA = 1.2 V, VB = 0 V or 2.4 V
−32 0 µA VA = 1.2 V, VB = −1.4 V
Differential (Receiver or Transceiver with Driver
Disabled)
IAB −4 +4 µA VA = VB, 1.4 V ≤ VA ≤ 3.8 V
Power-Off Input Current
0 V ≤ V
CC
≤ 1.5 V
A (Receiver or Transceiver) IA(OFF) 0 32 µA VB = 1.2 V, VA = 3.8 V
−20 +20 µA VB = 1.2 V, VA = 0 V or 2.4 V
−32 0 µA VB = 1.2 V, VA = −1.4 V
B (Receiver or Transceiver) IB(OFF) 0 32 µA VA = 1.2 V, VB = 3.8 V
−20 +20 µA VA = 1.2 V, VB = 0 V or 2.4 V
−32 0 µA VA = 1.2 V, VB = −1.4 V
Differential (Receiver or Transceiver) IAB(OFF) −4 +4 µA VA = VB, 1.4 ≤ VA ≤ 3.8 V
Input Capacitance (Transceiver with Driver Disabled) CA or CB 5 pF VI = 0.4 sin(30e6πt) V + 0.5 V,2
other input = 1.2 V, DE = 0 V
Differential Input Capacitance (Transceiver with
Driver Disabled)
CAB 3 pF VAB = 0.4 sin(30e6πt) V,2 DE = 0 V
Input Capacitance Balance (CA/CB) (Transceiver
with Driver Disabled)
CA/B 0.99 1.01 DE = 0 V
POWER SUPPLY
Supply Current ICC
Only Driver Enabled 13 22 mA DE, RE = VCC, RL = 50 Ω
Both Driver and Receiver Disabled 1 4 mA DE = 0 V, RE= VCC, RL = no load
Both Driver and Receiver Enabled 16 24 mA DE = VCC, RE = 0 V, RL = 50 Ω
Only Receiver Enabled
13
mA
DE,
RE
= 0 V, R
L
= 50 Ω
1 All typical values are given for VCC = 3.3 V and TA = 25°C.
2 HP4194A impedance analyzer (or equivalent).
RECEIVER INPUT THRESHOLD TEST VOLTAGES
RE = 0 V, H = high, L = low
Table 3. Test Voltages for Type 1 Receiver
Applied Voltages Input Voltage, Differential Input Voltage, Common Mode Receiver Output
VA (V) VB (V) VID (V) VIC (V) RO (V)
2.4 0 2.4 1.2 H
0 2.4 −2.4 1.2 L
3.8 3.75 0.05 3.775 H
3.75 3.8 −0.05 3.775 L
−1.35 −1.4 0.05 −1.375 H
−1.4 −1.35 −0.05 −1.375 L
Data Sheet ADN4691E/ADN4693E/ADN4696E/ADN4697E
Rev. B | Page 5 of 20
Table 4. Test Voltages for Type 2 Receiver
Applied Voltages Input Voltage, Differential Input Voltage, Common Mode Receiver Output
VA (V) VB (V) VID (V) VIC (V) RO (V)
+2.4 0 +2.4 +1.2 H
0 +2.4 −2.4 +1.2 L
+3.8 +3.65 +0.15 +3.725 H
+3.8 +3.75 +0.05 +3.775 L
−1.25 −1.4 +0.15 −1.325 H
−1.35 −1.4 +0.05 −1.375 L
TIMING SPECIFICATIONS
VCC = 3.0 V to 3.6 V; TA = TMIN to TMAX, unless otherwise noted.1
Table 5.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
DRIVER
Maximum Data Rate 200 Mbps
Propagation Delay
t
PLH
, t
PHL
1
1.5
2.4
ns
See Figure 24, Figure 27
Differential Output Rise/Fall Time tR, tF 1 1.6 ns See Figure 24, Figure 27
Pulse Skew |tPHL – tPLH| tSK 0 100 ps See Figure 24, Figure 27
Part-to-Part Skew2 tSK(PP) 1 ns See Figure 24, Figure 27
Period Jitter, RMS (1 Standard Deviation)3 tJ(PER) 2 3 ps 100 MHz clock input4 (see Figure 26)
Peak-to-Peak Jitter3, 5 tJ(PP) 30 130 ps 200 Mbps 215 − 1 PRBS input6 (see Figure 29)
Disable Time from High Level tPHZ 7 ns See Figure 25, Figure 28
Disable Time from Low Level tPLZ 7 ns See Figure 25, Figure 28
Enable Time to High Level tPZH 7 ns See Figure 25, Figure 28
Enable Time to Low Level tPZL 7 ns See Figure 25, Figure 28
RECEIVER
Propagation Delay tRPLH, tRPHL 2 4 6 ns CL = 15 pF (see Figure 30, Figure 33)
Rise/Fall Time tR, tF 1 2.3 ns CL = 15 pF (see Figure 30, Figure 33)
Pulse Skew |tRPHL – tRPLH| tSK CL = 15 pF (see Figure 30, Figure 33)
Type 1 Receiver (ADN4691E, ADN4693E)
100
300
ps
Type 2 Receiver (ADN4696E, ADN4697E) 300 500 ps
Part-to-Part Skew2 tSK(PP) 1 ns CL = 15 pF (see Figure 30, Figure 33)
Period Jitter, RMS (1 Standard Deviation)3 tJ(PER) 4 7 ps 100 MHz clock input7 (see Figure 32)
Peak-to-Peak Jitter3, 5 tJ(PP) 200 Mbps 215 − 1 PRBS input8 (see Figure 35)
Type 1 Receiver (ADN4691E, ADN4693E) tJ(PP) 300 700 ps
Type 2 Receiver (ADN4696E, ADN4697E) 450 800 ps
Disable Time from High Level tRPHZ 10 ns See Figure 31, Figure 34
Disable Time from Low Level tRPLZ 10 ns See Figure 31, Figure 34
Enable Time to High Level tRPZH 15 ns See Figure 31, Figure 34
Enable Time to Low Level tRPZL 15 ns See Figure 31, Figure 34
1 All typical values are given for VCC = 3.3 V and TA = 25°C.
2 tSK(PP) is defined as the difference between the propagation delays of two devices between any specified terminals. This specification applies to devices at the same VCC
and temperature, and with identical packages and test circuits.
3 Jitter parameters are guaranteed by design and characterization. Values do not include stimulus jitter.
4 tR = tF = 0.5 ns (10% to 90%), measured over 30,000 samples.
5 Peak-to-peak jitter specifications include jitter due to pulse skew (tSK).
6 tR = tF = 0.5 ns (10% to 90%), measured over 100,000 samples.
7 |VID| = 400 mV (ADN4696E, ADN4697E), VIC = 1.1 V, tR = tF = 0.5 ns (10% to 90%), measured over 30,000 samples.
8 |VID| = 400 mV (ADN4696E, ADN4697E), VIC = 1.1 V, tR = tF = 0.5 ns (10% to 90%), measured over 100,000 samples.
ADN4691E/ADN4693E/ADN4696E/ADN4697E Data Sheet
Rev. B | Page 6 of 20
ABSOLUTE MAXIMUM RATINGS
TA = TMIN to TMAX, unless otherwise noted.
Table 6.
Parameter Rating
VCC −0.5 V to +4 V
Digital Input Voltage (DE, RE, DI) −0.5 V to +4 V
Receiver Input (A, B) Voltage
Half-Duplex (ADN4691E, ADN4696E) −1.8 V to +4 V
Full-Duplex (ADN4693E, ADN4697E) −4 V to +6 V
Receiver Output Voltage (RO)
−0.3 V to +4 V
Driver Output (A, B, Y, Z) Voltage −1.8 V to +4 V
ESD Rating (A, B, Y, Z Pins)
HBM (Human Body Model)
Air Discharge ±15 kV
Contact Discharge ±8 kV
IEC 61000-4-2, Air Discharge ±10 kV
IEC 61000-4-2, Contact Discharge ±8 kV
ESD Rating (Other Pins, HBM) ±4 kV
ESD Rating (All Pins)
FICDM ±1.25 kV
Operating Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
θJA is specified for the worst case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 7. Thermal Resistance
Package Type θJA Unit
8-Lead SOIC 121 °C/W
14-Lead SOIC 86 °C/W
ESD CAUTION
Data Sheet ADN4691E/ADN4693E/ADN4696E/ADN4697E
Rev. B | Page 7 of 20
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
R
O
1
RE
2
DE
3
DI
4
V
CC
8
B
7
A
6
GND
5
ADN4691E/
ADN4696E
TOP VIEW
(Not to Scal e)
10355-003
Figure 3. ADN4691E/ADN4696E Pin Configuration
NC
1
2
3
4
V
CC
14
13
12
11
510
GND
6
Y
9
GND
7
NC
8
NC = NO CONNECT
ADN4693E/
ADN4697E
TOP V IEW
(No t t o Scale)
RO
RE
DE
DI
V
CC
A
B
Z
10355-004
Figure 4. ADN4693E/ADN4697E Pin Configuration
Table 8. Pin Function Descriptions
ADN4691E/
ADN4696E
Pin No.1
ADN4693E/
ADN4697E
Pin No.1 Mnemonic Description
1 2 RO Receiver Output. Type 1 receiver (ADN4691E/ADN4693E), when enabled:
If A − B ≥ 50 mV, then RO = logic high. If A − B ≤ −50 mV, then RO = logic low.
Type 2 receiver (ADN4696E/ADN4697E), when enabled:
If A − B ≥ 150 mV, then RO = logic high. If A − B ≤ 50 mV, then RO = logic low.
Receiver output is undefined outside these conditions.
2 3 RE Receiver Output Enable. A logic low on this pin enables the receiver output, RO. A logic high on this
pin places RO in a high impedance state.
3 4 DE
Driver Output Enable. A logic high on this pin enables the driver differential outputs. A logic
low on this pin places the driver differential outputs in a high impedance state.
4 5 DI Driver Input. Half-duplex (ADN4691E/ADN4696E), when enabled:
A logic low on DI forces A low and B high, whereas a logic high on DI forces A high and B low.
Full-duplex (ADN4693E/ADN4697E), when enabled:
A logic low on DI forces Y low and Z high, whereas a logic high on DI forces Y high and Z low.
5 6, 7 GND Ground.
N/A 9 Y Noninverting Driver Output Y.
N/A 10 Z Inverting Driver Output Z.
6 N/A A Noninverting Receiver Input A and Noninverting Driver Output A.
N/A 12 A Noninverting Receiver Input A.
7 N/A B Inverting Receiver Input B and Inverting Driver Output B.
N/A 11 B Inverting Receiver Input B.
8 13, 14 VCC Power Supply (3.3 V ± 0.3 V).
N/A 1, 8 NC No Connect. Do not connect to these pins.
1 N/A means not applicable.
ADN4691E/ADN4693E/ADN4696E/ADN4697E Data Sheet
Rev. B | Page 8 of 20
TYPICAL PERFORMANCE CHARACTERISTICS
0
2
4
6
8
10
12
14
16
18
20
020 40 60 80 100 120
SUPPLY CURREN T, ICC (mA)
FREQUENCY (MHz)
DRIVER
RECEIVER (VID = 250mV , VIC = 1V)
10355-005
Figure 5. Power Supply Current (ICC) vs. Frequency
(VCC = 3.3 V, TA = 25°C; Receiver VID = 250 mV, VIC = 1 V)
0
2
4
6
8
10
12
14
16
18
20
–50 –30 –10 10 30 50 70 90
SUPPLY CURREN T, I
CC
(mA)
TEMPERAT URE ( °C)
DRIVER
RECEIVER (V
ID
= 250mV, V
IC
= 1V)
10355-006
Figure 6. Power Supply Current vs. Temperature (Data Rate = 200 Mbps,
VCC = 3.3 V; Receiver VID = 250 mV, VIC = 1 V)
0
5
10
15
20
25
30
35
40
00.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
RECEIVER LOW LEVEL OUT P UT CURRENT, I
OL
(mA)
RECEIVER LOW LEVEL OUTPUT VOLTAGE, V
OL
(V)
V
CC
=3V
V
CC
=3.3V
V
CC
=3.6V
10355-007
Figure 7. Receiver Output Current vs. Output Voltage (Output Low)
(TA = 25°C)
–50
–45
–40
–35
–30
–25
–20
–15
–10
–5
0
00.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
RECEIVER HIGH LEVEL OUT P UT CURRENT (mA)
RECEIVER HIGH LEVEL OUTPUT VOLTAGE, V
OH
(V)
V
CC
= 3.0V
V
CC
= 3.3V
V
CC
= 3.6V
10355-008
Figure 8. Receiver Output Current vs. Output Voltage (Output High)
(TA = 25°C)
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
0246810 12 14
DIFFERENTIAL OUTPUT VOLTAGE, VOD (V)
OUTPUT CURRE NT, IO (mA)
10355-009
Figure 9. Driver Differential Output Voltage vs. Output Current
(VCC = 3.3 V, TA = 25°C)
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
–40 –20 020 40 60 80
DRIVE R P ROPAGAT IO N DE LAY (ns)
TEMPERATURE, TA (°C)
t
PLH
t
PHL
10355-010
Figure 10. Driver Propagation Delay vs. Temperature
(Data Rate = 2 Mbps, VCC = 3.3 V)
Data Sheet ADN4691E/ADN4693E/ADN4696E/ADN4697E
Rev. B | Page 9 of 20
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
–50 –30 –10 10 30 50 70 90
RECEIVER PROPAGATION DELAY (ns)
TEMPERAT URE , T
A
(° C)
t
RPLH
t
RPHL
10355-011
Figure 11. Receiver Propagation Delay vs. Temperature
(Data Rate = 2 Mbps, VCC = 3.3 V, VID = 400 mV, VIC = 1.1 V)
0
0.5
1.0
1.5
2.0
2.5
3.0
20 30 40 50 60 70 80 90 100
ADDED DRIV E R P E RIO D JIT TER ( ps)
FREQUENCY (MHz)
10355-012
Figure 12. Driver Jitter (Period) vs. Frequency
(VCC = 3.3 V, TA = 25°C, Clock Input)
0
20
40
60
80
100
120
020 40 60 80 100 120 140 160 180 200
ADDED DRIV E R P E AK-TO-PEAK JIT TER ( ps)
DATA RATE (Mb p s)
10355-013
Figure 13. Driver Jitter (Peak-to-Peak) vs. Data Rate
(VCC = 3.3 V, TA = 25°C, PRBS 215 − 1 Input)
0
20
40
60
80
100
120
–50 –30 –10 10 30 50 70 90
ADDED DRIV E R P E AK-TO-PE AK JITTER ( ps)
TEMPERAT URE , T
A
(° C)
10355-014
Figure 14. Driver Jitter (Peak-to-Peak) vs. Temperature
(Data Rate = 200 Mbps, VCC = 3.3 V, PRBS 215 − 1 Input)
0
1
2
3
4
5
6
7
020 40 60 80 100 120
ADDED RECEIVE R P E RIO D JITTER (ps)
FREQUENCY (MHz)
10355-015
Figure 15. Receiver Jitter (Period) vs. Frequency
(VCC = 3.3 V, TA = 25°C, VID = 400 mV)
0
100
200
300
400
500
600
700
800
–50 –30 –10 10 30 50 70 90
ADDED RECEIVE R P E AK–TO –P E AK JIT TER (ps)
TEMPERAT URE ( °C)
10355-016
Figure 16. Receiver Jitter (Peak-to-Peak) vs. Temperature
(Data Rate = 200 Mbps, VCC = 3.3 V, VID = 400 mV, VIC = 1.1 V,
PRBS 215 − 1 Input)
ADN4691E/ADN4693E/ADN4696E/ADN4697E Data Sheet
Rev. B | Page 10 of 20
10355-017
1ns/DIV
200mV/DIV
Figure 17. ADN4696E Driver Output Eye Pattern
(Data Rate = 200 Mbps, PRBS 215 − 1 Input, RL = 50 Ω)
10355-018
2.5ns/DIV
500mV/DIV
Figure 18. ADN4696E Receiver Output Eye Pattern
(Data Rate = 200 Mbps, PRBS 215 − 1 Input, CL = 15 pF)
Data Sheet ADN4691E/ADN4693E/ADN4696E/ADN4697E
Rev. B | Page 11 of 20
TEST CIRCUITS AND SWITCHING CHARACTERISTICS
DRIVER VOLTAGE AND CURRENT MEASUREMENTS
DI
NOTES
1. 1% TOLERANCE FOR ALL RESISTORS
VOD
VTEST
49.9Ω
3.32kΩ
+
–
3.32kΩ –1V TO + 3.4V
10355-019
A/Y
B/Z
Figure 19. Driver Voltage Measurement over Common-Mode Range
DI
NOTES
1. C1, C2, AND C3 ARE 20% AND I NCLUDE PROBE/ST RAY
CAPACITANCE LE S S THAN 2cm F ROM DUT.
2. R1 AND R2 ARE 1%, METAL FILM, SURFACE MOUNT,
LES S THAN 2cm F ROM DUT.
V
OC
R1
24.9Ω
C1
1pF
C2
1pF
C3
2.5pF
R2
24.9Ω
10355-020
A/Y
B/Z
Figure 20. Driver Common-Mode Output Voltage Measurement
S1 S2
V
A(O)
, V
B(O)
,
V
Y(O)
OR V
Z(O)
A/Y
V
CC
R1
1.62kΩ
±1%
B/ZDE
10355-021
Figure 21. Maximum Steady-State Output Voltage Measurement
S1 DI S2
A/Y
B/Z V
TEST
V
CC
I
OS
–1V O R +3.4V
10355-022
Figure 22. Driver Short Circuit
NOTES
1. INPUT PULSE GENERATOR: 500kHz ; 50% ± 5% DUTY CYCLE; tR, tF ≤ 1ns.
2. VOC(PP) MEASURED ON TEST EQUIPMENT WITH –3dB BANDWIDTH ≥ 1GHz.
VOC(PP)
ΔVOC(SS)
VOC
B/Z
A/Y
≈ 0.7V
≈ 1.3V
10355-023
Figure 23. Driver Common-Mode Output Voltage (Steady State)
ADN4691E/ADN4693E/ADN4696E/ADN4697E Data Sheet
Rev. B | Page 12 of 20
DRIVER TIMING MEASUREMENTS
DI
NOTES
1. C1, C2, AND C3 ARE 20% AND I NCLUDE PROBE/ST RAY
CAPACITANCE LE S S THAN 2cm F ROM DUT.
2. R1 I S 1%, METAL FILM, SURFACE MOUN T,
LES S THAN 2cm F ROM DUT.
OUT
C1
1pF C3
0.5pF
C2
1pF
10355-024
A/Y
B/Z
R1
50Ω
Figure 24. Driver Timing Measurement
DI
DE
S1
VCC
NOTES
1. C1, C2, C3, AND C4 ARE 20% AND INCLUDE P ROBE/ S TRAY
CAPACITANCE LE S S THAN 2cm F ROM DUT.
2. R1 AND R2 ARE 1%, METAL FILM, SURFACE MOUN T,
LES S THAN 2cm F ROM DUT.
R1
24.9Ω
C1
1pF
C2
1pF
C3
2.5pF
R2
24.9Ω
10355-025
A/Y
B/Z
C4
0.5pF OUT
Figure 25. Driver Enable/Disable Time
NOTES
1. INPUT PULSE GENERATOR: AG IL E NT 8304A STIMULUS SYSTEM;
100MHz; 50% ± 1% DUTY CYCLE.
2. ME AS URE D US ING TEK TDS6604 W IT H TDSJIT 3 S O FTWARE.
VCC/2 VCC/2
VCC
0V 1/f0
INPUT
(CLOCK)
10355-026
0V 0V
1/f0
OUTPUT
VA – VB
OR
VY – VZ
(IDEAL)
0V 0V
tc(n)
tJ(PER) = |tc(n) – 1/f 0|
OUTPUT
VA – VB
OR
VY – VZ
(ACTUAL )
Figure 26. Driver Period Jitter Characteristics
NOTES
1. INPUT PULSE GENERATOR: 500kHz ; 50% ± 5% DUTY CYCLE; t
R
,t
F
≤ 1ns.
2. MEASURED ON TEST EQUIPMENT WITH –3dB BANDWIDTH ≥ 1GHz.
t
PLH
t
R
t
F
t
PHL
V
CC
V
SS
V
PH
V
PL
0% V
SS
10% V
SS
90% V
SS
0V
0V 0V
OUT
DI
10355-027
10% V
SS
90% V
SS
0.5V
CC
0.5V
CC
Figure 27. Driver Propagation, Rise/Fall Times and Voltage Overshoot
0.5VCC 0.5VCC
VCC
0V
0V
0V
~ –0.6V
~ 0.6V
–0.1V
0.1V 0.1V
DE
OUT
(DI = 0V )
OUT
(DI = VCC)
10355-028
t
PZH
t
PZL
–0.1V
t
PHZ
t
PLZ
NOTES
1. INPUT PULSE GENERATOR: 500kHz ; 50% ± 5% DUTY CYCLE;
t
R,
t
F≤ 1ns.
2. MEASURED ON TEST EQUIPMENT WITH –3dB BANDWIDTH ≥ 1GHz.
Figure 28. Driver Enable/Disable Times
NOTES
1. INPUT PULSE GENERATOR: AG IL E NT 8304A STIMULUS SYSTEM;
200Mb ps; 2
15
– 1PRBS.
2. ME AS URE D US ING TEK TDS6604 W IT H TDSJIT3 S OF TWARE.
V
A
– V
B
OR
V
Y
– V
Z
V
A
– V
B
OR
V
Y
– V
Z
V
CC
OUTPUT
INPUT
(PRBS)
0V
0.5V
CC
t
J(PP)
0V 0V
0.5V
CC
10355-029
Figure 29. Driver Peak-to-Peak Jitter Characteristics
Data Sheet ADN4691E/ADN4693E/ADN4696E/ADN4697E
Rev. B | Page 13 of 20
RECEIVER TIMING MEASUREMENTS
A
NOTES
1. C
L
IS 20%, CERAM IC, S UR FACE MOUNT, AND INCL UDE S
PROBE/STRAY CAPACITANCE < 2cm FRO M DUT.
V
OUT
C
L
15pF
B
10355-030
RO
RE
V
ID
Figure 30. Receiver Timing Measurement
A
1.4V
1.0V
1.2V
RE INP UT
NOTES
1. C
L
IS 20% AND INCLUDE S P ROBE/STR AY
CAPACITANCE < 2cm F ROM DUT.
2. R
L
IS 1% M ETAL FILM, SURFACE MOUN T, <2cm FRO M DUT.
V
OUT
C
L
15pF
R
L
499Ω
B
10355-031
RO
RE
V
TEST
Figure 31. Receiver Enable/Disable Time
NOTES
1. INPUT PULSE GENERATOR: AG IL E NT 8304A STIMULUS SYSTEM;
100MHz; 50% ± 1% DUTY CYCLE.
2. ME AS URE D US ING TEK TDS6604 W IT H TDSJIT3 S OF TWARE.
V
OH
V
OL
0V 1/f0
INPUT
(V
A
– V
B
)
10355-032
0.5V
CC
0.5V
CC
0.5V
CC
0.5V
CC
1/f0
OUTPUT
(IDEAL)
V
OH
V
OL
OUTPUT
(ACTUAL)
t
c(n)
t
J(PER)
= |
t
c(n)
– 1f0|
Figure 32. Receiver Period Jitter Characteristics
NOTES
1. INPUT PULSE GENERATOR: 50MHz; 50% ± 5% DUTY CYCLE; t
R
, t
F
≤ 1ns.
2. MEASURED ON TEST EQUIPMENT WITH –3dB BANDWIDTH ≥ 1GHz.
t
RPHL
V
A
0.5V
CC
0.5V
CC
V
B
V
OH
V
OL
V
ID
V
OUT
0V
90%
10%
90%
10%
0V
t
F
t
RPLH
t
R
10355-033
Figure 33. Receiver Propagation and Rise/Fall Times
0.5VCC 0.5VCC
VCC
0V
VCC
0V
VOL
VOH
0.5VCC
0.5VCC
VOH – 0.5V
RE INP UT
(VTEST = VCC)
(A = 1V)
VOUT
VOUT
(VTEST = 0V)
(A = 1.4V)
10355-034
t
RPZH
t
RPZL
VOL + 0.5V
t
RPHZ
t
RPLZ
NOTES
1. INPUT PULSE GENERATOR: 500kHz ; 50% ± 5% DUTY CYCLE ;
t
R,
t
F≤ 1ns.
Figure 34. Receiver Enable/Disable Times
NOTES
1. INPUT PULSE GENERATOR: AG IL E NT 8304A STIMULUS SYSTEM;
200Mb ps; 2
15
– 1PRBS.
2. M E AS URED US ING TEK TDS6604 WI TH TDS JIT 3 S OF TWARE.
V
OH
V
OL
V
A
V
B
OUTPUT
INPUT
(PRBS)
t
J(PP)
0.5V
CC
0.5V
CC
10355-035
Figure 35. Receiver Peak-to-Peak Jitter Characteristics
ADN4691E/ADN4693E/ADN4696E/ADN4697E Data Sheet
Rev. B | Page 14 of 20
THEORY OF OPERATION
The ADN4691E/ADN4693E/ADN4696E/ADN4697E are trans-
ceivers for transmitting and receiving multipoint, low voltage
differential signaling (M-LVDS) at high speed (data rates up
to 200 Mbps). Each device has a differential line driver and a
differential line receiver, allowing each device to send and
receive data.
Multipoint LVDS expands on the established LVDS low voltage
differential signaling method by allowing bidirectional commu-
nication between more than two nodes. Up to 32 nodes can
connect on an M-LVDS bus.
HALF-DUPLEX/FULL-DUPLEX OPERATION
Half-duplex operation allows a transceiver to transmit or
receive, but not both at the same time. However, with full-
duplex operation, a transceiver can transmit and receive
simultaneously. The ADN4691E/ADN4696E are half-duplex
devices in which the driver and the receiver share differential
bus terminals. The ADN4693E/ADN4697E are full-duplex
devices that have dedicated driver output and receiver input
pins. Figure 37 and Figure 38 show typical half- and full-duplex
bus topologies, respectively, for M-LVDS.
THREE-STATE BUS CONNECTION
The outputs of the device can be placed in a high impedance
state by disabling the driver or receiver. This allows several
driver outputs to connect to a single M-LVDS bus. Note that, on
each bus line, only one driver can be enabled at a time, but
many receivers can be enabled at the same time.
The driver can be enabled or disabled using the driver enable
pin (DE). DE enables the driver outputs when taken high; when
taken low, DE puts the driver outputs into a high impedance state.
Similarly, an active low receiver enable pin (RE) controls the
receiver. Taking RE low enables the receiver, whereas taking it
high puts the receiver outputs into a high impedance state.
Truth tables for driver and receiver output states under various
conditions are shown in Table 10, Table 11, Table 12, and Table 13.
TRUTH TABLES
Table 9. Truth Table Abbreviations
Abbreviation Description
H High level
L
Low level
X Don’t care
I Indeterminate
Z High impedance (off)
NC Disconnected
Driver, Half-Duplex (ADN4691E/ADN4696E)
Table 10. Transmitting (See Table 9 for Abbreviations)
Power
Inputs Outputs
DE DI A B
Yes H H H L
Yes H L L H
Yes H NC L H
Yes L X Z Z
Yes NC X Z Z
≤1.5 V X X Z Z
Driver, Full-Duplex (ADN4693E/ADN4697E)
Table 11. Transmitting (See Table 9 for Abbreviations)
Power
Inputs Outputs
DE DI Y Z
Yes H H H L
Yes H L L H
Yes H NC L H
Yes L X Z Z
Yes NC X Z Z
≤1.5 V X X Z Z
Type 1 Receiver (ADN4691E/ADN4693E)
Table 12. Receiving (see Table 9 for Abbreviations)
Power
Inputs Output
A − B RE RO
Yes ≥50 mV L H
Yes ≤−50 mV L L
Yes −50 mV < A − B < 50 mV L
I
Yes NC L I
Yes X H
Z
Yes X NC Z
No X X Z
Type 2 Receiver (ADN4696E/ADN4697E)
Table 13. Receiving (See Table 9 for Abbreviations)
Power
Inputs
Output
A − B RE RO
Yes ≥150 mV L
H
Yes ≤50 mV L L
Yes 50 mV < A − B < 150 mV L
I
Yes NC L L
Yes X H
Z
Yes X NC Z
No X X Z
Data Sheet ADN4691E/ADN4693E/ADN4696E/ADN4697E
Rev. B | Page 15 of 20
GLITCH-FREE POWER-UP/POWER-DOWN
To minimize disruption to the bus when adding nodes, the
M-LVDS outputs of the device are kept glitch-free when the
device is powering up or down. This feature allows insertion of
devices onto a live M-LVDS bus because the bus outputs are not
switched on before the device is fully powered. In addition, all
outputs are placed in a high impedance state when the device is
powered off.
FAULT CONDITIONS
The ADN4691E/ADN4693E/ADN4696E/ADN4697E contain
short-circuit current protection that protects the device under
fault conditions in the case of short circuits on the bus. This
protection limits the current in a fault condition to 24 mA at
the transmitter outputs for short-circuit faults between −1 V
and 3.4 V. Any network fault must clear to avoid data
transmission errors and to ensure reliable operation of the data
network and any devices that are connected to the network.
RECEIVER INPUT THRESHOLDS/FAIL-SAFE
Two receiver types are available, both of which incorporate
protection against short circuits.
The Type 1 receivers of the ADN4691E/ADN4693E incorporate
25 mV of hysteresis. This ensures that slow changing signals or
a loss of input does not result in oscillation of the receiver output.
Type 1 receiver thresholds are ±50 mV; therefore, the state of the
receiver output is indeterminate if the differential between A and
B is about 0 V. This state occurs if the bus is idle (approximately 0 V
on both A and B), with no drivers enabled on the attached nodes.
Type 2 receivers (ADN4696E/ADN4697E) have an open circuit
and bus-idle fail-safe. The input threshold is offset by 100 mV so
a logic low is present on the receiver output when the bus is idle
or when the receiver inputs are open.
The different receiver thresholds for the two receiver types are
illustrated in Figure 36. See Tabl e 12 and Table 13 for receiver
output states under various conditions.
TYPE 1 RECEIVER
OUTPUT
LOGIC 1
LOGIC 0
DIFFERENTIAL INP UT VOLTAGE (V
IA
– V
IB
) [V]
0.25
0.15
0.05
–0.05
–0.15
0
TYPE 2 RECEIVER
OUTPUT
LOGIC 1
LOGIC 0
UNDEFINED
10355-036
UNDEFINED
Figure 36. Input Threshold Voltages
ADN4691E/ADN4693E/ADN4696E/ADN4697E Data Sheet
Rev. B | Page 16 of 20
APPLICATIONS INFORMATION
M-LVDS extends the low power, high speed, differential signaling
of low voltage differential signaling (LVDS) to multipoint systems
where multiple nodes are connected over short distances in a
bus topology network.
With M-LVDS, a transmitting node drives a differential signal
across a transmission medium such as a twisted pair cable. The
transmitted differential signal allows other receiving nodes that
are connected along the bus to detect a differential voltage that
can then be converted back into a single-ended logic signal by
the receiver.
The communication line is typically terminated at both ends
by resistors (RT), the value of which is chosen to match the
characteristic impedance of the medium (typically 100 Ω).
For half-duplex multipoint applications such as the one shown
in Figure 37, only one driver can be enabled at any time. Full-
duplex nodes allow a master-slave topology as shown in Figure 38.
In this configuration, a master node can concurrently send and
receive data to/from slave nodes. At any time, only one slave
node can have a driver enabled to concurrently transmit data
back to the master node.
RO
NOTES
1. M AXIMUM NUM BE R OF NODES : 32.
2. R
T
IS EQUAL TO T HE CHARACTERISTIC IMP E DANCE OF THE CABL E US E D.
RE
A B
RD
R
T
R
T
ADN4696E
DE DI RO RE
A B
ADN4696E
DE DI RO RE
A B
ADN4696E
DE DI RO RE
A B
ADN4696E
DE DI
10355-037
RDRDRD
RDRDRDRD
Figure 37. ADN4696E Typical Half-Duplex M-LVDS Network (Type 2 Receivers with Threshold Offset for Bus-Idle Fail-Safe)
RO
NOTES
1. M AX I MUM NUMBE R OF NODES : 32.
2. RT IS EQ UAL TO THE CHARACTERISTIC IMP E DANCE OF THE CABL E US E D.
RE
A B Z Y MASTER SLAVE SLAVE SLAVE
RT
RT
ADN4697E
DE DI RO RE DE DI RO RE DE DI
A B Z Y
ADN4697E
A B Z Y
ADN4697E
A B Z Y
ADN4697E
RT
RT
RO RE DE DI
10355-038
RDRDRDRD
Figure 38. ADN4697E Typical Full-Duplex M-LVDS Master-Slave Network (Type 2 Receivers with Threshold Offset for Bus-Idle Fail-Safe)
Data Sheet ADN4691E/ADN4693E/ADN4696E/ADN4697E
Rev. B | Page 17 of 20
OUTLINE DIMENSIONS
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(INPARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USEIN DESIGN.
COMPLIANT TOJEDEC STANDARDS MS-012-AA
012407-A
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
0.50 (0.0196)
0.25 (0.0099) 45°
8°
0°
1.75 (0.0688)
1.35 (0.0532)
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0040)
4
1
85
5.00(0.1968)
4.80(0.1890)
4.00(0.1574)
3.80 (0.1497)
1.27 (0.0500)
BSC
6.20 (0.2441)
5.80 (0.2284)
0.51(0.0201)
0.31 (0.0122)
COPLANARITY
0.10
Figure 39. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
CONTROLLING DIMENSIONS ARE IN MIL LI M E TERS; INCH DI M E NS IO NS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFE RE NCE ON LY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JE DE C S TANDARDS MS- 012- AB
060606-A
14 8
7
1
6.20 ( 0. 2441)
5.80 ( 0. 2283)
4.00 ( 0. 1575)
3.80 ( 0. 1496)
8.75 ( 0. 3445)
8.55 ( 0. 3366)
1.27 ( 0. 0500)
BSC
SEATING
PLANE
0.25 ( 0. 0098)
0.10 ( 0. 0039)
0.51 ( 0. 0201)
0.31 ( 0. 0122)
1.75 ( 0. 0689)
1.35 ( 0. 0531)
0.50 ( 0. 0197)
0.25 ( 0. 0098)
1.27 ( 0. 0500)
0.40 ( 0. 0157)
0.25 ( 0. 0098)
0.17 ( 0. 0067)
COPLANARITY
0.10
8°
0°
45°
Figure 40. 14-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-14)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
ADN4691EBRZ –40°C to +85°C 8-Lead Standard Small Outline Package (SOIC_N) R-8
ADN4691EBRZ-RL7 –40°C to +85°C 8-Lead Standard Small Outline Package (SOIC_N) R-8
ADN4693EBRZ –40°C to +85°C 14-Lead Standard Small Outline Package (SOIC_N) R-14
ADN4693EBRZ-RL7 –40°C to +85°C 14-Lead Standard Small Outline Package (SOIC_N) R-14
ADN4696EBRZ –40°C to +85°C 8-Lead Standard Small Outline Package (SOIC_N) R-8
ADN4696EBRZ-RL7 –40°C to +85°C 8-Lead Standard Small Outline Package (SOIC_N) R-8
ADN4697EBRZ –40°C to +85°C 14-Lead Standard Small Outline Package (SOIC_N) R-14
ADN4697EBRZ-RL7 –40°C to +85°C 14-Lead Standard Small Outline Package (SOIC_N) R-14
EVAL-ADN469xEHDEBZ Evaluation Board for Half-Duplex (ADN4691E/ADN4696E)
EVAL-ADN469xEFDEBZ Evaluation Board for Full-Duplex (ADN4693E/ADN4697E)
1 Z = RoHS Compliant Part.
ADN4691E/ADN4693E/ADN4696E/ADN4697E Data Sheet
Rev. B | Page 18 of 20
NOTES
Data Sheet ADN4691E/ADN4693E/ADN4696E/ADN4697E
Rev. B | Page 19 of 20
NOTES
ADN4691E/ADN4693E/ADN4696E/ADN4697E Data Sheet
Rev. B | Page 20 of 20
NOTES
©2011–2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D10355-0-1/16(B)