M29F080D70N6 - STMicroelectronics

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PRELIMINARY DATA

April 2002

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

M29F080D

8 Mbit (1Mb x8, Uniform Block)

5V Supply Flash Memory

FEATURES SUMMARY

■SUPPLY VOLTAGE

–V

CC = 5V ±10% f or PROGRAM , ERASE and

READ OPERATIONS

■ACCESS TIME: 55, 70, 90ns

■PRO GRAMMIN G TIME

– 10µs per Byte typica l

■16 UNIFORM 64Kbyte MEMORY BLOCKS

■PROGRAM/ERASE CONTROLLER

– Embedded Byte Program algori thms

■ERASE SUSPEND and RESUM E MOD ES

– Read and Program another Block during

Erase Su spend

■UNLOCK BYPASS PROGRAM COMMAND

– Fas ter Production/Batc h Prog ramm ing

■TEMPORARY BLOCK UNPROTECTION

MODE

■COMMON FLASH INTERFACE

– 64 bit Security Code

■LOW POWER CONSUMPTION

– Standby and Autom atic Standby

■100,000 PROGRAM/ERASE CYCL ES per

BLOCK

■ELECTRONIC SIGNATURE

– Manufacturer Code: 20h

– Devi ce Code: F1h

Figure 1. Packages

TSOP40 (N)

10 x 20mm

SO44 (M)

M29F080D

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TABLE OF CONT ENTS

SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 3. TSOP Connec tions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 4. SO Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 5. Block Addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Address Inputs (A0-A19). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

D ata Inputs/Ou tputs (DQ0-DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Chip Enable (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Out put Enabl e (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

W rite Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Reset/Block Temporary Unprotect (RP).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

R eady/Busy Out put (RB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

VCC Supply Volt age (5V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

VSS Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

BUS OPERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Bus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Autom at ic Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Special Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Ele ctronic Signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Block Protection and Blocks Unprotection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Table 2. Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0

R ead/Res et Comm and.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Auto Se lect Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0

Unlock Bypass Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Unlock Bypass Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Unlock Bypass Reset Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

C hip Erase Comm and. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1

Block Erase Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Erase S uspend Com ma nd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Erase Resume Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2

R ead CFI Query Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Block Protect and Chip Unprotect Commands.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 3. Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

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M29F080D

Table 4. Program, Erase Times and Prog ram, Erase Enduranc e Cyc les . . . . . . . . . . . . . . . . . . . . 13

STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Data Polling Bit (DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Toggl e Bit (DQ6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Error Bit (DQ5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Erase Timer Bit (DQ3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Alternative Toggle Bit (DQ2).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 5. Status Register Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 5

Figure 6. Data Polling Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 5

Figure 7. Data Toggle Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 6. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 7. Operating and AC Meas urem ent Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 8. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 9. AC Meas urement Load Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 8. Device Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 7

Table 9. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 10. Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 10. Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 9

Figure 11. Write AC Wavef orms, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 11. Write AC Characteristics, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 12. Write AC Waveforms, Chip Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 12. Write AC Characteristics, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 13. Reset/Block Temporary Unprotect AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 13. Reset/Block Temporary Unprotect AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 22

PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3

TSO P40 – 40 lead Plastic Thin Small Outlin e, 10 x 20mm, Package Out line . . . . . . . . . . . . . . . . 23

TSO P40 – 40 lead Plastic Thin Small Outlin e, 10 x 20mm, Package Mechanical Data . . . . . . . . 23

SO44 – 44 lead Plastic Small Outline, 525 mils body width, Packa ge Outline. . . . . . . . . . . . . . . . 24

SO44 – 44 lead Plastic Small Outline, 525 mils body width, Packa ge Mechan ical Data . . . . . . . . 24

PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 14. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 15. Document Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

APPENDIX A. BLOCK ADDRESS TABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 16. Block Addresses, M29F080D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

M29F080D

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APPENDIX B. COMMON FLASH INTERFACE (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 17. Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Table 18. CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Table 19. CFI Query System Interface Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 20. Device Geometry Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Table 21. Primary Algorithm -Spe cific Extende d Query Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 22. Security Code Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

APPENDIX C. BLOCK PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Programmer Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1

In-System Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1

Table 23. Programm er Techni que Bu s Operations , BYTE = V IH or VIL . . . . . . . . . . . . . . . . . . . . . 31

Figure 14. Programmer Equipment G roup Protect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 15. Programmer Equipment Chip Unprotect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 16. In-System Equipment Group Protect Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 17. In-System Equipment Chip Unprotect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

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M29F080D

SUMMARY DESCRIPTION

The M29F080D is a 8 Mbit (1Mb x8) non-volatile

memory that can be read, erased and repro-

grammed. These operations can be performed us-

ing a single low voltage 5V supply. On power-up

the memory defaults to its Read mode where it can

be read in the same way as a ROM or EPROM.

The memory is divided into 16 uniform blocks of

64Kbytes (see Figure 5, Block Addresses) that

can be erased independently so it is possible to

preserve valid data while old data is erased.

Bl ocks can be protected in groups of 4 to prevent

accidental Program or Erase commands from

modifying the memory. Program and Erase com-

mands are written to the Command Interface of

the memory. An on-chip Program/Erase Controller

simplifies the process of programming or erasing

the memory by taking care of all of the speci al op-

erations that are required to update the memory

contents. The end of a program or erase operati on

can be detected and any error conditions identi-

fied. The command set required to control the

memory is consistent with JEDEC standards.

Chip Enabl e, Output Enable and Write Enable sig-

nals control the bus operation of the memory.

They allow simple connection to most micropro-

cessors, often without additional logic.

The memory is offered in TSOP40 (10 x 20mm) and

SO44 pack ages. Access times of 55, 70 and 90ns

are available. The memory is supplied with all the

bi ts erased ( set t o ’ 1’).

Figu re 2. Lo gi c D iag ram Tab le 1. S i gn a l Nam es

AI06141

A0-A19

DQ0-DQ7

VCC

M29F080D

VSS

A0-A19 Address Inputs

DQ0-DQ7 Data Inputs/Outputs

EChip Enable

GOutput Enable

WWrite Enable

RP Reset/Block Temporary Unprotect

RB Ready/Busy Output

VCC Supply Voltage

VSS Ground

NC Not Connected Internally

M29F080D

6/36

Figu re 3. TSOP C onnections Figu re 4. SO C onnections

DQ1

DQ2A10

A4 A2

A14

A17

A18

DQ7

A13

A19

DQ5

DQ3

VSS

VCC

DQ4

DQ6

A12

A11

VCC

AI06142

M29F080D

20 21

A15

A16 G

VSS

DQ0

A17

A18

A19

A16

DQ6DQ2

VSS VCC

VSS DQ4

A13

RP VCC

A10

AI06143

M29F080D

2322

17DQ0

DQ1

DQ7

A15

A14

DQ3 21 DQ5

A11 A12

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M29F080D

Figure 5. Block Addresses

Note: Also see Appe ndi x A, Tabl e 16 for a full l i st i ng of the Bl ock Addresses .

AI06144

64 KByte

0FFFFFh

0F0000h

64 KByte

01FFFFh

010000h

64 KByte

00FFFFh

000000h

M29F080D

Block Addresses

0CFFFFh

Total of 16

64 KByte Blocks

64 KByte

0EFFFFh

0E0000h

0DFFFFh

0D0000h

64 KByte

020000h

02FFFFh

M29F080D

8/36

SIGNAL DESCRIPTIONS

See Figure 2, Logic Diag ram, and T able 1, Sign al

Names, for a brief overview of the signals connect-

ed to this device.

Address Inputs (A0-A19). The Address Inputs

select the cell s in the memory arra y to access dur-

ing Bus Read operations. During Bus Wri te opera-

tions they control the commands sent to the

Comman d Interface of the internal state machine.

Data Inputs/Outputs (DQ0-DQ7). The Data I/O

outputs the data stored at the selected address

during a Bus Read operation. During Bus Write

operations they represent the commands sent to

the Command Interface of the internal state ma-

chine.

Chip Enable (E). The Chip Enable, E, activates

the memor y, allowing Bus Read and Bus Write op-

erations to be performed. When Chip Enable is

High, VIH, all other pins are ignored.

Output Enable (G). The Output Enable, G, con-

trols the Bus Read operation of the memory.

Write Enable (W). T he Write Enable, W, controls

the Bus Write operation of the memory’s Com-

ma nd Inte r fa ce.

Reset/Block Temporar y Unprotect (RP). The

Reset/Block Temporary Unprotect pin can be

used to apply a Hardware Reset to the mem ory or

to temporarily u nprotect al l Block s that have been

protected.

A Hardware Reset is achieved by holding Reset/

Block Temporary Unprotect Low, VIL, for at least

tPLPX. After Reset/Block Temporary Unprotect

goes High, V IH, the memory will be read y for Bus

Read and Bus Write operations after tPHEL or

tRHEL, whichever occurs last. See the Ready/ Busy

Output section, Table 13 and Figure 13, Reset/

Temporary Unprot ect AC Charact e ristics for more

details.

Holding RP at VID will temporarily unprotect the

protected Blocks in the memory. Program and

Erase operations on all blocks will be possible.

The transition from VIH to VID must be slower than

tPHPHH.

Ready/Busy Output (RB). The Ready/Busy pin

is an open-drain output that can be used to identify

when the device is performing a P rogr am or Erase

operation. During Program or Erase operations

Ready/Busy is Low, V OL. Ready/Busy is high-im-

pedance during Read mode, Auto Select mode

and Erase Suspend m ode.

After a Hardware Reset, Bus Read and Bus Write

operations cannot begin until Ready/Busy be-

comes h igh-impeda nc e. See Tabl e 13 and Figure

13, Reset/Temporary Unprotect AC Characteris-

tics.

The use of an open-drain output allows the Ready/

Busy pins from several memories to be connected

to a single pull-up resistor. A Low will then indicate

that one, or more, of the memories is busy.

VCC Supply Volta ge (5V). VCC provides the

power supply for all operations (Read, Program

and Erase).

The Command Interface is dis abled when the VCC

Supply Voltage is less than the Lockout Voltage,

VLKO. This prevent s Bus Write operations from ac-

cidentally damaging the data during power up,

power down and power surges. If the Program/

Erase Controller is programming or erasing during

this time then the operation aborts and the memo-

ry contents being altered will be invalid.

A 0.1µF capacitor should be connected between

the V CC Supply Voltage pin and the VSS Ground

pin to decoupl e the current surges from t he power

supply, see Figure 10, AC Measurement Load Cir-

cuit. The PCB track widths must be sufficient to

carry the currents required during program and

erase operat ions, ICC3.

VSS Ground. VSS is the reference for all voltage

measurements.

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M29F080D

BUS OPERATIONS

There are five s tandard bus operations t hat control

the device. These are Bus Read, Bus Wri te, Out-

put Disable, Standby and Automat ic Standby. See

Tables 2, Bus Operations, for a summary. Typical-

ly glitches of less than 5ns on Chip Enable or Write

Enable are i gnored by t he mem ory and do not a f-

fect bus operations.

Bus Read. Bus Read operations read from the

memory cells, or specific registers in the Com-

mand Interface. A valid Bus Read operation in-

volves setting the desi red address on the Address

Inputs, appl ying a Low s ig nal, VIL, to Chip Enable

and Output Enable and keeping Write Enable

High, VIH. The Dat a I nputs/Ou tputs will output the

value, see Figure 10, Read Mode AC Waveforms,

and Table 10, Read AC Characteristics, for details

of when the output becomes valid.

Bus Write. Bus Write operations write to the

Command Interface. A valid Bus Write operation

begins by setting the desire d address on the Ad-

dress Inputs. The Address Inputs are latched by

the Command Interface on the falling edge of Chip

Enable or Write Enable, whichever occurs last.

The Dat a Input s/Outpu ts a re latched by the Com-

mand Interface on the rising edge of Chip Enab le

or Write Enable, whichever occurs first. Output En-

able must remai n High, VIH, during the whole Bus

Write operation. See Figures 11 and 12, Write AC

Waveforms, and Tables 11 and 12, Write AC

Characteristics, for details of the timing require-

ments.

Outp ut Disable. The Data Inputs/Outputs are in

the high impeda nce state when Output Enable is

High, VIH.

Standby. When Chip Enable is High, VIH, the

memory enters Standby mode and the Data In-

puts/Outputs pins are placed in the high-imped-

ance state. To reduce the Supply Current to the

Standby Supply Current, ICC2, Chip Enable should

be held within VCC ± 0.2V. For t he Standby current

level see Table 9, DC Characteristics.

During program or erase operations the memory

will continue to use the Program/Erase Supply

Current, ICC3, for Program or Erase operations un-

til the operation com pletes .

Automatic Standby. If CMOS levels (VCC ± 0.2V)

are used to drive the bus and the bus is inact ive for

300ns or more the memory enters Automatic

Standby where the internal Supply Current is re-

duced to the Standby Supply Current, ICC2. The

Data Inputs/Outputs will still output data if a Bus

Read operation is in progress.

Special Bus Operations

Additional bus operations can be performed to

read the Electronic Signature and also to apply

and remove Block Protection. These bus opera-

tions are intended for use by programming equip-

ment and are not usually used in applications.

They require VID to be applied to some pins.

Electronic Sign atur e. The memory has two

codes, the manufacturer code and the device

code, that can be read to identify the memory.

These co des can be read by applying the s ignals

listed in Tables 2, Bus Operati ons.

Block Protection and Blocks Unprotection.

Blocks can be protected in groups of 4 against ac-

cidental Program or Erase. See Appendix A, Table

16, Block Addresses, for details of which blocks

must be protected toget her as a group . Protected

blocks can be unprotected to allow data to be

changed.

There are two methods available for protecting

and unprotecting the blocks, one for use on pro-

gramming equipment and the other for in-system

use. Bloc k Protec t and Chi p Unprot ect operat ions

are described i n Appendix C.

Table 2. Bus Operati ons

No te: X = VIL or VIH.

Operation E G W Address Inputs

A0-A19 Data Input s/Out puts

DQ7-DQ0

Bus Read VIL VIL VIH Cell Address Data Output

Bus Write VIL VIH VIL Command Address Data Input

Output Disable X VIH VIH XHi-Z

Standby VIH XXX Hi-Z

Read Manufacturer

Code VIL VIL VIH A0 = VIL, A1 = VIL, A9 = VID, Others

VIL or VIH 20h

Read Device Code VIL VIL VIH A0 = VIH, A1 = VIL,

A9 = VID, Others VIL or VIH F1h

M29F080D

10/36

COMMAND INTERFACE

All Bus Write operations t o the memory are in ter-

preted by the Command Interface. Commands

consist of one or more sequential Bus Write oper-

ations. Failure to observe a val id sequence of Bus

Write operations will result in the memory return-

ing to Read mode. The long command sequences

are imposed to maximize data security.

Refer to Table 3, Commands, in conjunction with

the follo wing t ext descri ptions .

Read/Reset Comm and. The Read/Reset com-

mand returns the memory to its Read mode where

it behaves like a ROM or EPROM, unless other-

wise s tated. It also resets t he errors in the S tatus

can be used to issue the Read/Reset command.

The Read/Reset Command can be issued, be-

tween Bus Write cycles before the start of a pro-

gram or erase operation, to return the device to

read mode. Once the program or eras e operation

has started the Read/Res et command is no longer

accepted. The Read/Reset command will not

abort an Erase operation when issued while in

Erase Suspend.

Auto Select Command. The Auto Select com-

mand i s us ed to read the Man ufacturer Code, the

Device Code and the Block Protection Status.

Three consecutive Bus Write operations are re-

quired to issue the Auto Select command. Once

the Auto Select command is issued the memory

remains in Auto Select mode until a Read/Reset

command is issued. Read CFI Query and Read/

Reset commands are accepted in Auto Select

mode, all other commands are ignored .

From the Auto Select mode the Manufacturer

Code can be read using a Bus Read operation

with A 0 = VIL and A1 = VIL. The other address bits

may be set to e ither VIL or VIH. The Ma nufa cturer

Code for STMicroelectronics is 20h.

The Device Code can b e read using a Bus Read

operation with A0 = VIH and A1 = VIL. The other

address bits may be set to either V IL or VIH. The

Device Code for the M29F 080D F1 h.

T he B lock P rot ec tion Sta tus of each block c an be

read using a Bus Read operation with A0 = VIL,

A1 = VIH, and A 12-A1 9 spec ifying t h e address of

th e block. The oth er addres s bits may be s et to ei-

ther VIL or VIH. I f th e addr es sed b lock i s p rot ect ed

then 01h is output on Data Inputs/Outputs DQ0-

DQ7, otherwise 00h is output.

Progra m Command . The Program command

can be used to program a value to one address in

the memory array at a time. The command re-

quires four Bus Write operations, the final write op-

eration latches the address and data in the internal

state machine and starts the Program/Erase Con-

troller.

If the address falls in a protected block then the

Program command is ignored, the data remains

unchanged. The Status Register is nev er read and

no error condition is given.

During the program operation the memory will ig-

nore all co mmands. I t is not possible t o issue any

command to abort or pause the operation. Typical

program times are given in Table 4. Bus Read op-

erations during the program operation will output

the Status Register on the Data Inputs/Outputs.

See the section on the Status Register for more

details.

After the program operation has completed the

memory will return to the Read mode, unless an

error has occurred. When an error occurs the

memory will continue to output the Status Regis-

ter. A Read/Reset command must be issued to re-

set the error condition and return to Read mode.

Note that t he Program command cannot change a

bit set at ’0’ back to ’1’. One of the Erase Com-

mands must be used to set all the bits in a block or

in the whole memory from ’0’ to ’1’.

Unlock Bypass Comma nd. The Unlock Bypass

command is used in conjunction with the Unlock

Bypass Program c ommand to program the memo-

ry. When the cycle time to the device is long (as

with some EPROM programmers) considerable

time saving can be made by using these com-

mands. Three Bus Write operations are required

to issue the Unlock Bypass comm and.

Once the Unlock Bypass command has been is-

sued the memory will only accept the Unlock By-

pass Program command and the Unlock Bypass

Reset command. The memory can be read as if in

Read mode.

Unlock Bypass Prog ram Comm an d. The Un-

lock Bypass Program command can be used to

program one address in the memory array at a

time. The comm and requires tw o Bus Write oper-

ations, the final write operation latches the ad-

dress and data in the internal state machine and

starts the Program/Erase Controller.

The Program operation using the Unlock Bypass

Program c ommand behaves identically to the Pro-

gram operation using the Program command. A

protected block cannot be program m ed; the oper-

ation cannot be aborted and the Status Register is

read. Errors must be reset using the Read/Reset

command, w hich l eaves the d evice in Unlo ck By-

pass Mode. See the Program command for details

on the behavior.

Unlock Bypass Reset Comman d. The Unlock

Bypass Re set comm and can be used to return to

Read/Reset mode from Unlock Bypass Mode.

Two Bus Write operations are requir ed to issue the

Unlock Bypass Reset command. Read/Reset

11/36

M29F080D

command does not exit from Unlock Bypass

Mode.

Chip Erase Command. The Chip Erase com-

mand can be used to erase the entire chip. Six Bus

Write operations are required to issue the Chip

Erase Command and start the Program/Erase

Controller.

If any blocks are protected then these are ignored

and all the other blocks are erased. If all of the

blocks a re p rote cted the Chip Era se o perat i on ap-

pears to start but will terminate within about 100µs,

leaving the data unchange d. No error co ndition is

given when protected blocks are ignored.

During the erase operation the memory wi l l ignore

all commands , including the E rase Suspen d com-

mand. It is no t possible to i ssue any c ommand t o

abort the operation. Typical chip erase times are

given in Table 4. All Bus Read operations during

the Chip Erase operation will output the Status

tion on the Status Regist er for more details.

After the Chip Erase operation has com pleted the

memory will return to the Read Mode, unless an

error has occurred. When an error occurs the

memory will continue to output the Status Regis-

ter. A Read/Reset command must be issued to re-

set the error condition and return to Read Mode.

The Chip Erase Command sets all of the bits in un-

protected blocks of the memory to ’ 1’. All previous

data is lost.

Block Erase Command. The Block Erase com-

mand can be used to erase a list of one or more

blocks. Six Bus Write operations are required to

select the first block in the list. Each additional

block in the list can be selected by repeating the

sixth Bus Wr ite operation using the address of the

additional block. The Bl ock Erase operation st arts

the Program/Erase Controller about 50µs after the

last Bus Write operation. Once the Program/Erase

Controller starts it is not possible to select any

more blocks. Each additional block must therefore

be selected within 50µs of the last block. The 50µs

timer r estarts when an additional block is select ed.

The Status Register can be read after the sixth

Bus Write operati on. See the Status Regist er sec-

tion for details on how to identify if the Program/

Erase Controller has started the Block Erase oper-

ation.

If any selected blocks are protect ed then t hese are

ignored and all the other selected blocks are

erased. If all of the selected blocks are protected

the Block Erase operation appears to start but will

terminate within about 100µs, l eaving the data un-

changed. No error condition is given when protect-

ed blocks are ignored.

During the Blo ck Erase ope ra tion the me mory will

ignore all commands except the Erase Suspend

co mmand. Typical b lock e rase times a re g iven in

Table 4. All Bus Read operations during the Block

Erase op eratio n w ill ou t pu t the S t a tus R eg i st er on

the Data Inputs/Outputs. See the section on the

Status Regist er for more details.

After the Block Erase operation has completed the

memory will return to the Read Mode, unless an

error has occurred. When an error occurs the

memory will continue to output the Status Regis-

ter. A Read/Reset command must be issued to re-

set the error condition and return to Read mode.

The Block Erase Command sets all of the bits in

the unprotected selec ted bl ocks to ’1’ . All previous

data in the selected blocks is lost.

Erase Suspend Comm and. The Erase Suspend

Comman d m ay be used to temporari ly suspend a

Block Erase operation and return the memory to

Read mode. The command requires one Bus

Write operation.

The Prog ram/Eras e Controlle r will sus pend within

15µs of the Erase Suspend Command being is-

sued. Once the Program/Erase Controller has

stopped the memory will be set t o Read mode and

the Erase will be suspended. If the Erase Sus pend

command is issued during the period when the

memory is waiting for an additional block (before

the Program/Erase Controller starts) then the

Erase is susp ended i mmedi ately and wi ll start im-

mediately when the Erase Resume Command is

issued. It is not possible to select any further

blocks to erase after the Erase Resume.

M29F080D

12/36

During Erase Suspend it is possible to Read and

Program cells in blocks that are not being erased;

both Read and Program operations behave as

normal on these blocks. If any attempt is made to

program in a protec ted block or in the suspen ded

block then the Program command is ignored and

the data remains unchanged. The St atus Register

is not read and no error condi tion is gi ven. Re ad-

ing from blocks that are being erased will output

the Status Register.

It is also possible to issue the Auto Select, Read

CFI Query and Unlock Bypass commands during

an Erase Suspend. The Read/Reset command

must be i ssued to return the device to Read A rray

mode before the Resume command will be ac-

cepted.

Erase Resum e Command. The Erase Resume

command must be used to restart the Program/

Erase Control l er after an Erase Suspend. The de-

vice must be in Read Array mode before the Re-

sume command will be accepted. An erase can be

suspended and resum ed more than onc e.

Read CFI Query Comman d. The Read CFI

Query Command is used to read data from the

Common Flash Interface (CFI) Mem ory Area. This

command is valid when the device i s in the Read

Array mode, or when the device is i n Autoselected

mode.

One Bus Write cycle is required to issue the Read

CFI Query Command. Once the command is is-

sued subsequen t Bus Read ope rations read from

the Common Flash Interface Memory Area .

The Read/Reset command must be issued to re-

turn the device to the previous mode (the Read Ar-

ray mode or Autoselected mode). A second Read/

Reset command would be needed if the device is

to be put in t he Read Array mode from Autoselect-

ed mode.

See Appendix B, Tables 17, 18, 19, 20, 21 and 22

for details on the information contained in the

Common Flash Interface (CFI) memory area.

Block Protect and Chip Unprotect Com-

mands. Groups of blocks can be protected

against accident al Program or Erase. The Protec-

tion Groups are shown in Appendix A, Table 16.

The whole chip can be unprotected to allow the

data inside the blocks to be changed.

Block Protect and Chip Unprotect operations are

described in Appendix C.

13/36

M29F080D

Table 3. Command s

Note: X Don’ t Care, PA P rogram Address, PD Pro gram Data, BA An y address in the B lo ck. All va l ues in the table a re i n hexadec imal.

Table 4. Pro gra m , Erase Times and Progra m, Erase E nduran ce Cycle s

Note: 1. TA = 25°C, VCC = 5V.

Command

Length

Bus Write Operations

1st 2nd 3rd 4th 5th 6th

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

Read/Reset 1X F0

3 555 AA 2AA 55 X F0

Auto Select 3 555 AA 2AA 55 555 90

Program 4 555 AA 2AA 55 555 A0 PA PD

Unlock Bypass 3 555 AA 2AA 55 555 20

Unlock Bypass

Program 2X A0PAPD

Unlock Bypass Reset 2 X 90 X 00

Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10

Block Erase 6+ 555 AA 2AA 55 555 80 555 AA 2AA 55 BA 30

Erase Suspend 1 X B0

Erase Resume 1 X 30

Read CFI Query 1 55 98

Parameter Min Typ (1) Typical after

100k W/E Cycles (1) Max Unit

Chip Erase 12 12 60 s

Block Erase (64 Kbytes) 0.8 6 s

Program (Byte) 10 200 µs

Chip Program (Byte by Byte) 12 60 s

Program/Erase Cycles (per Block) 100,000 cycles

M29F080D

14/36

STATUS REGISTER

Bus Read operations from any address always

read the Status Register during Program and

Erase operations. It is also read during Erase Sus-

pend when an address within a block being erased

is acce ssed .

The bits in the Status Register are s um marized in

Table 5, Status Register Bits.

Data Polling Bit (DQ7). The Data Polling Bit can

be used to identify whether the Program/Erase

Controller has successfully completed its opera-

tion or if it has responded to an Erase Suspend.

The Data Polling Bit is output on DQ7 when the

Status Register is read.

During Program operations the Data Polling Bit

outputs the complement of the bit being pro-

grammed to DQ7. After successful completion of

the Program operation the memory returns to

Read mode and Bus Read operations from t he ad-

dress just programmed output DQ7, not its com-

plement.

During Erase ope rations the Data Po lling Bit out-

puts ’0’, the complement of the erased state of

DQ7. Aft er suc cessful completion of the Erase op-

eration the memory returns to Read Mod e.

In Erase Suspend mode the Data Polling Bit will

output a ’1’ during a Bus Read operation within a

block being erased. The Data Polling Bit will

change f rom a ’0’ to a ’ 1’ when the Program/ Erase

Controller has suspe nded the Erase operation.

Figure 6, Data Polling Flowchart, gives an exam-

ple of how to use the Data Polling Bit. A V alid Ad-

dress is the address being programmed or an

address within the block being erased.

Toggle Bit (DQ6). The Toggle Bit can be used to

identify whether the Program/Er as e Controller has

successfully completed its operation or if it has re-

sponded to an Erase Suspend. The Toggle Bit is

output on DQ6 when the Status Register is read.

During Program and Erase operations the Toggle

Bit changes f rom ’0 ’ to ’ 1’ to ’ 0’, et c., with succes-

sive Bus Read operations at any address. After

successful completion of the operation t he memo-

ry returns to Read mode.

During Erase Suspend mode the Toggle Bit will

output when addressing a cell wi thin a bl ock being

erased. The Toggle Bit will stop t oggling when the

Program/Erase Controller has suspended the

Erase operation.

If any attempt is ma de to erase a protected bl ock,

the o peration is aborted, n o error is sig nalle d and

DQ6 toggles for approximately 100µs. If any at-

tempt is made to program a protected block or a

suspended b lock, the operatio n is aborted, no er-

ror is signalled and DQ6 toggl es for approximately

1µs.

Figure 7 , Data Toggle Flowchart, g ives an exam-

ple of how to use the Data Toggle Bit.

Error Bit (DQ5). The Error Bit can be used to

identify errors detected by the Program/Erase

Controller. The Error Bit is set to ’1’ when a Pro-

gram, Block Erase or Chip Erase operation fails to

write the correct data to the memory. If the Error

Bit is set a Rea d/Re se t comm and must be issued

before other command s are issued. The Error bit

is output on DQ5 when the Status Register is read.

Note that t he Program command cannot change a

bit set to ’0’ back to ’1’ and attempting to do so will

set DQ5 to ‘1’. A Bus Read operation to that ad-

dres s w ill s how the bit is s ti ll ‘0’. On e of the Erase

commands must be used to set all the bits in a

block or in the whole m emo ry from ’0’ to ’1’.

Erase Timer Bit (DQ3). The Erase Timer Bit can

be used to identify the start of Program/Erase

Controller operation during a Block Erase com-

mand. Once the Program/Erase Controller starts

erasing the E rase Ti mer Bit is set to ’ 1’ . Before the

Program/Erase Controller starts the Erase Timer

Bit is set to ’0’ and additional block s to be eras ed

may be written to the Command Interface. The

Erase Timer Bit is output on DQ3 when the Status

Alternative Toggle Bit (DQ2). The Alternative

Toggle Bit can be used to monitor the Program/

Erase controller during Erase operations. The Al-

ternative Toggle Bit is output on DQ2 when the

Status Register is read.

During Chip Erase and Block Erase operations the

Toggle Bit changes from ’0’ to ’1’ to ’0’, etc., with

successive Bus Re ad operations from addresses

within the blocks being erased. A protected block

is treated the same as a block not being erased.

Once t he operation completes the m emory returns

to Read mode.

During Erase Suspend the Alternative Toggle Bit

changes from ’0’ to ’1’ to ’0’, etc. with successive

Bus Read operations from addresses within the

blocks being erased. Bus Read operations to ad-

dresses within blocks not being erased will output

the memory cell data as if in Read mode.

After an Erase operation that caus es t he Error Bit

to be set the Alternative Toggle Bit can be used to

identify which block or bloc ks have caused the er-

ror. The Alternative Toggle Bit changes from ’0’ to

’1’ to ’0’, etc. with successive Bus Read Opera-

tions from addresses within blocks that have not

erased correctly. The Alternative Toggle Bit does

not change if the addressed block has erased cor-

rectly.

15/36

M29F080D

Table 5. Status Register Bits

No te : Unspecified data bits sh ould be ignored.

Figu re 6. Da ta Po lli ng Fl owch ar t Figu r e 7. Da ta To ggle Flowchar t

Operation Address DQ7 DQ6 DQ5 DQ3 DQ2 RB

Program Any Address DQ7 Toggle 0 ––0

Program During Erase

Suspend Any Address DQ7 Toggle 0 – – 0

Program Error Any Address DQ7 Toggle 1 – – 0

Chip Erase Any Address 0 Toggle 0 1 Toggle 0

Block Erase before

timeout Erasing Block 0 Toggle 0 0 Toggle 0

Non-Erasing Block 0 Toggle 0 0 No Toggle 0

Block Erase Erasing Block 0 Toggle 0 1 Toggle 0

Non-Erasing Block 0 Toggle 0 1 No Toggle 0

Erase Suspend Erasing Block 1 No Toggle 0 – Toggle 1

Non-Erasing Block Data read as normal 1

Erase Error Good Block Address 0 Toggle 1 1 No Toggle 0

Faulty Block Address 0 Toggle 1 1 Toggle 0

READ DQ5 & DQ7

at VALID ADDRESS

START

READ DQ7

at VALID ADDRESS

FAIL PASS

AI05278

DQ7

DATA YES

YES

DQ5

= 1

DQ7

DATA YES

READ DQ6

START

READ DQ6

TWICE

FAIL PASS

AI05279

DQ6

TOGGLE NO

YES

DQ5

= 1

YES

DQ6

TOGGLE

READ

DQ5 & DQ6

M29F080D

16/36

MAX I MUM R AT I N G

Stressing the device ab ove t he rati ng l isted in t he

Absolute Maxi mum Ratings table may cause per-

manent damage to the device. Exposure to Abso-

lute Maximum Rating conditions for extended

periods may affect device reliability. These are

stress ratings only and operation of the device at

these or any other conditions above those indicat-

ed in the Operating sections of this specification is

not implied. Refer also to the STMicroelectronics

SURE Program and other relevant quality docu-

ments.

Table 6. Absolute Maximum Ratings

Note: 1. Min i m um Voltage ma y unders hoot to –2 V or oversho ot to VCC +2V d uri ng tran si t i on for a ma xim um of 20ns.

Symbol Parameter Min Max Unit

TBIAS Temperature Under Bias –50 125 °C

TSTG Storage Temperature –65 150 °C

VIO Input or Output Voltage (1) –0.6 VCC + 0.6 V

VCC Supply Voltage –0.6 6 V

VID Identification Voltage –0.6 13.5 V

17/36

M29F080D

DC AND AC PARAMETERS

This section summarizes the operating measure-

ment conditions, a nd the DC and AC characteris-

tics of the device. The parameters in the DC and

AC characteristics Tables that follow, are derived

from tests performed under the Measurement

Conditions summarized in Table 7, Operating and

AC Measurement Conditions. Designers should

check t hat the operating cond itions in their circuit

match the operating conditions when relying on

the quot ed parameters.

Table 7. Operating and AC Measurem en t Conditions

Figure 8. AC Measurement I/O Wavefo rm Figure 9. AC Measurem ent Load Circuit

Table 8. Device Capacitance

No te : Sam pled o nl y, not 100% te st ed.

Parameter

M29F080D

Unit55 70/ 90

Min Max Min Max

VCC Supply Voltage 4.5 5.5 4.5 5.5 V

Ambient Operati ng Tem peratur e – 40 85 – 40 85 °C

Load Capacitance (CL)30 100 pF

Input Rise and Fall Times 10 10 ns

Input Pulse Voltages 0 to 3 0.45 to 2.4 V

Input and Output Timing Ref. Voltages 1.5 0.8 and 2.0 V

AI05276

High Speed (55ns)

1.5V

2.4V

Standard (70, 90ns)

0.45V

2.0V

0.8V

AI05277

1.3V

OUT

CL includes JIG capacitance

3.3kΩ

1N914

DEVICE

UNDER

TEST

VCC

0.1µF

Symbol Parameter Test Condition Min Max Unit

CIN Input Capacitance VIN = 0V 6pF

OUT Output Capacitance VOUT = 0V 12 pF

M29F080D

18/36

Table 9. DC Characteristics

Not e: 1. Sampled only, not 100% tested.

Symbol Parameter Test Condition Min Max Unit

ILI Input Leakage Current 0V ≤ VIN ≤ VCC ±1 µA

ILO Output Leakage Current 0V ≤ VOUT ≤ VCC ±1 µA

ICC1 Supply Current (Read) E = VIL, G = VIH, f = 6MHz 20 mA

ICC2 Supply Current (Standby) TTL E = VIH 2mA

CC3 Supply Current (Standby) CMOS E = VCC ± 0.2V,

RP = VCC ±0.2V 150 µA

ICC4 (1) Supply Current (Program/Erase) Program/Erase

Controller active 20 mA

VIL Input Low Voltage –0.5 0.8 V

VIH Input High Voltage 2 VCC + 0.5 V

VOL Output Low Voltage IOL = 5.8mA 0.45 V

VOH Output High Voltage TTL IOH = –2.5mA 2.4 V

Output High Voltage CMOS IOH = –100µA VCC – 0.4 V

VID Identification Voltage 11.5 12.5 V

IID Identification Current A9 = VID 100 µA

VLKO (1) Program/Erase Lockout Supply

Voltage 3.2 4.2 V

19/36

M29F080D

Figure 10. Read AC Wavefo rms

Table 10. Read AC Characteristics

Not e: 1. Sampled only, not 100% tested.

Symbol Alt Parameter Test Condition M29F080D Unit

55 70/ 90

tAVAV tRC Address Valid to Next Address Valid E = VIL,

G = VIL Min 55 70 ns

tAVQV tACC Address Valid to Output Valid E = VIL,

G = VIL Max 55 70 ns

tELQX (1) tLZ Chip Enable Low to Output Transition G = VIL Min 0 0 ns

tELQV tCE Chip Enable Low to Output Valid G = VIL Max 55 70 ns

tGLQX (1) tOLZ Output Enable Low to Output Transition E = VIL Min 0 0 ns

tGLQV tOE Output Enable Low to Output Valid E = VIL Max 30 30 ns

tEHQZ (1) tHZ Chip Enable High to Output Hi-Z G = VIL Max 18 20 ns

tGHQZ (1) tDF Output Enable High to Output Hi-Z E = VIL Max 18 20 ns

tEHQX

tGHQX

tAXQX tOH Chip Enable, Output Enab le or Address

Transition to Output Transition Min 0 0 ns

AI06145

tAVAV

tAVQV tAXQX

tELQX tEHQZ

tGLQV

tGLQX tGHQX

VALID

A0-A19

DQ0-DQ7

tELQV tEHQX

tGHQZ

VALID

M29F080D

20/36

Figure 11. Write AC Waveforms, Wr ite Enable Controlled

Table 11. Write AC Characteristics, Write Enable Controlle d

Not e: 1. Sampled only, not 100% tested.

Symbol Alt Parameter M29F080D Unit

55 70/ 90

tAVAV tWC Address Valid to Next Address Valid Min 55 70 ns

tELWL tCS Chip Enable Low to Write Enable Low Min 0 0 ns

tWLWH tWP Write Enable Low to Write Enable High Min 45 45 ns

tDVWH tDS Input Valid to Write Enable High Min 45 45 ns

tWHDX tDH Write Enable High to Input Transition Min 0 0 ns

tWHEH tCH Write Enable High to Chip Enable High Min 0 0 ns

tWHWL tWPH Write Enable High to Write Enable Low Min 20 20 ns

tAVWL tAS Address Valid to Write Enable Low Min 0 0 ns

tWLAX tAH Write Enable Low to Address Transition Min 45 45 ns

tGHWL Output Enable High to Write Enable Low Min 0 0 ns

tWHGL tOEH Write Enable High to Output Enable Low Min 0 0 ns

tWHRL (1) tBUSY Program/Erase Valid to RB Low Max 30 30 ns

tVCHEL tVCS VCC High to Chip Enable Low Min 50 50 µs

AI06146

A0-A19

DQ0-DQ7

VALID

VCC

tVCHEL

tWHEH

tWHWL

tELWL

tAVWL

tWHGL

tWLAX

tWHDX

tAVAV

tDVWH

tWLWHtGHWL

tWHRL

21/36

M29F080D

Figure 12. Write AC Waveforms, Chip Enable Control led

Table 12. W rite AC Characteristics, Chip Enable Controlled

Not e: 1. Sampled only, not 100% tested.

Symbol Alt Parameter M29F080D Unit

55 70/ 90

tAVAV tWC Address Valid to Next Address Valid Min 55 70 ns

tWLEL tWS Write Enable Low to Chip Enable Low Min 0 0 ns

tELEH tCP Chip Enable Low to Chip Enable High Min 45 45 ns

tDVEH tDS Input Va lid to Chip Enable High Min 45 45 ns

tEHDX tDH Chip Enable High to Input Transition Min 0 0 ns

tEHWH tWH Chip Enable High to Write Enable High Min 0 0 ns

tEHEL tCPH Chip Enable Hi gh to Chip Enable Low Min 20 20 ns

tAVEL tAS Address Valid to Chip Enable Low Min 0 0 ns

tELAX tAH Chip Enable Low to Address Transition Min 45 45 ns

tGHEL Output Enable High Chip Enable Low Min 0 0 ns

tEHGL tOEH Chip Enable High to Output Enable Low Min 0 0 ns

tEHRL (1) tBUSY Program/Erase Valid to RB Low Max 30 30 ns

tVCHWL tVCS VCC High to Write Enable Low Min 50 50 µs

AI06147

A0-A19

DQ0-DQ7

VALID

VCC

tVCHWL

tEHWH

tEHEL

tWLEL

tAVEL

tEHGL

tELAX

tEHDX

tAVAV

tDVEH

tELEHtGHEL

tEHRL

M29F080D

22/36

Figure 13. Reset/Block Tem porary Unp rotec t AC Waveforms

Table 13. Reset/Block Temporary Unprotect AC Characteristics

Not e: 1. Sampled only, not 100% tested.

Symbol Alt Parameter M29F080D Unit

55 70/ 90

tPHWL (1)

tPHEL

tPHGL (1) tRH RP High to Write Enable Low, Chip Enable Low,

Output Enable Low Min 50 50 ns

tRHWL (1)

tRHEL (1)

tRHGL (1) tRB RB High to Write Enable Low, Chip Enable Low,

Output Enable Low Min 0 0 ns

tPLPX tRP RP Pulse Width Min 500 500 ns

tPLYH (1) tREADY RP Low to Read Mode Max 10 10 µs

tPHPHH (1) tVIDR RP Rise Time to VID Min 500 500 ns

AI02931B

RP tPLPX

tPHWL, tPHEL, tPHGL

tPLYH

tPHPHH

E, G

tRHWL, tRHEL, tRHGL

23/36

M29F080D

PACKAGE MECHANICAL

TSOP40 – 40 lead Plastic Thin S mall Outline, 10 x 20mm, Package Ou tline

Not e: Drawing is not to scale.

TSOP40 – 40 lead Plastic Thin S mall Outline, 10 x 20mm, Package M echan ic al Data

Symbol millimeters inches

Typ Min Max Typ Min Max

A 1.200 0.0472

A1 0.050 0.150 0.0020 0.0059

A2 0.950 1.050 0.0374 0.0413

B 0.170 0.270 0.0067 0.0106

C 0.100 0.210 0.0039 0.0083

D 19.800 20.200 0.7795 0.7953

D1 18.300 18.500 0.7205 0.7283

E 9.900 10.100 0.3898 0.3976

e 0.500 – – 0.0197 – –

L 0.500 0.700 0.0197 0.0276

α0° 5° 0° 5°

N40 40

CP 0.100 0.0039

TSOP-a

1 N

N/2

DIE

LA1 α

M29F080D

24/36

SO44 – 44 lead Plastic Small Outline, 525 mils bo dy width , Packag e Outline

Not e: Drawing is not to scale.

SO44 – 44 lead Plastic Small Outline, 525 mils bo dy width , Packag e Mechanical Data

Symbol millimeters inches

Typ Min Max Typ Min Max

A 2.80 0.1102

A1 0.10 0.0039

A2 2.30 2.20 2.40 0.0906 0.0866 0.0945

b 0.40 0.35 0.50 0.0157 0.0138 0.0197

C 0.15 0.10 0.20 0.0059 0.0039 0.0079

CP 0.08 0.0030

E 13.30 13.20 13.50 0.5236 0.5197 0.5315

D 28.20 28.00 28.40 1.1102 1.1024 1.1181

e 1.27 – – 0.0500 – –

HE 16.00 15.75 16.25 0.6299 0.6201 0.6398

L 0.80 0.0315

N44 44

α88

SO-d

LA1 α

eCP

25/36

M29F080D

PAR T NUMBERING

Table 14. Ordering Information Scheme

Devices are shipped from the factory wit h the memory content bits erased t o ’1’.

For a list of availabl e options (S peed, P ack age, et c...) or for further information on any aspect of this de-

vice, pleas e contact the ST Sales Office nearest to you.

RE VISION HISTORY

Table 15. Document Revisio n History

Example: M29F080D 55 N 1 T

Device Type

M29

Operating Voltage

F = VCC = 5V ± 10%

Device Function

080D = 8 Mbit (1Mb x8), Uniform Block

Speed

55 = 55 ns

70 = 70 ns

90 = 90 ns

Package

N = TSOP40: 10 x 20 mm

M = SO44

Temperature Range

1 = 0 to 70 °C

6 = –40 to 85 °C

Option

T = Tape & Reel Packing

Date Version Revision Details

03-Dec-2001 -01 First Issue

05-Apr-2002 -02 Description of Ready/Busy signal clarified (and Figure 13 modified)

Clarified allowable commands during block erase

Clarified the mode the device returns to in the CFI Read Query command section

M29F080D

26/36

APPENDIX A. BLOCK ADDRESS TABLE

Table 16. B lock A ddresses, M29F080D

#Size,

KByte Addr ess R ange Pro tectio n Gr oup

15 64 0F0000h-0FFFFFh

14 64 0E0000h-0EFFFFh

13 64 0D0000h-0DFFFFh

12 64 0C0000h-0CFFFFh

11 64 0B0000h-0BFFFFh

10 64 0A0000h-0AFFFFh

9 64 090000h-09FFFFh

8 64 080000h-08FFFFh

7 64 070000h-07FFFFh

6 64 060000h-06FFFFh

5 64 050000h-05FFFFh

4 64 040000h-04FFFFh

3 64 030000h-03FFFFh

2 64 020000h-02FFFFh

1 64 010000h-01FFFFh

0 64 000000h-00FFFFh

27/36

M29F080D

APPENDIX B. COM MON FLASH I NTE RFACE (CFI)

The Common Flash Interface is a JEDEC ap-

proved, standardized data structure that can be

read from the Flash memory device. It allows a

system sof tware t o query the de vic e to determine

various electrical and timing parameters, density

information and functions supported by t he mem-

ory. The system can interface easily with the de-

vice, enabling the s oftware to upgrad e itse lf when

necessary.

When the CFI Query Command is issued the de-

vice enters CFI Query mode and the data structure

is read from the memory. Tables 17, 18, 19, 20, 21

and 22 show the addresses used to retrieve the

data.

The CFI data structure also contains a security

area where a 64 bi t unique security number is writ-

ten (see Table 22, Security Code area). This area

can be accessed only in Read mode by the final

user. It is impos sible to change t he secu rity num-

ber after it has been written by ST. Issue a Read

command to return to Read mode.

Table 17. Q uer y Stru cture Overvi ew

Note: Query data are always presented on the lowest order data outputs.

Table 18. CFI Query Identification String

Address Sub-section Name Descript ion

10h CFI Query Identification String Command set ID and algorithm data offset

1Bh System Interface Information Device timing & voltage information

27h Device Geometr y Defin ition Flash device layout

40h Primary Algorithm-specific Extended Query

table Additional information specific to the Primary

Algorithm (optional)

61h Security Code Area 64 bit unique device number

Address Data Description Value

10h 51h "Q"

11h 52h Query Unique ASCII String "QRY" "R"

12h 59h "Y"

13h 02h Primary Algorithm Command Set and Control Interface ID code 16 bit ID code

defining a specific algorithm AMD

Compatible

14h 00h

15h 40h Address for Primary Algorithm extended Query table (see Table 20) P = 40h

16h 00h

17h 00h Alternate Vendor Command Set and Control Interf ace ID Code second v endor

- specified algorithm supported NA

18h 00h

19h 00h Address for Alternate Algorithm extended Query table NA

1Ah 00h

M29F080D

28/36

Table 19. C FI Query S ystem Interface I nform atio n

No te : 1. Not support ed in the CF I

Address Data Description Value

1Bh 45h VCC Logic Supply Minimum Program/Erase voltage

bit 7 to 4 BCD value in volts

bit 3 to 0 BCD value in 100 mV 4.5V

1Ch 55h VCC Logic Supply Maximum Program/Erase voltage

bit 7 to 4 BCD value in volts

bit 3 to 0 BCD value in 100 mV 5.5V

1Dh 00h VPP [Programming] Supply Minimum Program/Erase voltage

00h not supported NA

1Eh 00h VPP [Programming] Supply Maximum Program/Erase voltage

00h not supported NA

1Fh 04h Typical timeout per single byte program = 2n µs 16µs

20h 00h Typical timeout for minimum size write buffer program = 2n µs NA

21h 0Ah Typical timeout per individual block erase = 2n ms 1s

22h 00h Typical timeout for full chip erase = 2n ms see note (1)

23h 04h Maximum timeout for byte program = 2n times typical 256µs

24h 00h Maximum timeout for write buffer program = 2n times typical NA

25h 03h Maximum timeout per individual block erase = 2n times typica l 8s

26h 00h Maximum timeout for chip erase = 2n times typical see note (1)

29/36

M29F080D

Table 20. Device Geo metry Defi nition

Address Data Description Value

27h 14h Device Size = 2n in number of bytes 1 MByte

28h

29h 00h

00h Flash Device Interface Code description x8 only

Async.

2Ah

2Bh 00h

00h Maximum number of bytes in multi-byte program or page = 2n NA

2Ch 01h Number of Erase Block Regions within the device.

It specifies the number of regions within the device containing contiguous

Erase Blocks of the same size. 1

2Dh

2Eh 0Fh

00h Re gion 1 Info r mation

Number of identical size erase block = 000Fh+1 16

2Fh

30h 00h

01h Region 1 Info r matio n

Block size in Region 1 = 0100h * 256 byte 64 Kbyte

M29F080D

30/36

Table 21. Primary Algorithm- Speci fic Extended Qu ery Ta ble

Table 22. Security Code Area

Address Data Description Value

40h 50h

Primary Algorithm extended Query table unique ASCII string “PRI”

"P"

41h 52h "R"

42h 49h "I"

43h 31h Major version number, ASCII "1"

44h 30h Minor version number, ASCII "0"

45h 00h Address Sensitive Unlock (bits 1 to 0)

00 = required, 01= not required

Silicon Revision Number (bits 7 to 2)

Yes

46h 02h Erase Suspend

00 = not supported, 01 = Read only, 02 = Read and Write 2

47h 04h Block Protection

00 = not supported, x = number of blocks per group 4

48h 01h Temporary Block Unprotect

00 = not supported, 01 = supported yes

49h 04h Block Protect /Unprotect

04 = M29W400B mode 4

4Ah 00h Simultan eous Operati ons, 00 = not supp or te d No

4Bh 00h Burst Mode, 00 = not supported, 01 = supported No

4Ch 00h Page Mode, 00 = not supported, 01 = 4 page word, 02 = 8 page word No

Address Data Description

61h XX

64 bit: unique device number

62h XX

63h XX

64h XX

65h XX

66h XX

67h XX

68h XX

31/36

M29F080D

APPENDIX C. BLOCK PRO TE CTION

Block protection can be used to prevent any oper-

ation from modifying the data stored in the memo-

ry. The blocks are protected in groups, refer to

Appendix A, Table 1 6 for details of the Protection

Groups. Once p rotected, Program and Erase op-

erations within the protected group fail to change

the data.

There are three techniques that can be used to

control Block Protection, these are the Program-

mer technique, the In- System technique and Tem-

porary Unprotection. Temporary Unprotection is

controlled by the Reset/Block Temporary Unpro-

tection pin, RP; this is des cribed in the S ign al De-

scriptions section.

To protect the Extended Block issue the Enter Ex-

tended Block command and then use either the

Programmer or In-System technique. Once pro-

tected issue the Exit Extended B lock c ommand to

return to read mode. The Extended B lock protec-

tion is irreversible, once protected the protection

cannot be undone.

Programme r Techniq ue

The Programmer technique uses high (VID) volt-

age levels on some of the bus pins. These cannot

be achieved using a standard microproc essor bus,

therefore the technique is recommended only for

use in Programming Equipment.

To protect a group of bloc ks follow the flowchart i n

Figure 14, Programmer Equipment Block Protect

Flowchart. To unprotect the whole chip it is neces-

sary to protect all of the groups first, then all

groups can be unprotected at the same time. To

unprotect the chip follow Figure 15, Programmer

Equipment Chip Unprotect Flowchart. Table 23,

Programmer Technique Bus Operations, gives a

summary of each operation.

The timing on these flowcharts is critical. Care

should be taken t o ensure that, where a pau se is

specified, it is followed as clos ely as possible. Do

not abort the procedure be fore reaching the end.

Chip Unprotect can take several seconds and a

user message should be provided to show that the

operation is progressing.

In-System Technique

The In-System technique requires a high voltage

level on the Reset/Blocks Temporary Unprotect

pin, RP . This can be achieved without violating the

maximum ratings of the components on the micro-

processor bus, therefore this techniqu e is suitable

for use after the memory has been fit ted to the sys-

tem.

To protect a group of bloc ks follow the flowchart i n

Figure 16, I n-S ystem Block Protect F lowchart . T o

unprotect the who le chip it is nece ssary to prot ect

all of the groups first, then all the groups can be

unprotected at the same time. To unprotect the

chip follow Figure 17, In-System Chip Unprotect

Flowchart.

The timing on these flowcharts is critical. Care

should be taken t o ensure that, where a pau se is

specified, it is followed as clos ely as possible. Do

not allow the m icroprocessor t o service interrupts

that will upset the timing and do not abort the pro-

cedure before reaching the end. Chip Unprotect

can take several seconds and a user message

should be provided to show that the operation is

progressing.

Table 23. Program mer Tech niqu e Bus Op erati ons, BYTE = VIH or VIL

Note: 1. Blo ck Protection Groups are show n i n Appendix A, Tab l e 16.

Operation E G W Address Inputs

A0-A19 Data Input s/Out puts

DQ15 A–1, DQ14 -DQ0

Block (Group)

Protect(1) VIL VID VIL Pulse A9 = VID, A12-A19 Block Address

Others = X X

Chip Unprotect VID VID VIL Pulse A9 = VID, A12 = VIH, A15 = VIH

Others = X X

Block (Group)

Protection Verify VIL VIL VIH A0 = VIL, A1 = V IH, A6 = VIL, A9=V

ID,

A12-A19 Block Address

Others = X

Pass = XX01h

Retry = XX00h

Block (Group)

Unprotection Verify VIL VIL VIH A0 = VIL, A1 = VIH, A 6 = VIH, A9 = VID,

A12-A19 Block Address

Others = X

Retry = XX01h

Pass = XX00h

M29F080D

32/36

Figure 14. Programmer Equipment Group Protect Flowchart

Note: Block Protection Groups are shown in Appendix A, Table 16.

ADDRESS = GROUP ADDRESS

AI05574

G, A9 = VID,

E = VIL

n = 0

Wait 4µs

Wait 100µs

W = VIL

W = VIH

E, G = VIH,

A0, A6 = VIL,

A1 = VIH

A9 = VIH

E, G = VIH

++n

= 25

START

FAIL

PASS

YES

DATA

01hYES

W = VIH

E = VIL

Wait 4µs

G = VIL

Wait 60ns

Read DATA

Verify Protect Set-upEnd

A9 = VIH

E, G = VIH

33/36

M29F080D

Fi gure 15. Progra m m er Equipmen t Chi p Unp rot ec t Flowc har t

Note: Block Protection Groups are shown in Appendix A, Table 16.

PROTECT ALL GROUPS

AI05575

A6, A12, A15 = VIH(1)

E, G, A9 = VID

DATA

W = VIH

E, G = VIH

ADDRESS = CURRENT GROUP ADDRESS

A0 = VIL, A1, A6 = VIH

Wait 10ms

00h

INCREMENT

CURRENT GROUP

n = 0

CURRENT GROUP = 0

Wait 4µs

W = VIL

++n

= 1000

START

YES

YESNO

NO LAST

GROUP

YES

E = VIL

Wait 4µs

G = VIL

Wait 60ns

Read DATA

FAIL PASS

Verify Unprotect Set-upEnd

A9 = VIH

E, G = VIH A9 = VIH

E, G = VIH

M29F080D

34/36

Figu re 16 . In- S ys te m Eq ui pm ent Grou p P rot ec t Fl owcha rt

Note: Block Protection Groups are shown in Appendix A, Table 16.

AI05576

WRITE 60h

ADDRESS = GROUP ADDRESS

A0 = VIL, A1 = VIH, A6 = VIL

n = 0

Wait 100µs

WRITE 40h

ADDRESS = GROUP ADDRESS

A0 = VIL, A1 = VIH, A6 = VIL

RP = VIH ++n

= 25

START

FAIL

PASS

YES

DATA

01hYES

RP = VIH

Wait 4µs

Verify Protect Set-upEnd

READ DATA

ADDRESS = GROUP ADDRESS

A0 = VIL, A1 = VIH, A6 = VIL

RP = VID

ISSUE READ/RESET

COMMAND

ISSUE READ/RESET

COMMAND

WRITE 60h

ADDRESS = GROUP ADDRESS

A0 = VIL, A1 = VIH, A6 = VIL

35/36

M29F080D

Figure 17. In-System Equipment Chi p Unprotect Flowchart

Note: Block Protection Groups are shown in Appendix A, Table 16.

AI05577

WRITE 60h

ANY ADDRESS WITH

A0 = VIL, A1 = VIH, A6 = VIH

n = 0

CURRENT GROUP = 0

Wait 10ms

WRITE 40h

ADDRESS = CURRENT GROUP ADDRESS

A0 = VIL, A1 = VIH, A6 = VIH

RP = VIH

++n

= 1000

START

FAIL PASS

YES

DATA

00h

YESNO

RP = VIH

Wait 4µs

READ DATA

ADDRESS = CURRENT GROUP ADDRESS

A0 = VIL, A1 = VIH, A6 = VIH

RP = VID

ISSUE READ/RESET

COMMAND

ISSUE READ/RESET

COMMAND

PROTECT ALL GROUPS

INCREMENT

CURRENT GROUP

LAST

GROUP

YES

WRITE 60h

ANY ADDRESS WITH

A0 = VIL, A1 = VIH, A6 = VIH

Verify Unprotect Set-upEnd

M29F080D

36/36

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