S-8233A Series
www.sii-ic.com
BATTERY PROTECTION IC
FOR 3-SERIAL-CELL PACK
© Seiko Instruments Inc., 1997-2013 Rev.6.0_01
Seiko Instruments Inc. 1
The S-8233A Series is a series of lithium-ion rechargeable battery protection ICs incorporating high-accuracy
voltage detection circuits and delay circuits. It is suitable for a 3-serial-cell lithium-ion rechargeable battery
pack.
Features
(1) Internal high-accuracy voltage detection circuit
y Overcharge detection voltage 4.10 ± 0.05 V to 4.35 ± 0.05 V
50 mV- step
y Overcharge release voltage 3.85 ± 0.10 V to 4.35 ± 0.10 V
50 mV- step
(The overcharge release voltage can be selected within the range where a difference from
overcharge detection voltage is 0 V to 0.3 V)
y Overdischarge detection voltage 2.00 ± 0.08 V to 2.70 ± 0.08 V
100 mV- step
y Overdischarge release voltage 2.00 ± 0.10 V to 3.70 ± 0.10 V
100 mV - step
(The overdischarge release voltage can be selected within the range where a difference from
overdischarge detection voltage is 0 V to 1.0 V)
y Overcurrent detection voltage 1 0.15 ± 0.015 V to 0.50 ± 0.05 V
50 mV-step
(2) High-withstand voltage device (absolute maximum rating: 26 V)
(3) Wide operating voltage range: 2 V to 24 V
(4) The delay time for every detection can be set via an external capacitor.
(5) Three overcurrent detection levels (protection for short-circuiting)
(6) Internal charge/discharge prohibition circuit via the control pin
(7) The function for charging batteries from 0 V is available.
(8) Low current consumption
y Operation 50 μA max. (+25 °C)
y Power-down 0.1 μA max. (+25 °C)
(9) Lead-free, Sn 100%, halogen-free*1
*1. Refer to “ Product Name Structure” for details.
Applications
y Lithium-ion rechargeable battery packs
y Lithium polymer rechargeable battery packs
Package
y 16-Pin TSSOP
BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK
S-8233A Series Rev.6.0_01
Seiko Instruments Inc.
2
Block Diagram
Battery 1
Overcharge
Battery 3
Overdischarge
Battery 3
Overcharge
Battery 2
Overcharge
Battery 2
Overdischarge
Overcharge
delay circuit
Battery 1
Overdischarge
Battery 3
Overcharge
Battery 2
Overcharge
Battery 1
Overcharge
Reference
volta
g
e 3
Reference
voltage 2
Reference
voltage 1
Control
Logic
Overcurrent
detection
circuit
Overdischarge
delay circuit
Overcurrent1,
delay circuit
Overcurrent 2,3
delay circuit
−
+
−
+
−
+
−
+
−
+
−
+
DOP
VMP
COVT
CDT
CCT
COP
CTL
VSS
CD3
VC2
CD2
CD1
VC1
VCC
Floating
detection circuit
Figure 1
Remark The delay time for overcurrent detection 2 and 3 is fixed by an internal IC circuit. The delay time
cannot be changed via an external capacitor.
BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK
Rev.6.0_01 S-8233A Series
Seiko Instruments Inc. 3
Product Name Structure
1. Product name
S-8233A x FT − TB − x
Environmental code
U : Lead-free (Sn 100%), halogen-free
G : Lead-free (for details, please contact our sales office)
IC direction in tape specifications*1
Package name (abbreviation)
FT: 16-Pin TSSOP
Serial code
Assigned from A to Z in alphabetical order
*1. Refer to the tape specifications.
2. Package
Drawing Code
Package Name Package Tape Reel
16-Pin TSSOP FT016-A-P-SD FT016-A-C-SD FT016-A-R-SD
3. Product name list
Table 1
Product name / Item
Overcharge
detection
voltage
V
Cu
Overcharge
release
voltage
V
CD
Overdischarge
detection
voltage
V
DD
Overdischarge
release
voltage
V
DU
Overcurrent
detection
voltage1
V
IOV1
0 V battery
charge
function
Conditioning
function
S-8233ACFT-TB-x 4.25 V 4.05 V 2.00 V 2.30 V 0.20 V
−
Available
S-8233ADFT-TB-x 4.10 V 4.10 V 2.00 V 2.30 V 0.20 V
−
Unavailable
S-8233AEFT-TB-x 4.25 V 4.10 V 2.30 V 2.70 V 0.15 V
−
Available
S-8233AFFT-TB-x 4.35 V 4.05 V 2.40 V 2.70 V 0.50 V Available Available
S-8233AGFT-TB-x 4.25 V 4.05 V 2.40 V 2.70 V 0.40 V Available Available
S-8233AIFT-TB-x 4.25 V 4.10 V 2.30 V 3.00 V 0.15 V
−
Available
S-8233AJFT-TB-x 4.35 V 4.05 V 2.40 V 2.70 V 0.30 V
−
Available
S-8233AKFT-TB-x 4.35 V 4.05 V 2.40 V 2.70 V 0.15 V
−
Available
S-8233ALFT-TB-x 4.35 V 4.05 V 2.40 V 2.70 V 0.40 V Available Available
S-8233AMFT-TB-x 4.35 V 4.05 V 2.40 V 2.70 V 0.30 V Available Available
S-8233ANFT-TB-x 4.35 V 4.05 V 2.40 V 2.40 V 0.15 V Available Available
S-8233AOFT-TB-x 4.35 V 4.05 V 2.40 V 2.70 V 0.15 V Available Available
S-8233APFT-TB-x 4.25 V 4.05 V 2.70 V 3.00 V 0.30 V Available Available
S-8233ARFT-TB-x 4.35 V 4.05 V 2.00 V 2.70 V 0.30 V Available Available
S-8233ASFT-TB-x 4.25 V 4.05 V 2.40 V 2.70 V 0.50 V Available Available
Remark 1. Please contact our sales office for the products with the detection voltage value other than those
specified above.
2. x: G or U
3. Please select products of environmental code = U for Sn 100%, halogen-free products.
BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK
S-8233A Series Rev.6.0_01
Seiko Instruments Inc.
4
Pin Configuration
Table 2
Pin No. Symbol Description
1 DOP
Connects FET gate for discharge control (CMOS output)
2 NC
No connection
*1
3 COP
Connects FET gate for charge control (Nch open-drain output)
4 VMP
Detects voltage between VCC to VMP(Overcurrent detection pin)
5 COVT
Connects capacitor for overcurrent detection1 delay circuit
6 CDT
Connects capacitor for overdischarge detection delay circuit
7 CCT
Connects capacitor for overcharge detection delay circuit
8 VSS
Negative power input, and connects negative voltage for battery 3
9 CTL
Charge/discharge control signal input
10 CD3
Battery 3 conditioning signal output
11 VC2
Connects battery 2 negative voltage and battery 3 positive voltage
12 CD2
Battery 2 conditioning signal output
13 VC1
Connects battery 1 negative voltage and battery 2 positive voltage
14 CD1
Battery 1 conditioning signal output
15 NC
No connection
*1
VSS
VMP
VCC
CTL
14
13
12
11
10
9
7
6
5
4
3
2
1
DOP
COP
CCT
COVT
CDT
VC1
VC2
CD1
CD3
CD2
16-Pin TSSOP
Top view
8
15
16
NC
NC
Figure 2
16 VCC
Positive power input and connects battery 1 positive voltage
*1. The NC pin is electrically open. The NC pin can be connected to
VCC or VSS.
BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK
Rev.6.0_01 S-8233A Series
Seiko Instruments Inc. 5
Absolute Maximum Ratings
Table 3
(Ta = 25°C unless otherwise specified)
Item Symbol Applied Pin Absolute Maximum Ratings Unit
Input voltage between VCC and VSS VDS − V
SS−0.3 ~ VSS+26 V
Input pin voltage VIN VC1, VC2, CTL,
CCT, CDT, COVT
VSS−0.3 ~ VCC+0.3 V
VMP Input pin voltage VVMP VMP VSS−0.3 ~ VSS+26 V
CD1 output pin voltage VCD1 CD1 VC1−0.3 ~ VCC+0.3 V
CD2 output pin voltage VCD2 CD2 VC2−0.3 ~ VCC+0.3 V
CD3 output pin voltage VCD3 CD3 VSS−0.3 ~ VCC+0.3 V
DOP output pin voltage VDOP DOP VSS−0.3 ~ VCC+0.3 V
COP output pin voltage VCOP COP VSS−0.3 ~ VSS+26 V
− 300 (When not mounted on board) mW
Power dissipation PD − 1100*1 mW
Operating ambient temperature Topr − −20 ~ +70 °C
Storage temperature Tstg − −40 ~ +125 °C
*1. When mounted on board
[Mounted board]
(1) Board size : 114.3 mm × 76.2 mm × t1.6 mm
(2) Board name : JEDEC STANDARD51-7
Caution The absolute maximum ratings are rated values exceeding which the product could suffe
r
physical damage. These values must therefore not be exceeded under any conditions.
050 100 150
800
400
0
Power Dissipation (P
D
) [mW]
Ambient Temperature (Ta) [°C]
1000
600
200
1200
1400
Figure 3 Power Dissipation of Package (When Mounted on Board)
BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK
S-8233A Series Rev.6.0_01
Seiko Instruments Inc.
6
Electrical Characteristics
Table 4 (1 / 2)
(Ta = 25°C unless otherwise specified)
Item Symbol Condition Min. Typ. Max. Unit
Test
Condition
Test
Circuit
Detection voltage
Overcharge detection voltage 1 V
CU1
4.10 to 4.35 Adjustment V
CU1
−
0.05 V
CU1
V
CU1
+0.05 V 1 1
Overcharge release voltage 1 V
CD1
3.85 to 4.35 Adjustment V
CD1
−
0.10 V
CD1
V
CD1
+0.10 V 1 1
Overdischarge detection voltage 1 V
DD1
2.00 to 2.70 Adjustment V
DD1
−
0.08 V
DD1
V
DD1
+0.08 V 1 1
Overdischarge release voltage 1 V
DU1
2.00 to 3.70 Adjustment V
DU1
−
0.10 V
DU1
V
DU1
+0.10 V 1 1
Overcharge detection voltage 2 V
CU2
4.10 to 4.35 Adjustment V
CU2
−
0.05 V
CU2
V
CU2
+0.05 V 2 1
Overcharge release voltage 2 V
CD2
3.85 to 4.35 Adjustment V
CD2
−
0.10 V
CD2
V
CD2
+0.10 V 2 1
Overdischarge detection voltage 2 V
DD2
2.00 to 2.70 Adjustment V
DD2
−
0.08 V
DD2
V
DD2
+0.08 V 2 1
Overdischarge release voltage 2 V
DU2
2.00 to 3.70 Adjustment V
DU2
−
0.10 V
DU2
V
DU2
+0.10 V 2 1
Overcharge detection voltage 3 V
CU3
4.10 to 4.35 Adjustment V
CU3
−
0.05 V
CU3
V
CU3
+0.05 V 3 1
Overcharge release voltage 3 V
CD3
3.85 to 4.35 Adjustment V
CD3
−
0.10 V
CD3
V
CD3
+0.10 V 3 1
Overdischarge detection voltage 3 V
DD3
2.00 to 2.70 Adjustment V
DD3
−
0.08 V
DD3
V
DD3
+0.08 V 3 1
Overdischarge release voltage 3 V
DU3
2.00 to 3.70 Adjustment V
DU3
−
0.10 V
DU3
V
DU3
+0.10 V 3 1
Overcurrent detection voltage 1
*1
V
IOV1
0.15 to 0.50V Adjustment V
IOV1
x 0.9 V
IOV1
V
IOV1
x 1.1 V 4 2
Overcurrent detection voltage 2 V
IOV2
V
CC
Reference 0.54 0.6 0.66 V 4 2
Overcurrent detection voltage 3 V
IOV3
V
SS
Reference 1.0 2.0 3.0 V 4 2
Voltage temperature factor 1
*2
T
COE1
Ta = -20 to 70°C
*4
−
1.0 0 1.0 mV/
°
C
−
−
Voltage temperature factor 2
*3
T
COE2
Ta = -20 to 70°C
*4
−
0.5 0 0.5 mV/
°
C
−
−
Delay time
Overcharge detection delay time 1 t
CU1
C
CCT
= 0.47
μ
F 0.5 1.0 1.5 s 9 6
Overcharge detection delay time 2 t
CU2
C
CCT
= 0.47
μ
F 0.5 1.0 1.5 s 10 6
Overcharge detection delay time 3 t
CU3
C
CCT
= 0.47
μ
F 0.5 1.0 1.5 s 11 6
Overdischarge detection delay time 1 t
DD1
C
CDT
= 0.1
μ
F 20 40 60 ms 9 6
Overdischarge detection delay time 2 t
DD2
C
CDT
= 0.1
μ
F 20 40 60 ms 10 6
Overdischarge detection delay time 3 t
DD3
C
CDT
= 0.1
μ
F 20 40 60 ms 11 6
Overcurrent detection delay time 1 t
IOV1
C
COVT
= 0.1
μ
F 10 20 30 ms 12 7
Overcurrent detection delay time 2 t
IOV2
−
2 4 8 ms 12 7
Overcurrent detection delay time 3 t
IOV3
FET gate capacitor = 2000 pF 100 300 550
μ
s 12 7
Operating voltage
Operating voltage between VCC and VSS
*5
V
DSOP
−
2.0
−
24 V
−
−
Current consumption
Current consumption
(during normal operation) I
OPE
V1 = V2 = V3 = 3.5 V
−
20 50
μ
A 5 3
Current consumption for cell 2 I
CELL2
V1 = V2 = V3 = 3.5 V
−
300 0 300 nA 5 3
Current consumption for cell 3 I
CELL3
V1 = V2 = V3 = 3.5 V
−
300 0 300 nA 5 3
Current consumption at power down I
PDN
V1 = V2 = V3 = 1.5 V
−
−
0.1
μ
A 5 3
Internal resistance
V1 = V2 = V3 = 3.5 V 0.40 0.90 1.40 M
Ω
6 3 Resistance between
VCC and VMP R
VCM
V1 = V2 = V3 = 3.5 V
*6
0.20 0.50 0.80 M
Ω
6 3
V1 = V2 = V3 = 1.5 V 0.40 0.90 1.40 M
Ω
6 3 Resistance between
VSS and VMP R
VSM
V1 = V2 = V3 = 1.5 V
*6
0.20 0.50 0.80 M
Ω
6 3
Input voltage
CTL"H" Input voltage V
CTL(H)
−
V
CC
x0.8
−
−
V
−
−
CTL"L" Input voltage V
CTL(L)
−
−
−
V
CC
x0.2 V
−
−
BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK
Rev.6.0_01 S-8233A Series
Seiko Instruments Inc. 7
Table 4 (2 / 2)
(Ta = 25°C unless otherwise specified)
Item Symbol Condition Min. Typ. Max. Unit
Test
Condition
Test
Circuit
Output voltage
DOP"H" voltage V
DO(H)
I
OUT
= 10
μ
A V
CC
-0.5
−
−
V 7 4
DOP"L" voltage V
DO(L)
I
OUT
= 10
μ
A
−
−
V
SS
+0.1 V 7 4
COP"L" voltage V
CO(L)
I
OUT
= 10
μ
A
−
−
V
SS
+0.1 V 8 5
COP OFF LEAK current I
COL
V1 = V2 = V3 = 4.5 V
−
−
100 nA 14 9
CD1"H" voltage V
CD1(H)
I
OUT
= 0.1
μ
A V
CC
-0.5
−
−
V 13 8
CD1"L" voltage V
CD1(L)
I
OUT
= 10
μ
A
−
−
V
C1
+0.1 V 13 8
CD 2"H" voltage V
CD2(H)
I
OUT
= 0.1
μ
A V
CC
-0.5
−
- V 13 8
CD 2"L" voltage V
CD2(L)
I
OUT
= 10
μ
A
−
−
V
C2
+0.1 V 13 8
CD3"H" voltage V
CD3(H)
I
OUT
= 0.1
μ
A V
CC
-0.5
−
−
V 13 8
CD3"L" voltage V
CD3(L)
I
OUT
= 10
μ
A
−
−
V
SS
+0.1 V 13 8
0 V battery charging function
0 V charging start voltage V
0CHAR
−
*6
−
−
1.4 V 15 10
*1.
If overcurrent detection voltage 1 is 0.50 V, both overcurrent detection voltages 1 and 2 are 0.54 to 0.55 V, but V
IOV2
> V
IOV1
.
*2.
Voltage temperature factor 1 indicates overcharge detection voltage, overcharge release voltage, overdischarge detection voltage, and
overdischarge release voltage.
*3.
Voltage temperature factor 2 indicates overcurrent detection voltage.
*4.
Since products are not screened at high and low temperature, the specification for this temperature range is guaranteed by design, not
tested in production.
*5.
The DOP and COP logic must be established for the operating voltage.
*6.
This spec applies for only 0 V battery charging function available type.
BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK
S-8233A Series Rev.6.0_01
Seiko Instruments Inc.
8
Test Circuits
(1) Test condition 1 Test circuit 1
Set V1, V2, and V3 to 3.5 V under normal status. Increase V1 from 3.5 V gradually. The V1 voltage
when COP = 'H' is overcharge detection voltage 1 (VCU1). Decrease V1 gradually. The V1 voltage when
COP = 'L' is overcharge release voltage 1 (VCD1). Further decrease V1. The V1 voltage when DOP = 'H'
is overdischarge voltage 1 (VDD1). Increase V1 gradually. The V1 voltage when DOP = 'L' is
overdischarge release voltage 1 (VDU1).
Remark The voltage change rate is 150 V/s or less.
(2) Test condition 2 Test circuit 1
Set V1, V2, and V3 to 3.5 V under normal status. Increase V2 from 3.5 V gradually. The V2 voltage
when COP = 'H' is overcharge detection voltage 2 (VCU2). Decrease V2 gradually. The V2 voltage when
COP = 'L' is overcharge release voltage 2 (VCD2). Further decrease V2. The V2 voltage when DOP = 'H'
is overdischarge voltage 2 (VDD2). Increase V2 gradually. The V2 voltage when DOP = 'L' is
overdischarge release voltage 2 (VDU2).
Remark The voltage change rate is 150 V/s or less.
(3) Test condition 3 Test circuit 1
Set V1, V2, and V3 to 3.5 V under normal status. Increase V3 from 3.5 V gradually. The V3 voltage
when COP = 'H' is overcharge detection voltage 3 (VCU3). Decrease V3 gradually. The V3 voltage when
COP = 'L' is overcharge release voltage 3 (VCD3). Further decrease V3. The V3 voltage when DOP = 'H'
is overdischarge voltage 3 (VDD3). Increase V3 gradually. The V3 voltage when DOP = 'L' is
overdischarge release voltage 3 (VDU3).
Remark The voltage change rate is 150 V/s or less.
(4) Test condition 4 Test circuit 2
Set V1, V2, V3 to 3.5 V and V4 to 0 V under normal status. Increase V4 from 0 V gradually. The V4
voltage when DOP = 'H' and COP = 'H', is overcurrent detection voltage 1 (VIOV1).
Set V1, V2, and V3 to 3.5 V and V4 to 0 V under normal status. Fix the COVT pin at VSS, increase V4
from 0 V gradually. The V4 voltage when DOP = 'H' and COP = 'H' is overcurrent detection voltage 2
(VIOV2).
Set V1, V2, and V3 to 3.5 V and V4 to 0 V under normal status. Fix the COVT pin at VSS, increase V4
gradually from 0 V at 400 μs to 2 ms. The V4 voltage when DOP = 'H' and COP = 'H' is overcurrent
detection voltage 3 (VIOV3).
(5) Test condition 5 Test circuit 3
Set S1 to ON, V1, V2, and V3 to 3.5 V, and V4 to 0 V under normal status and measure current
consumption. I1 is the normal status current consumption (IOPE), I2, the cell 2 current consumption
(ICELL2), and I3, the cell 3 current consumption (ICELL3).
Set S1 to ON, V1, V2, and V3 to 1.5 V, and V4 to 4.5 V under overdischarge status. Current
consumption I1 is power-down current consumption (IPDN).
(6) Test condition 6 Test circuit 3
Set S1 to ON, V1, V2, and V3 to 3.5 V, and V4 to 10.5 V under normal status. V4/I4 is the internal
resistance between VCC and VMP (RVCM).
Set S1 to ON, V1, V2, and V3 to 1.5 V, and V4 to 4.1 V under overdischarge status. (4.5-V4)/I4 is the
internal resistance between VSS and VMP (RVSM).
BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK
Rev.6.0_01 S-8233A Series
Seiko Instruments Inc. 9
(7) Test condition 7 Test circuit 4
Set S1 to ON, S2 to OFF, V1, V2, and V3 to 3.5 V, and V4 to 0 V under normal status. Increase V5 from
0 V gradually. The V5 voltage when I1 = 10 μA is DOP'L' voltage (VD0(L)).
Set S1 to OFF, S2 to ON, V1, V2, V3 to 3.5 V, and V4 to VIOV2+0.1 V under overcurrent status. Increase
V6 from 0 V gradually. The V6 voltage when I2 = 10 μA is the DOP'H' voltage (VDO(H)).
(8) Test condition 8 Test circuit 5
Set V1, V2, V3 to 3.5 V and V4 to 0 V under normal status. Increase V5 from 0 V gradually. The V5
voltage when I1 = 10 μA is the COP'L' voltage (VC0(L)).
(9) Test condition 9 Test circuit 6
Set V1, V2, V3 to 3.5 V under normal status. Increase V1 from 3.5 V to 4.5 V immediately (within 10 μs).
The time after V1 becomes 4.5 V until COP goes 'H' is the overcharge detection delay time 1 (tCU1).
Set V1, V2, V3 to 3.5 V under normal status. Decrease V1 from 3.5 V to 1.9 V immediately (within 10 μs).
The time after V1 becomes 1.9 V until DOP goes 'H' is the overdischarge detection delay time 1 (tDD1).
(10) Test condition 10 Test circuit 6
Set V1, V2, V3 to 3.5 V under normal status. Increase V2 from 3.5 V to 4.5 V immediately (within 10 μs).
The time after V2 becomes 4.5 V until COP goes 'H' is the overcharge detection delay time 2 (tCU2).
Set V1, V2, V3 to 3.5 V under normal status. Decrease V2 from 3.5 V to 1.9 V immediately (within 10 μs).
The time after V2 becomes 1.9 V until DOP goes 'H' is the overdischarge detection delay time 2 (tDD2).
(11) Test condition 11 Test circuit 6
Set V1, V2, V3 to 3.5 V under normal status. Increase V3 from 3.5 V to 4.5 V immediately (within 10 μs).
The time after V3 becomes 4.5 V until COP goes 'H' is the overcharge detection delay time 3 (tCU3).
Set V1, V2, V3 to 3.5 V under normal status. Decrease V3 from 3.5 V to 1.9 V immediately (within 10 μs).
The time after V3 becomes 1.9 V until DOP goes 'H' is the overdischarge detection delay time 3 (tDD3).
(12) Test condition 12 Test circuit 7
Set V1, V2, V3 to 3.5 V and S1 to OFF under normal status. Increase V4 from 0 V to 0.55 V immediately
(within 10 μs). The time after V4 becomes 0.55 V until DOP goes 'H' is the overcurrent detection delay
time 1 (tI0V1).
Set V1, V2, V3 to 3.5 V and S1 to OFF under normal status. Increase V4 from 0 V to 0.75 V immediately
(within 10 μs). The time after V4 becomes 0.75 V until DOP goes 'H' is the overcurrent detection delay
time 2 (tIOV2)
Set S1 to ON to inhibit overdischarge detection. Set V1, V2, V3 to 4.0 V and increase V4 from 0 V to 6.0
V immediately (within 1 μs) and decrease V1, V2, and V3 to 2.0 V at a time. The time after V4 becomes
6.0 V until DOP goes 'H' is the overcurrent detection delay time 3 (tIOV3).
BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK
S-8233A Series Rev.6.0_01
Seiko Instruments Inc.
10
(13) Test condition 13 Test circuit 8
Set S4 to ON, S1, S2, S3, S5, and S6 to OFF, V1, V2, V3 to 3.5 V and V4, V6, and V7 to 0 V under
normal status. Increase V5 from 0 V gradually. The V5 voltage when I2 = 10 μA is the CD1'L' voltage
(VCD1(L))
Set S5 to ON, S1, S2, S3, S4, and S6 to OFF, V1, V2, and V3 to 3.5 V and V4, V5, and V7 to 0 V under
normal status. Increase V6 from 0 V gradually. The V6 voltage when I3 = 10 μA is the CD2'L' voltage
(VCD2(L)).
Set S6 to ON, S1, S2, S3, S4, and S5 to OFF, V1, V2, and V3 to 3.5 V and V4, V5, and V6 to 0 V under
normal status. Increase V7 from 0 V gradually. The V7 voltage when I4 = 10 μA is the CD3'L' voltage
(VCD3(L)).
Set S1 to ON, S2, S3, S4, S5, and S6 to OFF, V1 to 4.5 V, V2 and V3 to 3.5 V and V5, V6, and V7 to 0 V
under overcharge status. Increase V4 from 0 V gradually. The V4 voltage when I1 = 0.1 μA is the
CD1'H' voltage (VCD1(H)).
Set S2 to ON, S1, S3, S4, S5, and S6 to OFF, V2 to 4.5 V, V1 and V3 to 3.5 V and V5, V6, and V7 to 0 V
under overcharge status. Increase V4 from 0 V gradually. The V4 voltage when I1 = 0.1 μA is the
CD2'H' voltage (VCD2(H)).
Set S3 to ON, S1, S2, S4, S5, and S6 to OFF, V3 to 4.5 V, V1 and V2 to 3.5 V and V5, V6, and V7 to 0 V
under overcharge status. Increase V4 from 0 V gradually. The V4 voltage when I1 = 0.1 μA is the
CD3'H' voltage (VCD3(H)).
(14) Test condition 14 Test circuit 9
Set V1, V2, and V3 to 4.5 V under overcharge status. The current I1 flowing to COP pin is COP OFF
LEAK current (ICOL).
(15) Test condition 15 Test circuit 10
Set V1, V2, and V3 to 0 V, and V8 to 2 V, and decrease V8 gradually. The V8 voltage when COP = 'H'
(VSS + 0.1 V or higher) is the 0V charge start voltage (V0CHAR).
BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK
Rev.6.0_01 S-8233A Series
Seiko Instruments Inc. 11
VSS
DOP
CTL
VC2
COP
VMP
VC1
CCT
COVT
CDT
VCC
CD3
CD2
CD1
V3
V2
V1
1 MΩ
S-8233A
VSS
DOP
CTL
VC2
COP
VMP
VC1
CCT
COVT
CDT
VCC
CD3
CD2
CD1
V3
V2
V1
V4
1 MΩ
S-8233A
Test circuit 1 Test circuit 2
VSS
DOP
CTL
VC2
COP
VMP
VC1
CCT
COVT
CDT
VCC
CD3
CD2
CD1
V3
V2
I2
I3
S1
I1
I4
V1
V4
S-8233A
VSS
DOP
CTL
VC2
COP
VMP
VC1
CCT
COVT
CDT
VCC
CD3
CD2
CD1
V3
V2
V1
V5
S1 I1
S2 I2
V6
V4
S-8233A
Test circuit 3 Test circuit 4
VSS
DOP
CTL
VC2
COP
VMP
VC1
CCT
COVT
CDT
VCC
CD3
CD2
CD1
V3
V2
V5 I1
V1
V4
S-8233A
VSS
DOP
CTL
VC2
COP
VMP
VC1
CCT
COVT
CDT
VCC
CD3
CD2
V1
V3
V2
CD1
C3
C2
C1
1 MΩ
C1 = 0.47 μF
C2 = 0.1 μF
C3 = 0.1 μF
S-8233A
Test circuit 5 Test circuit 6
Figure 4 (1 / 2)
BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK
S-8233A Series Rev.6.0_01
Seiko Instruments Inc.
12
VSS
DOP
CTL
VC2
COP
VMP
VC1
CCT
COVT
CDT
VCC
CD3
CD2
V1
V3
V2
CD1
C3
C2
S1
C1
C1 = 0.47
μ
F
C2 = 0.1 μF
C3 = 0.1 μF
V4
1 MΩ
S-8233A
VSS
DOP
CTL
VC2
COP
VMP
VC1
CCT
COVT
CDT
VCC
CD3
CD2
CD1
V3
V2
1 MΩ
V1
V5
V7
V6
V4
S1
S5
S6
S2
S4
S3
I1
I2
I3
I4
S-8233A
Test circuit 7 Test circuit 8
VSS
DOP
CTL
VC2
COP
VMP
VC1
CCT
COVT
CDT
VCC
CD3
CD2
V1
V3
V2
CD1
I1
S-8233A
VSS
DOP
CTL
VC2
COP
VMP
VC1
CCT
COVT
CDT
VCC
CD3
CD2
V1
V3
V2
CD1
1 MΩ
V8
S-8233A
Test circuit 9 Test circuit 10
Figure 4 (2 / 2)
BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK
Rev.6.0_01 S-8233A Series
Seiko Instruments Inc. 13
Operation
Remark Refer to “ Battery Protection IC Connection Example”.
Normal status
This IC monitors the voltages of the three serially-connected batteries and the discharge current to control
charging and discharging. If the voltages of all the three batteries are in the range from the overdischarge
detection voltage (VDD) to the overcharge detection voltage (VCU), and the current flowing through the
batteries becomes equal or lower than a specified value (the VMP pin voltage is equal or lower than
overcurrent detection voltage 1), the charging and discharging FETs turn on. In this status, charging and
discharging can be carried out freely. This status is called the normal status. In this status, the VMP and
VCC pins are shorted by the RVCM resistor.
Overcurrent status
This IC is provided with the three overcurrent detection levels (VIOV1,VIOV2 and VIOV3) and the three
overcurrent detection delay time (tIOV1,tIOV2 and tIOV3) corresponding to each overcurrent detection level.
If the discharging current becomes equal to or higher than a specified value (the VMP pin voltage is equal
to or higher than the overcurrent detection voltage) during discharging under normal status and it
continues for the overcurrent detection delay time (tIOV) or longer, the discharging FET turns off to stop
discharging. This status is called an overcurrent status. The VMP and VCC pins are shorted by the RVCM
resistor at this time. The charging FET turns off.
When the discharging FET is off and a load is connected, the VMP pin voltage equals the VSS potential.
The overcurrent status returns to the normal status when the load is released and the impedance
between the EB- and EB+ pins (see Figure 9) is 100 MΩ or higher. When the load is released, the VMP
pin, which and the VCC pin are shorted with the RVCM resistor, goes back to the VCC potential. The IC
detects that the VMP pin potential returns to overcurrent detection voltage 1 (VIOV1) or lower (or the
overcurrent detection voltage 2 (VIOV2) or lower if the COVT pin is fixed at the 'L' level and overcurrent
detection 1 is inhibited) and returns to the normal status.
Overcharge status
If one of the battery voltages becomes higher than the overcharge detection voltage (VCU) during charging
under normal status and it continues for the overcharge detection delay time (tCU) or longer, the charging
FET turns off to stop charging. This status is called the overcharge status. The 'H' level signal is output
to the conditioning pin corresponding to the battery which exceeds the overcharge detection voltage until
the battery becomes equal to lower than the overcharge release voltage (VCD). The battery can be
discharged by connecting an Nch FET externally. The discharging current can be limited by inserting
R11, R12 and R13 resistors (see Figure 9). The VMP and VCC pins are shorted by the RVCM resistor
under the overcharge status.
The overcharge status is released in two cases:
<1> The battery voltage which exceeded the overcharge detection voltage (VCU) falls below the
overcharge release voltage (VCD), the charging FET turns on and the normal status returns.
<2> If the battery voltage which exceeded the overcharge detection voltage (VCU) is equal or higher than
the overcharge release voltage (VCD), but the charger is removed, a load is placed, and discharging
starts, the charging FET turns on and the normal status returns.
The release mechanism is as follows: the discharge current flows through an internal parasitic diode of
the charging FET immediately after a load is installed and discharging starts, and the VMP pin voltage
decreases by about 0.6 V from the VCC pin voltage momentarily. The IC detects this voltage
(overcurrent detection voltage 1 or higher), releases the overcharge status and returns to the normal
status.
BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK
S-8233A Series Rev.6.0_01
Seiko Instruments Inc.
14
Overdischarge status
If any one of the battery voltages falls below the overdischarge detection voltage (VDD) during discharging
under normal status and it continues for the overdischarge detection delay time (tDD) or longer, the
discharging FET turns off and discharging stops. This status is called the overdischarge status. When
the discharging FET turns off, the VMP pin voltage becomes equal to the VSS voltage and the IC's
current consumption falls below the power-down current consumption (IPDN). This status is called the
power-down status. The VMP and VSS pins are shorted by the RVSM resistor under the overdischarge
and power-down statuses.
The power-down status is canceled when the charger is connected and the voltage between VMP and
VSS is 3.0 V or higher (overcurrent detection voltage 3). When all the battery voltages becomes equal to
or higher than the overdischarge release voltage (VDU) in this status, the overdischarge status changes to
the normal status.
Delay circuits
The overcharge detection delay time (tCU1 to tCU3), overdischarge detection delay time (tDD1 to tDD3), and
overcurrent detection delay time 1 (tIOV1) are changed with external capacitors (C4 to C6).
The delay times are calculated by the following equations:
Min. Typ. Max.
tCU[s] = Delay factor ( 1.07, 2.13, 3.19)×C4 [μF]
tDD[s] = Delay factor ( 0.20, 0.40, 0.60)×C5 [μF]
tIOV1[s] = Delay factor ( 0.10, 0.20, 0.30)×C6 [μF]
Caution The delay time for overcurrent detection 2 and 3 is fixed by an internal IC circuit. The
delay time cannot be changed via an external capacitor.
CTL pin
If the CTL pin is floated under normal status, it is pulled up to the VCC potential in the IC, and both the
charging and discharging FETs turn off to inhibit charging and discharging. Both charging and
discharging are also inhibited by applying the VCC pin to the CTL pin externally. At this time, the VMP
and VCC pins are shorted by the RVCM resistor.
When the CTL pin becomes equal to VSS potential, charging and discharging are enabled and go back to
their appropriate statuses for the battery voltages.
Caution Please note unexpected behavior might occur when electrical potential difference
between the CTL pin ('L' level) and VSS is generated through the external filter (RVSS and
CVSS) as a result of input voltage fluctuations.
0 V battery charging function
This function is used to recharge the three serially-connected batteries after they self-discharge to 0 V.
When the 0 V charging start voltage (V0CHAR) or higher is applied to between VMP and VSS by connecting
the charger, the charging FET gate is fixed to VSS potential.
When the voltage between the gate sources of the charging FET becomes equal to or higher than the
turn-on voltage by the charger voltage, the charging FET turns on to start charging. At this time, the
discharging FET turns off and the charging current flows through the internal parasitic diode in the
discharging FET. If all the battery voltages become equal to or higher than the overdischarge release
voltage (VDU), the normal status returns.
Caution In the products without 0 V battery charging function, the resistance between VCC and
VMP and between VSS and VMP are lower than the products with 0 V battery charging
function. It causes to that overcharge detection voltage increases by the drop voltage of
R5 (see Figure 9) with sink current at VMP.
The COP output is undefined below 2.0 V on VCC-VSS voltage in the products without 0
V battery charging function.
BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK
Rev.6.0_01 S-8233A Series
Seiko Instruments Inc. 15
Voltage temperature factor
Voltage temperature factor 1 indicates overcharge detection voltage, overcharge release voltage,
overdischarge detection voltage, and overdischarge release voltage.
Voltage temperature factor 2 indicates overcurrent detection voltage.
The Voltage temperature factors 1 and 2 are expressed by the oblique line parts in Figure 5.
V
CU25
Ex. Voltage temperature factor of overcharge detection voltage Typ.
−20 25
+1 mV/°C
V
CU
[V]
V
CU25
is the overcharge detection voltage at 25°C
70 Ta [°C]
−1 mV/°C
Figure 5
BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK
S-8233A Series Rev.6.0_01
Seiko Instruments Inc.
16
Timing Chart
1. Overcharge detection
VCU
VCD
VDU
VDD
VCC
VSS
VSS
VCHA
VCC
VIOV1
VSS
<1> <2> <1> <2> <1> <1> <5> <3>
<2>&<3>
<3>
High-Z
High-Z
High-Z
High-Z
*1. <1>Normal status, <2>Overcharge status, <3>Overdischarge status, <4>Overcurrent status, <5>Power-down status
Remark The charger is assumed to charge with a constant current. VCHA indicates the open voltage of the charger.
Battery
voltage
DOP pin
COP pin
VMP pin
Charger
connected
Load
connected
Status*1
Delay
Delay
Delay
Delay
Delay
V1 battery V2 battery V3 battery
Figure 6
2. Overdischarge detection
VCU
VCD
VDU
VDD
Battery
voltage
DOP pin
VCC
VSS
VSS
VCHA
VCC
VIOV1
VSS
COP pin
VMP pin
Charger
connected
Delay Delay
Load
connected
Status*1
<1> <5> <3> <1> <5> <3> <1> <5> <3> <1> <2> <1> <5> <3> <1>
High-Z
*1. <1>Normal status, <2>Overcharge status, <3>Overdischarge status, <4>Overcurrent status, <5>Power-down status
Remark The charger is assumed to charge with a constant current. VCHA indicates the open voltage of the charger.
Delay
Delay Delay
V1 battery V2 battery V3 battery
Figure 7
BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK
Rev.6.0_01 S-8233A Series
Seiko Instruments Inc. 17
3. Overcurrent detection
High-Z
VCU
VCD
VDU
VDD
Battery
voltage
DOP pin
VCC
VSS
VSS
COP pin
VMP pin
Charger
connected
Delay tIOV1 Delay tIOV2
Load
connected
Status*
<1> <4> <1> <4> <1> <4> <1> <1>
CTL pin
V
SSÆVCC
VCC
VIOV1
VIOV2
VIOV3
Delay
tIOV3
Inhibit charging and
discharging
High-Z
High-Z
High-Z
CTL pin
V
CCÆVSS
*1. <1>Normal status, <2>Overcharge status , <3>Overdischarge status, <4>Overcurrent status
V1, V2, and V3 batteries
Figure 8
BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK
S-8233A Series Rev.6.0_01
Seiko Instruments Inc.
18
Battery Protection IC Connection Example
EB-
R1
Battery 1
Battery 3
Battery 2
R2
C1
C2
C3
R11
R13
R12
FET-A
FET1
FET3
FET2
R3
High: Inhibit over
discharge
detection.
VSS
DOP
VC2
VC1
VCC
CD1
CD3
CD2
EB+
S-8233A series
CTL
COP
VMP
C4
C5
C6
CCT
COVT
CDT
Overcharge delay
time setting
Overcurrent delay
time setting
Overdischarge delay
time setting
Nch open
drain
GND: Normal operation
Floating: Inhibit charging
and discharging.
R7
R6
10 KΩ
R5
1 KΩ
1 MΩ
FET-C
FET-B
Figure 9
[Description of Figure 9]
y R11, R12, and R13 are used to adjust the battery conditioning current.The conditioning current
during overcharge detection is given by Vcu (overcharge detection voltage)/R (R: resistance).To
disable the conditioning function, open CD1, CD2, and CD3.
y The overcharge detection delay time (tCU1 to tCU3), overdischarge detection delay time (tDD1 to tDD3),
and overcurrent detection delay time (tIOV1) are changed with external capacitors (C4 to C6). See the
electrical characteristics.
y R6 is a pull-up resistor that turns FET-B off when the COP pin is opened. Connect a 100 kΩ to 1 MΩ
resistor.
y R5 is used to protect the IC if the charger is connected in reverse. Connect a 10 kΩ to 50 kΩ
resistor.
y If capacitor C6 is absent, rush current occurs when a capacitive load is connected and the IC enters
the overcurrent mode. C6 must be connected to prevent it.
y If capacitor C5 is not connected, the IC may enter the overdischarge status due to variations of
battery voltage when the overcurrent occurs. In this case, a charger must be connected to return to
the normal status. To prevent this, connect an at least 0.01 μF capacitor to C5.
y If a leak current flows between the delay capacitor connection pin (CCT, CDT, or COVT) and VSS,
the delay time increases and an error occurs. The leak current must be 100 nA or less.
y Overdischarge detection can be disabled by using FET-C. The FET-C off leak must be 0.1 μA or
less. If overdischarge is inhibited by using this FET, the current consumption does not fall below 0.1
μA even when the battery voltage drops and the IC enters the overdischarge detection mode.
y R1, R2, and R3 must be 1 kΩ or less.
y R7 is the protection of the CTL when the CTL pin voltage higher than VCC voltage. Connect a 300 Ω
to 5 kΩ resister. If the CTL pin voltage never greater than the VCC voltage (ex. R7 connect to VSS),
without R7 resistance is allowed .
BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK
Rev.6.0_01 S-8233A Series
Seiko Instruments Inc. 19
Caution 1. The above constants may be changed without notice.
2. If any electrostatic discharge of 2000 V or higher is not applied to the S-8233A series
with a human body model, R1, R2, R3, C1, C2, and C3 are unnecessary.
3. It has not been confirmed whether the operation is normal or not in circuits other than
the above example of connection. In addition, the example of connection shown above
and the constant do not guarantee proper operation. Perform through evaluation using
the actual application to set the constant.
Precautions
y If a charger is connected in the overdischarge status and one of the battery voltages becomes equal to or
higher than the overcharge release voltage (VCU) before the battery voltage which is below the
overdischarge detection voltage (VDD) becomes equal to or higher than the overdischarge release voltage
(VDU), the overdischarge and overcharge statuses are entered and the charging and discharging FETs turn
off. Both charging and discharging are disabled. If the battery voltage which was higher than the
overcharge detection voltage (VCU) falls to the overcharge release voltage (VCD) due to internal
discharging, the charging FET turns on.
If the charger is detached in the overcharge and overdischarge status, the overcharge status is released,
but the overdischarge status remains. If the charger is connected again, the battery status is monitored
after that. The charging FET turns off after the overcharge detection delay time, the overcharge and
overdischarge statuses are entered.
y If any one of the battery voltages is equal to or lower than the overdischarge release voltage (VDU) when
they are connected for the first time, the normal status may not be entered. If the VMP pin voltage is made
equal to or higher than the VCC voltage (if a charger is connected), the normal status is entered.
y If the CTL pin floats in power-down mode, it is not pulled up in the IC, charging and discharging may not be
inhibited. However, the overdischarge status becomes effective. If the charger is connected, the CTL pin
is pulled up, and charging and discharging are inhibited immediately.
y Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in
electrostatic protection circuit.
y SII claims no responsibility for any disputes arising out of or in connection with any infringement by
products including this IC of patents owned by a third party.
BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK
S-8233A Series Rev.6.0_01
Seiko Instruments Inc.
20
Characteristics (Typical Data)
1. Detection voltage temperature characteristics
4.15
4.25
4.35
-40 -20 0 20 40 60 80 100
Ta [°C]
VCU [V]
Overcharge detection voltage vs. temperature
VCU = 4.25 V
4.00
4.10
4.20
-40 -20 020 40 60 80 100
VCD = 4.10 V
Ta [°C]
VCD [V]
Overcharge release voltage vs. temperature
2.25
2.35
2.45
-40 -20 0 20 40 60 80 100
VDD = 2.35 V
Ta [°C]
VDD [V]
Overdischarge detection voltage vs. temperature
2.75
2.85
2.95
-40 -20 020 40 60 80 100
VDU = 2.85 V
Ta [°C]
VDU [V]
Overdischarge release voltage vs. temperature
0.25
0.30
0.35
-40 -20 0 20 40 60 80 100
VIOV1 = 0.3 V
Ta [°C]
VIOV1 [V]
Overcurrent1 detection voltage vs. temperature
0.55
0.60
0.65
-40 -20 020 40 60 80 100
VIOV2 = 0.6 V
Ta [°C]
VIOV2 [V]
Overcurrent2 detection voltage vs. temperature
BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK
Rev.6.0_01 S-8233A Series
Seiko Instruments Inc. 21
2. Current consumption temperature characteristics
0
25
50
-40 -20 0 20 40 60 80 100
VCC = 10.5 V
Ta [°C]
IOPE [μA]
Current consumption vs. temperature in normal mode
0.0
0.5
1.0
-40 -20 020 40 60 80 100
VCC = 4.5 V
Ta [°C]
IPDN [nA]
Current consumption vs. temperature in power-down mode
3. Delay time temperature characteristics
tCU [s]
Overcharge detection time vs. temperature
0.5
1.0
1.5
-40 -20 0 20 40 60 80 100
C = 0.47
μ
F
VCC = 11.5 V
Ta [°C]
20
40
60
-40 -20 020 40 60 80 100
C = 0.1
μ
F
VCC = 8.5 V
Ta [°C]
tDD [ms]
Overdischarge detection time vs. temperature
10
20
30
-40 -20 0 20 40 60 80 100
C = 0.1
μ
F
VCC = 10.5 V
Ta [°C]
tIOV1 [ms]
Overcurrent1 detection time vs. temperature
Overcurrent2 detection time vs. temperature
2
5
8
-40 -20 020 40 60 80 100
Ta [°C]
tIOV2 [ms]
VCC = 10.5 V
BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK
S-8233A Series Rev.6.0_01
Seiko Instruments Inc.
22
0.10
0.25
0.40
-40 -20 0 20 40 60 80 100
Ta [°C]
tIOV3 [ms]
Overcurrent3 (load short) detection time vs. temperature
VCC = 6.0 V
4. Delay time vs. power supply voltage
0
0.5
1.0
3 6 9 12 15
VCC [V]
tIOV3 [ms]
Ta = 25°C
Overcurrent 3 (load short) detection time vs. power supply voltage
Caution Please design all applications of the S-8233A Series with safety in mind.
0.17±0.05
9
18
16
5.1±0.2
0.22±0.08
0.65
No.
TITLE
SCALE
UNIT mm
Seiko Instruments Inc.
No. FT016-A-P-SD-1.1
FT016-A-P-SD-1.1
TSSOP16-A-PKG Dimensions
4.0±0.1
2.0±0.1
ø1.5+0.1
-0
ø1.6±0.1
8.0±0.1
4.2±0.2
6.5 +0.4
-0.2
0.3±0.05
1.5±0.1
(7.2)
No.
TITLE
SCALE
UNIT mm
8
1
9
16
Seiko Instruments Inc.
No. FT016-A-C-SD-1.1
FT016-A-C-SD-1.1
TSSOP16-A-Carrier Tape
Feed direction
No.
TITLE
SCALE
UNIT mm
17.4±1.0
Seiko Instruments Inc.
No. FT016-A-R-SD-2.0
FT016-A-R-SD-2.0
TSSOP16-A- Reel
QTY. 2,000
Enlarged drawing in the central part
2±0.5
ø13±0.2
ø21±0.8
21.4±1.0
17.4 +2.0
-1.5
www.sii-ic.com
• The information described herein is subject to change without notice.
• Seiko Instruments Inc. is not responsible for any problems caused by circuits or diagrams described herein
whose related industrial properties, patents, or other rights belong to third parties. The application circuit
examples explain typical applications of the products, and do not guarantee the success of any specific
mass-production design.
• When the products described herein are regulated products subject to the Wassenaar Arrangement or other
agreements, they may not be exported without authorization from the appropriate governmental authority.
• Use of the information described herein for other purposes and/or reproduction or copying without the
express permission of Seiko Instruments Inc. is strictly prohibited.
• The products described herein cannot be used as part of any device or equipment affecting the human
body, such as exercise equipment, medical equipment, security systems, gas equipment, vehicle equipment,
in-vehicle equipment, aviation equipment, aerospace equipment, and nuclear-related equipment, without prior
written permission of Seiko Instruments Inc.
• The products described herein are not designed to be radiation-proof.
• Although Seiko Instruments Inc. exerts the greatest possible effort to ensure high quality and reliability, the
failure or malfunction of semiconductor products may occur. The user of these products should therefore
give thorough consideration to safety design, including redundancy, fire-prevention measures, and
malfunction prevention, to prevent any accidents, fires, or community damage that may ensue.
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