__ PRELIMINARY intel. | 27960CX | PIPELINED BURST ACCESS 1M (128K x 8) CHMOS EPROM m Synchronous 4 Byte Data Burst Access m Pipelined Addressing for Optimal Bus Bandwidth on 80960CA m No Glue Interface to 80960CA Next Addressing Overlaps Last Data m High Performance Clock to Data Out Byte Oe to 33 Miz BOS60CA Performance @ CHMOS IIE for High Performance and : . Low Power... w Asynch Microcontroller Reset Function . 125 mA Active, 30 mA Standby . Returns to Known State with High-Z TTL Compatible Inputs Outputs a 1 Mbit Density Configures as 128K x 8 Intels 27960CX is a 5V only, 1 048, 576 bit, Erasable Programmable Read Only Memory, organized as 128K words of 8 bits. The 27960CX provides a no glue synchronous burst interface to the 8O960CA bus. Internally the 27960CX is organized in 4 byte blocks, in which each byte is accessed sequentially. The internal state machine is. factory configured to generate either 1 or 2 wait-states between. the address and first data byte. High performance outputs provide zero wait-state data to data accesses at clock frequencies up to 33 MHz. Pipelining capability allows addresses to overi evious data, further optimizing bus bandwidth in 80960CA applications. An asynchronous microcontroller RESET feature puts the outputs in the high impedance state and takes the internal state machine to a known state where a new burst access.can begin. The 27960CX is available in 44-lead PLCC package, providing optimum cost effectiveness. 4 The 27960CX is manufactured on Intels 1 micron CHMOS Il!-E technology. The Quick-Pulse Programming algorithm provides fast, reliable programming with throughput under 17 seconds for optimized equipment. *CHMOS is a Patented Process of Intel Corporation. X PREDECODER Ao- Aig : Yunmnoor um roar mMAPraw mMz--IToOPpeEe Y DECODER 290236-1 Figure 1. 27960CX Burst EPROM Block Diagram September 1991 4-19 Order Number: 290236-006intel. 27960CX PRELIMINARY 27960CX BURST EPROM EPROMs are established as the preferred code stor- age device in embedded applications. The non-vola- tile, flexible, reliable, cost effective EPROM makes a product easier to design, manufacture and service. Until recently, however, EPROMs could not match the performance needs of high-end systems. The 27960CX was designed to support the 80960CA em- bedded processor. It utilizes the burst interface to offer near zero wait-state performance without the high cost normally associated with this performance. In embedded designs, board space and cost must be kept at a minimum without impacting perform- ance and reliability. The 27960CX removes the need for expensive high-speed shadow RAM backed up by slow EPROM or ROM for non-volatile code stor- age. Code optimization concerns are reduced with off-chip code fetches no longer crippling to sys- tem performance. FONTs can be run directly out of these EPROMs at the same performance as high- speed DRAMs. With the 27960CX, the EPROM is the ideat code or FONT storage device for your 80960CA system. *CERQUAD is availabie in a socket only version. Architecture The 27960CX provides a no-glue, synchronous burst interface to the 80960CAs bus. It operates in pipe- lined or non-pipelined modes. Internally, the 27960CX is organized in 4 byte blocks which are accessed sequentially. A burst access begins on the first clock pulse after ADS and CS are asserted. The address of the 4 byte block is latched on the rising edge of clock following ADS. After a preset number of wait-states (1 or 2), data is output one byte at a time on each subsequent clock cycle. A burst ac- cess is terminated on the rising edge of clock with BLAST asserted. High performance outputs provide zero wait-state data to data accesses at clock fre- quencies up to 33 MHz. Extra power and ground Pins dedicated to the outputs reduce the effects of fast output switching on device performance. The pipelining capability of the 27960CX allows the address to overlap the last data byte of the burst, further optimizing bus band width in 8O960CA appli- cations. In the pipelined mode, with a non-buffered interface, the 27960CX delivers 4 bytes of data in 6 clock cycles at 33 MHz. In a 32-bit configuration, this translates into a read bandwidth of 88 Mbytes/ sec. Performance capability of the 27960CX in dif- ferent 80960CA systems is given in Table I. cs ADDRESS 17 DATA (FF arseocx _ 8 BURST ADS EPROM __ BAST zak x8 RESET Sy CLK ____ PGM _______ > 290236-2 Figure 2. 27960CX Burst EPROM Signal Set279600X PRELIMINARY Table 1. Performance Capability 33MHz 2WS_ Non:Buffered: 4 Words/6 Clock Cycles > 88 Mbytes/Sec : ADDR | Ao) | WS | WS | | | | Aoy | WS | WS | | | | Ago] WS DATA | | | | Doo | Dor | Do2:| Dos |- . | Dio | Day | Diz | Dig | PCLK Cy Co Ca | Gy Cs Ce Gr Cy | Cop C3 Ca Cs Ce Cy 25MHz 2WS_ Buffered: 4 Words/6 Clock Cycles > 66 Mbytes/Sec ADDR | Ao | ws | wS | | | Tf Ao | ws | ws i | | | Ago | ws DATA |; _ | Doo | Dor | Doz | Dos | | Dio | Dir | Dia | Org | PCLK Cy Co Cg C4 C5 Cg C7 Cy Co C3 C4 Cs Ce Cy 16 MHz 1WS Buttered: 4 Words/5 Clock Cycles 51 Mbytes/Sec ADDR | Ao | ws | | ~ | | Ao | WS} - | | Ago | ws DATA | | | Doo | Dor | Oo2 | Dog | | Ov } Ory | Dy2 | Dig | PCLK | Cy Co | Cg | Cy | Cy | Ce | Cr | Co | Cg | Cy | Co | ir | = [a ssw th JBB es 65 4 35 2 1 44-43 42 dg 07 39D A, Ves ye DAs Voc: 04 9 3s7RA, 10 : 36 i N27960CX . Bas 4 44 LEAD PLCC Ae Vgs3 412 s4FAy 0.650" x 0.650" sais "TOP VIEW SSFAo Dy Pl Ay Vssq Pl Ag Vec2 lA, B, pal Ay 18 19 20 21.22 23 24 25 26 27 28 SERB TST F ee 290236-3 Figure 3. 27960CX 44 Lead PLCC Pinout 4-21intl. a70800x PRELIMINARY PIN DESCRIPTIONS Symbol Pin Funetion Ao-Ai6' 23-39 ADDRESS INPUTS: During a burst operation, A2z-A16 provides the , base address pointing to.a block of four consective bytes. Ag and Ay select the first byte of the burst access. The 27960CX latches addresses in the first clock cycle. An internal address generator increments addresses Ap and.A; for subsequent bytes of the burst. Do-D7 18,.17, 14, DATA INPUTS/OUTPUTS 13, 11, 10, 7,6 . ADS 42 ADDRESS STROBE: Indicates the start of a new bus access. ADS is . active low in the first clock cycle of a. bus access. cs - 3 CHIP SELECT: Master device enable. When asserted (active low) data can be written to and read from the device. In read mode, enables the state machine and the 1/0 circuitry. NOTE: 1. The address decode path is independent of CS, i.e., X and Y decoding is always powered up. . 2. For programming, CS should remain low for the entire cycle. Program and verify functions are done one byte at a time. 3. TS going high does not terminate a concurrent burst cycle. ' BLAST 1 BURST LAST: Termiriates aoncurrent burst data cycle at the rising edge of the CLK. It must be asserted by the fourth data byte. RESET 22 RESET: Resets the state machine into a known state, tri-states the outputs. RESET must be asserted for a:minimum of 10 clock cycles. At - least 5 clock cycles are required after deassertion of RESET before .. beginning the next cycle. will abort a concurrent bus cycle. PGM 43 - PROGRAM-PULSE CONTROL INPUT. Vpp 2 _ PROGRAMMING POWER SUPPLY Vss 5, 8, 12, GROUND 15, 19, 21 , Voc 9, 16, 20, 44 ' SUPPLY VOLTAGE INPUT 4-22intel. 27960CX PRELIMINARY INTERFACE EXAMPLE Overview This example illustrates 8-, 16- and 32-bit wide 27960CX interfaces to the 80960CA. The designs offer a simple no-glue interface. , A non-buffered 27960CX system organized as 256K x 32 is shown in Figure 4A. Since the 27960CX is capable of driving a 80 pF load, large, non-buffered systems can be implemented by stacking up to 2 banks of 4 EPROMs, resulting in a.256K x 32 memo- ty subsystem. The input capacitive load seen on the address lines (due to the EPROM only) is 24 pF for a 128K x 32 system and 48 pF for a 256K x 32 system. Fhe EPROM. is specified at 6 pF for input capacitance (15 pF max) and 12 pF typical for out- put capacitance. Larger systems can be implement- ed with buffers (Figure 4B). Chip Select Logic High order address lines are decoded to provide TS. Qualification with other signals is not required. The chip select logic can be implemented with standard asynchronous decoders, PALs or PLDs (like Intel's 85C508). CS, DEC cs, ~ -{ ts Pes: [ts [les cs cs cs: Ss . 27960CX | 27960CX] 27960Cx 27960CX aDbress V| 128K 128K 128K 128K x x x x 8 8 8 8 80960CA ps Lb Ly ud 290236-4 Figure 4A. 256K x 32 Non-Buffered Burst EPROM Memory System ADDRESS DRIVER 27960CX 128K x . 8 ADDRESS 80960CA cs 27960CX 128K cs 27960CX 128K x 8 27960CX 128K x 8 M 8 290236-5 Figure 4B. Buffered Burst EPROM Memory System 4-23intel. a760cx PRELIMINARY Schematics In a non-buffered, 16-bit system (Figure 6A) BET and Ag connect to the lower order address bits of Figure 5 shows a non-buffered, 128K x 32 27960CX the 27960CX. BET connects to Ag of both EPROMs, EPROM system. while Ag connects to both Aj's. Chip select logic, the only external logic that is re- in a non-buffered, 8-bit system (Figure 6B) BEO and quired for this interface, can be derived from the BET connect to Ao and A; respectively. global system chip select circuitry. DECODER |. CS (850508) ADDRESS as | @s cs = Ag-Atg _ AgmAt6 - Mom Aig ) AgmAig x05 17 27960CX 27960CX 27960Cx 27960CX - pL ADS 128Kx8 ADS 12BKx8 pl aos 128Kx8 ADS 128Kx8 PCLK . .- : ADs pI CLK : clk CLK CLK BLAST . : 80960CA BLAST - Pi BLAST BLAST Py BLAST { - 8 8 8 8 fen [eet [ot [eset DATA , , /- 5 "32 7 290236-6 Figure 5. 128K x 32 27960CX Burst EPROM System DECODER (85C508) ADDRESS cs Ag-Aig cs Ag~Aig ADS 27960 CLK 128K x a BLAST Ay Ay ADS _279600x CLK 128K x BF BLAST Ay Ao 80960CA" 16 290236-7 Figure 6A. 27960CX Burst EPROM in a 16-Bit System 4-24intel. 27960CX PRELIMINARY ADDRESS 80960CA [- 8 DECODER (85C508) : cs Ag-Aig ADS = 27960Cx cuk 128K x 8 BLAST Ay Ao 290236-6 Figure 6B. 27960CX Burst EPROM in a 8-Bit System Waveforms Figure 7 shows the timing waveforms of a 27960CX pipelined read in a 32-bit system. CS Setup Time CS setup time is the time between CS being assert- ed and the first CLK rising edge (during the address cycle). Since a memory access begins on the first CLK rising edge after ADS and CS are asserted, a minimum CS setup time of 7 ns (tgycH) at 33 MHz is 4-25 required. With the 80960CAs maximum valid ad- dress delay of 14 ns at 33 MHz, 9:ns remains for CS decoding logic. Bootup The wait state configuration (1 or 2), of the 27960CX is programmed by the user into the 80960CA Region Table parameters of NRAD, NRDD, and NXDA. NRADD is always 0 for the27960CX.27960CX PRELIMINARY CLK following the last data word of the burst. 0 in this case! ArwAte rH MX 04 X os K o X Xu Xe XX xx 27960CX OOES NOT USE THIS INFORMATION . . 4 NRAD = 2 \L/ Lf \W RXDA = 9 ay \ / , PIPELINED BURST READ mst 1 7 AY | ALS 290236-9 NOTES: 1. The EPROM can also operate in non pipelined mode i.e, next address and ADS can be asserted in the clock cycie 2.2 -0-0- 0 Burst Read 2 indicates the number of wait states to access the first word 0s indicate the number of wait states for subsequent data words: Figure 7. Two Cycles ofa 27960CX 2 Wait State 4 Byte Read (2-0-0-0 Burst Read) in a 32 Bit System During boot-up (Figure 8), the 80960CA picks up its Region Table data from addresses FFFF FFOO, FFFF FFO4; FFFF FFO8 and FFFF FFOC. Only the least significant byte of each of the above four 32-bit accesses is used to configure the Region Table. For boot-up, the wait-state parameters NRAD and NXDA default to 31 and 3 respectively. During boot-up, the 27960CX will wrap around the first word of the four- word burst and hold the first word until BLAST is asserted. 27960CX DEVICE NAMES The device names on the 27960CX were derived as mnemonics that correspond to the number of wait states and expected operating frequency for the de- vice. For example, the 25 MHz, 2 wait state 27960CX is named 27960C2-25. AC TIMING DERIVATIONS The AC timings for the 27960CX were generated specifically to meet the requirements of the 80960CA microprocessor. In each case the applica- ble 80960CA clock frequency and AC timing were taken together with an address buffer delay (if need- ed) and a typical 2 ns guardband to generate the 27960CX AC timing. Worst case timings were 4-26 always assumed. On timings where the EPROM. is faster than the microprocessor, we specified the time required by the EPROM and left the excess time as additional system guardband. The example below shows how the 27960C2-33 taveoh Heing was derived. @33 MHz the clock cycle is ~ 30 ns. tov2-of the 80960CA is 3 ns 14.ns. Typical 2 ns guardband. 27960C2-33 tavegh 30 ns 14.ns 2ns 14 ns Decoders are needed for the systems chip select decoding. For the 27960CX timings we assumed a 10 ns chip select decoder for 16 MHz and a 7 ns decoder for 25 MHz and 33 MHz systems. The ex- ample below shows how the 27960C2-33 tsvch tim- ing was derived. @33 MHz the clock cycle is ~ 30 ns. tove of the 80960CA is 3 ns 14 ns. Decoder = 7 ns 27960C2-33 tsvch = 30 ns 14ns 7 ns = 9ns27960CX PRELIMINARY ~w 0 7 ad N o PCLK Tae: 290236-10 Figure 8. 27960CX/80960CA Bootup Timing . 4-27are 3 27860CX PRELIMINARY 0, Vssi CLK cs vr _ BLAST Voce PGM 40S NC NC Vss2 Veer % v. _ 44-LEAD PLCC: ss3 . TOP VIEW 02 ssa Voc2 DoUocoodoooo Ae Ms BINARY SEQUENCE FROM Ag TO Aya As 290296-12 Ma Vpp = +5V R=1Kn CS = GND As Voo= +5V GND =O0V CLK = 1MHz M2 , Ay Mo 4g Ag Ay Ag 290236-11 Figure 9. 27960CX Burn in Blasing Diagram - System Buffering Considerations For large system applications. buffering may be re- quired between the microprocessor and memory: de- vices. The 25 and 16 MHz 27960CX AC timings take . this into account. For applications not requiring buff- ering these devices will provide additional | system guardband. The list below shows the buffers used in generating the 27960CX timings: Input Output Buffer Buffer 25 MHz 8ns 5ns 16 MHz 10 ns . 7ns 4-28 Note that the 25 MHz buffers are slightly faster in keeping with the increased sensitivity for higher per- formance. Significantly faster buffers are available for applications requiring. them. The example below shows. the tchqv: tinting analysis for a buffered 27960C2-25. @25 MHz the clock cycle is ~ 40 ns. tix, of. the 8O960CA is 5 ns. Output buffer fer 25 MHz = 5 ns 27960C2-25 tcHay = 40 ns 5ns 5ns , = 30 nsintel. 27960CX PRELIMINARY ABSOLUTE MAXIMUM RATINGS* NOTICE: This data sheet contains preliminary infor-. mation on new products in production. The specifica- Read Operating Temperature...... 0C to + 70C(8) tions are subject to change without notice. Verify with Case Temperature Under Bias . . 10C to + 80C(8) your oat tet Sales office that you have the latest fore final a n. Storage Temperature .......... 65C to + 125C = ene 9 *WARNING: Stressing the device beyond the Absolute All Input or Output Voltages Maximum Ratings may cause permanent damage. with Respect to Ground ...... 0.6V to +6.5V(4) These are stress ratings only. Opration beyond the Voltage on Ag Operating Conditions is not recommended and ex- with Respect to Ground..... 0.6V to + 13.0V(4) fended exposure beyond the Operating Conditions Vpp Supply Voltage may affect device reliability. ; with Respect to Ground..... 0.6V to + 14.0V(4) Voc Supply Voltage with Respect to Ground...... 0.6V to + 7.0V(4) READ OPERATION DC CHARACTERISTICS orc < Ty +70C, Voc = 5V +10%, TTL Inputs | . Symbol Parameter Notes Min Max Unit | . - Test Condition let Input Load Current 1 BA | Vin = 5.5V lo Output Leakage Current 10 pA | Vout = 5.5V Ipp Vpp Load Current Read 10 BA | Vpp = Oto Voc, PGM = Vin Isp Voc Standby | Switching 2 45 mA | TS = Vin, f = 33 MHz Stable 2 30 mA | CS = Vin Ioc Voc Active Current 1,3,7 125 mA | SS = Viz, f = 33 MHz, lour = OmA Vin Input Low Voltage 4 0.5 0.8 v Vin Input High Voltage 2.0 Voo +1] V VoL Output Low Voltage 0.45 Vi | lop = 2.1mMmA Vou Output High Voltage 5 Voc 0.8 Ve low = 100 pA 5 2.4 Ve| lon = 400 pA los Output Short Circuit 6 100 mA NOTES: 1. Maximum current is with outputs unloaded. 2. loc standby current assumes no output loading i.e., loy = lo, = O MA. 3. Ic is the sum of current through Voc3 + Vcocs4 and does not include the current through Vcoc1 and Voce. (Vcc; and Voce supply power to the output drivers. Vocg and Voos supply power to the reset of the device.) 4. Minimum DC input voitage on input and output pins is 0.5V. During transitions, this level may undershoot to 2.0V-for periods less than 20 ns. 5. Maximum DC voltage on input and output pins is Voc + 0.5V which may overshoot to Voc + 2. ov for periods less than 20 ns. 6. One output shorted for no more than one second. log is sampled but not 100% tested. 7. loc max measured with a 10.11 Ff capacitor between Voc and Vss. 8. This specification defines commercial product operating temperatures. 4-29ntel. 27960CX PRELIMINARY EXPLANATION OF AC SYMBOLS The nomenclature used for timing parameters are as per IEEE STD 662-1980 IEEE Standard Terminology for Semiconductor Memory. Each timing symbol has five characters. The first is always a t (for time). The second character repre- sents a signal name. e.g., (CLK, ADS, etc.). The third character represents the signals level (high or low) for the signal indicated by the second character. The fourth character represents a signal name at which a transition occurs marking the end of the time interval being specified. AC CHARACTERISTICS: READ OPERATION 0C < Ta < +70C, Voc = 5V +10% The fifth character represents the signal level indi- cated for the fourth character. The list below show character representations. : : A: Address R: Reset B: BLAST - Q: - Data C: Clock s: CS H: Logic High Level t Time L: ADS/Logic Low Level Vv: Valid P: Vpp Programming Voltage Z:. Tri-state Level X: No longer a valid driven logic level 27960C2-33 27960C2-25 27960C 1-16 Versions 33 MHz 25 MHz 16 MHz Unit / 2 Wait State 2 Wait State 1 Wait State , No. | Symbol Parameter Notes; Mii Max''| Min Max Min Max 1 tAVCoH Address Valid to CLKo 12. 10 22 ns CLK High 2 | toyHax | CLK High to. 2 0) 0 0 ns _, | Address Invalid , tttcH | ADS tow to CLK High CLKy 22 ns tcHLH | CLK high to ADS High 5 22 32 6 40 ns tsvcH | CS Valid to 1 , 14 ns CLK High 6 | toyHsx | CLK High to 2 0 0 0 ns CS Invalid 7 tcHav | CLK High to Data Valid 7 27 30 40 ns tcHax | CLK High to Data Invalid 5 ; 5 5 ns tcHaz | CLK HightoDataHighZ | 6 25 30 30 ns 10 tsvcH | BLAST Valid to 8 8 22 ns CLK High 11 tcHex | CLK High to 3 5 22 5 32 5 40 ns BLAST invalid NOTES: 1. Valid signal jevel is meant to be either a logic high or logic tow. - 2, The subscript .N represents the number of wait states for this parameter. CS can be de-asserted (high) after the number of wait states (N) has expired and the EPROM will continue to burst out data for the current cycle. 3. BLAST # must be returned high before the next rising clock edge. 4. The sum of tcHav + tavcH + Nok will not equal actual tavay if independent test conditions are used to obtain taycH and iv (N = number of wait states). 5. Al must be returned high before the next rising clock edge. 6. Sampled, not 100% tested. The transition is measured +500 mV from steady state voltage. 7. For capacitive loads above 80 pF, tcHay can be derated by 1 ns/20 pF. 4-30PRELIMINARY 27960CX intel. 1-9E2062 {swig viva yaav 41D Figure 10. 27960CX Pipelined 2 Wait State AC Waveforms 4-31intel . 27960CX PRELIMINARY AC CONDITIONS OF TEST Input Rise and Fall Times (10% to 90%)... eee eee eee 4ns Input Timing Reference Level ................ 1.5V Input Pulse Levels.................. 0.45V to 2.4V Output Timing Reference Level .............. 1.5V Table 2. Mode Table Mode CS | PGM | BLAST | ADS | RESET | Ay Vep | Voc | OUTPUT Read Vin | Vin | Vin | via T Vig X | Voc |Vocol Dour Standby(6) Vin | X X X Vie X | Voc (5) | Voc | HighZ Program Mi} Vin Vin | Vin) | Vin X (3) (3) Din Program Verify Vic | Vin | Vint) | Vay Vin | X (3) (3) | Dour Program Inhibit Vin | XxX X X | Vn | x (3) (3) | HighZ ID Byte 0: Manufacturer | Vi_ | Vin Vin) | Vy (2) Vin Vivo) |} Vee | Voc 89H 1D Byte 1: Part (27960) | Vw} Vin | Vint) | vin | Vay Vin | Voc | Voc | EOH ID Byte 2: CX Vir | View Vin | Vy (2) Vin Vip)"}> Voc Voc 01B ID Byte 3: 1 Wait State {| Vit | Vin Vin) | Viy(2) Vin Vip(?) Voc Voc 01B 2 Wait States . , 10B Reset X Xx X Xx Vit x Veco Voc High Z NOTES: 1. Vin until data terminated at which time BLAST must go to Viz. 2. Need to toggle from Viy to Vi_ to Vip. 3. See DC Programming Characteristics for Voc, Vip and V; 4. X can be Vi, or Vin. 5. Vpp = Vcc to meet standy current specification. 6. The device must be in the idle state (by asserting CAPACITANCE(1) T, = 25C, f = 1.0 MHz Voco > _Vpp > V; RESET of using BLA pp voltages. will cause a slight increase in standby current. BLAS T) before going into standby. Symbol Parameter Typ Max Unit Condition Cin Input Capacitance 4 6 pF Vin = OV Court Output Capacitance 12 15 - pF Vout = OV Cvpp Vpp Capacitance . 40 45 pF Vin = OV NOTE: 1. Sampled. Not 100% tested. 4-32intel. 279600x PRELIMINARY AC INPUT/OUTPUT REFERENCE WAVEFORMS AC TESTING LOAD CIRCUIT VOH INPUT ZV VOL TIMING PARAMETER DEVICE 70a vn a OUTPUT CL = 80 pF VOL L 290236-15 . nenesen'4 CL includes jig capacitance rut and outa rings are monsed Wom |_| Portonan t= SPF and FL = 4050 and output rise and fall time = 4 ns. CLOCK CHARACTERISTICS Versions 33 MHz 25 MHz 20 MHz 16 MHz Units Symbol | Parameter Min Max Min Max Min Max Min Max CLK Period 30.3 40 50 62.5 ns tpr Rise Time 1 4 1 4 1 4] 1 4 ns tpr Fall Time 1 4 1 4 1 4 1 4 ns tp Low Time (t/2) - 2 | t/2 | (t/2)- 3] t/2 | (t/2)- 4] 1/2 | (t/2) 4] t/2 ns tex High Time | (t/2)- 2) t/2 | (27-3) v2 | 27-4] v2 | a/7-4] v2 | ns Max Rise Time for Programming CLK = 100 ns CLOCK WAVEFORM 290236-16 4-33intel. 27960CX PRELIMINARY Program/Program Verify Initially, and after each erasure, all bits of the EPROM are in the 1s state. Data is introduced by selectively programming 0s into the desired bit locations. Although only 0s can be programmed, both 1s and 0s can be present in the data word. Ultraviolet erasure is the only way to change O's to 1's. Programming mode is entered when Vpp is raised to 12.75V. Program/Verify operation is synchronous with the clock and can only be initiated following an idle state. Program and Program Verify take place in 3 clock cycles. In the first clock cycle, addresses and data are input and programming occurs. Pro- gram Verify follows in the second clock cycle and the third clock cycie terminates synchronous Pro- gram/Verify operation, returning the state machine to the idle state with outputs at high impedance. As in the Read mode, Az-Aj point to a four byte block in the memory array. During programming, the internal address increment circuitry is disabled and the programmer must supply Ag and A, to point to an individual byte within the four byte block that is to be programmed. Only one byte is programmed in each 3 cycle Program/Verify sequence. Program Inhibit The Program Inhibit mode allows parallel program- ming and verification of multiple devices with differ- ent data. With Vpp at 12.75V, a Program/Verify se- quence is initiated for any device that receives a val- id ADS pulse and rising clock edge while CS is as- serted. A PGM pulse programs data in the first cycle of the sequence and data for Program Verify is out- put in the second cycle. The Program/Verify se- quence is inhibited on any devices for which is not asserted. Data will not be programmed and the outputs will remain in their high impedance state. inteligent Identifier Mode The devices manufacturer, product type, and con- figuration are stored in a four byte block that can be accessed by using the intgligent Identifier4 mode. 4-34 The programmer can verify the device identifier and choose the programming algorithm that corresponds to the Intel 27960CX. The intgligent identifier can also be used to verify that the product is configured with the desired Read mode options for wait states. intgligent Identifier mode.is entered when Ag (pin 32) is raised to its high voltage (Vip) level. The internal state machine is then set for intglligent Identifier Read operation. Reading the identifier is similar to a Read operation on a one wait state configured prod- uct. Up to four bytes can be read in a single burst access. inergen. Identifier read is terminated by a synchronous BLAST input, returning the state ma- chine to the idle state with outputs at high imped- ance. The four byte block code for the intgligent Identifier code is located at address 00H through 03H and is encoded as follows: MEANING (A1, AO) DATA Intel ID Byte 00 89h 27960 Byte 01 E0h CX Byte 10 01b 1 Wait State Byte 11 O1b 2 Wait States Byte 11 10b RESET MODE Due to the synchronous nature of the 27960CX, the various operating modes must be initiated from a known idle state. During normal operation, the inter- nal state machine returns to an idle state at the ter- mination of a bus access (after BLAST is asserted). During initial device power up, the state machine is in an indeterminant state. The reset mode is provid- ed to force operation into the idle state. Reset mode is entered when the RESET pin is asserted. Output pins are asynchronously set to the high impedance state and address latches are put into the flow through mode. A reset is successfully completed and the state machine set in an idle state when RESET has been asserted for a minimum of 10 clock cycles and deasserted for five clock cycles.27960CX PRELIMINARY ADDRESS = FIRST LOCATION Vpp =12.75V Vor = 6.254 PROGRAM ONE 100 ys PULSE INCREMENT X INCREMENT ADDRESS DEVICE FAILED COMPARE ALL BYTES TO ORIGINAL FAIL DEVICE PASSED 290236-17 Figure 11. Quick-Pulse Programming Algorithm 4-35intel. 27960CX PRELIMINARY QUICK-PULSE PROGRAMMING ALGORITHM The Quick-Puise Programming algorithm programs Intels 27960CX. Developed to substantially reduce programming throughput time, this algorithm allows optimized equipment to program a 27960CX< in un- der 17 seconds. Actual programming time depends on the programmer used. The Quick-Pulse Programming algorithm uses a 100 us pulse followed by a byte verification to deter- mine when the addressed byte is correctly pro- grammed. The algorithm terminates if 25 100 ys pulses fail to program a byte. Figure 11 shows the : 27960CX Quick-Pulse Programming algorithm flow- chart." ~ , The entire program-pulse/byte-verify sequence is . performed with Voc = 6.25V and Vpp = 12.75V. The program equipment must establish Voc before applying voltages to any other pins. When program- ming is complete, all bytes should be compared to the original data with Voc = 5.0V and Vpp 12.75V. D.C. PROGRAMMING CHARACTERISTICS 1, = 25 +5C Symbol Parameter Notes Min Max Unit Condition lu Input Load Current 10 PA | Vin = Vinor Vit loc Voc Program Current 1 125 mA | CS= Vit Ipp Vpp Program Current 1 50 mA | CS=ViL Vit Input Low Voltage 0.5 0.8 Vv Vin Input High Voltage 2.0 Voc + 0.5 Vv Voi Output Low Voltage(Verify) 0.40 V | iol = 2.1mA Vou Output High Voitage(Verify) Voc 0.8 Vv lon = 400 pA Vio Ag intgligent Identifier 11.5 125 cy Voltage Voc Supply Voltage (Program) 2 6.0 6.5 Vv Vpp Program Voltage 12.5 13.0 Vv NOTES: 1. The maximium current value is with outputs unloaded. 2. Voc must be applied simultaneously or before Vpp and removed simultaneously or after Vpp. 3. During programming clock levels are Viy4 and Vj. 4-36intel. 27960CX PRELIMINARY A.C. PROGRAMMING, RESET AND ID CHARACTERISTICS Ta = 25C +5C No. Symbol Parameter Notes Min Max Unit 1 taveL Address Valid to PGM Low 2 ps 2 tcHax | CLK High to Address Invalid 50 ns 3 tLLCH ADS Low to CLK High - 4 50 ns 4 tcHLH CLK High to.ADS High 2 50 ns 5 tsvcH CS Valid to CLK High 50 ns 6 tcHsx CLK High to CS Invalid 3 ns 7 tcHov CLK High to Dour Valid 100 ns 8 tcHax CLK High to Dot Invalid 0 ns 9 tevcH BLAST Valid to CLK High 50 ns 10 tcHBx CLK High to BLAST Invalid 4 50 ns 11 tove DATA Valid to PGM Low 2 rm) 12 tpLPH PGM Program Pulse Width 95 105 ps 13 tpHax PGM High to Din Invalid 2 ps 14 toLPL CLK Low to PGM Low 50 ns 15 tazcH Din Tri-State to CLK High 2 ps 16 tycs Voc Program Voltage to CLK High 7 2 ps 17 typs Vpp Program Voltage to CLK High 7 2 BS 18 tagHCH Ag Vip Voltage to CLK High 2 ps 19 tCHAgX CLK High to Ag Not Vip Voltage 2 ps 20 tavcH RESET Valid to CLK High 6 50 ns a1 tCHCL CLK High to CLK Low 5 100 ns 22 toLcH CLK Low to CLK High 5 100 ns NOTES: 1. If GS is low, ADS can go low no sooner than the falling edge of the previous CLK. 2. ADS must return high prior to the next rising edge of clock. 3. CS must remain tow until after the rising edge of CLKt. 4. BLAST must return high prior to the next rising edge of CLK. 5. Max CLK rise/fall time is 100 ns. 6. RESET must be low for 10 clock cycles and high for 5 clock cycles. 7. Voc must be applied simultaneously or before Vpp and removed simultaneously or after Vpp. 4-37intel. 379600x PRELIMINARY | @ a oS thn ADDR : ADDRESS 0 : : ADDRESS 1 DATA 0 IN qa DATA 1 () (2) | e 3 : __ in . + Pou : j Vin : f 6 @ 290236-18 Figure 12. 27960CX Programming Waveforms 4-38intel. 7e60cx PRELIMINARY RESET and inteligent identifier Waveforms | @ 2 a cto ULF Ft f FLrLP LT Lee so Xe Se 3 om : (PDO Vep i . YXXXXXEKXEKLY | & Figure 13. 27960CX RESET and ID Waveforms 4-39