NCP81031MNTWG - ON Semiconductor

March, 2011 − Rev. P0

1Publication Order Number:

NCP81031/D

NCP81031

Product Preview

Low Voltage Synchronous

Buck Controller with Power

Saving and Transient

Enhancement Features

The NCP81031 is a simple single phase solution with differential

phase current sensing, low current power saving mode of operation,

and on board gate drivers to provide accurately regulated power. It can

be set up to synchronize to an external clock or PWM signal within

certain frequency range.

The adaptive non overlap gate drive and power saving operation

circuit provide a low switching loss and high efficiency solution for

server, notebook, and desktop systems. A high performance

operational error amplifier is provided to simplify compensation of the

system. The NCP81031 features include soft−start sequence, accurate

overvoltage and over current protection, UVLO for VCC and VCCP,

and thermal shutdown.

Features

•High Performance Operational Error Amplifier

•Internal Soft−Start/Stop

•±0.5% internal Voltage Accuracy, 0.8 V voltage reference

•OCP accuracy, Four Re−entry Times Before Latch

•“Lossless” Differential Inductor Current Sensing

•Internal high precision current sensing amplifier

•Oscillator Frequency Range of 100 kHz − 1000 kHz

•20 ns Adaptive FET Non−overlap Time of internal Gate Driver

•5.0 V to 12 V Operation

•Support 1.5 V to 19 V Vin

•Vout from 0.8 V to 3.3 V (5 V with 12 VCC)

•Chip enable through OSC pin

•Latched Over Voltage Protection (OVP)

•Internally fixed OCP Threshold

•Guaranteed Startup Into Pre−Charged Loads

•Thermally Compensated Current Monitoring

•Thermal Shutdown Protection

•Integrated MOSFET Drivers

•Integrated BOOST diode with internal Rbst = 2.2 W

•Automatic Power Saving Mode to Maximize Efficiency During Light

Load Operation

•Sync Function

•Remote Ground Sensing

•Enhanced Transient Protection

•This is a Pb−Free Device

Applications

•Desktop and Server Systems

This document contains information on a product under development. ON Semiconductor

reserves the right to change or discontinue this product without notice.

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QFN16

CASE 485G

MARKING

DIAGRAMS

See detailed ordering and shipping information in the package

dimensions section on page 10 of this data sheet.

ORDERING INFORMATION

16 13

310

211

GND

PGOOD

SYNC

COMP

VSEN

FBG

CSN/VO

BOOT

VCCP

VCC

ROSC/EN

CSP

PIN CONNECTIONS

XXXXX

ALYWG

XXXXX = Specific Device Code

A = Assembly Location

L = Wafer Lot

Y = Year

W = Work Week

G= Pb−Free Package

(Note: Microdot may be in either location)

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Figure 1. NCP81031 BLOCK DIAGRAM

BOOT

VCCP

GND

CSP

CSN/VO

COMP

Control Logic,

Protection,

RAMP

Generator and

PWM Logic

−

CDIFF

UVLO

Control

−

VREF*75%

VREF*125%

UVP

OVP

OSC

Error Amplifier

Current Sense

Amplifier

−

VREF*50%

OVP,

UNLATCHED

0.8V

VSEN

FBG

PGOOD

SYNC

ROSC/EN Programmable

OSC

VCC

1.24V

2.2 W

Over Current

Detector

PIN DESCRIPTIONS

Pin No. Symbol Description

1 VCCP Power supply for MOSFET drivers

2 LG Bottom gate MOSFET driver pin.

3 LX Switch node

4 BOOT Supply rail for the floating top gate drier.

5 UG Top gate MOSFET driver pin.

6 PGOOD Power Good. It is an open−drain output set free after SS (with 3x clock delay) as long as the output

voltage monitored through VSEN is within specifications.

7 SYNC Synchronization Pin. The controller synchronizes on the falling edge of a square wave provided to

this pin. Short to GND if not used.

8 COMP Output of the error amplifier. The device cannot be disabled by grounding this pin

9 FB Inverting input to the error amplifier

10 VSEN Output Voltage Sensing

11 FBG Remote Ground Sense

12 CSN/VO Inductor differential sense inverting input

13 CSP Inductor differential sense non−inverting input

14 ROSC/EN Programs the switching frequency; EN: Pull−low to disable the device

15 VCC Supply rail for the controller internal circuitry.

16 GND Ground reference

THERMAL PAD Connects with the Silicon substrate for good thermal contact with the PCB. Connect to GND plane

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RF1

JP3

ETCH

CH1

RVFB1

RFB2

RSEN1

RNTC1

RISO1

RFB3

CF1

ENABLE

VCCP

RS4

ROSC1

VOUT

CSEN1

CFB2

RS3

LOUT1

VIN

CBOOT1

+COUT1

VCC

R2 R1

NCP5230

BOOT 4

COMP

LG 2

LX 3

GND

UG 5

VCC 15

CSP

CSN/VO

VCCP 1

ROSC/EN

PGOOD

SYNC

FBG

VSEN

SYNC

PGOOD

Figure 2. Typical Application Circuit

ABSOLUTE MAXIMUM RATINGS

Rating Symbol VMAX VMIN Unit

Controller Power Supply Voltages to GND VCC, VCCP 15 −0.3 V

Boost Supply Voltage Input BOOT 35V wrt/GND

40 V <100 ns

wrt/GND

15 wrt/LX

−0.3 V

High−Side Driver Output

(Top Gate)

UG 35 V

40 V ≤ 50 ns

wrt/GND

15 wrt/LX

−0.3 wrt/LX

−5 V < 200 ns

Switching Node

(Bootstrap Supply Return)

LX 35

40 < 100 ns

−5

−10 V < 200 ns

Low−Side Driver Output

(Bottom Gate)

LG 15 V −0.3

−5 V < 200 ns

Logic Inputs VLOGIC 6−0.3 V

All Other Pins 6−0.3 V

PGOOD PGOOD 7.0 −0.3 V

SYNC SYNC 7.0 −0.3 V

Current Sense Amplifier CSP,

CSN/VO

with

VCC = 12 V

10 −0.3 V

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect

device reliability.

*All signals referenced to GND unless noted otherwise.

NCP81031

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THERMAL INFORMATION

Rating Symbol Typ Unit

Thermal Resistance, Junction−to−Ambient RqJA 60 °C/W

Thermal Resistance, Junction−to−Case RqJC 18 °C/W

Operating Junction Temperature Range TJ−40 to 125 °C

Operating Ambient Temperature Range TA0 to 85 °C

Maximum Storage Temperature Range TSTG −55 to +150 °C

Moisture Sensitivity Level QFN Package MSL 1 −

ELECTRICAL CHARACTERISTICS Unless otherwise stated: 0°C < TA < 85°C; 4.5 V < VCC < 13.2 V; CVCC = 0.1 mF

Parameter Test Conditions Min Typ Max Unit

SUPPLY OPERATING CONDITIONS

VCC Voltage Range 4.5 13.2 V

VCCP Voltage Range 4.5 13.2 V

dV/dt on VCC (Note 1) −10 10 V/ms

dV/dt on VCCP (Note 1) −10 10 V/ms

VCC AND BOOT INPUT SUPPLY CURRENT

VCC Operating Current VCC = 5 V, EN = High

VCC = 12 V, EN = High

5.0 mA

VCC Quiescent Supply Current (low power mode) VCC = 5 V, EN = Low

VCC = 12 V, EN = Low

200 uA

VCCP INPUT SUPPLY CURRENT

VCCP Operating Current

UG and LG Open

VCCP = 5 V, EN = High

VCCP = 12 V, EN = High 3.5 5.0

VCCP Operating Current VCCP = 5 V, EN = Low

VCCP = 12 V, EN = Low

200 mA

VCC SUPPLY VOLTAGE

VCC UVLO Start Threshold VCC Rising 4.45 V

VCC UVLO Hysteresis VCC Rising or Falling 300 mV

VCCP SUPPLY VOLTAGE

VCCP UVLO Start Threshold 4.1 V

VCCP UVLO Hysteresis 200 mV

ERROR AMPLIFIER COMP

Open Loop DC Gain (Note 1) 120 dB

Open Loop Unity Gain Bandwidth (Note 1) 15 18 MHz

Slew Rate (Note 1) COMP pin to GND with 100 pF

load

8V/ms

VREF

Internal Reference Voltage 0.800 V

Output Voltage Accuracy Reference and Error Amplifier

excluding external resistive

divider tolerance, Vout to FBG

−0.5 0.5 %

CURRENT SENSE AMPLIFIERS

Common Mode Input Voltage Range(Note 1, GNG,

output within 10mV)

VCC ≤ 7.5 V −0.3 −3.5 V

1. Guaranteed by design.

2. For propagation delays, ”tpdh” refers to the specified signal going high ”tpdl” refers to it going low. Reference Gate Timing Diagram.

NCP81031

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ELECTRICAL CHARACTERISTICS Unless otherwise stated: 0°C < TA < 85°C; 4.5 V < VCC < 13.2 V; CVCC = 0.1 mF

Parameter UnitMaxTypMinTest Conditions

CURRENT SENSE AMPLIFIERS

Common Mode Input Voltage Range (Note 1, GNG,

output within 10 mV)

VCC > 7.5 V −0.3 −5.5 V

OSCILLATOR (with no ROSC Resistor Defaults to 200 kHz)

Switching Frequency Accuracy ROSC open −10 −10 %

OSC Gain (Note 1) 10 −kHz /

Disable threshold ROSC/EN pin, Vdis_th − − 0.75 V

MODULATORS (PWM Comparators)

Minimum Pulse Width Fsw = 200 kHz, OSC open 80 ns

Minimum Turn Off Time (LG on) Fsw = 200 kHz, OSC open 250 300 400 ns

Magnitude of the PWM Ramp VIN = 5 V or 12 V 1.50 V

Maximum Duty Cycle OSC/EN = OPEN 80 −95 %

Minimum Skip mode frequency In light load, maximum time for

LG to turn on after HG turns off

30 − − kHz

SOFT−START

Soft Start Time @ 200 kHz 1024 clock cycles, OSC/EN open 5.12 ms

SOFT−OFF

Soft OFF bleeding resistor Rdis 200 W

OVER CURRENT PROTECTION

First Over Current Threshold CSP−CSN, 4xMasking 17 20 23 mV

Second Over Current Threshold CSP−CSN, Immediate action 30 mV

SYNC PIN

Synchronization Input VIL, square wave 1.0 V

Synchronization Input VIH, square wave 2.5 V

PROTECTION AND PGOOD

Output Voltage Logic Low, Sinking 4 mA 0.4 V

OVP Threshold VSEN rising above 1.25 * Vref 120 125 130 %

UVP Threshold VSEN falling below 0.75 * Vref 70 75 80 %

Unlatched Overvoltage Threshold Vth_disoff with respect to 0.5 Vref 40 50 60 %

ZERO CURRENT DETECTION (LX Pin)

Blanking Time before Zero Current Detection (Note 1) Blanking Time after LG is < 1.0 V 40 ns

Capture Time for LX Voltage (Note 1) Time to capture LX voltage once

LG is < 1.0 V (must be within

dead time limits)

20 ns

Negative LX detection voltage Vbdls 200 300 400 mV

Positive LX detection voltage Vbdhs 0.2 0.5 1 V

Time for Vth adjustment and settling time (Note 1) 300 kHz 3−3.7 ms

Initial Negative Current Detection Threshold Voltage Set

Point (Note 1)

LX−GND, Includes ± 2 mV Offset

Range

−6.0 −4.0 −2.0 mV

Vth adjustable Range (Note 1) −16 0 15 mV

1. Guaranteed by design.

2. For propagation delays, ”tpdh” refers to the specified signal going high ”tpdl” refers to it going low. Reference Gate Timing Diagram.

NCP81031

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ELECTRICAL CHARACTERISTICS Unless otherwise stated: 0°C < TA < 85°C; 4.5 V < VCC < 13.2 V; CVCC = 0.1 mF

Parameter UnitMaxTypMinTest Conditions

HIGH SIDE DRIVER UG

RH_TG Output Resistance, Sourcing VBOOT − VLX = 12 V,

Cload = 3 nF

2.5 5 W

RH_TG Output Resistance, Sinking VBOOT − VLX = 12V 2 2.5 W

TrDRVH Transition Time CLOAD = 3 nF −16 −ns

TfDRVH Transition Time CLOAD = 3 nF −11 −

TpdhDRVH Propagation Delay (Notes 1, 2) Driving High, CLOAD = 3 nF,

VCC = 12 V, VCCP =12 V

10 20 30 ns

UG Internal Resistor to LX Unbiased, BOOT − LX = 0 45 kW

LOW SIDE DRIVER LG

RH_BG Output Resistance, Sourcing VLX = GND, Cload = 3 nF 2 3 W

RL_BG Output Resistance, Sinking VLX = VCC 1 1.5 W

TrDRVL Transition Time CLOAD = 3 nF −16 −ns

TfDRVL Transition Time CLOAD = 3 nF −11 −

TpdhDRVL Propagation Delay (Notes 1, 2) Driving High, CLOAD = 3 nF,

VCCP = 12 V, VCCP = 12 V

TBD 18 TBD ns

LX Internal Resistor to GND 45 kW

THERMAL SHUTDOWN

Tsd Thermal Shutdown (Note 1) 150 180 −°C

Tsdhys Thermal Shutdown Hysteresis (Note 1) 50 °C

1. Guaranteed by design.

2. For propagation delays, ”tpdh” refers to the specified signal going high ”tpdl” refers to it going low. Reference Gate Timing Diagram.

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Figure 3. Gate Timing Diagram

Switching Frequency

Connecting a resistor from ROSC/EN to external voltage

source Vpu will configure the frequency. Normal range

would be 100 kHz to 1 MHz. With no resistor connected to

the pin, the oscillator frequency is 200 kHz. The switching

frequency will follow the relationship:

FSW +200 kHz *

Vpu *1.240

ROSC

@10 kHz

mA(eq. 1)

When Rosc = infinity (no resistor connected), Fsw =

200 kHz; when Vpu = ground, the frequency programmed

will be higher than 200 kHz.

Soft−Start

Soft−Start will begin if VCC, VCCP are both above their

UVLO threshold and EN pin is set free. IC initially waits a

fixed delay time and then ramping−up the reference in 1024

clock cycles in closed−loop regulation. After digital soft

start, PGOOD signal will be released with three clock cycles

delay.

Protection active during soft−start:

•Overvoltage Protection always enabled;

•Undervoltage Protection is enabled after reference

voltage ramps up to 80% of the final value. In

soft−start, a UVP fault will directly restart a complete

soft−start.

Synchronization Function

Synchronize through the SYNCH pin. Synchronization

function allows different converters to share the same input

filter reducing the resulting Irms and reducing the need for

total caps to sustain the load. Synchronized systems also

exhibits higher noise immunity and better regulation.

The device synchronizes the high−side MOSFET turn−on

with the falling edge of the SYNCH pin input signal. In order

for internal switching to track the external signal, the

external signal has to fall within 0−40% frequency window

above the internal frequency set by the OSC pin. SYNCH

pin can be connected to other regulators’ PWM, phase node,

gate signals according to the desired phase−shift with proper

voltage scaling.

Protection Scheme

•PGOOD

•Overvoltage Protection (OV)

•Undervoltage Protection (UV)

•PreOVP Protection, monitor CSN/VO when IC is

disabled.

•Vin detection: If UV is triggered during SS, it will

restart SS after a fixed delay.

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Vin

VCC

OSC/EN

Vout.

LG (Stays Low

until first PWM

pulse except in

case of a Fault)

SoftStart Normal

UV monitor

OCP/

Normal

shutdown

Vth_disoff

(50%Vref)

UVLO_VCCPOR_VCC

Vref = 0.8 V

OVP

(125%Vref)

Softstop

~5ms@200kHzz

80% Vrer

1024cycle

0.75V

1.24V

Pre-OVP valid

Figure 4. Start Up and Shutdown Timing Diagram

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VCC> POR &

VCCDR> UVLO_ VCCDR

BOOT >UVLO_BOOT

Soft Start ,

Normal Operation

OCP, OVP, UVP detection

OVP OCP

TG OFF, BG ON

PGOOD=0

TG OFF, BG

OFF

Vout< Vth_disoff

Vo discharge

mode

Yes

Vcc<UVLO_Vcc, Or

EN<Vdis_th Or

Boot<UVLO_Boot

PWR

Fosc detection

OVP

Yes

4 times

reentry

UVP

UV (after Vout reaches UV

threshold in softstart )

TG OFF, BG

OFF

PGOOD=0

After 4 times reentry for

1st threshod

or immediately over 2nd

threshold

PreOVP detection

VCC> POR &

VCCDR > UVLO _VCCDR (16−

pin)

Yes

BG on

VSEN >OV Vth

EN>Vdis_th

Figure 5. State Diagram

During Soft−start, UV is active once Vout reaches the UVP

threshold and OVP is always active. In normal operating

conditions, a UVP Fault will latch off the UG and LG.

Requires a VCC or EN cycle to recover.

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ORDERING INFORMATION

Device Package Tape & Reel Size†

NCP81031MNTWG QFN16

(Pb−Free)

3000 / Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

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PACKAGE DIMENSIONS

QFN16 3x3, 0.5P

CASE 485G−01

ISSUE E

ÇÇÇ

16X

SEATING

PLANE

0.10 C

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMENSION b APPLIES TO PLATED

TERMINAL AND IS MEASURED BETWEEN

0.25 AND 0.30 MM FROM TERMINAL.

4. COPLANARITY APPLIES TO THE EXPOSED

PAD AS WELL AS THE TERMINALS.

0.10 C TOP VIEW

SIDE VIEW

BOTTOM VIEW

PIN 1

LOCATION

0.05 C

(A3)

NOTE 4

16X

0.10 C

0.05 C

A B

NOTE 3

16X

DIM MIN MAX

MILLIMETERS

A0.80 1.00

A1 0.00 0.05

A3 0.20 REF

b0.18 0.30

D3.00 BSC

D2 1.65 1.85

E3.00 BSC

E2 1.65 1.85

e0.50 BSC

L0.30 0.50

0.18 TYP

DETAIL A

ALTERNATE TERMINAL

CONSTRUCTIONS

ÉÉ

ÇÇ

ÉÉ

DETAIL B

MOLD CMPDEXPOSED Cu

ALTERNATE

CONSTRUCTIONS

DETAIL A

DETAIL B

L1 0.00 0.15

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

RECOMMENDED

0.50

PITCH

1.84 3.30

DIMENSIONS: MILLIMETERS

0.58

16X

0.30

16X

OUTLINE

PACKAGE

0.10 C A B

e/2

SOLDERING FOOTPRINT*

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to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights

nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications

intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should

Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,

and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death

associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal

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PUBLICATION ORDERING INFORMATION

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USA/Canada

Europe, Middle East and Africa Technical Support:

Phone: 421 33 790 2910

Japan Customer Focus Center

Phone: 81−3−5773−3850

NCP81031/D

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NCP81031MNTWG