Blackfin(R) Embedded Processor ADSP-BF536/ADSP-BF537 Preliminary Technical Data FEATURES Up to 600 MHz High-Performance Blackfin Processor Two 16-Bit MACs, Two 40-Bit ALUs, Four 8-Bit Video ALUs, 40-Bit Shifter RISC-Like Register and Instruction Model for Ease of Programming and Compiler-Friendly Support Advanced Debug, Trace, and Performance-Monitoring 0.8 V to 1.2 V Core VDD with On-chip Voltage Regulation 2.5 V and 3.3 V-Tolerant I/O with Specific 5 V-Tolerant Pins 182-Ball MBGA and 208-Ball Sparse MBGA Packages Lead Bearing and Lead Free Package Choices MEMORY Up to 132K Bytes of On-Chip Memory: 16K Bytes of Instruction SRAM/Cache 48K Bytes of Instruction SRAM 32K Bytes of Data SRAM/Cache 32K Bytes of Data SRAM 4K Bytes of Scratchpad SRAM External Memory Controller with Glueless Support for SDRAM and Asynchronous 8/16-Bit Memories Flexible Booting Options from External Flash, SPI and TWI Memory or from SPI, TWI, and UART Host Devices JTAG TEST AND EMULATION Two Dual-Channel Memory DMA Controllers Memory Management Unit Providing Memory Protection PERIPHERALS IEEE 802.3-Compliant 10/100 Ethernet MAC Controller Area Network (CAN) 2.0B Interface Parallel Peripheral Interface (PPI), Supporting ITU-R 656 Video Data Formats Two Dual-Channel, Full-Duplex Synchronous Serial Ports (SPORTs), Supporting Eight Stereo I2S Channels 12 Peripheral DMAs, 2 Mastered by the Ethernet MAC Two Memory-to-Memory DMAs With External Request Lines Event Handler With 32 Interrupt Inputs Serial Peripheral Interface (SPI)-Compatible Two UARTs with IrDA(R) Support Two-Wire Interface (TWI) Controller Eight 32-Bit Timer/Counters with PWM Support Real-Time Clock (RTC) and Watchdog Timer 32-Bit Core Timer 48 General-Purpose I/Os (GPIOs), 8 with High Current Drivers On-Chip PLL Capable of 1x to 63x Frequency Multiplication Debug/JTAG Interface EVENT CONTROLLER/ CORE TIMER WATCHDOG TIMER RTC VOLTAGE REGULATOR B ETHERNET MAC CAN TWI L1 INSTRUCTION MEMORY MMU GPIO PORT H L1 DATA MEMORY PORT J SPORT0 SPORT1 CORE / SYSTEM BUS INTERFACE PPI GPIO PORT G UART 0-1 DMA CONTROLLER SPI GPIO PORT F TIMERS 0-7 BOOT ROM EXTERNAL PORT FLASH, SDRAM CONTROL Figure 1. Functional Block Diagram Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc. Rev. PrD Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106 U.S.A. Tel:781/329-4700 www.analog.com Fax:781/326-8703 (c) 2005 Analog Devices, Inc. All rights reserved. ADSP-BF536/ADSP-BF537 Preliminary Technical Data TABLE OF CONTENTS General Description ................................................. 3 Portable Low-Power Architecture ............................. 3 Designing an Emulator-Compatible Processor Board (Target) ................................................. 17 System Integration ................................................ 3 Related Documents .............................................. 17 ADSP-BF536/BF537 Processor Peripherals ................. 3 Pin Descriptions .................................................... 18 Blackfin Processor Core .......................................... 4 Specifications ........................................................ 22 Memory Architecture ............................................ 4 Recommended Operating Conditions ...................... 22 Internal (On-chip) Memory ................................. 5 Absolute Maximum Ratings ................................... 24 External (Off-Chip) Memory ................................ 5 ESD Sensitivity ................................................... 24 I/O Memory Space ............................................. 5 Timing Specifications ........................................... 25 Booting ........................................................... 6 Asynchronous Memory Read Cycle Timing ............ 27 Event Handling ................................................. 6 Asynchronous Memory Write Cycle Timing ........... 28 Core Event Controller (CEC) ................................ 7 SDRAM Interface Timing .................................. 29 System Interrupt Controller (SIC) .......................... 7 External Port Bus Request and Grant Cycle Timing .. 30 Event Control ................................................... 7 External DMA Request Timing ............................ 31 DMA Controllers .................................................. 8 Parallel Peripheral Interface Timing ...................... 32 Real-Time Clock ................................................... 9 Serial Ports ..................................................... 33 Watchdog Timer .................................................. 9 Serial Peripheral Interface (SPI) Port--Master Timing ....................................................... 38 Timers ............................................................... 9 Serial Peripheral Interface (SPI) Port--Slave Timing . 39 Serial Ports (SPORTs) .......................................... 10 Serial Peripheral Interface (SPI) Port ....................... 10 Universal Asynchronous Receiver-Transmitter (UART) Ports--Receive and Transmit Timing ..... 40 UART Ports (UARTs) .......................................... 11 General-Purpose Port Timing ............................. 41 Controller Area Network (CAN) ............................ 11 Timer Cycle Timing .......................................... 42 TWI Controller Interface ...................................... 11 JTAG Test And Emulation Port Timing ................. 43 10/100 Ethernet MAC .......................................... 11 TWI Controller Timing ..................................... 44 Ports ................................................................ 12 10/100 Ethernet MAC Controller Timing ............... 48 General-Purpose I/O (GPIO) .............................. 12 Output Drive Currents ......................................... 51 Parallel Peripheral Interface (PPI) ........................... 13 Power Dissipation ............................................... 54 Dynamic Power Management ................................ 13 Test Conditions .................................................. 54 Full-On Operating Mode - Maximum Performance . 13 Output Enable Time ......................................... 54 Active Operating Mode - Moderate Power Savings .. 13 Output Disable Time ......................................... 54 Sleep Operating Mode - High Dynamic Power Savings ....................................................... 13 Example System Hold Time Calculation ................ 55 Deep Sleep Operating Mode - Maximum Dynamic Power Savings .............................................. 13 Environmental Conditions .................................... 55 182-Ball Mini-BGA Pinout ....................................... 56 208-Ball Sparse Mini-BGA Pinout .............................. 59 Hibernate Operating Mode - Maximum Static Power Savings ....................................................... 14 Outline Dimensions ................................................ 62 Power Savings ................................................. 14 Ordering Guide ..................................................... 64 Voltage Regulation .............................................. 14 Clock Signals ..................................................... 14 Booting Modes ................................................... 16 Instruction Set Description ................................... 16 Development Tools ............................................. 17 Rev. PrD | Page 2 of 64 | January 2005 Preliminary Technical Data ADSP-BF536/ADSP-BF537 REVISION HISTORY Revision PrD: Corrections to PrC because of changes to Ordering Guide, addition of driver type to Table 9, other minor corrections. Changes to: Features ................................................................. 1 Clock Signals ......................................................... 14 Figure 6 ................................................................ 15 Figure 7 ................................................................ 15 Booting Modes ....................................................... 16 Table 9 ................................................................. 18 Figure 10 .............................................................. 26 Table 16 ............................................................... 26 Table 46 ................................................................48 Output Drive Currents ............................................ 51 Table 50 ............................................................... 56 Table 51 ............................................................... 57 208-Ball Sparse Mini-BA Pinout ................................ 59 Table 52 ............................................................... 59 Table 53 ............................................................... 60 Figure 54 title ........................................................ 63 Ordering Guide ..................................................... 64 GENERAL DESCRIPTION The ADSP-BF536/BF537 processors are members of the Blackfin family of products, incorporating the Analog Devices/Intel Micro Signal Architecture (MSA). Blackfin processors combine a dual-MAC state-of-the-art signal processing engine, the advantages of a clean, orthogonal RISC-like microprocessor instruction set, and single-instruction, multiple-data (SIMD) multimedia capabilities into a single instruction-set architecture. The ADSP-BF536/BF537 processors are completely code and pin compatible, differing only with respect to their performance and on-chip memory. Specific performance and memory configurations are shown in Table 1. Table 1. Processor Comparison Maximum performance Instruction SRAM/Cache Instruction SRAM Data SRAM/Cache Data SRAM Scratchpad ADSP-BF536 400 MHz 16K bytes 48K bytes 16K bytes 16K bytes 4K bytes ADSP-BF537 600 MHz 16K bytes 48K bytes 32K bytes 32K bytes 4K bytes By integrating a rich set of industry-leading system peripherals and memory, Blackfin processors are the platform of choice for next-generation applications that require RISC-like programmability, multimedia support and leading-edge signal processing in one integrated package. PORTABLE LOW-POWER ARCHITECTURE Blackfin processors provide world-class power management and performance. Blackfin processors are designed in a low power and low voltage design methodology and feature on-chip Dynamic Power Management, the ability to vary both the voltage and frequency of operation to significantly lower overall power consumption. Varying the voltage and frequency can result in a substantial reduction in power consumption, compared with just varying the frequency of operation. This translates into longer battery life for portable appliances. SYSTEM INTEGRATION The ADSP-BF536/BF537 processors are highly integrated system-on-a-chip solutions for the next generation of embedded network connected applications. By combining industry-stanRev. PrD | dard interfaces with a high performance signal processing core, users can develop cost-effective solutions quickly without the need for costly external components. The system peripherals include an IEEE-compliant 802.3 10/100 Ethernet MAC, a CAN 2.0B controller, a TWI controller, two UART ports, an SPI port, two serial ports (SPORTs), nine general purpose 32-bit timers (eight with PWM capability), a real-time clock, a watchdog timer, and a Parallel Peripheral Interface. ADSP-BF536/BF537 PROCESSOR PERIPHERALS The ADSP-BF536/BF537 processor contains a rich set of peripherals connected to the core via several high bandwidth buses, providing flexibility in system configuration as well as excellent overall system performance (see the block diagram on page 1). The general-purpose peripherals include functions such as UARTs, SPI, TWI, Timers with PWM (Pulse Width Modulation) and pulse measurement capability, general purpose I/O pins, a Real-Time Clock, and a Watchdog Timer. This set of functions satisfies a wide variety of typical system support needs and is augmented by the system expansion capabilities of the part. The ADSP-BF536/BF537 processor contains dedicated Page 3 of 64 | January 2005 ADSP-BF536/ADSP-BF537 Preliminary Technical Data network communication modules and high-speed serial and parallel ports, an interrupt controller for flexible management of interrupts from the on-chip peripherals or external sources, and power management control functions to tailor the performance and power characteristics of the processor and system to many application scenarios. All of the peripherals, except for general-purpose I/O, CAN, TWI, Real-Time Clock, and timers, are supported by a flexible DMA structure. There are also separate memory DMA channels dedicated to data transfers between the processor's various memory spaces, including external SDRAM and asynchronous memory. Multiple on-chip buses running at up to 133 MHz provide enough bandwidth to keep the processor core running along with activity on all of the on-chip and external peripherals. The ADSP-BF536/BF537 processor includes an on-chip voltage regulator in support of the ADSP-BF536/BF537 processor Dynamic Power Management capability. The voltage regulator provides a range of core voltage levels when supplied from a single 2.25 V to 3.6 V input. The voltage regulator can be bypassed at the user's discretion. BLACKFIN PROCESSOR CORE As shown in Figure 2 on page 5, the Blackfin processor core contains two 16-bit multipliers, two 40-bit accumulators, two 40-bit ALUs, four video ALUs, and a 40-bit shifter. The computation units process 8-bit, 16-bit, or 32-bit data from the register file. The compute register file contains eight 32-bit registers. When performing compute operations on 16-bit operand data, the register file operates as 16 independent 16-bit registers. All operands for compute operations come from the multiported register file and instruction constant fields. Each MAC can perform a 16-bit by 16-bit multiply in each cycle, accumulating the results into the 40-bit accumulators. Signed and unsigned formats, rounding, and saturation are supported. The ALUs perform a traditional set of arithmetic and logical operations on 16-bit or 32-bit data. In addition, many special instructions are included to accelerate various signal processing tasks. These include bit operations such as field extract and population count, modulo 232 multiply, divide primitives, saturation and rounding, and sign/exponent detection. The set of video instructions include byte alignment and packing operations, 16bit and 8-bit adds with clipping, 8-bit average operations, and 8bit subtract/absolute value/accumulate (SAA) operations. Also provided are the compare/select and vector search instructions. For certain instructions, two 16-bit ALU operations can be performed simultaneously on register pairs (a 16-bit high half and 16-bit low half of a compute register). By also using the second ALU, quad 16-bit operations are possible. The 40-bit shifter can perform shifts and rotates and is used to support normalization, field extract, and field deposit instructions. Rev. PrD | The program sequencer controls the flow of instruction execution, including instruction alignment and decoding. For program flow control, the sequencer supports PC relative and indirect conditional jumps (with static branch prediction), and subroutine calls. Hardware is provided to support zero-overhead looping. The architecture is fully interlocked, meaning that the programmer need not manage the pipeline when executing instructions with data dependencies. The address arithmetic unit provides two addresses for simultaneous dual fetches from memory. It contains a multiported register file consisting of four sets of 32-bit Index, Modify, Length, and Base registers (for circular buffering), and eight additional 32-bit pointer registers (for C-style indexed stack manipulation). Blackfin processors support a modified Harvard architecture in combination with a hierarchical memory structure. Level 1 (L1) memories are those that typically operate at the full processor speed with little or no latency. At the L1 level, the instruction memory holds instructions only. The two data memories hold data, and a dedicated scratchpad data memory stores stack and local variable information. In addition, multiple L1 memory blocks are provided, offering a configurable mix of SRAM and cache. The Memory Management Unit (MMU) provides memory protection for individual tasks that may be operating on the core and can protect system registers from unintended access. The architecture provides three modes of operation: User mode, Supervisor mode, and Emulation mode. User mode has restricted access to certain system resources, thus providing a protected software environment, while Supervisor mode has unrestricted access to the system and core resources. The Blackfin processor instruction set has been optimized so that 16-bit opcodes represent the most frequently used instructions, resulting in excellent compiled code density. Complex DSP instructions are encoded into 32-bit opcodes, representing fully featured multifunction instructions. Blackfin processors support a limited multi-issue capability, where a 32-bit instruction can be issued in parallel with two 16-bit instructions, allowing the programmer to use many of the core resources in a single instruction cycle. The Blackfin processor assembly language uses an algebraic syntax for ease of coding and readability. The architecture has been optimized for use in conjunction with the C/C++ compiler, resulting in fast and efficient software implementations. MEMORY ARCHITECTURE The ADSP-BF536/BF537 processor views memory as a single unified 4G byte address space, using 32-bit addresses. All resources, including internal memory, external memory, and I/O control registers, occupy separate sections of this common address space. The memory portions of this address space are arranged in a hierarchical structure to provide a good cost/performance balance of some very fast, low-latency on-chip memory as cache or SRAM, and larger, lower-cost and performance off-chip memory systems. See Figure 3 on page 6, and Figure 4 on page 6. Page 4 of 64 | January 2005 Preliminary Technical Data ADSP-BF536/ADSP-BF537 ADDRESS ARITHMETIC UNIT SP FP P5 P4 P3 P2 I3 I2 L3 L2 B3 B2 M3 M2 I1 L1 B1 M1 I0 L0 B0 M0 DAG0 DAG1 SEQUENCER P1 P0 ALIGN DECODE LD0 32 BITS LD1 32 BITS SD 32 BITS R7 R6 R7.H R6.H R7.L R6.L R5 R4 R5.H R4.H R5.L R4.L R3 R3.H R3.L R2 R1 R2.H R1.H R2.L R1.L R0 R0.H R0.L LOOP BUF FER 16 16 8 8 BARREL SHIFTER 8 40 8 CONTROL UNIT 40 A0 A1 DATA ARITHMETIC UNI T Figure 2. Blackfin Processor Core The on-chip L1 memory system is the highest-performance memory available to the Blackfin processor. The off-chip memory system, accessed through the External Bus Interface Unit (EBIU), provides expansion with SDRAM, flash memory, and SRAM, optionally accessing up to 516M bytes of physical memory. The memory DMA controller provides high-bandwidth datamovement capability. It can perform block transfers of code or data between the internal memory and the external memory spaces. Internal (On-chip) Memory The ADSP-BF536/BF537 processor has three blocks of on-chip memory providing high-bandwidth access to the core. The first block is the L1 instruction memory, consisting of 64K bytes SRAM, of which 16K bytes can be configured as a four-way set-associative cache. This memory is accessed at full processor speed. The second on-chip memory block is the L1 data memory, consisting of up to two banks of up to 32K bytes each. Each memory bank is configurable, offering both Cache and SRAM functionality. This memory block is accessed at full processor speed. The third memory block is a 4K byte scratchpad SRAM which runs at the same speed as the L1 memories, but is only accessible as data SRAM and cannot be configured as cache memory. Rev. PrD | External (Off-Chip) Memory External memory is accessed via the EBIU. This 16-bit interface provides a glueless connection to a bank of synchronous DRAM (SDRAM) as well as up to four banks of asynchronous memory devices including flash, EPROM, ROM, SRAM, and memory mapped I/O devices. The PC133-compliant SDRAM controller can be programmed to interface to up to 512M bytes of SDRAM. A separate row can be open for each SDRAM internal bank and the SDRAM controller supports up to 4 internal SDRAM banks, improving overall performance. The asynchronous memory controller can be programmed to control up to four banks of devices with very flexible timing parameters for a wide variety of devices. Each bank occupies a 1M byte segment regardless of the size of the devices used, so that these banks will only be contiguous if each is fully populated with 1M byte of memory. I/O Memory Space The ADSP-BF536/BF537 processors do not define a separate I/O space. All resources are mapped through the flat 32-bit address space. On-chip I/O devices have their control registers mapped into memory-mapped registers (MMRs) at addresses near the top of the 4G byte address space. These are separated into two smaller blocks, one which contains the control MMRs for all core functions, and the other which contains the registers Page 5 of 64 | January 2005 ADSP-BF536/ADSP-BF537 Preliminary Technical Data 0xFFFF FFFF 0xFFFF FFFF CORE MMR REGISTERS (2M BYTE) CORE MMR REGISTERS (2M BYTE) 0xFFE0 0000 0xFFE0 0000 SYSTEM MMR REGISTERS (2M BYTE) SYSTEM MMR REGISTERS (2M BYTE) 0xFFC0 0000 0xFFC0 0000 RESERVED RESERVED 0xFFB0 1000 0xFFB0 1000 0xFFA1 4000 INSTRUCTION SRAM / CACHE (16K BYTE) 0xFFA1 0000 RESERVED 0xFFA0 C000 INSTRUCTION BANK B SRAM (16K BYTE) 0xFFA0 8000 INSTRUCTION BANK A SRAM (32K BYTE) 0xFFA0 0000 SCRATCHPAD SRAM (4K BYTE) 0xFFB0 0000 RESERVED 0xFFA1 4000 INSTRUCTION SRAM / CACHE (16K BYTE) 0xFFA1 0000 RESERVED 0xFFA0 C000 INSTRUCTION BANK B SRAM (16K BYTE) 0xFFA0 8000 INSTRUCTION BANK A SRAM (32K BYTE) 0xFFA0 0000 RESERVED RESERVED 0xFF90 8000 0xFF90 8000 DATA BANK B SRAM / CACHE (16K BYTE) INTERNAL MEMORY MAP RESERVED INTERNAL MEMORY MAP SCRATCHPAD SRAM (4K BYTE) 0xFFB0 0000 DATA BANK B SRAM / CACHE (16K BYTE) 0xFF90 4000 0xFF90 4000 RESERVED DATA BANK B SRAM (16K BYTE) 0xFF90 0000 0xFF90 0000 RESERVED RESERVED 0xFF80 8000 0xFF80 8000 DATA BANK A SRAM / CACHE (16K BYTE) DATA BANK A SRAM / CACHE (16K BYTE) 0xFF80 4000 0xFF80 4000 DATA BANK A SRAM (16K BYTE) RESERVED 0xFF80 0000 0xFF80 0000 RESERVED 0xEF00 0800 EXTERNAL MEMORY MAP BOOT ROM (2K BYTE) 0xEF00 0000 RESERVED 0x2040 0000 ASYNC MEMORY BANK 3 (1M BYTE) 0x2030 0000 ASYNC MEMORY BANK 2 (1M BYTE) 0x2020 0000 ASYNC MEMORY BANK 1 (1M BYTE) 0x2010 0000 ASYNC MEMORY BANK 0 (1M BYTE) BOOT ROM (2K BYTE) 0xEF00 0000 RESERVED 0x2040 0000 ASYNC MEMORY BANK 3 (1M BYTE) 0x2030 0000 ASYNC MEMORY BANK 2 (1M BYTE) 0x2020 0000 ASYNC MEMORY BANK 1 (1M BYTE) 0x2010 0000 ASYNC MEMORY BANK 0 (1M BYTE) 0x2000 0000 EXTERNAL MEMORY MAP RESERVED 0xEF00 0800 0x2000 0000 SDRAM MEMORY (16M BYTE - 512M BYTE) SDRAM MEMORY (16M BYTE - 512M BYTE) 0x0000 0000 0x0000 0000 Figure 3. ADSP-BF536 Internal/External Memory Map Figure 4. ADSP-BF537 Internal/External Memory Map * Non-Maskable Interrupt (NMI) - The NMI event can be generated by the software watchdog timer or by the NMI input signal to the processor. The NMI event is frequently used as a power-down indicator to initiate an orderly shutdown of the system. needed for setup and control of the on-chip peripherals outside of the core. The MMRs are accessible only in supervisor mode and appear as reserved space to on-chip peripherals. Booting The ADSP-BF536/BF537 processor contains a small on-chip boot kernel, which configures the appropriate peripheral for booting. If the ADSP-BF536/BF537 processor is configured to boot from boot ROM memory space, the processor starts executing from the on-chip boot ROM. For more information, see Booting Modes on page 16. * Exceptions - Events that occur synchronously to program flow (i.e., the exception will be taken before the instruction is allowed to complete). Conditions such as data alignment violations and undefined instructions cause exceptions. * Interrupts - Events that occur asynchronously to program flow. They are caused by input pins, timers, and other peripherals, as well as by an explicit software instruction. Event Handling The event controller on the ADSP-BF536/BF537 processor handles all asynchronous and synchronous events to the processor. The ADSP-BF536/BF537 processor provides event handling that supports both nesting and prioritization. Nesting allows multiple event service routines to be active simultaneously. Prioritization ensures that servicing of a higher-priority event takes precedence over servicing of a lower-priority event. The controller provides support for five different types of events: * Emulation - An emulation event causes the processor to enter emulation mode, allowing command and control of the processor via the JTAG interface. Each event type has an associated register to hold the return address and an associated return-from-event instruction. When an event is triggered, the state of the processor is saved on the supervisor stack. The ADSP-BF536/BF537 processor Event Controller consists of two stages, the Core Event Controller (CEC) and the System Interrupt Controller (SIC). The Core Event Controller works with the System Interrupt Controller to prioritize and control all system events. Conceptually, interrupts from the peripherals enter into the SIC, and are then routed directly into the generalpurpose interrupts of the CEC. * Reset - This event resets the processor. Rev. PrD | Page 6 of 64 | January 2005 Preliminary Technical Data ADSP-BF536/ADSP-BF537 Core Event Controller (CEC) Table 3. System Interrupt Controller (SIC) The CEC supports nine general-purpose interrupts (IVG15-7), in addition to the dedicated interrupt and exception events. Of these general-purpose interrupts, the two lowest-priority interrupts (IVG15-14) are recommended to be reserved for software interrupt handlers, leaving seven prioritized interrupt inputs to support the peripherals of the ADSP-BF536/BF537 processor. Table 2 describes the inputs to the CEC, identifies their names in the Event Vector Table (EVT), and lists their priorities. Table 2. Core Event Controller (CEC) Priority (0 is Highest) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Event Class EVT Entry Emulation/Test Control Reset Non-Maskable Interrupt Exception Reserved Hardware Error Core Timer General Interrupt 7 General Interrupt 8 General Interrupt 9 General Interrupt 10 General Interrupt 11 General Interrupt 12 General Interrupt 13 General Interrupt 14 General Interrupt 15 EMU RST NMI EVX -- IVHW IVTMR IVG7 IVG8 IVG9 IVG10 IVG11 IVG12 IVG13 IVG14 IVG15 System Interrupt Controller (SIC) The System Interrupt Controller provides the mapping and routing of events from the many peripheral interrupt sources to the prioritized general-purpose interrupt inputs of the CEC. Although the ADSP-BF536/BF537 processor provides a default mapping, the user can alter the mappings and priorities of interrupt events by writing the appropriate values into the Interrupt Assignment Registers (IAR). Table 3 describes the inputs into the SIC and the default mappings into the CEC. Peripheral Interrupt Event PLL Wakeup DMA Error (generic) DMAR0 Block Interrupt DMAR1 Block Interrupt DMAR0 Overflow Error DMAR1 Overflow Error CAN Error Ethernet Error SPORT 0 Error SPORT 1 Error PPI Error SPI Error UART0 Error UART1 Error Real-Time Clock DMA Channel 0 (PPI) DMA Channel 3 (SPORT 0 RX) DMA Channel 4 (SPORT 0 TX) DMA Channel 5 (SPORT 1 RX) DMA Channel 6 (SPORT 1 TX) TWI DMA Channel 7 (SPI) DMA Channel 8 (UART0 RX) DMA Channel 9 (UART0 TX) DMA Channel 10 (UART1 RX) DMA Channel 11 (UART1 TX) CAN RX CAN TX DMA Channel 1 (Ethernet RX) Port H Interrupt A DMA Channel 2 (Ethernet TX) Event Control The ADSP-BF536/BF537 processor provides the user with a very flexible mechanism to control the processing of events. In the CEC, three registers are used to coordinate and control events. Each register is 16 bits wide: * CEC Interrupt Latch Register (ILAT) - The ILAT register indicates when events have been latched. The appropriate bit is set when the processor has latched the event and cleared when the event has been accepted into the system. Rev. PrD | Page 7 of 64 | January 2005 Default Mapping IVG7 IVG7 IVG7 IVG7 IVG7 IVG7 IVG7 IVG7 IVG7 IVG7 IVG7 IVG7 IVG7 IVG7 IVG8 IVG8 IVG9 IVG9 IVG9 IVG9 IVG10 IVG10 IVG10 IVG10 IVG10 IVG10 IVG11 IVG11 IVG11 IVG11 IVG11 Peripheral Interrupt ID 0 1 1 1 1 1 2 2 2 2 2 2 2 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 17 18 ADSP-BF536/ADSP-BF537 Preliminary Technical Data source triggered the interrupt. A set bit indicates the peripheral is asserting the interrupt, and a cleared bit indicates the peripheral is not asserting the event. Table 3. System Interrupt Controller (SIC) (Continued) Peripheral Interrupt Event Port H Interrupt B Timer 0 Timer 1 Timer 2 Timer 3 Timer 4 Timer 5 Timer 6 Timer 7 Port F, G Interrupt A Port G Interrupt B DMA Channels 12 and 13 (Memory DMA Stream 0) DMA Channels 14 and 15 (Memory DMA Stream 1) Software Watchdog Timer Port F Interrupt B Default Mapping IVG11 IVG12 IVG12 IVG12 IVG12 IVG12 IVG12 IVG12 IVG12 IVG12 IVG12 IVG13 Peripheral Interrupt ID 18 19 20 21 22 23 24 25 26 27 28 29 IVG13 30 IVG13 IVG13 31 31 This register is updated automatically by the controller, but it may be written only when its corresponding IMASK bit is cleared. * CEC Interrupt Mask Register (IMASK) - The IMASK register controls the masking and unmasking of individual events. When a bit is set in the IMASK register, that event is unmasked and will be processed by the CEC when asserted. A cleared bit in the IMASK register masks the event, preventing the processor from servicing the event even though the event may be latched in the ILAT register. This register may be read or written while in supervisor mode. (Note that general-purpose interrupts can be globally enabled and disabled with the STI and CLI instructions, respectively.) * CEC Interrupt Pending Register (IPEND) - The IPEND register keeps track of all nested events. A set bit in the IPEND register indicates the event is currently active or nested at some level. This register is updated automatically by the controller but may be read while in supervisor mode. The SIC allows further control of event processing by providing three 32-bit interrupt control and status registers. Each register contains a bit corresponding to each of the peripheral interrupt events shown in Table 3 on page 7. * SIC Interrupt Mask Register (SIC_IMASK)- This register controls the masking and unmasking of each peripheral interrupt event. When a bit is set in the register, that peripheral event is unmasked and will be processed by the system when asserted. A cleared bit in the register masks the peripheral event, preventing the processor from servicing the event. * SIC Interrupt Wakeup Enable Register (SIC_IWR) - By enabling the corresponding bit in this register, a peripheral can be configured to wake up the processor, should the core be idled when the event is generated. (For more information, see Dynamic Power Management on page 13.) Because multiple interrupt sources can map to a single generalpurpose interrupt, multiple pulse assertions can occur simultaneously, before or during interrupt processing for an interrupt event already detected on this interrupt input. The IPEND register contents are monitored by the SIC as the interrupt acknowledgement. The appropriate ILAT register bit is set when an interrupt rising edge is detected (detection requires two core clock cycles). The bit is cleared when the respective IPEND register bit is set. The IPEND bit indicates that the event has entered into the processor pipeline. At this point the CEC will recognize and queue the next rising edge event on the corresponding event input. The minimum latency from the rising edge transition of the generalpurpose interrupt to the IPEND output asserted is three core clock cycles; however, the latency can be much higher, depending on the activity within and the state of the processor. DMA CONTROLLERS The ADSP-BF536/BF537 processor has multiple, independent DMA controllers that support automated data transfers with minimal overhead for the processor core. DMA transfers can occur between the ADSP-BF536/BF537 processor's internal memories and any of its DMA-capable peripherals. Additionally, DMA transfers can be accomplished between any of the DMA-capable peripherals and external devices connected to the external memory interfaces, including the SDRAM controller and the asynchronous memory controller. DMA-capable peripherals include the Ethernet MAC, SPORTs, SPI port, UARTs, and PPI. Each individual DMA-capable peripheral has at least one dedicated DMA channel. The ADSP-BF536/BF537 processor DMA controller supports both 1-dimensional (1D) and 2-dimensional (2D) DMA transfers. DMA transfer initialization can be implemented from registers or from sets of parameters called descriptor blocks. The 2D DMA capability supports arbitrary row and column sizes up to 64K elements by 64K elements, and arbitrary row and column step sizes up to 32K elements. Furthermore, the column step size can be less than the row step size, allowing implementation of interleaved data streams. This feature is especially useful in video applications where data can be deinterleaved on the fly. Examples of DMA types supported by the ADSP-BF536/BF537 processor DMA controller include: * SIC Interrupt Status Register (SIC_ISR) - As multiple peripherals can be mapped to a single event, this register allows the software to determine which peripheral event Rev. PrD | Page 8 of 64 | * A single, linear buffer that stops upon completion * A circular, auto-refreshing buffer that interrupts on each full or fractionally full buffer January 2005 Preliminary Technical Data ADSP-BF536/ADSP-BF537 * 1-D or 2-D DMA using a linked list of descriptors RTXI * 2-D DMA using an array of descriptors, specifying only the base DMA address within a common page In addition to the dedicated peripheral DMA channels, there are two memory DMA channels provided for transfers between the various memories of the ADSP-BF536/BF537 processor system. This enables transfers of blocks of data between any of the memories--including external SDRAM, ROM, SRAM, and flash memory--with minimal processor intervention. Memory DMA transfers can be controlled by a very flexible descriptorbased methodology or by a standard register-based autobuffer mechanism. The ADSP-BF536/BF537 processors also include an external DMA controller capability via dual external DMA request pins when used in conjunction with the External Bus Interface Unit (EBIU). This functionality can be used when a high speed interface is required for external FIFOs and high bandwidth communications peripherals such as USB 2.0. It allows control of the number of data transfers for memDMA. The number of transfers per edge is programmable. This feature can be programmed to allow memDMA to have an increased priority on the external bus relative to the core. REAL-TIME CLOCK The ADSP-BF536/BF537 processor Real-Time Clock (RTC) provides a robust set of digital watch features, including current time, stopwatch, and alarm. The RTC is clocked by a 32.768 KHz crystal external to the ADSP-BF536/BF537 processor. The RTC peripheral has dedicated power supply pins so that it can remain powered up and clocked even when the rest of the processor is in a low-power state. The RTC provides several programmable interrupt options, including interrupt per second, minute, hour, or day clock ticks, interrupt on programmable stopwatch countdown, or interrupt at a programmed alarm time. The 32.768 KHz input clock frequency is divided down to a 1 Hz signal by a prescaler. The counter function of the timer consists of four counters: a 60-second counter, a 60-minute counter, a 24-hour counter, and an 32,768-day counter. X1 C1 C2 SUGGESTED COMPONENTS: ECLIPTEK EC38J (THROUGH-HOLE PACKAGE) EPSON MC405 12 PF LOAD (SURFACE MOUNT PACKAGE) C1 = 22 PF C2 = 22 PF R1 = 10 M NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1. CONTACT CRYSTAL MANUFACTURER FOR DETAILS. C1 AND C2 SPECIFICATIONS ASSUME BOARD TRACE CAPACITANCE OF 3 PF. Figure 5. External Components for RTC WATCHDOG TIMER The ADSP-BF536/BF537 processor includes a 32-bit timer that can be used to implement a software watchdog function. A software watchdog can improve system availability by forcing the processor to a known state through generation of a hardware reset, non-maskable interrupt (NMI), or general-purpose interrupt, if the timer expires before being reset by software. The programmer initializes the count value of the timer, enables the appropriate interrupt, then enables the timer. Thereafter, the software must reload the counter before it counts to zero from the programmed value. This protects the system from remaining in an unknown state where software, which would normally reset the timer, has stopped running due to an external noise condition or software error. If configured to generate a hardware reset, the watchdog timer resets both the core and the ADSP-BF536/BF537 processor peripherals. After a reset, software can determine if the watchdog was the source of the hardware reset by interrogating a status bit in the watchdog timer control register. The timer is clocked by the system clock (SCLK), at a maximum frequency of fSCLK. When enabled, the alarm function generates an interrupt when the output of the timer matches the programmed value in the alarm control register. There are two alarms: The first alarm is for a time of day. The second alarm is for a day and time of that day. The stopwatch function counts down from a programmed value, with one-second resolution. When the stopwatch is enabled and the counter underflows, an interrupt is generated. Like the other peripherals, the RTC can wake up the ADSPBF536/BF537 processor from Sleep mode upon generation of any RTC wakeup event. Additionally, an RTC wakeup event can wake up the ADSP-BF536/BF537 processor from Deep Sleep mode, and wake up the on-chip internal voltage regulator from the Hibernate operating mode. Connect RTC pins RTXI and RTXO with external components as shown in Figure 5. Rev. PrD | RTXO R1 TIMERS There are nine general-purpose programmable timer units in the ADSP-BF536/BF537 processor. Eight timers have an external pin that can be configured either as a Pulse Width Modulator (PWM) or timer output, as an input to clock the timer, or as a mechanism for measuring pulse widths and periods of external events. These timers can be synchronized to an external clock input to the several other associated PF pins, an external clock input to the PPI_CLK input pin, or to the internal SCLK. The timer units can be used in conjunction with the two UARTs and the CAN controller to measure the width of the pulses in the data stream to provide a software auto-baud detect function for the respective serial channels. Page 9 of 64 | January 2005 ADSP-BF536/ADSP-BF537 Preliminary Technical Data The timers can generate interrupts to the processor core providing periodic events for synchronization, either to the system clock or to a count of external signals. In addition to the eight general-purpose programmable timers, a ninth timer is also provided. This extra timer is clocked by the internal processor clock and is typically used as a system tick clock for generation of operating system periodic interrupts. SERIAL PORTS (SPORTS) The ADSP-BF536/BF537 processor incorporates two dualchannel synchronous serial ports (SPORT0 and SPORT1) for serial and multiprocessor communications. The SPORTs support the following features: * I2S capable operation. * Bidirectional operation - Each SPORT has two sets of independent transmit and receive pins, enabling eight channels of I2S stereo audio. * Buffered (8-deep) transmit and receive ports - Each port has a data register for transferring data words to and from other processor components and shift registers for shifting data in and out of the data registers. * Clocking - Each transmit and receive port can either use an external serial clock or generate its own, in frequencies ranging from (fSCLK/131,070) Hz to (fSCLK/2) Hz. * Word length - Each SPORT supports serial data words from 3 to 32 bits in length, transferred most-significant-bit first or least-significant-bit first. The SPI interface uses three pins for transferring data: two data pins (Master Output-Slave Input, MOSI, and Master InputSlave Output, MISO) and a clock pin (Serial Clock, SCK). An SPI chip select input pin (SPISS) lets other SPI devices select the processor, and seven SPI chip select output pins (SPISEL7-1) let the processor select other SPI devices. The SPI select pins are reconfigured Programmable Flag pins. Using these pins, the SPI port provides a full-duplex, synchronous serial interface, which supports both master/slave modes and multimaster environments. The SPI port's baud rate and clock phase/polarities are programmable, and it has an integrated DMA controller, configurable to support transmit or receive data streams. The SPI's DMA controller can only service unidirectional accesses at any given time. The SPI port's clock rate is calculated as: f SCLK SPI Clock Rate = --------------------------------2 x SPI_Baud Where the 16-bit SPI_Baud register contains a value of 2 to 65,535. During transfers, the SPI port simultaneously transmits and receives by serially shifting data in and out on its two serial data lines. The serial clock line synchronizes the shifting and sampling of data on the two serial data lines. * Framing - Each transmit and receive port can run with or without frame sync signals for each data word. Frame sync signals can be generated internally or externally, active high or low, and with either of two pulsewidths and early or late frame sync. * Companding in hardware - Each SPORT can perform A-law or -law companding according to ITU recommendation G.711. Companding can be selected on the transmit and/or receive channel of the SPORT without additional latencies. * DMA operations with single-cycle overhead - Each SPORT can automatically receive and transmit multiple buffers of memory data. The processor can link or chain sequences of DMA transfers between a SPORT and memory. * Interrupts - Each transmit and receive port generates an interrupt upon completing the transfer of a data word or after transferring an entire data buffer or buffers through DMA. * Multichannel capability - Each SPORT supports 128 channels out of a 1024-channel window and is compatible with the H.100, H.110, MVIP-90, and HMVIP standards. SERIAL PERIPHERAL INTERFACE (SPI) PORT The ADSP-BF536/BF537 processor has an SPI-compatible port that enables the processor to communicate with multiple SPIcompatible devices. Rev. PrD | Page 10 of 64 | January 2005 Preliminary Technical Data ADSP-BF536/ADSP-BF537 UART PORTS (UARTS) The ADSP-BF536/BF537 processor provides two full-duplex Universal Asynchronous Receiver/Transmitter (UART) ports, which are fully compatible with PC-standard UARTs. Each UART port provides a simplified UART interface to other peripherals or hosts, supporting full-duplex, DMA-supported, asynchronous transfers of serial data. A UART port includes support for 5 to 8 data bits, 1 or 2 stop bits, and none, even, or odd parity. Each UART port supports two modes of operation: The ADSP-BF536/BF537 CAN controller offers the following features: * 32 mailboxes (8 receive only, 8 transmit only, 16 configurable for receive or transmit). * Dedicated acceptance masks for each mailbox. * Additional data filtering on first two bytes. * Support for both the standard (11-bit) and extended (29bit) identifier (ID) message formats. * Support for remote frames. * PIO (Programmed I/O) - The processor sends or receives data by writing or reading I/O-mapped UART registers. The data is double-buffered on both transmit and receive. * DMA (Direct Memory Access) - The DMA controller transfers both transmit and receive data. This reduces the number and frequency of interrupts required to transfer data to and from memory. The UART has two dedicated DMA channels, one for transmit and one for receive. These DMA channels have lower default priority than most DMA channels because of their relatively low service rates. Each UART port's baud rate, serial data format, error code generation and status, and interrupts are programmable: * Supporting bit rates ranging from (fSCLK/ 1,048,576) to (fSCLK/16) bits per second. * Supporting data formats from 7 to12 bits per frame. * Both transmit and receive operations can be configured to generate maskable interrupts to the processor. The UART port's clock rate is calculated as: f SCLK UART Clock Rate = ----------------------------------------------16 x UART_Divisor Where the 16-bit UART_Divisor comes from the DLH register (most significant 8 bits) and DLL register (least significant 8 bits). In conjunction with the general-purpose timer functions, autobaud detection is supported. The capabilities of the UARTs are further extended with support for the Infrared Data Association (IrDA(R)) Serial Infrared Physical Layer Link Specification (SIR) protocol. * Active or passive network support. * CAN wakeup from Hibernation Mode (lowest static power consumption mode). * Interrupts, including: TX Complete, RX Complete, Error, Global. The electrical characteristics of each network connection are very demanding so the CAN interface is typically divided into two parts: a controller and a transceiver. This allows a single controller to support different drivers and CAN networks. The ADSP-BF536/BF537 CAN module represents only the controller part of the interface. The controller interface supports connection to 3.3V high-speed, fault-tolerant, single-wire transceivers. TWI CONTROLLER INTERFACE The ADSP-BF536/BF537 processor includes a Two Wire Interface (TWI) module for providing a simple exchange method of control data between multiple devices. The TWI is compatible with the widely used I2C bus standard. The TWI module offers the capabilities of simultaneous Master and Slave operation, support for both 7-bit addressing and multimedia data arbitration. The TWI interface utilizes two pins for transferring clock (SCL) and data (SDA) and supports the protocol at speeds up to 400k bits/sec. The TWI interface pins are compatible with 5 V logic levels. Additionally, the ADSP-BF536/BF537 processor's TWI module is fully compatible with Serial Camera Control Bus (SCCB) functionality for easier control of various CMOS camera sensor devices. 10/100 ETHERNET MAC CONTROLLER AREA NETWORK (CAN) The ADSP-BF536/BF537 processor offers a CAN controller that is a communication controller implementing the Controller Area Network (CAN) 2.0B (active) protocol. This protocol is an asynchronous communications protocol used in both industrial and automotive control systems. The CAN protocol is well suited for control applications due to its capability to communicate reliably over a network since the protocol incorporates CRC checking message error tracking, and fault node confinement. The ADSP-BF536/BF537 processor offers the capability to directly connect to a network by way of an embedded Fast Ethernet Medium Access Controller (MAC) that supports both 10-BaseT (10Mbits/sec) and 100-BaseT (100Mbits/sec) operation. The 10/100 Ethernet MAC peripheral on the ADSPBF536/BF537 is fully compliant to the IEEE 802.3-2002 standard and it provides programmable features designed to minimize supervision, bus utilization, or message processing by the rest of the processor system. Some standard features are: * Support of MII and RMII protocols for external PHYs. * Full Duplex and Half Duplex modes. Rev. PrD | Page 11 of 64 | January 2005 ADSP-BF536/ADSP-BF537 Preliminary Technical Data * Data framing and encapsulation: generation and detection of preamble, length padding, and FCS. * Media access management (in Half-Duplex operation): collision and contention handling, including control of retransmission of collision frames and of back-off timing. * Flow control (in Full-Duplex operation): generation and detection of PAUSE frames. * Station management: generation of MDC/MDIO frames for read-write access to PHY registers. * SCLK operating range down to 25MHz (Active and Sleep operating modes). * Internal loopback from TX to RX. Some advanced features are: * Buffered crystal output to external PHY for support of a single crystal system. * Automatic checksum computation of IP header and IP payload fields of RX frames. * Independent 32-bit descriptor-driven RX and TX DMA channels. * Frame status delivery to memory via DMA, including frame completion semaphores, for efficient buffer queue management in software. * Programmable MDC clock rate and preamble suppression. * In RMII operation, 7 unused pins may be configured as GPIO pins for other purposes. PORTS Because of the rich set of peripherals, the ADSP-BF536/BF537 processor groups the many peripheral signals to four ports-- Port F, Port G, Port H, and Port J. Most of the associated pins are shared by multiple signals. The ports function as multiplexer controls. Eight of the pins (Port F7-0) offer high source/high sink current capabilities. General-Purpose I/O (GPIO) The ADSP-BF536/BF537 processor has 48 bi-directional, general-purpose I/O (GPIO) pins allocated across three separate GPIO modules--PORTFIO, PORTGIO, and PORTHIO, associated with Port F, Port G, and Port H, respectively. Port J does not provide GPIO functionality. Each GPIO-capable pin shares functionality with other ADSP-BF536/BF537 processor peripherals via a multiplexing scheme; however, the GPIO functionality is the default state of the device upon power-up. Neither GPIO output or input drivers are active by default. Each general-purpose port pin can be individually controlled by manipulation of the port control, status, and interrupt registers: * TX DMA support for separate descriptors for MAC header and payload to eliminate buffer copy operations. * Convenient frame alignment modes support even 32-bit alignment of encapsulated RX or TX IP packet data in memory after the 14-byte MAC header. * Programmable Ethernet event interrupt supports any combination of: * Any selected RX or TX frame status conditions. * PHY interrupt condition. * Wakeup frame detected. * Any selected MAC management counter(s) at halffull. * DMA descriptor error. * 47 MAC management statistics counters with selectable clear-on-read behavior and programmable interrupts on half maximum value. * Programmable RX address filters, including a 64-bin address hash table for multicast and/or unicast frames, and programmable filter modes for broadcast, multicast, unicast, control, and damaged frames. * Advanced power management supporting unattended transfer of RX and TX frames and status to/from external memory via DMA during low-power Sleep mode. * System wakeup from Sleep operating mode upon magic packet or any of four user-definable wakeup frame filters. * Support for 802.3Q tagged VLAN frames. Rev. PrD | Page 12 of 64 | * GPIO Direction Control Register - Specifies the direction of each individual GPIO pin as input or output. * GPIO Control and Status Registers - The ADSPBF536/BF537 processor employs a "write one to modify" mechanism that allows any combination of individual GPIO pins to be modified in a single instruction, without affecting the level of any other GPIO pins. Four control registers are provided. One register is written in order to set pin values, one register is written in order to clear pin values, one register is written in order to toggle pin values, and one register is written in order to specify a pin value. Reading the GPIO status register allows software to interrogate the sense of the pins. * GPIO Interrupt Mask Registers - The two GPIO Interrupt Mask registers allow each individual GPIO pin to function as an interrupt to the processor. Similar to the two GPIO Control Registers that are used to set and clear individual pin values, one GPIO Interrupt Mask Register sets bits to enable interrupt function, and the other GPIO Interrupt Mask register clears bits to disable interrupt function. GPIO pins defined as inputs can be configured to generate hardware interrupts, while output pins can be triggered by software interrupts. * GPIO Interrupt Sensitivity Registers - The two GPIO Interrupt Sensitivity Registers specify whether individual pins are level- or edge-sensitive and specify--if edge-sensitive--whether just the rising edge or both the rising and falling edges of the signal are significant. One register selects the type of sensitivity, and one register selects which edges are significant for edge-sensitivity. January 2005 Preliminary Technical Data ADSP-BF536/ADSP-BF537 * Entire Field Mode--The entire incoming bitstream is read in through the PPI. This includes active video, control preamble sequences, and ancillary data that may be embedded in horizontal and vertical blanking intervals. Though not explicitly supported, ITU-R-656 output functionality can be achieved by setting up the entire frame structure (including active video, blanking, and control information) in memory and streaming the data out the PPI in a frame sync-less mode. The processor's 2D DMA features facilitate this transfer by allowing the static frame buffer (blanking and control codes) to be placed in memory once, and simply updating the active video information on a per-frame basis. The general-purpose modes of the PPI are intended to suit a wide variety of data capture and transmission applications. The modes are divided into four main categories, each allowing up to 16 bits of data transfer per PPI_CLK cycle: * Data Receive with Internally Generated Frame Syncs. * Data Receive with Externally Generated Frame Syncs. * Data Transmit with Internally Generated Frame Syncs * Data Transmit with Externally Generated Frame Syncs These modes support ADC/DAC connections, as well as video communication with hardware signalling. Many of the modes support more than one level of frame synchronization. If desired, a programmable delay can be inserted between assertion of a frame sync and reception/transmission of data. In the Active mode, it is possible to disable the PLL through the PLL Control register (PLL_CTL). If disabled, the PLL must be re-enabled before transitioning to the Full-On or Sleep modes. Table 4. Power Settings Full On Active Sleep Deep Sleep Hibernate Enabled Enabled/ Disabled Enabled Disabled Disabled Core Power * Vertical Blanking Only Mode--The PPI only transfers Vertical Blanking Interval (VBI) data, as well as horizontal blanking information and control byte sequences on VBI lines. In the Active mode, the PLL is enabled but bypassed. Because the PLL is bypassed, the processor's core clock (CCLK) and system clock (SCLK) run at the input clock (CLKIN) frequency. In this mode, the CLKIN to CCLK multiplier ratio can be changed, although the changes are not realized until the Full-On mode is entered. DMA access is available to appropriately configured L1 memories. System Clock (SCLK) * Active Video Only Mode--The PPI does not read in any data between the End of Active Video (EAV) and Start of Active Video (SAV) preamble symbols, or any data present during the vertical blanking intervals. In this mode, the control byte sequences are not stored to memory; they are filtered by the PPI. Active Operating Mode - Moderate Power Savings Core Clock (CCLK) Three distinct ITU-R-656 modes are supported: In the Full-On mode, the PLL is enabled and is not bypassed, providing capability for maximum operational frequency. This is the power-up default execution state in which maximum performance can be achieved. The processor core and all enabled peripherals run at full speed. PLL Bypassed In ITU-R-656 modes, the PPI receives and parses a data stream of 8-bit or 10-bit data elements. On-chip decode of embedded preamble control and synchronization information is supported. Full-On Operating Mode - Maximum Performance PLL The ADSP-BF536/BF537 processor provides a Parallel Peripheral Interface (PPI) that can connect directly to parallel A/D and D/A converters, ITU-R-601/656 video encoders and decoders, and other general-purpose peripherals. The PPI consists of a dedicated input clock pin, up to 3 frame synchronization pins, and up to 16 data pins. further reducing power dissipation. Control of clocking to each of the ADSP-BF536/BF537 processor peripherals also reduces power consumption. See Table 4 for a summary of the power settings for each mode. Mode PARALLEL PERIPHERAL INTERFACE (PPI) No Yes Enabled Enabled Enabled Enabled On On - Disabled Disabled Disabled Enabled Disabled Disabled On On Off Sleep Operating Mode - High Dynamic Power Savings The Sleep mode reduces dynamic power dissipation by disabling the clock to the processor core (CCLK). The PLL and system clock (SCLK), however, continue to operate in this mode. Typically an external event or RTC activity will wake up the processor. When in the Sleep mode, assertion of wakeup will cause the processor to sense the value of the BYPASS bit in the PLL Control register (PLL_CTL). If BYPASS is disabled, the processor will transition to the Full On mode. If BYPASS is enabled, the processor will transition to the Active mode. When in the Sleep mode, system DMA access to L1 memory is not supported. DYNAMIC POWER MANAGEMENT Deep Sleep Operating Mode - Maximum Dynamic Power Savings The ADSP-BF536/BF537 processor provides five operating modes, each with a different performance/power profile. In addition, Dynamic Power Management provides the control functions to dynamically alter the processor core supply voltage, The Deep Sleep mode maximizes dynamic power savings by disabling the clocks to the processor core (CCLK) and to all synchronous peripherals (SCLK). Asynchronous peripherals, such as the RTC, may still be running but will not be able to access Rev. PrD | Page 13 of 64 | January 2005 ADSP-BF536/ADSP-BF537 Preliminary Technical Data internal resources or external memory. This powered-down mode can only be exited by assertion of the reset interrupt (RESET) or by an asynchronous interrupt generated by the RTC. When in Deep Sleep mode, an RTC asynchronous interrupt causes the processor to transition to the Active mode. Assertion of RESET while in Deep Sleep mode causes the processor to transition to the Full On mode. The Dynamic Power Management feature of the ADSPBF536/BF537 processor allows both the processor's input voltage (VDDINT) and clock frequency (fCCLK) to be dynamically controlled. Hibernate Operating Mode - Maximum Static Power Savings Power Savings Factor The hibernate mode maximizes static power savings by disabling the voltage and clocks to the processor core (CCLK) and to all the synchronous peripherals (SCLK). The internal voltage regulator for the processor can be shut off by writing b#00 to the FREQ bits of the VR_CTL register. This disables both CCLK and SCLK. Furthermore, it sets the internal power supply voltage (VDDINT) to 0V to provide the greatest power savings mode. Any critical information stored internally (memory contents, register contents, etc.) must be written to a non-volatile storage device prior to removing power if the processor state is to be preserved. As explained above, the savings in power dissipation can be modeled by the following equations: f CCLKRED V DDINTRED 2 T RED = -------------------------------- x -------------------------------------- x ------------------ f CCLKNOM V DDINTNOM T NOM % Power Savings = ( 1 - Power Savings Factor ) x 100% where the variables in the equations are: * fCCLKNOM is the nominal core clock frequency * fCCLKRED is the reduced core clock frequency * VDDINTNOM is the nominal internal supply voltage Since VDDEXT is still supplied in this mode, all of the external pins tri-state, unless otherwise specified. This allows other devices that may be connected to the processor to have power still applied without drawing unwanted current. The internal supply regulator can be woken up by CAN or by Ethernet. It can also be woken up by a Real-Time Clock wakeup event or by asserting the RESET pin, both of which initiate the hardware reset sequence. Power Savings As shown in Table 5, the ADSP-BF536/BF537 processor supports three different power domains. The use of multiple power domains maximizes flexibility, while maintaining compliance with industry standards and conventions. By isolating the internal logic of the ADSP-BF536/BF537 processor into its own power domain, separate from the RTC and other I/O, the processor can take advantage of Dynamic Power Management, without affecting the RTC or other I/O devices. There are no sequencing requirements for the various power domains. Table 5. Power Domains Power Domain All internal logic, except RTC RTC internal logic and crystal I/O All other I/O * TNOM is the duration running at fCCLKNOM * TRED is the duration running at fCCLKRED VOLTAGE REGULATION The ADSP-BF536/BF537 processor provides an on-chip voltage regulator that can generate processor core voltage levels (0.85V to 1.2V guaranteed from -5% to 10%) from an external 2.25 V to 3.6 V supply. Figure 6 shows the typical external components required to complete the power management system. The regulator controls the internal logic voltage levels and is programmable with the Voltage Regulator Control Register (VR_CTL) in increments of 50 mV. To reduce standby power consumption, the internal voltage regulator can be programmed to remove power to the processor core while keeping I/O power supplied. While in Hibernate mode, VDDEXT can still be applied, eliminating the need for external buffers. The voltage regulator can be activated from this power down state by assertion of the RESET pin, which will then initiate a boot sequence. The regulator can also be disabled and bypassed at the user's discretion. CLOCK SIGNALS VDD Range VDDINT VDDRTC VDDEXT The ADSP-BF536/BF537 processor can be clocked by an external crystal, a sine wave input, or a buffered, shaped clock derived from an external clock oscillator. The power dissipated by a processor is largely a function of the clock frequency of the processor and the square of the operating voltage. For example, reducing the clock frequency by 25% results in a 25% reduction in power dissipation, while reducing the voltage by 25% reduces power dissipation by more than 40%. Further, these power savings are additive, in that if the clock frequency and supply voltage are both reduced, the power savings can be dramatic. Rev. PrD | * VDDINTRED is the reduced internal supply voltage If an external clock is used, it should be a TTL compatible signal and must not be halted, changed, or operated below the specified frequency during normal operation. This signal is connected to the processor's CLKIN pin. When an external clock is used, the XTAL pin must be left unconnected. Alternatively, because the ADSP-BF536/BF537 processor includes an on-chip oscillator circuit, an external crystal may be used. The crystal should be connected across the CLKIN and XTAL pins, with two capacitors connected as shown in Figure 7. Capacitor values are dependent on crystal type and should be Page 14 of 64 | January 2005 Preliminary Technical Data ADSP-BF536/ADSP-BF537 signal in other timing specifications as well. While active by default, it can be disabled by the EBIU_SDGCTL and EBIU_AMGCTL registers. VDDEXT 100 F 10 H VDDINT 0.1 F 100 F 1 F 2.25V - 3.6V INPUT VOLTAGE RANGE DYNAMIC MODIFI CATION REQUI RES PLL SEQ UENCING FDS9431A DYNAMIC MO DIFICATIO N ON-THE-FLY ZHCS1000 PLL .5x - 64x CLKI N VROUT1-0 + 1, 2, 4, 8 CCLK + 1:15 SCLK VCO EXTERNAL COMPONENTS NOTE: VROUT1-0 SHOULD BE TIED TOGETHER EXTERNALLY AND DESIGNER SHOULD MINIMIZE TRACE LENGTH TO FDS9431A. SCLK CCLK Figure 6. Voltage Regulator Circuit SCLK 133 MHZ specified by the crystal manufacturer. A parallel-resonant, fundamental frequency, microprocessor-grade crystal should be used. CLKIN XTAL CLKOUT CLKBUF Figure 8. Frequency Modification Methods All on-chip peripherals are clocked by the system clock (SCLK). The system clock frequency is programmable by means of the SSEL3-0 bits of the PLL_DIV register. The values programmed into the SSEL fields define a divide ratio between the PLL output (VCO) and the system clock. SCLK divider values are 1 through 15. Table 6 illustrates typical system clock ratios: Table 6. Example System Clock Ratios PROCESSOR Signal Name SSEL3-0 Figure 7. External Crystal Connections The CLKBUF pin is an output pin, and is a buffer version of the input clock. This pin is particularly useful in Ethernet applications to limit the number of required clock sources in the system. In this type of application, a single 25 MHz or 50 MHz crystal may be applied directly to the ADSP-BF536/BF537 processor. The 25 MHz or 50 MHz output of CLKBUF can then be connected to an external Ethernet MII or RMII PHY device. Note that with the 300 MHz version ADSP-BF536, the XTAL max that can be applied is 30 MHz. The Blackfin core is running at a different clock rate than the on-chip peripherals. As shown in Figure 8 on page 15, the core clock (CCLK) and system peripheral clock (SCLK) are derived from the input clock (CLKIN) signal. An on-chip PLL is capable of multiplying the CLKIN signal by a user programmable 1x to 63x multiplication factor (bounded by specified minimum and maximum VCO frequencies). The default multiplier is 10x, but it can be modified by a software instruction sequence in the PLL_CTL register. On-the-fly CCLK and SCLK frequency changes can be effected by simply writing to the PLL_DIV register. Whereas the maximum allowed CCLK and SCLK rates depend on the applied voltages VDDINT and VDDEXT, the VCO is always permitted to run up to the frequency specified by the part's speed grade. The CLKOUT pin reflects the SCLK frequency to the off-chip world. It belongs to the SDRAM interface, but it functions as reference Rev. PrD | 0001 0110 1010 Divider Ratio Example Frequency Ratios VCO/SCLK (MHz) VCO SCLK 1:1 100 100 6:1 300 50 10:1 500 50 Note that the divisor ratio must be chosen to limit the system clock frequency to its maximum of fSCLK. The SSEL value can be changed dynamically without any PLL lock latencies by writing the appropriate values to the PLL divisor register (PLL_DIV). The core clock (CCLK) frequency can also be dynamically changed by means of the CSEL1-0 bits of the PLL_DIV register. Supported CCLK divider ratios are 1, 2, 4, and 8, as shown in Table 7. This programmable core clock capability is useful for fast core frequency modifications. Table 7. Core Clock Ratios Signal Name CSEL1-0 00 01 10 11 Page 15 of 64 | January 2005 Divider Ratio Example Frequency Ratios VCO/CCLK VCO CCLK 1:1 300 300 2:1 300 150 4:1 500 125 8:1 200 25 ADSP-BF536/ADSP-BF537 Preliminary Technical Data The maximum CCLK frequency not only depends on the part's speed grade (see page 64), it also depends on the applied VDDINT voltage. See Table 10 - Table 13 for details. The maximal system clock rate (SCLK) depends on the chip package and the applied VDDEXT voltage (see Table 15). off the host device from transmitting while the boot ROM is busy, the Blackfin processor will assert a flag pin to signal the host device not to send any more bytes until the flag is de-asserted. The flag is chosen by the user and this information will be transferred to the Blackfin processor via bits 8:5 of the FLAG header. BOOTING MODES * Boot from UART - Using an autobaud handshake sequence, a boot-stream-formatted program is downloaded by the Host. The Host agent selects a baud rate within the UART's clocking capabilities. When performing the autobaud, the UART expects a "@" (boot stream) character (eight bits data, one start bit, one stop bit, no parity bit) on the RXD pin to determine the bit rate. It then replies with an acknowledgement which is composed of 4 bytes: 0xBF, the value of UART_DLL, the value of UART_DLH, 0x00. The Host can then download the boot stream. When the processor needs to hold off the Host, it de-asserts CTS. Therefore, the Host must monitor this signal. The ADSP-BF536/BF537 processor has six mechanisms (listed in Table 8) for automatically loading internal and external memory after a reset. A seventh mode is provided to execute from external memory, bypassing the boot sequence. Table 8. Booting Modes BMODE2-0 000 001 010 011 100 101 110 111 Description Execute from 16-bit external memory (Bypass Boot ROM) Boot from 8-bit or 16-bit memory (EPROM/flash) Reserved Boot from serial SPI memory (EEPROM/flash) Boot from SPI host (slave mode) Boot from serial TWI memory (EEPROM/flash) Boot from TWI host (slave mode) Boot from UART host (slave mode) * Boot from serial TWI memory (EEPROM/flash) - The Blackfin processor operates in master mode and selects the TWI slave with the unique id 0xA0. It submits successive read commands to the memory device starting at two byte internal address 0x0000 and begins clocking data into the processor. The TWI memory device should comply with Philips I2C Bus Specification version 2.1 and have the capability to auto-increment its internal address counter such that the contents of the memory device can be read sequentially. The BMODE pins of the Reset Configuration Register, sampled during power-on resets and software-initiated resets, implement the following modes: * Execute from 16-bit external memory - Execution starts from address 0x2000 0000 with 16-bit packing. The boot ROM is bypassed in this mode. All configuration settings are set for the slowest device possible (3-cycle hold time; 15-cycle R/W access times; 4-cycle setup). * Boot from 8-bit and 16-bit external flash memory - The 8-bit or 16-bit flash boot routine located in boot ROM memory space is set up using Asynchronous Memory Bank 0. All configuration settings are set for the slowest device possible (3-cycle hold time; 15-cycle R/W access times; 4-cycle setup). The boot ROM evaluates the first byte of the boot stream at address 0x2000 0000. If it is 0x40, 8-bit boot is performed. A 0x60 byte is required for 16-bit boot. * Boot from TWI Host - The TWI Host agent selects the slave with the unique id 0x5F. The processor replies with an acknowledgement and the Host can then download the boot stream. The TWI Host agent should comply with Philips I2C Bus Specification version 2.1. An I2C multiplexer can be used to select one processor at a time when booting multiple processors from a single TWI. For each of the boot modes, a 10-byte header is first brought in from an external device. The header specifies the number of bytes to be transferred and the memory destination address. Multiple memory blocks may be loaded by any boot sequence. Once all blocks are loaded, program execution commences from the start of L1 instruction SRAM. In addition, bit 4 of the Reset Configuration Register can be set by application code to bypass the normal boot sequence during a software reset. For this case, the processor jumps directly to the beginning of L1 instruction memory. * Boot from serial SPI memory (EEPROM or flash). Eight-, 16-, or 24-bit addressable devices are supported as well as AT45DB041, AT45DB081, and AT45DB161 data flash devices from Atmel. The SPI uses the PF10/SPI SSEL1 output pin to select a single SPI EEPROM/flash device, submits a read command and successive address bytes (0x00) until a valid 8-, 16-, or 24-bit, or Atmel addressable device is detected, and begins clocking data into the processor. INSTRUCTION SET DESCRIPTION * Boot from SPI host device - The Blackfin processor operates in SPI slave mode and is configured to receive the bytes of the .LDR file from an SPI host (master) agent. To hold The Blackfin processor family assembly language instruction set employs an algebraic syntax designed for ease of coding and readability. The instructions have been specifically tuned to pro- Rev. PrD | To augment the boot modes, a secondary software loader can be added to provide additional booting mechanisms. This secondary loader could provide the capability to boot from flash, variable baud rate, and other sources. In all boot modes except Bypass, program execution starts from on-chip L1 memory address 0xFFA0 0000. Page 16 of 64 | January 2005 Preliminary Technical Data ADSP-BF536/ADSP-BF537 vide a flexible, densely encoded instruction set that compiles to a very small final memory size. The instruction set also provides fully featured multifunction instructions that allow the programmer to use many of the processor core resources in a single instruction. Coupled with many features more often seen on microcontrollers, this instruction set is very efficient when compiling C and C++ source code. In addition, the architecture supports both user (algorithm/application code) and supervisor (O/S kernel, device drivers, debuggers, ISRs) modes of operation, allowing multiple levels of access to core processor resources. The assembly language, which takes advantage of the processor's unique architecture, offers the following advantages: For details on target board design issues including mechanical layout, single processor connections, multiprocessor scan chains, signal buffering, signal termination, and emulator pod logic, see Analog Devices JTAG Emulation Technical Reference (EE-68) on the Analog Devices web site under www.analog.com/ee-notes. This document is updated regularly to keep pace with improvements to emulator support. RELATED DOCUMENTS The following publications that describe the ADSPBF536/BF537 processors (and related processors) can be ordered from any Analog Devices sales office or accessed electronically on our web site: * Seamlessly integrated DSP/MCU features are optimized for both 8-bit and 16-bit operations. * ADSP-BF537 Blackfin Processor Hardware Reference * A multi-issue load/store modified-Harvard architecture, which supports two 16-bit MAC or four 8-bit ALU + two load/store + two pointer updates per cycle. * ADSP-BF536 Blackfin Processor Anomaly List * Blackfin Processor Programming Reference * ADSP-BF537 Blackfin Processor Anomaly List * All registers, I/O, and memory are mapped into a unified 4G byte memory space, providing a simplified programming model. * Microcontroller features, such as arbitrary bit and bit-field manipulation, insertion, and extraction; integer operations on 8-, 16-, and 32-bit data-types; and separate user and supervisor stack pointers. * Code density enhancements, which include intermixing of 16- and 32-bit instructions (no mode switching, no code segregation). Frequently used instructions are encoded in 16 bits. DEVELOPMENT TOOLS The ADSP-BF536/BF537 processor is supported with a complete set of CROSSCORE(R) software and hardware development tools, including Analog Devices emulators and VisualDSP++(R) development environment. The same emulator hardware that supports other Blackfin processors also fully emulates the ADSP-BF536/BF537 processor. DESIGNING AN EMULATOR-COMPATIBLE PROCESSOR BOARD (TARGET) The Analog Devices family of emulators are tools that every system developer needs to test and debug hardware and software systems. Analog Devices has supplied an IEEE 1149.1 JTAG Test Access Port (TAP) on each JTAG processor. The emulator uses the TAP to access the internal features of the processor, allowing the developer to load code, set breakpoints, observe variables, observe memory, and examine registers. The processor must be halted to send data and commands, but once an operation has been completed by the emulator, the processor system is set running at full speed with no impact on system timing. To use these emulators, the target board must include a header that connects the processor's JTAG port to the emulator. Rev. PrD | Page 17 of 64 | January 2005 ADSP-BF536/ADSP-BF537 Preliminary Technical Data PIN DESCRIPTIONS ADSP-BF536/BF537 processor pin definitions are listed in Table 9. In order to maintain maximum functionality and reduce package size and pin count, some pins have dual, multiplexed functionality. In cases where pin functionality is reconfigurable, the default state is shown in plain text, while alternate functionality is shown in italics. Pins shown with an asterisk after their name (*) offer high source/high sink current capabilities. All pins are tristated during and immediately after reset with the exception of the external memory interface. On the external memory interface, the control and address lines are driven high during reset unless the BR pin is asserted. All I/O pins have their input buffers disabled with the exception of the pins noted in the data sheet that need pullups or pulldowns if unused. Table 9. Pin Descriptions Pin Name Memory Interface ADDR19-1 DATA15-0 ABE1-0/SDQM1-0 BR2 BG BGH Asynchronous Memory Control AMS3-0 ARDY AOE ARE AWE Synchronous Memory Control SRAS SCAS SWE SCKE CLKOUT SA10 SMS I/O Function Driver Type1 O I/O O I O O Address Bus for Async Access Data Bus for Async/Sync Access Byte Enables/Data Masks for Async/Sync Access Bus Request Bus Grant Bus Grant Hang A A A O I O O O Bank Select Hardware Ready Control Output Enable Read Enable Write Enable A A A O O O O O O O Row Address Strobe Column Address Strobe Write Enable Clock Enable Clock Output A10 Pin Bank Select A A A A B A A Rev. PrD | Page 18 of 64 | A A A January 2005 Preliminary Technical Data ADSP-BF536/ADSP-BF537 Table 9. Pin Descriptions (Continued) Pin Name I/O Function Port F: GPIO/UART1-0/Timer7-0/SPI/External DMA Request (* = High Source/High Sink Pin) PF0* - GPIO/UART0 TX/DMAR0 I/O GPIO/UART0 Transmit/DMA Request 0 PF1* - GPIO/UART0 RX/DMAR1/TACI1 I/O GPIO/UART0 Receive/DMA Request 1/Timer1 Alternate Input Capture PF2* - GPIO/UART1 TX/TMR7 I/O GPIO/UART1 Transmit/Timer7 PF3* - GPIO/UART1 RX/TMR6/TACI6 I/O GPIO/UART1 Receive/Timer6/Timer6 Alternate Input Capture PF4* - GPIO/TMR5/SPI SSEL6 I/O GPIO/Timer5/SPI Slave Select Enable 6 PF5* - GPIO/TMR4/SPI SSEL5 I/O GPIO/Timer4/SPI Slave Select Enable 5 PF6* - GPIO/TMR3/SPI SSEL4 I/O GPIO/Timer3/SPI Slave Select Enable 4 PF7* - GPIO/TMR2/PPI FS3 I/O GPIO/Timer2/PPI Frame Sync 3 PF8 - GPIO/TMR1/PPI FS2 I/O GPIO/Timer1/PPI Frame Sync 2 PF9 - GPIO/TMR0/PPI FS1 I/O GPIO/Timer0/PPI Frame Sync 1 PF10 - GPIO/SPI SSEL1 I/O GPIO/SPI Slave Select Enable 1 PF11 - GPIO/SPI MOSI I/O GPIO/SPI Master Out Slave In 3 PF12 - GPIO/SPI MISO I/O GPIO/SPI Master In Slave Out PF13 - GPIO/SPI SCK I/O GPIO/SPI Clock PF14 - GPIO/SPI SS/TACLK0 I/O GPIO/SPI Slave Select/Alternate Timer0 Clock Input PF15 - GPIO/PPI CLK/TMRCLK I/O GPIO/PPI Clock/External Timer Reference Port G: GPIO/PPI/SPORT1 PG0 - GPIO/PPI D0 I/O GPIO/PPI Data 0 PG1 - GPIO/PPI D1 I/O GPIO/PPI Data 1 PG2 - GPIO/PPI D2 I/O GPIO/PPI Data 2 PG3 - GPIO/PPI D3 I/O GPIO/PPI Data 3 PG4 - GPIO/PPI D4 I/O GPIO/PPI Data 4 PG5 - GPIO/PPI D5 I/O GPIO/PPI Data 5 PG6 - GPIO/PPI D6 I/O GPIO/PPI Data 6 PG7 - GPIO/PPI D7 I/O GPIO/PPI Data 7 PG8 - GPIO/PPI D8/DR1SEC I/O GPIO/PPI Data 8/SPORT1 Receive Data Secondary PG9 - GPIO/PPI D9/DT1SEC I/O GPIO/PPI Data 9/SPORT1 Transmit Data Secondary PG10 - GPIO/PPI D10/RSCLK1 I/O GPIO/PPI Data 10/SPORT1 Receive Serial Clock PG11 - GPIO/PPI D11/RFS1 I/O GPIO/PPI Data 11/SPORT1 Receive Frame Sync PG12 - GPIO/PPI D12/DR1PRI I/O GPIO/PPI Data 12/SPORT1 Receive Data Primary PG13 - GPIO/PPI D13/TSCLK1 I/O GPIO/PPI Data 13/SPORT1 Transmit Serial Clock PG14 - GPIO/PPI D14/TFS1 I/O GPIO/PPI Data 14/SPORT1 Transmit Frame Sync PG15 - GPIO/PPI D15/DT1PRI I/O GPIO/PPI Data 15/SPORT1 Transmit Data Primary Port H: GPIO/10/100 Ethernet MAC PH0 - GPIO/ETxD0 I/O GPIO/Ethernet MII or RMII Transmit D0 PH1 - GPIO/ETxD1 I/O GPIO/Ethernet MII or RMII Transmit D1 PH2 - GPIO/ETxD2 I/O GPIO/Ethernet MII Transmit D2 PH3 - GPIO/ETxD3 I/O GPIO/Ethernet MII Transmit D3 PH4 - GPIO/ETxEN I/O GPIO/Ethernet MII or RMII Transmit Enable Rev. PrD | Page 19 of 64 | January 2005 Driver Type1 C C C C C C C C D D D D D D D D D D D D D D D D D D D D D D D D D D D D D ADSP-BF536/ADSP-BF537 Preliminary Technical Data Table 9. Pin Descriptions (Continued) Pin Name I/O Port H: GPIO/10/100 Ethernet MAC, continued PH5 - GPIO/MII TxCLK/RMII REF_CLK I/O PH6 - GPIO/MII PHYINT/RMII MDINT I/O PH7 - GPIO/COL I/O PH8 - GPIO/ERxD0 I/O PH9 - GPIO/ERxD1 I/O PH10 - GPIO/ERxD2 I/O PH11 - GPIO/ERxD3 I/O PH12 - GPIO/ERxDV/TACLK5 I/O PH13 - GPIO/ERxCLK/TACLK6 I/O PH14 - GPIO/ERxER/TACLK7 I/O PH15 - GPIO/MII CRS/RMII CRS_DV I/O Function Driver Type1 GPIO/Ethernet MII Transmit Clock/RMII Reference Clock GPIO/Ethernet MII PHY Interrupt/RMII Management Data Interrupt GPIO/Ethernet Collision GPIO/Ethernet MII or RMII Receive D0 GPIO/Ethernet MII or RMII Receive D1 GPIO/Ethernet MII Receive D2 GPIO/Ethernet MII Receive D3 GPIO/Ethernet MII Receive Data Valid/Alternate Timer5 Input Clock GPIO/Ethernet MII Receive Clock/Alternate Timer6 Input Clock GPIO/Ethernet MII or RMII Receive Error/Alternate Timer7 Input Clock GPIO/Ethernet MII Carrier Sense/Ethernet RMII Carrier Sense and Receive Data Valid D D D D D D D D D D D D D D D Port J: SPORT0/TWI/SPI Select/CAN PJ0 - MDC PJ1 - MDIO PJ2 - SCL PJ3 - SDA PJ4 - DR0SEC/CANRX/TACI0 O I/O I/O I/O I PJ5 - DT0SEC/CANTX/SPI SSEL7 O PJ6 - RSCLK0/TACLK2 PJ7 - RFS0/TACLK3 PJ8 - DR0PRI/TACLK4 PJ9 - TSCLK0/TACLK1 PJ10 - TFS0/SPI SSEL3 PJ11 - DT0PRI/SPI SSEL2 Real Time Clock RTXI4 RTXO JTAG Port TCK TDO TDI TMS TRST5 EMU Clock CLKIN XTAL CLKBUF Mode Controls RESET NMI6 BMODE2-0 I/O I/O I I/O I/O O Ethernet Management Channel Clock Ethernet Management Channel Serial Data TWI Serial Clock TWI Serial Data SPORT0 Receive Data Secondary/CAN Receive/Timer0 Alternate Input Capture SPORT0 Transmit Data Secondary/CAN Transmit/SPI Slave Select Enable 7 SPORT0 Receive Serial Clock/Alternate Timer2 Clock Input SPORT0 Receive Frame Sync/Alternate Timer3 Clock Input SPORT0 Receive Data Primary/Alternate Timer4 Clock Input SPORT0 Transmit Serial Clock/Alternate Timer1 Clock Input SPORT0 Transmit Frame Sync/SPI Slave Select Enable 3 SPORT0 Transmit Data Primary/SPI Slave Select Enable 2 I O RTC Crystal Input RTC Crystal Output I O I I I O JTAG Clock JTAG Serial Data Out JTAG Serial Data In JTAG Mode Select JTAG Reset Emulation Output I O O Clock/Crystal Input Crystal Output Buffered XTAL Output I I I Reset Non-maskable Interrupt Boot Mode Strap 2-0 Rev. PrD | Page 20 of 64 | D E D E D D D D January 2005 Preliminary Technical Data ADSP-BF536/ADSP-BF537 Table 9. Pin Descriptions (Continued) Pin Name Voltage Regulator VROUT0 VROUT1 Supplies VDDEXT VDDINT VDDRTC GND Driver Type1 I/O Function O O External FET Drive External FET Drive P P P G I/O Power Supply Internal Power Supply (regulated from 2.25V to 3.6V) Real Time Clock Power Supply External Ground 1 See "Output Drive Currents" on page 51 for more information about each driver types. This pin should be pulled HIGH when not used. 3 This pin should always be pulled HIGH through a 4.7 K Ohms resistor if booting via the SPI port. 4 This pin should always be pulled LOW when not used. 5 This pin should be pulled LOW if the JTAG port will not be used. 6 This pin should always be pulled HIGH when not used. 2 Rev. PrD | Page 21 of 64 | January 2005 ADSP-BF536/ADSP-BF537 Preliminary Technical Data SPECIFICATIONS Note that component specifications are subject to change without notice. RECOMMENDED OPERATING CONDITIONS Parameter1 VDDINT VDDEXT VDDRTC VIH VIHCLKIN VIH5V VIL VIL5V TA Minimum 0.8 2.25 2.25 2.0 2.2 2.0 -0.3 -0.3 Internal Supply Voltage2 External Supply Voltage Real Time Clock Power Supply Voltage High Level Input Voltage3, 4, @ VDDEXT =maximum High Level Input Voltage5, @ VDDEXT =maximum High Level Input Voltage6, @ VDDEXT =maximum Low Level Input Voltage3, 7, @ VDDEXT =minimum Low Level Input Voltage6, @ VDDEXT =minimum Ambient Operating Temperature Industrial -40 1 Nominal 1.2 2.5 or 3.3 Maximum 1.32 3.6 3.6 3.6 3.6 5.0 0.6 0.8 Unit V V V V V V V V 85 C Specifications subject to change without notice. Voltage regulator output is guaranteed from -5% to 10% of specified values. 3 The ADSP-BF536/BF537 processor is 3.3 V tolerant (always accepts up to 3.6 V maximum VIH), but voltage compliance (on outputs, VOH) depends on the input VDDEXT, because VOH (maximum) approximately equals VDDEXT (maximum). This 3.3 V tolerance applies to bi-directional pins (DATA15-0, PF15-0, PG15-0, PH15-0, TFS0, TCLK0, RSCLK0, RFS0, MDIO) and input only pins (BR, ARDY, DR0PRI, DR0SEC, RTXI, TCK, TDI, TMS, TRST, CLKIN, RESET, NMI, and BMODE2-0). 4 Parameter value applies to all input and bi-directional pins except CLKIN, SDA, and SCL. 5 Parameter value applies to CLKIN pin only. 6 Certain ADSP-BF536/BF537 processor pins are 5.0 V tolerant (always accept up to 5.5 V maximum VIH), but voltage compliance (on outputs, VOH) depends on the input VDDEXT, because VOH (maximum) approximately equals VDDEXT (maximum). This 5.0 V tolerance applies to SDA and SCL pins only. The SDA and SCL pins are open drain and therefore require a pullup resistor. Consult the I2C specification version 2.1 for the proper resistor value. 7 Parameter value applies to all input and bi-directional pins except SDA and SCL. 2 Rev. PrD | Page 22 of 64 | January 2005 Preliminary Technical Data ADSP-BF536/ADSP-BF537 ELECTRICAL CHARACTERISTICS Parameter1 VOH Port F7-0 Port F15-8, Port G, Port H Max Combined for Port F7-0 Max Total for all Port F, Port G, and Port H Pins VOL Port F7-0 Port F15-8, Port G, Port H Max Combined for Port F7-0 Max Total for all Port F, Port G, and Port H Pins IIH IIL IOZH IOZL Max Total Current for all Port F, Port G, and Port H Pins CIN Test Conditions Min Max Unit @ VDDEXT = 3.3V +/- 10%, IOH = -10 mA @ VDDEXT = 2.5V +/- 10%, IOH = -6 mA IOH = -1 mA VDDEXT - 0.5V VDDEXT - 0.5V VDDEXT - 0.5V TBD TBD V V V V V TBD TBD V V V V V @ VDDEXT =maximum, VIN = VDD maximum @ VDDEXT =maximum, VIN = 0 V @ VDDEXT = maximum, VIN = VDD maximum TBD TBD TBD A A A @ VDDEXT = maximum, VIN = 0 V TBD A TBD mA TBD pF High Level Output Voltage2 Low Level Output Voltage2 @ VDDEXT = 3.3V +/- 10%, IOL = 10 mA @ VDDEXT = 2.5V +/- 10%, IOL = 6 mA IOL = 2 mA High Level Input Current3 Low Level Input Current4 Three-State Leakage Current4 Three-State Leakage Current5 Input Capacitance5, 6 fIN = 1 MHz, TAMBIENT = 25C, VIN = 2.5 V 1 Specifications subject to change without notice. 2 Applies to output and bidirectional pins. 3 Applies to input pins. 4 Applies to three-statable pins. 5 Applies to all signal pins. 6 Guaranteed, but not tested. Rev. PrD | Page 23 of 64 | January 2005 0.5V 0.5V 0.5V ADSP-BF536/ADSP-BF537 Preliminary Technical Data ABSOLUTE MAXIMUM RATINGS Internal (Core) Supply Voltage1 (VDDINT) External (I/O) Supply Voltage1 (VDDEXT) Input Voltage1 Output Voltage Swing1 Load Capacitance1,2 Storage Temperature Range1 Junction Temperature Underbias1 -0.3 V to +1.4 V -0.3 V to +3.8 V -0.5 V to +3.6 V -0.5 V to VDDEXT +0.5 V 200 pF -65C to +150C +125C a PRODUCT ADSP-BF537 SKBC2Z600X LOT NUMBER 367334.1 0.2 DATE CODE 0440 SINGAPORE B S = INTERNAL VOLTAGE K = TEMP RANGE BC2Z = PACKAGE 600 = SPEED GRADE X = X-GRADE PART SILICON REVISION ASSEMBLY 1 Stresses greater than those listed above may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 For proper SDRAM controller operation, the maximum load capacitance is 50 pF (at 3.3V) or 30 pF (at 2.5V) for ADDR19-1, DATA15-0, ABE1-0/SDQM1-0, CLKOUT, SCKE, SA10, SRAS, SCAS, SWE, and SMS. Figure 9. Product Information on Package ESD SENSITIVITY CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADSP-BF536/BF537 processor features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. PrD | Page 24 of 64 | January 2005 Preliminary Technical Data ADSP-BF536/ADSP-BF537 TIMING SPECIFICATIONS Table 10 through Table 13 describe the timing requirements for the ADSP-BF536/BF537 processor clocks. Take care in selecting MSEL, SSEL, and CSEL ratios so as not to exceed the maximum core clock and system clock. Table 14 describes Phase-Locked Loop operating conditions. Table 10. Core Clock Requirements--600 MHz Speed Grade1 Parameter fCCLK fCCLK fCCLK fCCLK fCCLK 1 Minimum Core Clock Frequency (VDDINT =1.2 V-5%) Core Clock Frequency (VDDINT =1.1 V-5%) Core Clock Frequency (VDDINT =1.0 V-5%) Core Clock Frequency (VDDINT =0.9 V-5%) Core Clock Frequency (VDDINT =0.8 V ) Maximum 600 TBD TBD TBD TBD Unit MHz MHz MHz MHz MHz The speed grade of a given part is printed on the chip's package as shown in Figure 9 on page 24 and can also be seen on the "Ordering Guide" on page 64. It stands for the Maximum allowed CCLK frequency at VDDINT = 1.2V and the maximum allowed VCO frequency at any supply voltage. Table 11. Core Clock Requirements--500 MHz Speed Grade1 Parameter fCCLK fCCLK fCCLK fCCLK fCCLK 1 Minimum Core Clock Frequency (VDDINT =1.2 V-5%) Core Clock Frequency (VDDINT =1.1 V-5%) Core Clock Frequency (VDDINT =1.0 V-5%) Core Clock Frequency (VDDINT =0.9 V-5%) Core Clock Frequency (VDDINT =0.8 V ) Maximum 500 TBD TBD TBD TBD Unit MHz MHz MHz MHz MHz The speed grade of a given part is printed on the chip's package as shown in Figure 9 on page 24 and can also be seen on the "Ordering Guide" on page 64. It stands for the Maximum allowed CCLK frequency at VDDINT = 1.2V and the maximum allowed VCO frequency at any supply voltage. Table 12. Core Clock Requirements--400 MHz Speed Grade1 Parameter fCCLK fCCLK fCCLK fCCLK fCCLK 1 Minimum Core Clock Frequency (VDDINT =1.2 V-5%) Core Clock Frequency (VDDINT =1.1 V-5%) Core Clock Frequency (VDDINT =1.0 V-5%) Core Clock Frequency (VDDINT =0.9 V-5%) Core Clock Frequency (VDDINT =0.8 V ) Maximum 400 TBD TBD TBD TBD Unit MHz MHz MHz MHz MHz The speed grade of a given part is printed on the chip's package as shown in Figure 9 on page 24 and can also be seen on the "Ordering Guide" on page 64. It stands for the Maximum allowed CCLK frequency at VDDINT = 1.2V and the maximum allowed VCO frequency at any supply voltage. Table 13. Core Clock Requirements--300 MHz Speed Grade1 Parameter fCCLK fCCLK fCCLK fCCLK fCCLK 1 Minimum Core Clock Frequency (VDDINT =1.2 V-5%) Core Clock Frequency (VDDINT =1.1 V-5%) Core Clock Frequency (VDDINT =1.0 V-5%) Core Clock Frequency (VDDINT =0.9 V-5%) Core Clock Frequency (VDDINT =0.8 V ) Maximum 300 TBD TBD TBD TBD Unit MHz MHz MHz MHz MHz The speed grade of a given part is printed on the chip's package as shown in Figure 9 on page 24 and can also be seen on the "Ordering Guide" on page 64. It stands for the Maximum allowed CCLK frequency at VDDINT = 1.2V and the maximum allowed VCO frequency at any supply voltage. Rev. PrD | Page 25 of 64 | January 2005 ADSP-BF536/ADSP-BF537 Preliminary Technical Data Table 14. Phase-Locked Loop Operating Conditions Parameter fVCO 1 Minimum 50 Voltage Controlled Oscillator (VCO) Frequency Maximum Unit 1 Speed Grade MHz The speed grade of a given part is printed on the chip's package as shown in Figure 9 on page 24 and can also be seen on the "Ordering Guide" on page 64. It stands for the Maximum allowed CCLK frequency at VDDINT = 1.2V and the maximum allowed VCO frequency at any supply voltage. Table 15. System Clock Requirements Parameter Condition 182 MBGA fSCLK fSCLK fSCLK fSCLK 208 MBGA fSCLK fSCLK fSCLK fSCLK Minimum Maximum Unit VDDEXT VDDEXT VDDEXT VDDEXT = 3.3 V, VDDINT >= TBD V = 3.3 V, VDDINT < TBD V = 2.5 V, VDDINT >= TBD V = 2.5 V, VDDINT < TBD V TBD TBD TBD TBD MHz MHz MHz MHz VDDEXT VDDEXT VDDEXT VDDEXT = 3.3 V, VDDINT >= TBD V = 3.3 V, VDDINT < TBD V = 2.5 V, VDDINT >= TBD V = 2.5 V, VDDINT < TBD V TBD TBD TBD TBD MHz MHz MHz MHz Table 16. Clock Input and Reset Timing Parameter Timing Requirements tCKIN CLKIN Period1 tCKINL CLKIN Low Pulse2 tCKINH CLKIN High Pulse2 tBUFDLAY CLKIN to CLKBUF delay tWRST RESET Asserted Pulsewidth Low3 Minimum Maximum Unit 25.0 10.0 10.0 100.0 ns ns ns ns ns TBD 11 tCKIN 1 Combinations of the CLKIN frequency and the PLL clock multiplier must not exceed the allowed fVCO, fCCLK, and fSCLK settings discussed in Table 10 through Table 15. Since by default the PLL is multiplying the CLKIN frequency by 10, 300 MHz and 400MHz speed grade parts can not use the full CLKIN period range. 2 Applies to bypass mode and non-bypass mode. 3 Applies after power-up sequence is complete. At power-up, the processor's internal phase-locked loop requires no more than 2000 CLKIN cycles, while RESET is asserted, assuming stable power supplies and CLKIN (not including start-up time of external clock oscillator). tCKIN CLKIN tCKINL tCKINH tBUFDLAY tBUFDLAY CLKBUF tWRST RESET Figure 10. Clock and Reset Timing Rev. PrD | Page 26 of 64 | January 2005 Preliminary Technical Data ADSP-BF536/ADSP-BF537 Asynchronous Memory Read Cycle Timing Table 17. Asynchronous Memory Read Cycle Timing Parameter Timing Requirements tSDAT DATA15-0 Setup Before CLKOUT tHDAT DATA15-0 Hold After CLKOUT tSARDY ARDY Setup Before CLKOUT tHARDY ARDY Hold After CLKOUT Switching Characteristic tDO Output Delay After CLKOUT1 Output Hold After CLKOUT 1 tHO 1 Minimum Maximum 2.1 0.8 4.0 0.0 ns ns ns ns 6.0 ns ns 0.8 Output pins include AMS3-0, ABE1-0, ADDR19-1, AOE, ARE. SETUP 2 CYCLES PROGRAMMED READ ACCESS 4 CYCLES HOLD 1 CYCLE ACCESS EXTENDED 3 CYCLES CLKOUT tDO tHO AMSx ABE1-0 BE, ADDRESS ADDR19-1 AOE tDO tHO ARE tSARDY tHARDY tHARDY ARDY tSARDY tSDAT tHDAT DATA15-0 READ Figure 11. Asynchronous Memory Read Cycle Timing Rev. PrD | Page 27 of 64 | January 2005 Unit ADSP-BF536/ADSP-BF537 Preliminary Technical Data Asynchronous Memory Write Cycle Timing Table 18. Asynchronous Memory Write Cycle Timing Parameter Timing Requirements tSARDY ARDY Setup Before CLKOUT tHARDY ARDY Hold After CLKOUT Switching Characteristic tDDAT DATA15-0 Disable After CLKOUT tENDAT DATA15-0 Enable After CLKOUT tDO Output Delay After CLKOUT1 Output Hold After CLKOUT 1 tHO 1 Minimum 4.0 0.0 1.0 6.0 0.8 PROGRAMMED WRITE ACCESS 2 CYCLES ACCESS EXTENDED 1 CYCLE HOLD 1 CYCLE CLKOUT t DO t HO AMSx ABE1-0 BE, ADDRESS ADDR19-1 tDO tHO AWE t HARDY t SARDY ARDY tSARDY t ENDAT DATA15-0 t DDAT WRITE DATA Figure 12. Asynchronous Memory Write Cycle Timing Rev. PrD | Page 28 of 64 | January 2005 Unit ns ns 6.0 Output pins include AMS3-0, ABE1-0, ADDR19-1, DATA15-0, AOE, AWE. SETUP 2 CYCLES Maximum ns ns ns ns Preliminary Technical Data ADSP-BF536/ADSP-BF537 SDRAM Interface Timing Table 19. SDRAM Interface Timing (VDDINT = 1.2 V) Parameter Timing Requirement tSSDAT DATA Setup Before CLKOUT tHSDAT DATA Hold After CLKOUT Switching Characteristic tSCLK CLKOUT Period1 tSCLKH CLKOUT Width High tSCLKL CLKOUT Width Low Command, ADDR, Data Delay After CLKOUT2 tDCAD tHCAD Command, ADDR, Data Hold After CLKOUT2 tDSDAT Data Disable After CLKOUT tENSDAT Data Enable After CLKOUT 1 2 Minimum Maximum 2.1 0.8 ns ns 7.5 2.5 2.5 ns ns ns ns ns ns ns 6.0 0.8 6.0 1.0 The tSCLK value is the inverse of the fSCLK specification discussed in Table 15. Package type and reduced supply voltages affect the best-case value of 7.5ns listed here. Command pins include: SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE. tSCLK tSCLKH CLKOUT t SSDAT t SCLKL tHSDAT DATA (IN) t DCAD tENSDAT tDCAD CMND ADDR (OUT) tHCAD NOTE: COMMAND = SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE. Figure 13. SDRAM Interface Timing Rev. PrD | Page 29 of 64 | tD SDA T tHCAD DATA(OUT) January 2005 Unit ADSP-BF536/ADSP-BF537 Preliminary Technical Data External Port Bus Request and Grant Cycle Timing Table 20 and Figure 14 describe external port bus request and bus grant operations. Table 20. External Port Bus Request and Grant Cycle Timing Parameter 1, 2 Timing Requirements tBS BR asserted to CLKOUT high setup tBH CLKOUT high to BR de-asserted hold time Switching Characteristics tSD CLKOUT low to xMS, address, and RD/WR disable CLKOUT low to xMS, address, and RD/WR enable tSE tDBG CLKOUT high to BG asserted setup tEBG CLKOUT high to BG de-asserted hold time tDBH CLKOUT high to BGH asserted setup tEBH CLKOUT high to BGH de-asserted hold time 1 2 Minimum Maximum 4.6 0.0 ns ns 4.5 4.5 3.6 3.6 3.6 3.6 ns ns ns ns ns ns These are preliminary timing parameters that are based on worst-case operating conditions. The pad loads for these timing parameters are 20 pF. CLKOUT tBS tBH BR tSD tSE AMSx tSD tSE ADDR19-1 ABE1-0 tSD tSE AWE ARE tDBG tEBG BG tDBH BGH Figure 14. External Port Bus Request and Grant Cycle Timing Rev. PrD | Page 30 of 64 | January 2005 Unit tEBH Preliminary Technical Data ADSP-BF536/ADSP-BF537 External DMA Request Timing Table 21 and Figure 15 describe the External DMA Request operations. Table 21. External DMA Request Timing Parameter Timing Parameters tDR DMARx asserted to CLKOUT high setup tDH CLKOUT high to DMARx de-asserted hold time Switching Characteristics tDO Output delay after CLKOUT1 Output hold after CLKOUT1 tHO 1 Minimum Maximum Unit TBD TBD TBD TBD ns ns TBD TBD TBD TBD ns ns System Outputs=DATA15-0, ADDR19-1, ABE1-0, AOE, ARE, AWE, AMS3-0, SRAS, SCAS, SWE, SCKE, CLKOUT, SA10, SMS, SCL, SDA, TSCLK0, TFS0, RFS0, RSCLK0, DT0PRI, DT0SEC, PF15-0, PG15-0, PH15-0, MDC, MDIO, RTX0, TD0, EMU, XTAL, CLKBUF, VROUT. CLKOUT tDR tDH DMAR0/1 tDO tHO AMSx Figure 15. External DMA Request Timing Rev. PrD | Page 31 of 64 | January 2005 ADSP-BF536/ADSP-BF537 Preliminary Technical Data Parallel Peripheral Interface Timing Table 22 and Figure 16 on page 32, Figure 17 on page 35, and Figure 18 on page 36 describe Parallel Peripheral Interface operations. Table 22. Parallel Peripheral Interface Timing Parameter Timing Requirements PPI_CLK Width1 tPCLKW tPCLK PPI_CLK Period1 Timing Requirements - GP Input and Frame Capture Modes tSFSPE External Frame Sync Setup Before PPI_CLK tHFSPE External Frame Sync Hold After PPI_CLK tSDRPE Receive Data Setup Before PPI_CLK Receive Data Hold After PPI_CLK tHDRPE Switching Characteristics - GP Output and Frame Capture Modes tDFSPE Internal Frame Sync Delay After PPI_CLK tHOFSPE Internal Frame Sync Hold After PPI_CLK tDDTPE Transmit Data Delay After PPI_CLK tHDTPE Transmit Data Hold After PPI_CLK 1 Minimum PPI_CLK tDFSPE tSFSPE tHFSPE tSDRPE tHDRPE PPI_FS1 PPI_FS2 PPIx Figure 16. Parallel Peripheral Interface Timing Rev. PrD | ns ns ns ns 10.0 tPCLKW tDDTPE 3.0 3.0 2.0 4.0 0.0 SAMPLE EDGE tHDTPE ns ns 0.0 DRIVE EDGE Page 32 of 64 | January 2005 Unit 6.0 15.0 10.0 PPI_CLK frequency cannot exceed fSCLK/2 tHOFSPE Maximum ns ns ns ns Preliminary Technical Data ADSP-BF536/ADSP-BF537 Serial Ports Table 23 through Table 28 on page 34 and Figure 17 on page 35 through Figure 19 on page 37 describe Serial Port operations. Table 23. Serial Ports--External Clock Parameter Timing Requirements tSFSE TFS/RFS Setup Before TSCLK/RSCLK1 tHFSE TFS/RFS Hold After TSCLK/RSCLK1 tSDRE Receive Data Setup Before RSCLK1 tHDRE Receive Data Hold After RSCLK1 TSCLK/RSCLK Width tSCLKEW tSCLKE TSCLK/RSCLK Period 1 Minimum Maximum 3.0 3.0 3.0 3.0 4.5 15.0 Unit ns ns ns ns ns ns Referenced to sample edge. Table 24. Serial Ports--Internal Clock Parameter Timing Requirements tSFSI TFS/RFS Setup Before TSCLK/RSCLK1 tHFSI TFS/RFS Hold After TSCLK/RSCLK1 tSDRI Receive Data Setup Before RSCLK1 tHDRI Receive Data Hold After RSCLK1 tSCLKEW TSCLK/RSCLK Width tSCLKE TSCLK/RSCLK Period 1 Minimum Maximum 8.0 -2.0 6.0 0.0 4.5 15.0 Unit ns ns ns ns ns ns Referenced to sample edge. Table 25. Serial Ports--External Clock Parameter Switching Characteristics tDFSE TFS/RFS Delay After TSCLK/RSCLK (Internally Generated TFS/RFS)1 tHOFSE TFS/RFS Hold After TSCLK/RSCLK (Internally Generated TFS/RFS)1 tDDTE Transmit Data Delay After TSCLK1 Transmit Data Hold After TSCLK1 tHDTE 1 Minimum Maximum Unit 10.0 ns ns ns ns 0.0 10.0 0.0 Referenced to drive edge. Table 26. Serial Ports--Internal Clock Parameter Switching Characteristics tDFSI TFS/RFS Delay After TSCLK/RSCLK (Internally Generated TFS/RFS)1 TFS/RFS Hold After TSCLK/RSCLK (Internally Generated TFS/RFS)1 tHOFSI tDDTI Transmit Data Delay After TSCLK1 tHDTI Transmit Data Hold After TSCLK1 tSCLKIW TSCLK/RSCLK Width 1 Referenced to drive edge. Rev. PrD | Page 33 of 64 | January 2005 Minimum Maximum Unit 3.0 ns ns ns ns ns -1.0 3.0 -2.0 4.5 ADSP-BF536/ADSP-BF537 Preliminary Technical Data Table 27. Serial Ports--Enable and Three-State Parameter Switching Characteristics tDTENE Data Enable Delay from External TSCLK1 Data Disable Delay from External TSCLK1 tDDTTE tDTENI Data Enable Delay from Internal TSCLK1 tDDTTI Data Disable Delay from Internal TSCLK1 1 Minimum Maximum 0.0 Unit 3.0 ns ns ns ns Maximum Unit 10.0 ns ns 10.0 -2.0 Referenced to drive edge. Table 28. External Late Frame Sync Parameter Switching Characteristics Data Delay from Late External TFS or External RFS with MCE = 1, MFD = 01,2 tDDTLFSE tDTENLFSE Data Enable from late FS or MCE = 1, MFD = 01,2 1 MCE = 1, TFS enable and TFS valid follow tDDTENFS and tDDTLFSE. 2 If external RFS/TFS setup to RSCLK/TSCLK > tSCLKE/2 then tDDTLSCK and tDTENLSCK apply, otherwise tDDTLFSE and tDTENLFS apply. Rev. PrD | Page 34 of 64 | January 2005 Minimum 0.0 Preliminary Technical Data ADSP-BF536/ADSP-BF537 DATA RECEIVE- INTERNAL CLOCK DATA RECEIVE- EXTERNAL CLOCK DRIVE EDGE SAMPLE EDGE DRIVE EDGE SAMPLE EDGE tSCLKIW tSCLKEW RSCLK RSCLK tDFSE tDFSE tHOFSE tSFSI tHFSI tHOFSE RFS tSFSE tHFSE tSDRE tHDRE RFS tSDRI tHDRI DR DR NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK, TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE. DATA TRANSMIT- INTERNAL CLOCK DATA TRANSMIT- EXTERNAL CLOCK DRIVE EDGE SAMPLE EDGE DRIVE EDGE SAMPLE EDGE tSCLKIW tSCLKEW TSCLK TSCLK tDFSI tHOFSI tDFSE tSFSI tHFSI tHOFSE TFS tSFSE TFS tDDTI tDDTE tHDTI tHDTE DT DT NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK OR TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE. DRIVE EDGE DRIVE EDGE TSCLK (EXT) TFS ("LATE", EXT.) TSCLK / RSCLK tDDTTE tDDTENE DT DRIVE EDGE DRIVE EDGE TSCLK (INT) TFS ("LATE", INT.) TSCLK / RSCLK tDDTENI tDDTTI DT Figure 17. Serial Ports Rev. PrD | Page 35 of 64 | January 2005 tHFSE ADSP-BF536/ADSP-BF537 Preliminary Technical Data EXTERNAL RFS WITH MCE = 1, MFD = 0 DRIVE SAMPLE DRIVE RSCLK tHOFSE/I tSFSE/I RFS tDDTE/I tDTENLFSE tHDTE/I 1ST BIT DT 2ND BIT tDDTLFSE LATE EXTERNAL TFS DRIVE SAMPLE DRIVE TSCLK tSFSE/I tHOFSE/I TFS tDDTE/I tDTENLFSE DT tHDTE/I 1ST BIT 2ND BIT tDDTLFSE Figure 18. External Late Frame Sync (Frame Sync Setup < tSCLKE/2) Rev. PrD | Page 36 of 64 | January 2005 Preliminary Technical Data ADSP-BF536/ADSP-BF537 EXTERNAL RFS WITH MCE=1, MFD=0 DRIVE SAMPLE DRIVE RSCLK tSFSE/I tHOFSE/I RFS tDDTE/I tHDTE/I tDTENLSCK DT 1ST BIT 2ND BIT tDDTLSCK LATE EXTERNAL TFS DRIVE SAMPLE DRIVE TSCLK tSFSE/I tHOFSE/I TFS tDDTE/I tDTENLSCK DT tHDTE/I 1ST BIT 2ND BIT tDDTLSCK Figure 19. External Late Frame Sync (Frame Sync Setup > tSCLKE/2) Rev. PrD | Page 37 of 64 | January 2005 ADSP-BF536/ADSP-BF537 Preliminary Technical Data Serial Peripheral Interface (SPI) Port--Master Timing Table 29 and Figure 20 describe SPI port master operations. Table 29. Serial Peripheral Interface (SPI) Port--Master Timing Parameter Timing Requirements tSSPIDM Data input valid to SCK edge (data input setup) tHSPIDM SCK sampling edge to data input invalid Switching Characteristics tSDSCIM SPISELx low to first SCK edge (x=0 or 1) tSPICHM Serial clock high period tSPICLM Serial clock low period tSPICLK Serial clock period tHDSM Last SCK edge to SPISELx high (x=0 or 1) Sequential transfer delay tSPITDM tDDSPIDM SCK edge to data out valid (data out delay) tHDSPIDM SCK edge to data out invalid (data out hold) Minimum tSPICHM tSPICLM tSPICLM tSPICHM tSPICLK tHDSM SCK (CPOL = 0) (OUTPUT) SCK (CPOL = 1) (OUTPUT) tDDSPIDM MOSI (OUTPUT) tHDSPIDM MSB CPHA=1 tSSPIDM MISO (INPUT) LSB tHSPIDM tSSPIDM MSB VALID LSB VALID tDDSPIDM MOSI (OUTPUT) CPHA=0 MISO (INPUT) tHSPIDM tHDSPIDM MSB tSSPIDM LSB tHSPIDM MSB VALID LSB VALID Figure 20. Serial Peripheral Interface (SPI) Port--Master Timing Rev. PrD | Page 38 of 64 | January 2005 Unit 7.5 -1.5 ns ns 2tSCLK -1.5 2tSCLK -1.5 2tSCLK -1.5 4tSCLK -1.5 2tSCLK -1.5 2tSCLK -1.5 0 -1.0 ns ns ns ns ns ns ns ns SPISELx (OUTPUT) tSDSCIM Maximum tSPITDM 6 4.0 Preliminary Technical Data ADSP-BF536/ADSP-BF537 Serial Peripheral Interface (SPI) Port--Slave Timing Table 30 and Figure 21 describe SPI port slave operations. Table 30. Serial Peripheral Interface (SPI) Port--Slave Timing Parameter Timing Requirements tSPICHS Serial clock high period tSPICLS Serial clock low period Serial clock period tSPICLK tHDS Last SCK edge to SPISS not asserted tSPITDS Sequential Transfer Delay tSDSCI SPISS assertion to first SCK edge tSSPID Data input valid to SCK edge (data input setup) tHSPID SCK sampling edge to data input invalid Switching Characteristics tDSOE SPISS assertion to data out active tDSDHI SPISS deassertion to data high impedance tDDSPID SCK edge to data out valid (data out delay) tHDSPID SCK edge to data out invalid (data out hold) Minimum 2tSCLK -1.5 2tSCLK -1.5 4tSCLK -1.5 2tSCLK -1.5 2tSCLK -1.5 2tSCLK -1.5 1.6 1.6 0 0 0 0 tSPICLS tSPICLS tSPICHS tSPICLK tHDS tSPITDS SCK (CPOL = 0) (INPUT) tSDSCI SCK (CPOL = 1) (INPUT) tDSOE tDDSPID tHDSPID MISO (OUTPUT) tSSPID MOSI (INPUT) LSB tHSPID tSSPID tHSPID MSB VALID tDSOE LSB VALID tDDSPID tDSDHI MSB LSB tHSPID CPHA=0 MOSI (INPUT) tDSDHI MSB CPHA=1 MISO (OUTPUT) tDDSPID tSSPID MSB VALID LSB VALID Figure 21. Serial Peripheral Interface (SPI) Port--Slave Timing Rev. PrD | Page 39 of 64 | January 2005 Unit ns ns ns ns ns ns ns ns 8 8 10 10 SPISS (INPUT) tSPICHS Maximum ns ns ns ns ADSP-BF536/ADSP-BF537 Preliminary Technical Data Universal Asynchronous Receiver-Transmitter (UART) Ports--Receive and Transmit Timing Figure 22 describes the UART ports receive and transmit operations. The maximum baud rate is SCLK/16. As shown in Figure 22, there is some latency between the generation of internal UART interrupts and the external data operations. These latencies are negligible at the data transmission rates for the UART. CLKOUT (SAMPLE CLOCK) UARTX RX DATA(5-8) STOP RECEIVE INTERNAL UART RECEIVE INTERRUPT UART RECEIVE BIT SET BY DATA STOP; CLEARED BY FIFO READ START UARTX TX DATA(5-8) STOP (1-2) TRANSMIT INTERNAL UART TRANSMIT INTERRUPT UART TRANSMIT BIT SET BY PROGRAM; CLEARED BY WRITE TO TRANSMIT Figure 22. UART Ports--Receive and Transmit Timing Rev. PrD | Page 40 of 64 | January 2005 Preliminary Technical Data ADSP-BF536/ADSP-BF537 General-Purpose Port Timing Table 31 and Figure 23 describe general-purpose port operations. Table 31. General-Purpose Port Timing Parameter Timing Requirement tWFI General-purpose port pin input pulsewidth tGPPIS General-purpose port pin input setup tGPPIH General-purpose port pin input hold Switching Characteristic General-purpose port pin output delay from CLKOUT low tGPOD Minimum tSCLK + 1 TBD TBD 0 CLKOUT tGPOD GPP OUTPUT tGPPIS tGPPIH GPP INPUT tWFI Figure 23. General-Purpose Port Timing Rev. PrD | Page 41 of 64 | Maximum January 2005 Unit ns ns ns 6 ns ADSP-BF536/ADSP-BF537 Preliminary Technical Data Timer Cycle Timing Table 32 and Figure 24 describe timer expired operations. The input signal is asynchronous in "width capture mode" and "external clock mode" and has an absolute maximum input frequency of fSCLK/2 MHz. Table 32. Timer Cycle Timing Parameter Timing Characteristics tWL Timer pulsewidth input low1 (measured in SCLK cycles) tWH Timer pulsewidth input high1 (measured in SCLK cycles) Timer input setup time before CLKOUT low tTIS tTIH Timer input hold time after CLKOUT low Switching Characteristic tHTO Timer pulsewidth output2 (measured in SCLK cycles) tTOD Timer output update delay after CLKOUT low 1 2 Minimum Maximum 1 1 TBD TBD 1 0 Unit SCLK SCLK ns ns (232-1) TBD SCLK ns The minimum pulsewidths apply for TMRx signals in width capture and external clock modes. They also apply to the PF15 or PPI_CLK signals in PWM output mode. The minimum time for tHTO is one cycle, and the maximum time for tHTO equals (232-1) cycles. CLKOUT tTOD TIMER OUTPUT tTIS tTIH TIMER INPUT Figure 24. Timer Cycle Timing Rev. PrD | Page 42 of 64 | January 2005 Preliminary Technical Data ADSP-BF536/ADSP-BF537 JTAG Test And Emulation Port Timing Table 33 and Figure 25 describe JTAG port operations. Table 33. JTAG Port Timing Parameter Timing Parameters tTCK TCK Period tSTAP TDI, TMS Setup Before TCK High TDI, TMS Hold After TCK High tHTAP tSSYS System Inputs Setup Before TCK High1 tHSYS System Inputs Hold After TCK High1 tTRSTW TRST Pulsewidth2 (measured in TCK cycles) Switching Characteristics tDTDO TDO Delay from TCK Low System Outputs Delay After TCK Low3 tDSYS Minimum Maximum 20 4 4 4 5 4 0 1 Unit ns ns ns ns ns TCK 10 12 ns ns System Inputs=DATA15-0, BR, ARDY, SCL, SDA, TFS0, TSCLK0, RSCLK0, RFS0, DR0PRI, DR0SEC, PF15-0, PG15-0, PH15-0, MDIO, RTXI, TCK, TD1, TMS, TRST, CLKIN, RESET, NMI, BMODE2-0. 2 50 MHz Maximum 3 System Outputs=DATA15-0, ADDR19-1, ABE1-0, AOE, ARE, AWE, AMS3-0, SRAS, SCAS, SWE, SCKE, CLKOUT, SA10, SMS, SCL, SDA, TSCLK0, TFS0, RFS0, RSCLK0, DT0PRI, DT0SEC, PF15-0, PG15-0, PH15-0, MDC, MDIO, RTX0, TD0, EMU, XTAL, CLKBUF, VROUT. tTCK TCK tSTAP tHTAP TMS TDI tDTDO TDO tSSYS tHSYS SYSTEM INPUTS tDSYS SYSTEM OUTPUTS Figure 25. JTAG Port Timing Rev. PrD | Page 43 of 64 | January 2005 ADSP-BF536/ADSP-BF537 Preliminary Technical Data TWI Controller Timing Table 34 through Table 41 and Figure 26 through Figure 29 describe the TWI Controller operations. Table 34. TWI Controller Timing: Bus Start/Stop Bits, Slave Mode, 100 kHz Parameter tSU:STA tHD:STA tSU:STO tHD:STO Start condition setup time Start condition hold time Stop condition setup time Stop condition hold time Minimum TBD TBD TBD TBD Maximum - Unit ns ns ns ns Minimum TBD TBD TBD TBD Maximum - Unit ns ns ns ns Minimum TBD TBD TBD TBD TBD TBD TBD TBD - Maximum TBD TBD TBD TBD Unit s s ns ns s s ns ns s ns s pF Table 35. TWI Controller Timing: Bus Start/Stop Bits, Slave Mode, 400 kHz Parameter tSU:STA tHD:STA tSU:STO tHD:STO Start condition setup time Start condition hold time Stop condition setup time Stop condition hold time Table 36. TWI Controller Timing: Bus Data Requirements, Slave Mode, 100 kHz Parameter tHIGH tLOW tR tF tSU:STA tHD:STA tHD:DAT tSU:DAT tSU:STO tTAA tBUF CB Clock high time Clock low time SDA and SCL rise time SDA and SCL fall time Start condition setup time Start condition hold time Data input hold time Data input setup time1 Stop condition setup time Output valid from clock2 Bus free time Bus capacitive loading 1 As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. TBD ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions. 2 A Fast mode TWI bus device can be used in a Standard mode TWI bus system, but the requirement TSU:DAT >= 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line. Before the SCL line is released, TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification). Rev. PrD | Page 44 of 64 | January 2005 Preliminary Technical Data ADSP-BF536/ADSP-BF537 Table 37. TWI Controller Timing: Bus Data Requirements, Slave Mode, 400 kHz Parameter tHIGH tLOW tR tF tSU:STA tHD:STA tHD:DAT tSU:DAT tSU:STO tTAA tBUF CB 1 Minimum TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD - Clock high time Clock low time SDA and SCL rise time SDA and SCL fall time Start condition setup time Start condition hold time Data input hold time Data input setup time1 Stop condition setup time Output valid from clock Bus free time Bus capacitive loading Maximum TBD TBD TBD TBD Unit s s ns ns s s s ns s ns s pF As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. TBD ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions. Table 38. TWI Controller Timing: Bus Start/Stop Bits, Master Mode, 100 kHz Parameter tSU:STA tHD:STA tSU:STO tHD:STO Start condition setup time Start condition hold time Stop condition setup time Stop condition hold time Minimum TBD TBD TBD TBD Maximum - Unit ns ns ns ns Minimum TBD TBD TBD TBD Maximum - Unit ns ns ns ns Minimum TBD TBD TBD TBD TBD TBD TBD TBD - Maximum TBD TBD TBD TBD Unit ms ms ns ns ms ms ns ns ms ns ms pF Table 39. TWI Controller Timing: Bus Start/Stop Bits, Master Mode, 400 kHz Parameter tSU:STA tHD:STA tSU:STO tHD:STO Start condition setup time Start condition hold time Stop condition setup time Stop condition hold time Table 40. TWI Controller Timing: Bus Data Requirements, Master Mode, 100 kHz Parameter tHIGH tLOW tR tF tSU:STA tHD:STA tHD:DAT tSU:DAT tSU:STO tTAA tBUF CB 1 Clock high time Clock low time SDA and SCL rise time SDA and SCL fall time Start condition setup time Start condition hold time Data input hold time Data input setup time1 Stop condition setup time Output valid from clock Bus free time Bus capacitive loading A Fast mode TWI bus device can be used in a Standard mode TWI bus system, but the requirement TSU:DAT >= 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line. Before the SCL line is released, TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification). Rev. PrD | Page 45 of 64 | January 2005 ADSP-BF536/ADSP-BF537 Preliminary Technical Data Table 41. TWI Controller Timing: Bus Data Requirements, Master Mode, 400 kHz Parameter tHIGH tLOW tR tF tSU:STA tHD:STA tHD:DAT tSU:DAT tSU:STO tTAA tBUF CB 1 Minimum TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD - Clock high time Clock low time SDA and SCL rise time SDA and SCL fall time Start condition setup time Start condition hold time Data input hold time Data input setup time1 Stop condition setup time Output valid from clock Bus free time Bus capacitive loading Maximum TBD TBD TBD TBD Unit ms ms ns ns ms ms ns ns ms ns ms pF A Fast mode TWI bus device can be used in a Standard mode TWI bus system, but the requirement TSU:DAT >= 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line. Before the SCL line is released, TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification). SCL tHD:STA tHD:STO tSU:STA tSU:STO SDA STOP START Figure 26. TWI Controller Timing: Bus Start/Stop Bits, Slave Mode tF tH IGH tR tLO W SCL tSU :S TA tH D :STA tH D :D A T tS U :D AT tS U :STO SDA (IN) tA A tA A tB UF SDA (OUT) Figure 27. TWI Controller Timing: Bus Data, Slave Mode Rev. PrD | Page 46 of 64 | January 2005 Preliminary Technical Data ADSP-BF536/ADSP-BF537 SCL tHD:STA tHD:STO tSU:STA tSU:STO SDA STOP START Figure 28. TWI Controller Timing: Bus Start/Stop Bits, Master Mode tF tH IGH tR tLO W SCL tSU :S TA tH D :STA tH D :D A T tS U :D AT tS U :STO SDA (IN) tA A tA A tB UF SDA (OUT) Figure 29. TWI Controller Timing: Bus Data, Master Mode Rev. PrD | Page 47 of 64 | January 2005 ADSP-BF536/ADSP-BF537 Preliminary Technical Data 10/100 Ethernet MAC Controller Timing Table 42 through Table 47 and Figure 30 through Figure 35 describe the 10/100 Ethernet MAC Controller operations. Table 42. 10/100 Ethernet MAC Controller Timing: MII Receive Signal 1 Parameter 1 tERXCLKF ERxCLK frequency (fsclk = SCLK frequency) Minimum None tERXCLKW tERXCLKIS tERXCLKIH ERxCLK width (tERxCLK = ERxCLK period) Rx input valid to ERxCLK rising edge (data in setup) ERxCLK rising edge to Rx input invalid (data in hold) tERxCLK x 35% 7.5 7.5 Maximum 25 MHz + 1% fSCLK + 1% tERxCLK x 65% - Unit ns ns ns ns MII inputs synchronous to ERxCLK are ERxD3-0, ERxDV, and ERxER. Table 43. 10/100 Ethernet MAC Controller Timing: MII Transmit Signal 1 Parameter 1 tETF ETxCLK frequency (fsclk = SCLK frequency) Minimum None tETXCLKW tETXCLKOV tETXCLKOH ETxCLK width (tETxCLK = ETxCLK period) ETxCLK rising edge to Tx output valid (data out valid) ETxCLK rising edge to Tx output invalid (data out hold) tETxCLK x 35% 0 Maximum 25 MHz + 1% fSCLK + 1% tETxCLK x 65% 20 - Unit ns ns ns ns MII outputs synchronous to ETxCLK are ETxD3-0. Table 44. 10/100 Ethernet MAC Controller Timing: RMII Receive Signal 1 Parameter 1 tEREFCLKF REF_CLK frequency (fsclk = SCLK frequency) tEREFCLKW tEREFCLKIS tEREFCLKIH EREF_CLK width (tEREFCLK = EREFCLK period) Rx input valid to RMII REF_CLK rising edge (data in setup) RMII REF_CLK rising edge to Rx input invalid (data in hold) Minimum None Maximum 50 MHz + 1% 2 x fSCLK + 1% tEREFCLK x 35% tEREFCLK x 65% 4 2 - Unit ns ns ns ns Minimum 2 Maximum 4 - Unit ns ns Minimum tETxCLK x 1.5 tERxCLK x 1.5 tETxCLK x 1.5 tERxCLK x 1.5 tETxCLK x 1.5 tETxCLK x 1.5 Maximum - Unit ns - ns - ns ns RMII inputs synchronous to RMII REF_CLK are ERxD1-0, RMII CRS_DV, and ERxER. Table 45. 10/100 Ethernet MAC Controller Timing: RMII Transmit Signal Parameter 1 tEREFCLKOV tEREFCLKOH 1 RMII REF_CLK rising edge to Tx output valid (data out valid) RMII REF_CLK rising edge to Tx output invalid (data out hold) RMII outputs synchronous to RMII REF_CLK are ETxD1-0. Table 46. 10/100 Ethernet MAC Controller Timing: MII/RMII Asynchronous Signal Parameter 1, 2 tECOLH COL pulse width high tECOLL COL pulse width low tECRSH tECRSL CRS pulse width high CRS pulse width low 1 MII/RMII asynchronous signals are COL, CRS. These signals are applicable in both MII and RMII modes. The asynchronous COL input is synchronized separately to both the ETxCLK and the ERxCLK, and must have a minimum pulse width high or low at least 1.5 times the period of the slower of the two clocks. 2 The asynchronous CRS input is synchronized to the ETxCLK, and must have a minimum pulse width high or low at least 1.5 times the period of ETxCLK. Rev. PrD | Page 48 of 64 | January 2005 Preliminary Technical Data ADSP-BF536/ADSP-BF537 Table 47. 10/100 Ethernet MAC Controller Timing: MII Station Management Parameter 1 tMDIOS tMDCIH tMDCOV tMDCOH 1 Minimum 10 10 25 0 MDIO input valid to MDC rising edge (setup) MDC rising edge to MDIO input invalid (hold) MDC falling edge to MDIO output valid MDC falling edge to MDIO output invalid (hold) Maximum - Unit ns ns ns ns MDC/MDIO is a 2-wire serial bidirectional port for controlling one or more external PHYs. MDC is an output clock whose minimum period is programmable as a multiple of the system clock SCLK. MDIO is a bidirectional data line. tERXCLK ERxCLK tERXCLKW ERxD3-0 ERxDV ERxER tERXCLKIS tERXCLKIH Figure 30. 10/100 Ethernet MAC Controller Timing: MII Receive Signal tETXCLK MII TxCLK tETXCLKW tETXCLKOH ETxD3-0 ETxEN tETXCLKOV Figure 31. 10/100 Ethernet MAC Controller Timing: MII Transmit Signal tREFCLK ERxCLK tREFCLKW ERxD1-0 ERxDV ERxER tERXCLKIS tERXCLKIH Figure 32. 10/100 Ethernet MAC Controller Timing: RMII Receive Signal Rev. PrD | Page 49 of 64 | January 2005 ADSP-BF536/ADSP-BF537 Preliminary Technical Data tREFCLK RMII REF_CLK tEREFCLKOH ETxD1-0 ETxEN tEREFCLKOV Figure 33. 10/100 Ethernet MAC Controller Timing: RMII Transmit Signal MII CRS, COL tECRSH tECOLH tECRSL tECOLL Figure 34. 10/100 Ethernet MAC Controller Timing: Asynchronous Signal MDC (OUTPUT) tMDCOH MDIO (OUTPUT) tMDCOV MDIO (INPUT) tMDIOS tMDCIH Figure 35. 10/100 Ethernet MAC Controller Timing: MII Station Management Rev. PrD | Page 50 of 64 | January 2005 Preliminary Technical Data ADSP-BF536/ADSP-BF537 OUTPUT DRIVE CURRENTS 150 SOURCE CURRENT (mA) 100 150 100 SOURCE CURRENT (mA) Figure 36 through Figure 45 show typical current-voltage characteristics for the output drivers of the ADSP-BF536/BF537 processor. The curves represent the current drive capability of the output drivers as a function of output voltage. See Table 9 on page 18 for information about which driver type corresponds to a particular pin. 50 TBD 0 -50 -100 50 TBD 0 -50 -150 0 0.5 1.0 1.5 2.0 2.5 3.0 2.5 3.0 SOURCE VOLTAGE (V) Figure 38. Drive Current B (Low VDDEXT) -100 -150 0 0.5 1.0 1.5 2.0 2.5 150 3.0 SOURCE VOLTAGE (V) 100 SOURCE CURRENT (mA) Figure 36. Drive Current A (Low VDDEXT) 150 SOURCE CURRENT (mA) 100 50 TBD 0 -50 -100 50 TBD 0 -50 -150 0 0 0.5 1.0 1.5 1.0 1.5 2.0 SOURCE VOLTAGE (V) Figure 39. Drive Current B (High VDDEXT) -100 -150 0.5 2.0 2.5 3.0 SOURCE VOLTAGE (V) Figure 37. Drive Current A (High VDDEXT) Rev. PrD | Page 51 of 64 | January 2005 Preliminary Technical Data 150 150 100 100 50 SOURCE CURRENT (mA) SOURCE CURRENT (mA) ADSP-BF536/ADSP-BF537 TBD 0 -50 -100 -50 0 0.5 1.0 1.5 2.0 2.5 3.0 -150 0 0.5 1.0 1.5 2.0 SOURCE VOLTAGE (V) SOURCE VOLTAGE (V) Figure 40. Drive Current C (Low VDDEXT) Figure 42. Drive Current D (Low VDDEXT) 150 150 100 100 50 TBD 0 -50 -100 -150 TBD 0 -100 SOURCE CURRENT (mA) SOURCE CURRENT (mA) -150 50 50 2.5 3.0 2.5 3.0 TBD 0 -50 -100 0 0.5 1.0 1.5 2.0 2.5 3.0 -150 0 0.5 1.0 1.5 2.0 SOURCE VOLTAGE (V) SOURCE VOLTAGE (V) Figure 41. Drive Current C (High VDDEXT) Figure 43. Drive Current D (High VDDEXT) Rev. PrD | Page 52 of 64 | January 2005 Preliminary Technical Data ADSP-BF536/ADSP-BF537 150 SOURCE CURRENT (mA) 100 50 TBD 0 -50 -100 -150 0 0.5 1.0 1.5 2.0 2.5 3.0 2.5 3.0 SOURCE VOLTAGE (V) Figure 44. Drive Current E (Low VDDEXT) 150 SOURCE CURRENT (mA) 100 50 TBD 0 -50 -100 -150 0 0.5 1.0 1.5 2.0 SOURCE VOLTAGE (V) Figure 45. Drive Current E (High VDDEXT) Rev. PrD | Page 53 of 64 | January 2005 ADSP-BF536/ADSP-BF537 Preliminary Technical Data POWER DISSIPATION Total power dissipation has two components: one due to internal circuitry (PINT) and one due to the switching of external output drivers (PEXT). Table 48 shows the power dissipation for internal circuitry (VDDINT). Internal power dissipation is dependent on the instruction execution sequence and the data operands involved. The external component of total power dissipation is caused by the switching of output pins. Its magnitude depends on: * Maximum frequency (f0) at which all output pins can switch during each cycle * Load capacitance (C0) of all switching output pins * Their voltage swing (VDDEXT) The external component is calculated using: IDDTYP2 IDDEFR3 IDDSLEEP45 IDDDEEPSLEEP4 IDDHIBERNATE5 Parameter IDDTYP2 IDDEFR3 IDDSLEEP45 IDDDEEPSLEEP4 IDDHIBERNATE5 Parameter IDDTYP2 IDDEFR3 IDDSLEEP45 IDDDEEPSLEEP4 IDDHIBERNATE5 fCCLK = 250 MHz VDDINT = 1.0 V TBD TBD TBD TBD 50 fCCLK = 400 MHz VDDINT = 1.0 V TBD TBD TBD TBD 50 - - - P TOTAL = P EXT + ( I DD x V DDINT ) Note that the conditions causing a worst-case PEXT differ from those causing a worst-case PINT . Maximum PINT cannot occur while 100% of the output pins are switching from all ones (1s) to all zeros (0s). Note, as well, that it is not common for an application to have 100% or even 50% of the outputs switching simultaneously. All timing parameters appearing in this data sheet were measured under the conditions described in this section. Output Enable Time Table 48. Internal Power Dissipation Parameter A typical power consumption can now be calculated for these conditions by adding a typical internal power dissipation: TEST CONDITIONS 2 P EXT = V DDEXT x C 0 f 0 Test Conditions1 fCCLK = fCCLK = 50 MHz 150 MHz VDDINT = VDDINT = 0.8 V 0.9 V TBD TBD TBD TBD TBD TBD TBD TBD 50 50 fCCLK = 200 MHz VDDINT = 0.9 V TBD TBD TBD TBD 50 The frequency f includes driving the load high and then back low. For example: DATA15-0 pins can drive high and low at a maximum rate of 1/(2 tSCLK) while in SDRAM burst mode. fCCLK = 400 MHz VDDINT = 1.2 V TBD TBD TBD TBD 50 fCCLK = 500 MHz VDDINT = 1.2 V TBD TBD TBD TBD 50 fCCLK = 600 MHz VDDINT = 1.2 V TBD TBD TBD TBD 50 Unit mA mA mA mA A Unit Output pins are considered to be enabled when they have made a transition from a high impedance state to the point when they start driving. The output enable time tENA is the interval from the point when a reference signal reaches a high or low voltage level to the point when the output starts driving as shown in the Output Enable/Disable diagram (Figure 46). The time tENA_MEASURED is the interval from when the reference signal switches to when the output voltage reaches 2.0 V (output high) or 1.0 V (output low). Time tTRIP is the interval from when the output starts driving to when the output reaches the 1.0 V or 2.0 V trip voltage. Time tENA is calculated as shown in the equation: t ENA = t ENA_MEASURED - t TRIP mA mA mA mA A Unit mA mA mA mA A 1 IDD data is specified for typical process parameters. All data at 25C. Processor executing 75% dual Mac, 25% ADD with moderate data bus activity. 3 Implementation of Enhanced Full Rate (EFR) GSM algorithm. 4 See the ADSP-BF536/BF537 Blackfin Processor Hardware Reference Manual for definitions of Sleep and Deep Sleep operating modes. 5 IDDHIBERNATE is measured @ VDDEXT = 3.65 V with VR off (VDDCORE = 0 V). 2 Rev. PrD | If multiple pins (such as the data bus) are enabled, the measurement value is that of the first pin to start driving. Output Disable Time Output pins are considered to be disabled when they stop driving, go into a high impedance state, and start to decay from their output high or low voltage. The time for the voltage on the bus to decay by V is dependent on the capacitive load, CL and the load current, IL. This decay time can be approximated by the equation: t DECAY = ( C L V ) I L The output disable time tDIS is the difference between tDIS_MEASURED and tDECAY as shown in Figure 46. The time tDIS_MEASURED is the interval from when the reference signal switches to when the output voltage decays V from the measured output high or output low voltage. The time tDECAY is calculated with test loads CL and IL, and with V equal to 0.5 V. Page 54 of 64 | January 2005 Preliminary Technical Data ADSP-BF536/ADSP-BF537 requiring the hold time. A typical V will be 0.4 V. CL is the total bus capacitance (per data line), and IL is the total leakage or three-state current (per data line). The hold time will be tDECAY plus the minimum disable time (for example, tDSDAT for an SDRAM write cycle). REFERENCE SIGNAL tDIS_MEASURED tDIS tENA-MEASURED tENA VOH (MEASURED) VOL (MEASURED) VOH (MEASURED) V VOH 2.0V (MEASURED) VOL (MEASURED) + V 1.0V tDECAY OUTPUT STOPS DRIVING 50 TO OUTPUT PIN VOL (MEASURED) 1.5V tTRIP 30pF OUTPUT STARTS DRIVING Figure 47. Equivalent Device Loading for AC Measurements (Includes All Fixtures) HIGH IMPEDANCE STATE. TEST CONDITIONS CAUSE THIS VOLTAGE TO BE APPROXIMATELY 1.5V. Figure 46. Output Enable/Disable INPUT OR OUTPUT Example System Hold Time Calculation To determine the data output hold time in a particular system, first calculate tDECAY using the equation given above. Choose V to be the difference between the ADSP-BF536/BF537 processor's output voltage and the input threshold for the device 1.5V 1.5V Figure 48. Voltage Reference Levels for AC Measurements (Except Output Enable/Disable) ENVIRONMENTAL CONDITIONS In Table 49, airflow measurements comply with JEDEC standards JESD51-2 and JESD51-6, and the junction-to-board measurement complies with JESD51-8. The junction-to-case measurement complies with MIL-STD-883 (Method 1012.1). All measurements use a 2S2P JEDEC test board. To determine the junction temperature on the application printed circuit board use: T J = T CASE + ( JT x P D ) where: Table 49. Thermal Characteristics TJ = Junction temperature (C) TCASE = Case temperature (C) measured by customer at top center of package. JT = From Table 49 PD = Power dissipation (see Power Dissipation on page 54 for the method to calculate PD) Values of JA are provided for package comparison and printed circuit board design considerations. JA can be used for a first order approximation of TJ by the equation: Parameter JA JMA JMA JB JC JT T J = T A + ( JA x P D ) where: TA = Ambient temperature (C) Values of JC are provided for package comparison and printed circuit board design considerations when an external heatsink is required. Values of JB are provided for package comparison and printed circuit board design considerations. Rev. PrD | Page 55 of 64 | January 2005 Condition 0 linear m/s air flow 1 linear m/s air flow 2 linear m/s air flow 0 linear m/s air flow Typical Unit C/W C/W C/W C/W C/W C/W ADSP-BF536/ADSP-BF537 Preliminary Technical Data 182-BALL MINI-BGA PINOUT Table 50 lists the mini-BGA pinout by signal mnemonic. Table 51 on page 57 lists the mini-BGA pinout by ball number. Table 50. 182-Ball Mini-BGA Ball Assignment (Alphabetically by Signal Mnemonic) Mnemonic ABE0 ABE1 ADDR1 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15 ADDR16 ADDR17 ADDR18 ADDR19 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 ADDR8 ADDR9 AMS0 AMS1 AMS2 AMS3 AOE ARDY ARE AWE BG BGH BMODE0 BMODE1 BMODE2 BR CLKBUF CLKIN Ball no. H13 H12 J14 M13 M14 N14 N13 N12 M11 N11 P13 P12 P11 K14 L14 J13 K13 L13 K12 L12 M12 E14 F14 F13 G12 G13 E13 G14 H14 P10 N10 N4 P3 L5 D14 A7 A12 Mnemonic CLKOUT DATA0 DATA1 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 DATA8 DATA9 EMU GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Ball no. B14 M9 N9 N6 P6 M5 N5 P5 P4 P9 M8 N8 P8 M7 N7 P7 M6 M2 A10 A14 D4 E7 E9 F5 F6 F10 F11 G4 G5 G11 H11 J4 J5 J9 J10 K6 K11 Mnemonic GND GND GND GND GND GND NMI PF0 PF1 PF10 PF11 PF12 PF13 PF14 PF15 PF2 PF3 PF4 PF5 PF6 PF7 PF8 PF9 PG0 PG1 PG10 PG11 PG12 PG13 PG14 PG15 PG2 PG3 PG4 PG5 PG6 PG7 Rev. PrD | Ball no. L6 L8 L10 M4 M10 P14 B10 M1 L1 J2 J3 H1 H2 H3 H4 L2 L3 L4 K1 K2 K3 K4 J1 G1 G2 D1 D2 D3 D5 D6 C1 G3 F1 F2 F3 E1 E2 Page 56 of 64 | Mnemonic PG8 PG9 PH0 PH1 PH10 PH11 PH12 PH13 PH14 PH15 PH2 PH3 PH4 PH5 PH6 PH7 PH8 PH9 PJ0 PJ1 PJ10 PJ11 PJ2 PJ3 PJ4 PJ5 PJ6 PJ7 PJ8 PJ9 RESET RTXO RTXI SA10 SCAS SCKE SMS January 2005 Ball no. E3 E4 C2 C3 B6 A2 A3 A4 A5 A6 C4 C5 C6 B1 B2 B3 B4 B5 C7 B7 D10 D11 B11 C11 D7 D8 C8 B8 D9 C9 C10 A8 A9 E12 C14 B13 C13 Mnemonic SRAS SWE TCK TDI TDO TMS TRST VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDRTC VROUT0 VROUT1 XTAL Ball no. D13 D12 P2 M3 N3 N2 N1 A1 C12 E6 E11 F4 F12 H5 H10 J11 J12 K7 K9 L7 L9 L11 P1 E5 E8 E10 G10 K5 K8 K10 B9 A13 B12 A11 Preliminary Technical Data ADSP-BF536/ADSP-BF537 Table 51 lists the mini-BGA pinout by ball number. Table 50 on page 56 lists the mini-BGA pinout by signal mnemonic. Table 51. 182-Ball Mini-BGA Ball Assignment (Numerically by Ball Number) Ball no. A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 C1 C2 C3 C4 C5 C6 C7 C8 C9 Mnemonic VDDEXT PH11 PH12 PH13 PH14 PH15 CLKBUF RTXO RTXI GND XTAL CLKIN VROUT0 GND PH5 PH6 PH7 PH8 PH9 PH10 PJ1 PJ7 VDDRTC NMI PJ2 VROUT1 SCKE CLKOUT PG15 PH0 PH1 PH2 PH3 PH4 PJ0 PJ6 PJ9 Ball no. C10 C11 C12 C13 C14 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 F1 F2 F3 F4 Mnemonic RESET PJ3 VDDEXT SMS SCAS PG10 PG11 PG12 GND PG13 PG14 PJ4 PJ5 PJ8 PJ10 PJ11 SWE SRAS BR PG6 PG7 PG8 PG9 VDDINT VDDEXT GND VDDINT GND VDDINT VDDEXT SA10 ARDY AMS0 PG3 PG4 PG5 VDDEXT Ball no. F5 F6 F10 F11 F12 F13 F14 G1 G2 G3 G4 G5 G10 G11 G12 G13 G14 H1 H2 H3 H4 H5 H10 H11 H12 H13 H14 J1 J2 J3 J4 J5 J9 J10 J11 J12 J13 Rev. PrD | Mnemonic GND GND GND GND VDDEXT AMS2 AMS1 PG0 PG1 PG2 GND GND VDDINT GND AMS3 AOE ARE PF12 PF13 PF14 PF15 VDDEXT VDDEXT GND ABE1 ABE0 AWE PF9 PF10 PF11 GND GND GND GND VDDEXT VDDEXT ADDR4 Page 57 of 64 | Ball no. J14 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 M1 M2 M3 M4 M5 M6 M7 M8 January 2005 Mnemonic ADDR1 PF5 PF6 PF7 PF8 VDDINT GND VDDEXT VDDINT VDDEXT VDDINT GND ADDR7 ADDR5 ADDR2 PF1 PF2 PF3 PF4 BMODE2 GND VDDEXT GND VDDEXT GND VDDEXT ADDR8 ADDR6 ADDR3 PF0 EMU TDI GND DATA12 DATA9 DATA6 DATA3 Ball no. M9 M10 M11 M12 M13 M14 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 Mnemonic DATA0 GND ADDR15 ADDR9 ADDR10 ADDR11 TRST TMS TDO BMODE0 DATA13 DATA10 DATA7 DATA4 DATA1 BGH ADDR16 ADDR14 ADDR13 ADDR12 VDDEXT TCK BMODE1 DATA15 DATA14 DATA11 DATA8 DATA5 DATA2 BG ADDR19 ADDR18 ADDR17 GND ADSP-BF536/ADSP-BF537 Preliminary Technical Data Figure 49 shows the top view of the mini-BGA ball configuration. Figure 50 shows the bottom view of the mini-BGA ball configuration. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 A B C D E F G H J K L M N P KEY: VDDINT VDDRTC GND VDDEXT NC VROUT I/O Figure 49. 182-Ball Mini-BGA Ball Configuration (Top View) 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P KEY: VDDINT VDDEXT GND I/O VDDRTC NC VROUT Figure 50. 182-Ball Mini-BGA Ball Configuration (Bottom View) Rev. PrD | Page 58 of 64 | January 2005 Preliminary Technical Data ADSP-BF536/ADSP-BF537 208-BALL SPARSE MINI-BGA PINOUT Table 52 lists the sparse mini-BGA pinout by signal mnemonic. Table 53 on page 60 lists the sparse mini-BGA pinout by ball number. Table 52. 208-Ball Sparse Mini-BGA Ball Assignment (Alphabetically by Signal Mnemonic) Mnemonic ABE0 ABE1 ADDR1 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15 ADDR16 ADDR17 ADDR18 ADDR19 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 ADDR8 ADDR9 AMS0 AMS1 AMS2 AMS3 AOE ARDY ARE AWE BG BGH BMODE0 BMODE1 BMODE2 BR CLKBUF CLKIN CLKOUT DATA0 DATA1 DATA10 DATA11 Ball no. P19 P20 R19 W18 Y18 W17 Y17 W16 Y16 W15 Y15 W14 Y14 T20 T19 U20 U19 V20 V19 W20 Y19 M20 M19 G20 G19 N20 J19 N19 R20 Y11 Y12 W13 W12 W11 F19 B14 A18 H19 Y10 W10 Y5 W5 Mnemonic DATA12 DATA13 DATA14 DATA15 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 DATA8 DATA9 EMU GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Ball no. Y4 W4 Y3 W3 Y9 W9 Y8 W8 Y7 W7 Y6 W6 T1 A1 A13 A20 G11 H9 H10 H11 H12 H13 J9 J10 J11 J12 J13 K9 K10 K11 K12 K13 L9 L10 L11 L12 L13 M9 M10 M11 M12 M13 Mnemonic GND GND GND GND GND GND GND GND GND NC NC NC NC NMI PF0 PF1 PF10 PF11 PF12 PF13 PF14 PF15 PF2 PF3 PF4 PF5 PF6 PF7 PF8 PF9 PG0 PG1 PG10 PG11 PG12 PG13 PG14 PG15 PG2 PG3 PG4 PG5 Rev. PrD | Ball no. N9 N10 N11 N12 N13 P11 V2 Y1 Y20 B2 W2 W19 Y13 C20 T2 R1 L2 K1 K2 J1 J2 H1 R2 P1 P2 N1 N2 M1 M2 L1 H2 G1 C2 B1 A2 A3 B3 A4 G2 F1 F2 E1 Page 59 of 64 | Mnemonic PG6 PG7 PG8 PG9 PH0 PH1 PH10 PH11 PH12 PH13 PH14 PH15 PH2 PH3 PH4 PH5 PH6 PH7 PH8 PH9 PJ0 PJ1 PJ10 PJ11 PJ2 PJ3 PJ4 PJ5 PJ6 PJ7 PJ8 PJ9 RESET RTXO RTXI SA10 SCAS SCKE SMS SRAS SWE TCK January 2005 Ball no. E2 D1 D2 C1 B4 A5 B9 A10 B10 A11 B11 A12 B5 A6 B6 A7 B7 A8 B8 A9 B12 B13 B19 C19 D19 E19 B18 A19 B15 B16 B17 B20 D20 A15 A14 L20 K20 H20 J20 K19 L19 W1 Mnemonic TDI TDO TMS TRST VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDRTC VROUT0 VROUT1 XTAL Ball no. V1 Y2 U2 U1 G7 G8 G9 G10 H7 H8 J7 J8 K7 K8 L7 L8 M7 M8 N7 N8 P7 P8 P9 P10 G12 G13 G14 H14 J14 K14 L14 M14 N14 P12 P13 P14 A16 E20 F20 A17 ADSP-BF536/ADSP-BF537 Preliminary Technical Data Table 53 lists the sparse mini-BGA pinout by ball number. Table 52 on page 59 lists the sparse mini-BGA pinout by signal mnemonic. Table 53. 208-Ball Sparse Mini-BGA Ball Assignment (Numerically by Ball Number) Ball no. A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 C1 C2 Mnemonic GND PG12 PG13 PG15 PH1 PH3 PH5 PH7 PH9 PH11 PH13 PH15 GND RTXI RTXO VDDRTC XTAL CLKIN PJ5 GND PG11 NC PG14 PH0 PH2 PH4 PH6 PH8 PH10 PH12 PH14 PJ0 PJ1 CLKBUF PJ6 PJ7 PJ8 PJ4 PJ10 PJ9 PG9 PG10 Ball no. C19 C20 D1 D2 D19 D20 E1 E2 E19 E20 F1 F2 F19 F20 G1 G2 G7 G8 G9 G10 G11 G12 G13 G14 G19 G20 H1 H2 H7 H8 H9 H10 H11 H12 H13 H14 H19 H20 J1 J2 J7 J8 Mnemonic PJ11 NMI PG7 PG8 PJ2 RESET PG5 PG6 PJ3 VROUT0 PG3 PG4 BR VROUT1 PG1 PG2 VDDEXT VDDEXT VDDEXT VDDEXT GND VDDINT VDDINT VDDINT AMS3 AMS2 PF15 PG0 VDDEXT VDDEXT GND GND GND GND GND VDDINT CLKOUT SCKE PF13 PF14 VDDEXT VDDEXT Ball no. J9 J10 J11 J12 J13 J14 J19 J20 K1 K2 K7 K8 K9 K10 K11 K12 K13 K14 K19 K20 L1 L2 L7 L8 L9 L10 L11 L12 L13 L14 L19 L20 M1 M2 M7 M8 M9 M10 M11 M12 M13 M14 Rev. PrD | Mnemonic GND GND GND GND GND VDDINT ARDY SMS PF11 PF12 VDDEXT VDDEXT GND GND GND GND GND VDDINT SRAS SCAS PF9 PF10 VDDEXT VDDEXT GND GND GND GND GND VDDINT SWE SA10 PF7 PF8 VDDEXT VDDEXT GND GND GND GND GND VDDINT Page 60 of 64 | Ball no. M19 M20 N1 N2 N7 N8 N9 N10 N11 N12 N13 N14 N19 N20 P1 P2 P7 P8 P9 P10 P11 P12 P13 P14 P19 P20 R1 R2 R19 R20 T1 T2 T19 T20 U1 U2 U19 U20 V1 V2 V19 V20 January 2005 Mnemonic AMS1 AMS0 PF5 PF6 VDDEXT VDDEXT GND GND GND GND GND VDDINT ARE AOE PF3 PF4 VDDEXT VDDEXT VDDEXT VDDEXT GND VDDINT VDDINT VDDINT ABE0 ABE1 PF1 PF2 ADDR1 AWE EMU PF0 ADDR3 ADDR2 TRST TMS ADDR5 ADDR4 TDI GND ADDR7 ADDR6 Ball no. W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Mnemonic TCK NC DATA15 DATA13 DATA11 DATA9 DATA7 DATA5 DATA3 DATA1 BMODE2 BMODE1 BMODE0 ADDR18 ADDR16 ADDR14 ADDR12 ADDR10 NC ADDR8 GND TDO DATA14 DATA12 DATA10 DATA8 DATA6 DATA4 DATA2 DATA0 BG BGH NC ADDR19 ADDR17 ADDR15 ADDR13 ADDR11 ADDR9 GND Preliminary Technical Data ADSP-BF536/ADSP-BF537 Figure 51 shows the top view of the sparse mini-BGA ball configuration. Figure 52 shows the bottom view of the sparse miniBGA ball configuration. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 A B C D E F G H J K L M N P R T U V W X KEY: VDDINT GND VDDRTC VDDEXT I/O VROUT NC Figure 51. 208-Ball Mini-BGA Ball Configuration (Top View) 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U V W X KEY: VDDINT VDDEXT GND I/O VDDRTC NC VROUT Figure 52. 208-Ball Mini-BGA Ball Configuration (Bottom View) Rev. PrD | Page 61 of 64 | January 2005 ADSP-BF536/ADSP-BF537 Preliminary Technical Data OUTLINE DIMENSIONS Dimensions in Figure 53--182-Ball Mini-BGA and Figure 54-- 208-Ball Sparse Mini-BGA are shown in millimeters. Figure 53. 182-Ball Mini-BGA Rev. PrD | Page 62 of 64 | January 2005 Preliminary Technical Data ADSP-BF536/ADSP-BF537 Figure 54. 208-Ball Sparse Mini-BGA Rev. PrD | Page 63 of 64 | January 2005 ADSP-BF536/ADSP-BF537 Preliminary Technical Data ORDERING GUIDE Part numbers that include "BC1" are 182-Ball mini-BGA. Part numbers that include "BC2" are 208-Ball Sparse mini-BGA. Part numbers that include "Z" are lead free. See Figure 9 on page 24 for more information about product information on the package. Part Number ADSP-BF536SBBC1300 ADSPBF536SBBC1Z300 ADSPBF536SBBC2Z300 ADSP-BF536SBBC1400 ADSPBF536SBBC1Z400 ADSPBF536SBBC2Z400 Temperature Range (Ambient) -40C to 85C -40C to 85C -40C to 85C -40C to 85C -40C to 85C -40C to 85C Speed Grade (Max) 300 MHz 300 MHz 300 MHz 400 MHz 400 MHz 400 MHz Operating Voltage 1.2 V internal, 2.5 V or 3.3 V I/O 1.2 V internal, 2.5 V or 3.3 V I/O 1.2 V internal, 2.5 V or 3.3 V I/O 1.2 V internal, 2.5 V or 3.3 V I/O 1.2 V internal, 2.5 V or 3.3 V I/O 1.2 V internal, 2.5 V or 3.3 V I/O ADSP-BF537SBBC1500 ADSPBF537SBBC1Z500 ADSPBF537SBBC2Z500 ADSP-BF537SKBC1600 ADSPBF537SKBC1Z600 ADSPBF537SKBC2Z600 -40C to 85C -40C to 85C -40C to 85C 0C to 70C 0C to 70C 0C to 70C 500 MHz 500 MHz 500 MHz 600 MHz 600 MHz 600 MHz 1.2 V internal, 2.5 V or 3.3 V I/O 1.2 V internal, 2.5 V or 3.3 V I/O 1.2 V internal, 2.5 V or 3.3 V I/O 1.2 V internal, 2.5 V or 3.3 V I/O 1.2 V internal, 2.5 V or 3.3 V I/O 1.2 V internal, 2.5 V or 3.3 V I/O (c) 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR05370-0-1/05(PrD) a Rev. PrD | Page 64 of 64 | January 2005 www.analog.com