Features
•Single 3-V Supply Voltage
•High Power-added Efficient Power Amplifier (Pout Typically 23 dBm)
•Ramp-controlled Output Power
•Low-noise Preamplifier (NF Typically 2.1 dB)
•Biasing for External PIN Diode T/R Switch
•Current-saving Standby Mode
•Few External Components
•QFN20 Package with Extended Performance
1. Description
The T7024 is a monolithic SiGe transmit/receive front-end IC with power amplifier,
low-noise amplifier and T/R switch driver. It is especially designed for operation in
TDMA systems like Bluetooth® and WDCT.
Due to the ramp-control feature and a very low quiescent current, an external switch
transistor for VS is not required.
Figure 1-1. Block Diagram
TX/RX/
Standby
Control
PA
LNA
TX
RX
PU
V1_PA
V3_PA_OUT
RAMP
LNA_OUT
PA_IN
V2_PA
LNA_IN
R_SWITCH
SWITCH_OUT
VS_LNARX_ON
Bluetooth/ISM
2.4-GHz
Front-end IC
T7024
4533I–BLURF–01/09
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T7024
2. Pin Configuration
Figure 2-1. Pinning QFN20
GND
RAMP
V3_PA_OUT
V3_PA_OUT
V3_PA_OUT
201716 1918
6910
11
12
15
13
14
5
4
1
3
2
78
T7024
GND
V1_PA
PA_IN
V2_PA
V2_PA
LNA_IN
GND
GND
VS_LNA
GND
LNA_OUT
RX_ON
R_SWITCH
SWITCH_OUT
PU
Table 2-1. Pin Description
Pin Symbol Function
1 LNA_OUT Low-noise amplifier output
2 RX_ON RX active high
3 PU Power-up active high
4 R_SWITCH Resistor to GND sets the PIN diode current
5 SWITCH_OUT Switched current output for PIN diode
6 GND Ground
7 LNA_IN Low-noise amplifier input
8 GND Ground
9 VS_LNA Supply voltage input for low-noise amplifier
10 GND Ground
11 V3_PA_OUT Inductor to power supply and matching network for power amplifier output
12 V3_PA_OUT Inductor to power supply and matching network for power amplifier output
13 V3_PA_OUT Inductor to power supply and matching network for power amplifier output
14 GND Ground
15 RAMP Power ramping control input
16 V2_PA Inductor to power supply for power amplifier
17 V2_PA Inductor to power supply for power amplifier
18 GND Ground
19 V1_PA Supply voltage for power amplifier
20 PA_IN Power amplifier input
Slug GND Ground
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4533I–BLURF–01/09
T7024
Electrostatic sensitive device.
Observe precautions for handling.
5. Handling
Do not operate this part near strong electrostatic fields. This IC meets class 1 ESD test require-
ment (HBM in accordance to EIA/JESD22-A114-A (October 97) and class A ESD test
requirement (MM) in accordance to EIA/JESD22-A115A.
3. Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Parameters Symbol Value Unit
Supply voltage
Pins VS_LNA, V1_PA, V2_PA, V3_PA_OUT VS6V
Junction temperature Tj150 °C
Storage temperature Tstg –40 to +125 °C
RF input power LNA PinLNA 5dBm
RF input power PA PinPA 10 dBm
4. Thermal Resistance
Parameters Symbol Value Unit
Junction ambient QFN20, slug soldered on PCB RthJA 27 K/W
6. Operating Range
All voltages are referred to ground (pins GND and slug). Power supply points are VS_LNA, V1_PA, V2_PA, V3_PA_OUT.
The table represents the sum of all supply currents depending on the TX/RX mode.
Parameters Symbol Min. Typ. Max. Unit
Supply voltage
Pins V1_PA, V2_PA and V3_PA_OUT VS2.7 3.0 4.6 V
Supply voltage, pin VS_LNA VS2.7 3.0 5.5 V
Supply current TX
Supply current RX
IS
IS
165
8
mA
mA
Standby current, PU = 0 IS_standby 10 µA
Ambient temperature Tamb –25 +25 +85 °C
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T7024
7. Electrical Characteristics
Test conditions (unless otherwise specified): VS = 3.0V, Tamb = 25°C
Parameters Test Conditions Symbol Min. Typ. Max. Unit
Power Amplifier(1)
Supply voltage Pins V1_PA, V2_PA, V3_PA_OUT VS2.7 3.0 4.6 V
Supply current TX IS_TX 165 mA
RX (PA off), VRAMP ≤ 0.1V IS_RX 10 µA
Standby current Standby IS_standby 10 µA
Frequency range TX f 2.4 2.5 GHz
Gain-control range TX ΔGp 60 42 dB
Power gain maximum TX, pin PA_IN to V3_PA_OUT Gp 28 30 33 dB
Power gain minimum TX, pin PA_IN to V3_PA_OUT Gp –40 –17 dB
Ramping voltage maximum TX, power gain (maximum)
Pin RAMP VRAMP max 1.7 1.75 1.83 V
Ramping voltage minimum TX, power gain (minimum)
Pin RAMP VRAMP min 0.1 V
Ramping current maximum TX, VRAMP = 1.75V, pin RAMP IRAMP max 0.5 mA
Power-added efficiency TX PAE 35 40 %
Saturated output power TX, input power = 0 dBm referred to
pins V3_PA_OUT Psat 22 23 24 dBm
Input matching(2) TX, pin PA_IN Load
VSWR < 1.5:1
Output matching(2) TX, pins V3_PA_OUT Load
VSWR < 1.5:1
Harmonics at Psat = 23 dBm TX, pins V3_PA_OUT 2 fo –30 dBc
TX, pins V3_PA_OUT 3 fo –30 dBc
T/R Switch Driver (Current Programming by External Resistor from R_SWITCH to GND)
Switch-out current output
Standby, pin SWITCH_OUT IS_O_standby 1µA
RX IS_O_RX 1µA
TX at 100ΩIS_O_100 1.7 mA
TX at 1.2 kΩIS_O_1k2 7mA
TX at 33 kΩIS_O_33k 17 mA
TX at ∞IS_O_R 19 mA
Low-noise Amplifier(3)
Supply voltage All, pin VS_LNA VS2.7 3.0 5.5 V
Supply current RX IS89mA
Supply current
(LNA and control logic)
TX (control logic active)
Pin VS_LNA IS0.5 mA
Notes: 1. Power amplifier shall be unconditionally stable, maximum duty cycle 100%, true CW operation, maximum load mismatch
and duration: load VSWR = 10:1 (all phases) 10s, ZG = 50Ω.
2. With external matching network, load impedance 50Ω.
3. Low-noise amplifier shall be unconditionally stable.
4. With external matching components.
5. LNA gain can be adjusted with RX_ON voltage according to Figure 9-10 on page 9. Please note, that for RX_ON below
1.4V the T/R switch driver switches to TX mode.
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4533I–BLURF–01/09
T7024
Standby current Standby, pin VS_LNA IS_standby 110µA
Frequency range RX f 2.4 2.5 GHz
Power gain(5) RX, pin LNA_IN to LNA_OUT Gp 15 16 19 dB
Noise figure RX NF 2.1 2.3 dB
Gain compression RX, referred to pin LNA_OUT O1dB –9 –7 –6 dBm
3rd-order input interception point RX IIP3 –16 –14 –13 dBm
Input matching(4) RX, pin LNA_IN VSWRin 2:1
Output matching(4) RX, pin LNA_OUT VSWRout 2:1
Logic Input Levels (RX_ON, PU)(5)
High input level = ‘1’ pins RX_ON and PU ViH 2.4 VS, LNA V
Low input level = ‘0’ ViL 00.5V
High input current = ‘1’ ViH = 2.4V IiH 40 60 µA
Low input current = ‘0’ IiL 0.2 µA
7. Electrical Characteristics (Continued)
Test conditions (unless otherwise specified): VS = 3.0V, Tamb = 25°C
Parameters Test Conditions Symbol Min. Typ. Max. Unit
Notes: 1. Power amplifier shall be unconditionally stable, maximum duty cycle 100%, true CW operation, maximum load mismatch
and duration: load VSWR = 10:1 (all phases) 10s, ZG = 50Ω.
2. With external matching network, load impedance 50Ω.
3. Low-noise amplifier shall be unconditionally stable.
4. With external matching components.
5. LNA gain can be adjusted with RX_ON voltage according to Figure 9-10 on page 9. Please note, that for RX_ON below
1.4V the T/R switch driver switches to TX mode.
8. Control Logic PA and LNA/Antenna Switch Driver
PU RX_ON Ramp(1) PA LNA Antenna Switch Driver Operation Mode
0 0 0 off off off standby
0 0 1 on off off (2)
010offon off (3)
0 1 1 on on off (4)
1 0 0 off off on (4)
1 0 1 on off on TX
110offon off RX
1 1 1 on on off (5)
Notes: 1. “0” = VRAMP ≤ 0.1V, “1” = VRAMP typically 1.75V, 1.3V < VRAMP < 1.83V controls gain and output power, compare Figure 9-5 on
page 7
2. Only for special operation, e.g. only PA operation, no LNA/switch driver operation
3. Only for special operation, e.g. no switch driver operation
4. Only for special operation
5. Only for special operation, e.g. separate TX/RX antennas, TX and RX operation at the same time
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T7024
9. Typical Operating Characteristics
Figure 9-1. LNA: Gain and Noise Figure versus Frequency
Figure 9-2. LNA: NF and Gain versus Temperature
Figure 9-3. LNA: Typical Switch-out Current versus Rswitch
3
0
1
2
5
4
15
0
5
10
25
20
Gain (dB)
NF (dB)
24002200 3000280026002000
Frequency (MHz)
Gain
NF
1.5
-2.5
-1.5
-2.0
-0.5
0.5
0.0
1.0
-1.0
2.5
2.0
Relative gain
relative NF (dB)
4020 80600-20-40
Temperature (°C)
Gain
NF V
S
= 3V
12
0
4
8
2.0
16
1000000100000100001000100101
Rswitch (Ω)
IS_O (mA)
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4533I–BLURF–01/09
T7024
Figure 9-4. PA: Output Power and PAE versus Supply Voltage
Figure 9-5. PA: Output Power and PAE versus Ramp Voltage
Figure 9-6. PA: Output Power and PAE versus Input Power
30
0
10
20
50
3.1 4.74.33.93.52.7
40
190
100
130
160
250
220
Pout (dBm), PAE (%)
Supply Voltage (V)
IS_TX (mA)
PAE
Pout
I_S_TX
f = 2.4 GHz
PinPA = 0 dBm
Vramp = 1.8V
1.4 2.01.81.61.2
150
0
50
100
250
200
IS_TX (mA)
Vramp (V)
10
-50
-30
-10
50
30
Pout (dBm), PAE (%)
PAE
Pout
I_S_TX
f = 2.4 GHz
PinPA = 0 dBm
VS = 3V
30
-10
0
10
20
50
40
Pout (dBm), PAE (%), Gp (dB)
-30
-40 -100-10-20
200
0
50
100
150
300
250
IS_TX (mA)
Input Power (dBm)
f = 2.4 GHz
PinPA = 0 dBm
VS = 3V
Vramp = 1.8V
I_S_TX
Gain
PAE
Pout
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4533I–BLURF–01/09
T7024
Figure 9-7. PA: Output Power and PAE versus Frequency
Figure 9-8. LNA: Supply Current versus Temperature
Figure 9-9. PA: Pout versus VRAMP and Temperature
30
0
10
20
50
40
150
0
50
100
250
200
Pout (dBm), PAE (%)
24402420 2500248024602400
Frequency (MHz)
IS_TX (mA)
PAE
Pout
I_S_TX
VS = 3V
PinPA = 0 dBm
Vramp = 1.8V
7.6
6.0
6.4
6.2
6.8
7.2
7.0
7.4
6.6
8.0
7.8
Supply current (mA)
4020 80600-20-40
Temperature (°C)
1.2 1.81.61.41.0
Vramp (V)
10
-20
-10
0
30
20
Pout (dBm)
f = 2.4 GHz
Pin = 0 dBm
VS = 3V
-40°C
-15
5
25
80
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4533I–BLURF–01/09
T7024
Figure 9-10. LNA Gain (dB) versus RX_ON (V)
10. Input/Output Circuits
Figure 10-1. Input Circuit PA_IN/V1_PA
Figure 10-2. Input Circuit RAMP/V1_PA
5
-5
-10
-15
-20
-25
0
20
10
15
Gain (dB)
1.5 2 2.5 31
RX_ON (V)
VS = 3V
PA_IN
V1_PA
GND
RAMP
V1_PA
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4533I–BLURF–01/09
T7024
Figure 10-3. Input Circuit V2_PA
Figure 10-4. Input/Output Circuit V3_PA_OUT
Figure 10-5. Input Circuit SWITCH_OUT/R_SWITCH
V3_PA_OUT
GND
SWITCH_OUT
R_SWITCH
V1_PA
GND
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4533I–BLURF–01/09
T7024
Figure 10-6. Input Circuit LNA_IN/VS_LNA
Figure 10-7. Input Circuit PU/RX_ON
Figure 10-8. Output Circuit LNA_OUT
LNA_IN
VS_LNA
GND
LNA_IN / PU
VS_LNA
LNA_OUT
VS_LNA
GND
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4533I–BLURF–01/09
T7024
Figure 10-9. Typical Application T7024
PA_INLNA_OUT
R1 is selected
with DIL-switch
blocking capacitors
depending on application
Pin diode replaced by
LED on application board
R1
Var
V1_PA
V2_PA
harm. termination
PU
PX_ON
PA_OUTV3_PAVS_LNASwitch_OUT LNA_IN
PA_RAMP
107698
161920
1
2
5
3
4
15
14
11
13
12
1718
T7024
3.3 pF
18 nH
1 pF2.2 pF
2.2 pF
1.8 pF
0.8 pF
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4533I–BLURF–01/09
T7024
12. Package Information
11. Ordering Information
Extended Type Number Package Remarks MOQ
T7024-PGPM QFN20 Taped and reeled
Pb free, halogen free 1500 pcs.
T7024-PGQM QFN20 Taped and reeled
Pb free, halogen free 6000 pcs.
Demoboard-T7024-PGM QFN20 Evaluation board QFN 1
20
5
1
610
2016
11
15
5
1
5
3.1
2.6
0.65 nom.
specifications
according to DIN
technical drawings
Issue: 1; 19.12.02
Drawing-No.: 6.543-5094.01-4
Package: QFN 20 - 5 x 5
Exposed pad 3.1 x 3.1
Dimensions in mm
Not indicated tolerances ± 0.05
0.28
0.6
0.9±0.1
0.05-0.05
+0
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4533I–BLURF–01/09
T7024
13. Recommended PCB Land Pattern
Figure 13-1. Recommended PCB Land Pattern
14. Revision History
Table 13-1. Recommended PCB Land Pattern Signs
Sign Description Size
A Distance of vias 1.6 mm
B Size of slug pattern 3.1 mm
C Distance slug to pins 0.33 mm
D Diameter of vias 1 mm
E Width of pin pattern 0.3 mm
F Distance of pin pattern 0.33 mm
A
C
E
F
D
B
Please note that the following page numbers referred to in this section refer to the specific revision
mentioned, not to this document.
Revision No. History
4533I-BLURF-01/09 • PSSO20 package variant deleted
4533H-BLURF-07/07
• Put datasheet in a new template
• Page 1: Block diagram changed
• Page 13: Figure 10-8 changed
4533I–BLURF–01/09
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