AT52BR6408A-70CI - Atmel Corporation

Stack Module Features

•64-Mbit Flash + 8-Mbit SRAM

•Power Supply of 2.7V to 3.1V

•Data I/O x16

•66-ball CBGA Package

64-Mbit Flash Feature s

•64-megabit (4M x 16) Flash Memory

•2.7V - 3.1V Read/Write

•High Performance

– Asynchronous Access Time – 70, 85 ns

•Sector Erase Architecture

– Eight 4K Word Sectors with Individual Write Lockout

– 32K Word Main Sectors with Individual Write Lockout

•Typical Sector Erase Time: 32K Word Sectors – 500 ms; 4K Word Sectors – 100 ms

•64M, Four Plane Organization, Permitting Concurrent Read in Any of Three Planes not

Being Programmed/Erased

– Memory Plane A: 16M of Memory Including Eight 4K Word Sectors

– Memory Plane B: 16M of Memory Consisting of 32K Word Sectors

– Memory Plane C: 16M of Memory Consisting of 32K Word Sectors

– Memory Plane D: 16M of Memory Consisting of 32K Word Sectors

•Suspend/Resume Feature for Erase and Program

– Supports Reading and Programming Data from Any Sector by Suspending Erase

of a Different Sector

– Supports Reading Any Word by Suspending Programming of Any Other Word

•Low-p ower Opera tio n

–30 mA Active

– 10 µA Standby

•1.8V I/O Option Reduces Overall System Power

•Data Polling and Toggle Bit for End of Program Detection

•VPP Pin for Write Protection and Accelerated Program/Erase Operations

•RESET Input for Device Initialization

•Top or Bottom Boot Block Configuration Available

•128-bit Protection Register

•Common Flash Interfa ce (CFI)

8-Mbit SRAM Features

•8-Mbit (512K x 16)

•2.7V to 3.1V VCC Operatio n

•70 ns Access Time

•Low-power

– 2 mA Typical (Active)

– 1 µA Typical (Standby)

•Industrial Temperature Range

Stack Module Description

The AT52 BR6408 A(T ) consi sts of a 64 -Mbi t Flash stacked with a n 8-Mb it SR AM in a

single CBGA package.

Stack Module Memory Contents

Device Memory Combination Flash Read Access

AT52BR6408A(T) 64M Flash + 8M SRAM Asynchronous, Page Mode

64-Mbit Flash,

8-Mbit SRAM

(x16 I/O)

AT52BR6408A

AT52BR6408AT

Preliminary

Rev. 3425A–STKD–1/04

2AT52BR6408A(T) 3425A–STKD–1/04

66C4 – CBGA

Top View

Pin Configurations

123456789101112

A20

A16

SGND

A18

A11

RESET

VPP

A17

A15

A10

A21

A19

SOE

A14

I/O11

A13

I/O15

I/O13

I/O12

I/O9

CE1

GND

I/O14

I/O4

SVCC

I/O2

I/O0

A12

SWE

I/O6

SCS

I/O10

I/O8

GND

I/O7

I/O5

VCC

I/O3

I/O1

SCE1

Pin Name Function

A0 - A21 Address

I/O0 - I/O15 Data Inputs/Outputs

CE1 Flash Chip Enable

SCE1 SRAM Chip Enable

SCS SRAM Chip Select

OE/SOE Output Enable/SRAM Output Enable

WE/SWE Write Enable/SRAM Write Enable

LB Lower Byte Control (SRAM)

UB Upper Byte Control (SRAM)

RESET Flash Reset

WP Flash Write Protect

VPP Flash Write Protecti on and Power Supply for Accelerated

Program/Erase Operation

VCC/SVCC Flash Power Supply/SRAM Power Supply

NC No Connect

GND/SGND Device Ground/SRAM Ground

AT52BR6408A(T)

3425A–STKD–1/04

64-Mbit Flash

Description The 64-Mbit Flash memory is divided into multiple sectors and planes for erase opera-

tions. The devices can be read or reprogrammed off a single 2.7V power supply, making

them ideally suited for in-system programming.

The 64-Mbit device is divided into four memory planes. A read operation can occ ur in

any of the three planes which is not being programmed or erased. This concurrent oper-

ation allows impr oved system performance by not requiring the system to wait for a

program or e ra se operation to c omp let e be for e a read is pe rfor med . T o f urther i ncre as e

the flexibility of the device, it contains an Erase Suspend and Program Suspend feature.

This feature will put the erase or program on hold for any amount of time and let the user

read data from or program data to any of the remaining sectors. There is no reason to

suspend the erase or program operation if the data to be read is in another memory

plane. The end of program or erase is detected by Data Polling or toggle bit.

The VPP pin provides data protection and faster programming and erase times. When

the VPP in put is bel ow 0.8V , the progr a m and eras e func tions are inhibi ted. When VPP is

at 1.65V or above, normal program and erase operations can be performed. With VPP at

12.0V, the program and erase operations are accelerated.

With VPP at 12V, a six-byte command (Enter Single Pulse Program Mode) to remove the

requirement of entering the three-byte program sequence is offered to further improve

progra mming time. After e nter i ng th e s ix- byte c ode , on ly s ing le pulses on th e wr it e c on-

trol lines are required for writing into the device. This mode (Single Pulse Word

Program) is exited by powering down the device, by taking the RESET pin to GN D or b y

a high-to-low transition on the VPP input. Erase, Erase Suspend/Resume, Program Sus-

pend/Resume and Read Reset comman ds will not wor k while in this mode; if entered

they will result in data being programmed into the device. It is not recommended that the

six-byt e code reside in the software of the f inal produ ct bu t only ex ist in external pro-

gramming code.

Device Operation COMMAND SEQUENCES: The device powers on in the read mode. Command

sequenc es are use d to pl ac e the de vi ce in oth er oper at ing modes such as pro gram and

erase. After the completion of a program or an erase cycle, the device enters the read

mode. The command sequ ences are written by applying a low pulse on the WE input

with CE low and OE hig h or by ap plyi ng a lo w- goi ng p uls e on th e CE in put with WE low

and OE high. The address is latched on the falling edge of the WE or CE pulse which-

ever occurs first. Valid data is latched on the rising edge of the WE or the CE pulse,

whichever occurs first. The addresses used in the command sequences are not affected

by entering the command sequences.

ASYNCHRONOUS READ: The 64-Mbit Flash is accessed l ike an EPROM. When CE

and OE are low and WE is hi gh, the dat a stored at the memor y locati on determi ned by

the address pins are asserted on the outputs. The outputs are put in the high impedance

state whenev er CE or OE is high. This dual-line control gives designers flexibility in pre-

venting bus conte nti on.

RESET: A RESET input pin is provided to ease some system applications. When

RESET is a t a log ic hi gh lev el, th e dev ice is in its stan dard ope ratin g mode. A low le vel

on the RESE T pin hal ts the pr ese nt de vi c e ope ratio n and puts th e ou tput s of the dev ice

in a high-impedance state. When a high level is reasserted on the RESET pin, the

device returns to read or standby mode, depending upon the state of the control pins.

4AT52BR6408A(T) 3425A–STKD–1/04

ERASE: Before a word can be reprogrammed it must be erased. The erased state of

the memo ry bits is a lo gical “1” . The entire m emory can be erased by using the C hip

Erase command or individual planes or sectors can be erased by using the Plane Erase

or Sector Erase commands.

CHIP ERASE : Chip Erase is a six-bus cycle operation. The automatic erase begins on

the rising edge of the last WE pulse. Chip Erase does not alter the data of the protected

sector s. Aft er the ful l chi p erase the devi ce wi ll retur n bac k to th e r ea d m ode . T he hard-

ware reset during Chip Erase will stop the erase but the data will be of unknown state.

Any command during Chip Erase except Erase Suspend will be ignored.

PLANE ERAS E: As a alternative to a full chip erase, the device is or ganized into four

planes that can be individually erased. The plane erase command is a six-bus cycle

operation. The plane whose address is valid at the sixth falling edge of WE will be

erased provided none of the sectors within the plane are protected.

SECTOR ERASE: As an alternative to a full chip erase or a plane erase, the device is

organized into multiple sectors that can be individually erased. The Sector Erase com-

mand is a s ix-bu s cyc le opera tion. T he sec tor wh ose addre ss is valid a t the six th fall ing

edge of WE will be erased provided the given sector has not been protected.

WORD PROGRAMMING: The device is programmed on a word-by-word basis. Pro-

gramming is accomplished via the internal device command register and is a four-bus

cycle operation. The programming address and data are latched in the fourth cycle. The

device will automatically generate the required internal programming pulses. Please

note tha t a “0” cann ot be pro grammed b ack to a “ 1”; only e ras e ope rati ons ca n co nver t

“0”s to “1”s.

FLEXIBLE SECTOR PROTECTION: The 64- Mbit device of fers two sec tor protec tion

modes, the Softlock and the Hardlock. The Softlock mode is optimized as sector protec-

tion for sectors whose content changes frequently. The Hardlock protection mode is

recommended for sectors whose content changes infrequently. Once either of these two

modes is enabled, the contents of the selected sector is read-only and cannot be erased

or programmed. Each sector can be independently programmed for either the Softlock

or Har dlock sector p rotec tion mo de. At p ower-u p and r eset, all secto rs hav e their S oft-

lock protection mode enabled.

SOFTLOCK AND UNLOCK: The Softlock protection mode can be disabled by issuing a

two-bus cyc le Unlock c ommand to t he selecte d sector. On ce a sector is unlock ed, its

contents can b e erased or prog ramm ed. To en able th e Softl ock pr otection m ode, a s ix-

bus cycle Softlock command must be issued to the selected sector.

HARDLOCK AND WRITE PROTECT (WP): The Hardlock sector protection mode oper-

ates in conjunction with the Write Protection (WP) pin. The Hardlock sector protection

mode can be enabled by issuing a six-bus cycle Hardlock software command to the

selected sector. The state of the Write Protect pin affects whether the Hardlock protec-

tion mode can be overridden.

• When the WP pin is low and the Hardlock protection mode is enabled, the sector

cannot be unlocked and the contents of the sector is read-only.

• When the WP pin is high, the Hardlock protection mode is overridden and the sector

can be unlocked via the Unlock command.

AT52BR6408A(T)

3425A–STKD–1/04

To di sable the Hardloc k s ector prote ction m ode , the chip mus t be either rese t o r power

cycled.

SECTOR PRO TECTION DETEC TION: A software method is available to determine if

the sector protection Softlock or Hardlock features are enabled. When the device is in

the soft ware produ ct iden tificati on mode (se e Software Product Id entif ication Ent ry and

Exit se ctions) a read from the I/O 0 and I/O 1 at addre ss lo cation 00002H withi n a sec tor

will show if the sector is unlocked, softlocked, or hardlocked.

Table 1. Hardlock and Softlock Protection Configurations in Conjunction with WP

VPP WP Hard-

lock Soft-

lock

Erase/

Prog

Allowed? Comments

VCC/5V 0 0 0 Yes No se ctor is locked

VCC/5V 0 0 1 No Sector is Softlocked. The

Unloc k comman d can unloc k

the sector.

VCC/5V 0 1 1 No Hardlock protection mode is

enabled. The sector cannot

be unloc ked.

VCC/5V 1 0 0 Yes No sector is locked.

VCC/5V 1 0 1 No Sector is Softlocked. The

Unloc k comman d can unloc k

the sector.

VCC/5V 1 1 0 Yes Hardlock protection mode is

overridden and the sector is

not locked.

VCC/5V 1 1 1 No Hardlock protection mode is

overridden and the sector

can be unlocked via the

Unlock command.

VIL x x x No Erase and Program

Operations cannot be

performed.

Table 2. Sector Protection Status

I/O1 I/O0 Sector Prote ction Status

0 0 Sector Not Locked

0 1 Softlock Enabled

1 0 Hardlo ck Enabl ed

1 1 Both Hardlock and Softlock Enabled

6AT52BR6408A(T) 3425A–STKD–1/04

PROGRAM/ERASE S TATUS : T he device pr ovid es several bi ts to deter mine the st atus

of a program or erase operation: I/O2, I/O3, I/O5, I/O6, and I/O7. All other status bits are

don’t care. Table 3 on page 11 and the following four sections describe the function of

these bits. To provide greater flexibili ty for system desi gners, the 64 -Mbit device c on-

tains a programmable configuration register. The configuration register allows the user

to specify the status bit operation. The configuration register can be set to one of two dif-

ferent values, “00” or “01”. If the configuration register is set to “00”, the part will

automa tica lly retu rn to the r ead mod e after a success ful prog ram or e rase o peratio n. If

the configuration register is set to a “01”, a Product ID Exit command must be given after

a successful program or erase operation before the part will return to the read mode. It

is important to note that whether the configuration register is set to a “00” or to a “01”,

any unsuccessful program or erase operation requires using the Product ID Exit com-

mand to return the device to read mode. The default value (af ter power-up) for the

configurati on registe r is “00 ”. Usin g the four- bus cycle s et configur ation regi ster com-

mand as shown in the Command Definition table on page 12, the value of the

configuration register can be changed. Voltages applied to the reset pin will not alter the

value of the co nfigura tion register . The val ue of the co nfig uration r egist er will aff ect th e

operation of the I/O7 status bit as described below.

DATA POLLING: The 64- Mbit de vice fea tures Data Po lling to indic ate the en d of a pr o-

gram cycle. If the status configuration register is set to a “00”, during a program cycle an

attem pted read of th e last word loaded wi ll resul t in the com plement of the loade d data

on I/O7. Once the program cycle has been completed, true data is valid on all outputs

and the nex t cycle may beg in. During a chip or sector erase operation, an atte mpt to

read the device will give a “0” on I/O7. Once the program or erase cycle has completed,

true data will be read from the device. Data Polling may begin at any time during the pro-

gram cycle. Please see Table 3 on page 11 for more details.

If the statu s b it con fig urati on r e gis ter i s set to a “01” , th e I/O 7 st a tus bi t wil l be low while

the device is actively programming o r erasing data. I/O 7 will go high wh en the devic e

has com ple ted a pr og ra m or e ra se ope ration. Once I/O7 ha s g one hig h, s tat us inf o rma-

tion on the other pins can be checked.

The Data Polli ng sta tus bit must be us ed in conj unc ti on with the erase /pr og ram and VPP

status bit as shown in the algorithm in Figures 2 and 3.

TOGGLE BIT: In addi tion to Data Polling , the 6 4-Mbit de vice pr ovides anothe r metho d

for dete rmining the end of a progr am or eras e cycle. During a pro gram or eras e opera-

tion, successive attempts to read data from the memory will result in I/O6 toggling

between one and zero. Once the program cycle has completed, I/O6 will stop toggling

and valid data will be read. Examining the toggle bit may begin at any time during a pro-

gram cycle. Please see Table 3 on page 11 for more details.

The to ggle bi t status bi t shou ld be us ed in conj uncti on with th e erase /progra m and VPP

status bit as shown in the algorithm in Figures 4 and 5 on page 10.

ERASE/PROGRAM STATUS BIT: The dev ice off ers a stat us bit on I/ O5 that ind icates

whether the program or erase operation has exceeded a specified internal pulse count

limit . If the stat us bit is a “ 1”, the de vice is un able to v erify tha t an erase or a word pro-

gram operation has been successfully performed. The device may also output a “1” on

I/O5 if the system tries to program a “1” to a location that was previously programmed to

a “0”. Only an erase op eration can change a “0” b ack to a “1”. If a program ( Sector

Erase) com mand is issued to a prote cted sec tor, the protected secto r will not be pro-

grammed (erased ). The dev ice will go to a sta tus read mo de and the I/O5 sta tus bit will

be set high, indicating the program (erase) operation did not complete as requested.

Once the erase/program s tatus bit has been set to a “1” , the system m ust write the

Produc t ID Exit comma nd to return to the read mod e. The erase/p rogr am st atus bit i s a

AT52BR6408A(T)

3425A–STKD–1/04

“0” while the erase or program operation is still in progress. Please see Table 3 on page

11 for more details.

VPP STATUS BI T: The 64-Mbit device provides a status bit on I/O3 that provides infor-

mation regarding the voltage level of the VPP pin. During a program or erase operation,

if the voltage on the VPP pin is not high enough to perform the desired operation suc-

cessful ly, the I/O3 sta tus bit will be a “1” . Once the VPP s tatus bit ha s been set to a “1”,

the system must wri te the P roduct ID E xit com mand to return to the read m ode. O n the

other ha nd, if the vo ltage level is hi gh enough to perfor m a program or eras e operatio n

successfully, the VPP status bit will output a “0”. Please see Table 3 on page 11 for more

details.

ERASE SUSPEND/ERASE RESUME: The Erase Suspe nd command al lows the sys-

tem to inte rru pt a se cto r erase operation an d then pro gram or r ead da ta from a di fferent

secto r within the same pl ane. Since this devi ce has a m ultiple plane a rchitec ture, the re

is no need to use the erase suspend featur e while erasing a sec tor when you want to

read data from a sector in another plane. After the Erase Suspend command is given,

the devic e requires a maxim um time of 15 µs to suspe nd the erase oper ation. After the

erase operation has been suspended, the plane that contains the suspended sector

enters the erase-suspend-read mode. The system can then read data or program data

to any ot her sect or within th e devic e. An ad dress is no t requi red duri ng the Eras e Sus-

pend command. During a sector erase suspend, another sec tor cannot be erased. To

resume the sector erase operation, the system must write the Erase Resume command.

The Erase Resume comm and is a one-bus cycle comm and, which does require the

plane ad dress. The device also supports an erase suspend during a complete chi p

erase. W hile the chip era se is susp ended, the user ca n read from any sec tor within the

memory that is protected. The command sequence for a chip erase suspend and a sec-

tor erase suspend are the same.

PROGRAM SUSPEND/PROGRAM RESUME: The Program Suspend command allows

the system to interrupt a programming operation and then read data from a different

word within th e memory. After the Prog ram Suspend command is given, the devic e

requires a maximum of 10 µs to suspend the programming operation. After the program-

ming operation has been suspended, the system can then read from any other word

within the dev ic e. An add re ss is n ot r equ ired during th e pr o gr am sus pe nd o per ati on . T o

res ume the progr amming oper ation , the sys tem m ust wr ite the P rogra m Res ume co m-

mand. The program suspend and resume are one-bus cycle commands. The command

sequence for the erase suspend and program suspend are the same, and the command

sequence for the erase resume and program resume are the same.

128-BIT PROTECTION REGISTER: Th e 64-M bit device c on tains a 128 -bit r eg is ter that

can be used for security purposes in system design. The protection register is divided

into tw o 64-bit b lock s. The two blocks are d esignate d as bl ock A and bloc k B. T he da ta

in block A is non-changeable and is programmed at the factory with a unique number.

The data in bl ock B is prog ramme d by the us er and can be lo cked out such tha t data in

the block cannot be reprogrammed. To program block B in the protection register, the

four-bus cycle Program Protection Register command must be used as shown in the

Command Definition i n Hex tabl e on page 12. To lock out bloc k B, the fou r-bus cy cle

lock pr ote ction r eg is ter co mmand must be us ed as sh own in the Comm and De fin ition i n

Hex table. Data bit D1 must be zero during the fourth bus cycle. All other data bits during

the four th bus cycle are don’t cares. T o determine whe ther block B is lock ed out, the

Product ID Entry command is given followed by a read operation from address 80H. If

data bit D1 is zero, block B is locked. If data bit D1 is one, block B can be repro-

grammed. Ple ase see the Protection Register Addressi ng Table on page 13 for the

addres s locations in the prote ction register. To read the protection re gister, the Produc t

ID Entry c ommand is given fol lowed by a normal r ead opera tion from an addr ess withi n

8AT52BR6408A(T) 3425A–STKD–1/04

the protec tion registe r. After deter mining whether block B is protected or not or readin g

the pro tection r egister , the Prod uct ID Exit comman d must be given prior to perfor ming

any other operation.

CFI: Common Flas h Interface (CFI ) is a published , standardi zed da ta structur e that

may be read from a Flash device. CFI allows system software to query the installed

devic e to de termin e the c onfigur ations, variou s electr ical a nd timi ng param eters, and

functions supported by the device. CFI is used to allow the system to learn how to inter-

face to the Flas h de vi c e mo st o pti mal ly. T he two pri mar y ben efi ts o f usin g CF I are ease

of u pgrading and sec ond sour ce avail ability. The com mand to enter t he CFI Query

mode is a one-bus cycle command which requires writing data 98h to address 55h. The

CFI Query command can be written when the device is ready to read data or can also

be written when the part i s in the product ID mode . Once in the CFI Query mo de, the

system can read CFI data at the addresses given in Table 4 on page 25. To exit the CFI

Query mode, the product ID exit command must be given. If the CFI Query command is

given while the part is in the product ID mode, then the product ID exit command must

first be give n to return the p art t o the prod uct I D mode . On ce i n the produc t ID mode , it

will be nec es sary to giv e an othe r prod uc t ID exit co mma nd to retu rn the part to the read

mode.

HARDWAR E DATA PROTECTION: Har dware fe atures prote ct a gainst inad verten t pr o-

grams to the 64-Mbit device in the following ways: (a) VCC sense: if VCC is below 1.8V

(typical), the program function is inhibited. (b) VCC power-on delay: once VCC has

reached the VCC sense level, the device will automatically time-out 10 ms (typical)

befor e progra mming. (c ) Program in hibit: ho lding any one of OE low, CE high or WE

high inhibits program c ycles. (d) Noise filter: puls es of less than 15 ns ( typical) on the

WE or CE inputs will not initiate a program cycle. (e) VPP is less than VILPP.

INPUT LEVELS: Whil e operati ng with a 2.7V to 3.1V power supp ly, the addres s inputs

and con trol inpu ts (OE, CE and WE) may be driven from 0 to 5.5V without adversely

affecting the operation of the device. The I/O lines can be driven from 0 to VCCQ + 0.6V.

AT52BR6408A(T)

3425A–STKD–1/04

Figure 1. Data Polling Algorithm

(Configuration Register = 00)

Notes : 1. VA = Valid address for progr am ming. During a se c-

tor erase operation, a valid address is any sector

address within the sector being erased. During

chip erase, a valid address is any non-protected

sector address.

2. I/O7 should be rechecked even if I/O5 = “1”

because I/O7 may change simultaneously with

I/O5.

START

Read I/O7 - I/O0

Addr = VA

I/O7 = Data?

I/O3, I/O5 = 1?

Read I/O7 - I/O0

Addr = VA

I/O7 = Data?

Program/Erase

Operation Not

Successful, Write

Product ID

Exit Command

YES

Program/Erase

Operation

Successful,

Device in

Read Mode

Figure 2. Data Polling Algorithm

(Config u rati on Regi st er = 01)

Note: 1. VA = Valid address for programming. During a sector

erase operation, a valid address is any sector address

within the sector being erased. During chip erase, a

valid address is any non-protected sector address.

START

Read I/O7 - I/O0

Addr = VA

I/O7 = 1?

I/O3, I/O5 = 1?

Program/Erase

Operation Not

Successful, Write

Product ID

Exit Command

YES

Program/Erase

Operation

Successful,

Write Product ID

Exit Command

10 AT52BR6408A(T) 3425A–STKD–1/04

Figure 3. Toggle Bit Algorithm

(Configuration Register = 00)

Note: 1. The system should recheck the toggle bit even if

I/O5 = “1” because the toggle bit may stop toggling

as I/O5 changes to “1”.

START

Read I/O7 - I/O0

Toggle Bit =

Toggle?

I/O3, I/O5 = 1?

Read I/O7 - I/O0

Twice

Toggle Bit =

Toggle?

Program/Erase

Operation Not

Successful, Write

Product ID

Exit Command

Program/Erase

Operation

Successful,

Device in

Read Mode

YES

Figure 4. Toggle Bit Algorithm

(Configuration Register = 01)

Note: 1. The system should recheck the toggle bit even if I/O5 =

“1” because the toggle bit may stop toggling as I/O5

changes to “1”.

START

Read I/O7 - I/O0

Toggle Bit =

Toggle?

I/O3, I/O5 = 1?

Read I/O7 - I/O0

Twice

Toggle Bit =

Toggle?

Program/Erase

Operation Not

Successful, Write

Product ID

Exit Command

Program/Erase

Operation

Successful,

Write Product ID

Exit Command

YES

AT52BR6408A(T)

3425A–STKD–1/04

Table 3. Status Bit Table

I/O7 I/O6 I/O2

Configuration

Read Address

In Plane A Plane B Plane C Plane D Plane A Plane B Plane C Plane D Plane A Plane B Plane C Plane D

While

Programming

in Plane A I/O7/0 DATA DATA DATA TOGGLE DATA DATA DATA 1 DATA DATA DATA

Programming

in Plane B DATA I/O7/0 DATA DATA DATA TOGGLE DATA DATA DATA 1 DATA DATA

Programming

in Plane C DATA DATA I/O7/0 DATA DATA DATA TOGGLE DATA DATA DATA 1 DATA

Programming

in Plane D DATA DATA DATA I/O7/0 DATA DATA DATA TOGGLE DATA DATA DATA 1

Erasing in

Plane A 0/0 DATA DATA DATA TOGGLE DATA DATA DATA TOGGLE DATA DATA DATA

Erasing in

Plane B DATA 0/0 DATA DATA DATA TOGGLE DATA DATA DATA TOGGLE DATA DATA

Erasing in

Plane C DATA DATA 0/0 DATA DATA DATA TOGGLE DATA DATA DATA TOGGLE DATA

Erasing in

Plane D DATA DATA DATA 0/0 DATA DATA DATA TOGGLE DATA DATA DATA TOGGLE

Erase

Suspend ed &

Read Erasing

Sector

1111 1 1 1 1TOGGLETOGGLETOGGLETOGGLE

Erase

Suspend ed &

Read Non-

erasing Sector

DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA

Erase

Suspend ed &

Program Non-

erasing Sector

in Plane A

I/O7/0 DATA DATA DATA TOGGLE DATA DATA DATA TOGGLE DATA DATA DATA

Erase

Suspend ed &

Program Non-

erasing Sector

in Plane B

DATA I/O7/0 DATA DATA DATA TOGGLE DATA DATA DATA TOGGLE DATA DATA

Erase

Suspend ed &

Program Non-

erasing Sector

in Plane C

DATA DATA I/O7/0 DATA DATA DATA TOGGLE DATA DATA DATA TOGGLE DATA

Erase

Suspend ed &

Program Non-

erasing Sector

in Plane D

DATA DATA DATA I/O7/0 DATA DATA DATA TOGGLE DATA DATA DATA TOGGLE

12 AT52BR6408A(T) 3425A–STKD–1/04

Notes: 1. The DATA FORMAT in each bus cycle is as follows: I/O15 - I/ O8 (Don’t Care); I/O7 - I/O0 (Hex). T he ADDRESS FORMAT in each bus cycle

is as follows: A11 - A0 (Hex), A11 - A21 (Don’t Care).

2. Since A11 is a Don’t Care, AAA can be replaced with 2AA.

3. Either one of the Product ID Exit commands can be used.

4. SA = sector address. Any word address within a sector can be used to designate the sector address (see pages 14 - 17 for details).

5. Once a sector is in the Hardlock protection mode, it cannot be disabled unless the chip is reset or power cycled.

6. PA is the plane address (A21 - A20).

7. For the 64-Mbit Bottom Boot: For the 64-Mbit Top Boot:

xxx = 0XX555 Status Read from Plane A xxx = 3XX555 Status Read from Plane A

xxx = 1XX555 Status Read from Plane B xxx = 2XX555 Status Read from Plane B

xxx = 2XX555 Status Read from Plane C xxx = 1XX555 Status Read from Plane C

xxx = 3XX555 Status Read from Plane D xxx = 0XX555 Status Read from Plane D

8. If data bit D1 is “0”, bloc k B is lock ed. If data bit D1 is “1”, block B can be reprogrammed.

9. The default state (after power-up) of the configuration register is “00”.

Command Definition in (Hex )(1)

Command Sequence Bus

Cycles

1st Bus

Cycle 2n d Bus

Cycle 3rd Bus

Cycle 4th Bus

Cycle 5th Bus

Cycle 6th Bus

Cycle

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

Read 1 Addr DOUT

Chip Erase 6 555 AA AAA(2) 55 555 80 555 AA AAA 55 555 10

Plane Eras e 6 555 AA AAA 55 555 80 555 AA AAA 55 PA(6) 20

Sector Er ase 6 555 AA AAA 55 555 80 555 AA AAA 55 SA(4) 30

Word Program 4 555 AA AAA 55 555 A0 Addr DIN

Enter Single-pulse Program

Mode 6 555 AA AAA 55 555 80 555 AA AAA 55 555 A0

Single-pulse Word Program

Mode 1AddrD

Sector Softl ock 6 555 AA AAA 55 555 80 555 AA AAA 55 SA(4) 40

Sector Unlock 2 555 AA SA(4) 70

Sector Hardlock 6 555 AA AAA 55 555 80 555 AA AAA 55 SA(4)(5) 60

Erase/Program Suspend 1 xxx B0

Erase/Program Resume 1 PA(6) 30

Product ID Entry 3 555 AA AAA 55 xxx(7) 90

Product ID Exit(3) 3 555 AA AAA 55 555 F0

Product ID Exit(3) 1 xxx FX

Program Protection

Lock Protection

Status of B lock B

Protection 4 555 AA AAA 55 555 90 80 DOUT(8)

Set Configuration Register 4 555 AA AAA 55 555 E0 xxx 00/01(9)

CFI Query 1 X55 98

AT52BR6408A(T)

3425A–STKD–1/04

Note: 1. All address lines not specified in the above table must be 0 when accessing the Protection Register, i.e., A21 - A8 = 0.

Absolute Maxim u m Ratings*

Temperature under Bias ................................ -55°C to +125°C *NOTICE: Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam-

age to the device. Th is is a s tress r ating only an d

funct ional ope rati on of the de vic e at these or an y

other conditions beyond those indicated in the

operational sections of this specification is not

implied. Exposure to absolute maximum rating

conditi ons for e xtended periods ma y affect device

reliability.

Storage Temperature..................................... -65°C to +150°C

All Input Voltages Except VPP

(including NC Pins)

with Respect to Ground...................................-0.6V to +6.25V

VPP Input Voltag e

with Respect to Ground.........................................0V to 13.0V

All Output Voltages

with Respect to Ground...........................-0.6V to VCCQ + 0.6V

Protection Register Addressing Table

Word Use Block A7 A6 A5 A4 A3 A2 A1 A0

0FactoryA10000001

1FactoryA10000010

2FactoryA10000011

3FactoryA10000100

4UserB10000101

5UserB10000110

6UserB10000111

7UserB10001000

14 AT52BR6408A(T) 3425A–STKD–1/04

Memory Org anization – 64-Mbit Bottom Boot

Plane Sector Size

(Words)

x16

Address Range

(A21 - A0)

A SA0 4K 00000 - 00FFF

A SA1 4K 01000 - 01FFF

A SA2 4K 02000 - 02FFF

A SA3 4K 03000 - 03FFF

A SA4 4K 04000 - 04FFF

A SA5 4K 05000 - 05FFF

A SA6 4K 06000 - 06FFF

A SA7 4K 07000 - 07FFF

A SA8 32K 08000 - 0FFFF

A SA9 32K 10000 - 17FFF

A SA10 32K 18000 - 1FFFF

A SA11 32K 20000 - 27FFF

A SA12 32K 28000 - 2FFFF

A SA13 32K 30000 - 37FFF

A SA14 32K 38000 - 3FFFF

A SA15 32K 40000 - 47FFF

A SA16 32K 48000 - 4FFFF

A SA17 32K 50000 - 57FFF

A SA18 32K 58000 - 5FFFF

A SA19 32K 60000 - 67FFF

A SA20 32K 68000 - 6FFFF

A SA21 32K 70000 - 77FFF

A SA22 32K 78000 - 7FFFF

A SA23 32K 80000 - 87FFF

A SA24 32K 88000 - 8FFFF

A SA25 32K 90000 - 97FFF

A SA26 32K 98000 - 9FFFF

A SA27 32K A0000 - A7FFF

A SA28 32K A8000 - AFFFF

A SA29 32K B 0000 - B7FFF

A SA30 32K B8000 - BFFFF

A SA31 32K C0000 - C7FFF

A SA32 32K C8000 - CFFFF

A SA33 32K D0000 - D7FFF

A SA34 32K D8000 - DFFFF

A SA35 32K E 0000 - E7FFF

A SA36 32K E8000 - EFFFF

A SA37 32K F0000 - F7FFF

A SA38 32K F8000 - FFFFF

B SA39 32K 100000 - 107FFF

B SA40 32K 108000 - 10FFFF

B SA41 32K 110000 - 117FFF

B SA42 32K 118000 - 11FFFF

B SA43 32K 120000 - 127FFF

B SA44 32K 128000 - 12FFFF

B SA45 32K 130000 - 137FFF

B SA46 32K 138000 - 13FFFF

B SA47 32K 140000 - 147FFF

B SA48 32K 148000 - 14FFFF

B SA49 32K 150000 - 157FFF

B SA50 32K 158000 - 15FFFF

B SA51 32K 160000 - 167FFF

B SA52 32K 168000 - 16FFFF

B SA53 32K 170000 - 177FFF

B SA54 32K 178000 - 17FFFF

B SA55 32K 180000 - 187FFF

B SA56 32K 188000 - 18FFFF

B SA57 32K 190000 - 197FFF

B SA58 32K 198000 - 19FFFF

B SA59 32K 1A0000 - 1A7FFF

B SA60 32K 1A8000 - 1AFFFF

B SA61 32K 1B0000 - 1B7FFF

B SA62 32K 1B8000 - 1BFFFF

B SA63 32K 1C0000 - 1C7FFF

B SA64 32K 1C8000 - 1CFFFF

B SA65 32K 1D0000 - 1D7FFF

B SA66 32K 1D8000 - 1DFFFF

B SA67 32K 1E0000 - 1E7FFF

B SA68 32K 1E8000 - 1EFFFF

B SA69 32K 1F0000 - 1F7FFF

B SA70 32K 1F8000 - 1FFFFF

C SA71 32K 200000 - 207FFF

C SA72 32K 208000 - 20FFFF

C SA73 32K 210000 - 217FFF

C SA74 32K 218000 - 21FFFF

C SA75 32K 220000 - 227FFF

C SA76 32K 228000 - 22FFFF

C SA77 32K 230000 - 237FFF

C SA78 32K 238000 - 23FFFF

C SA79 32K 240000 - 247FFF

C SA80 32K 248000 - 24FFFF

C SA81 32K 250000 - 257FFF

C SA82 32K 258000 - 25FFFF

C SA83 32K 260000 - 267FFF

C SA84 32K 268000 - 26FFFF

C SA85 32K 270000 - 277FFF

C SA86 32K 278000 - 27FFFF

C SA87 32K 280000 - 287FFF

C SA88 32K 288000 - 28FFFF

C SA89 32K 290000 - 297FFF

Memory Organiz ation – 64-Mbit Botto m Boot (Continued )

Plane Sector Size

(Words)

x16

Address Range

(A21 - A0)

AT52BR6408A(T)

3425A–STKD–1/04

C SA90 32K 298000 - 29FFFF

C SA91 32K 2A0000 - 2A7FFF

C SA92 32K 2A8000 - 2AF FFF

C SA93 32K 2B0000 - 2B7FFF

C SA94 32K 2B8000 - 2BF FFF

C SA95 32K 2C0000 - 2C7FFF

C SA96 32K 2C8000 - 2CFFFF

C SA97 32K 2D0000 - 2D7FFF

C SA98 32K 2D8000 - 2DFFFF

C SA99 32K 2E0000 - 2E7FFF

C SA100 32K 2E8000 - 2EFFFF

C SA101 32K 2F0000 - 2F7FFF

D SA102 32K 2F8000 - 2FFFFF

D SA103 32K 300000 - 307FFF

D SA104 32K 308000 - 30FFFF

D SA105 32K 310000 - 317FFF

D SA106 32K 318000 - 31FFFF

D SA107 32K 320000 - 327FFF

D SA108 32K 328000 - 32FFFF

D SA109 32K 330000 - 337FFF

D SA110 32K 338000 - 33FFFF

D SA111 32K 340000 - 347FFF

D SA112 32K 348000 - 34FFFF

Memory Org anization – 64-Mbit Bottom Boot (Contin ued)

Plane Sector Size

(Words)

x16

Address Range

(A21 - A0)

D SA113 32K 350000 - 357FFF

D SA114 32K 358000 - 35FFFF

D SA115 32K 360000 - 367FFF

D SA116 32K 368000 - 36FFFF

D SA117 32K 370000 - 377FFF

D SA118 32K 378000 - 37FFFF

D SA119 32K 380000 - 387FFF

D SA120 32K 388000 - 38FFFF

D SA121 32K 390000 - 397FFF

D SA122 32K 398000 - 39FFFF

D SA123 32K 3A0000 - 3A7FFF

D SA124 32K 3A8000 - 3AFFFF

D SA125 32K 3B0000 - 3B7FFF

D SA126 32K 3B8000 - 3BFFFF

D SA127 32K 3C0000 - 3C7FFF

D SA128 32K 3C8000 - 3CFFFF

D SA129 32K 3D0000 - 3D7FFF

D SA130 32K 3D8000 - 3DFFFF

D SA131 32K 3E0000 - 3E7FFF

D SA132 32K 3E8000 - 3EFFFF

D SA133 32K 3F0000 - 3F7FFF

D SA134 32K 3F8000 - 3FFFFF

Memory Or ganization – 64 -Mbit Bottom Boot ( Continued)

Plane Sector Size

(Words)

x16

Address Range

(A21 - A0)

16 AT52BR6408A(T) 3425A–STKD–1/04

Memory Organization – 64-Mbit Top Boot

Plane Sector Size

(Words)

x16

Address Range

(A21 - A0)

D SA0 32K 00000 - 07FFF

D SA1 32K 08000 - 0FFFF

D SA2 32K 10000 - 17FFF

D SA3 32K 18000 - 1FFFF

D SA4 32K 20000 - 27FFF

D SA5 32K 28000 - 2FFFF

D SA6 32K 30000 - 37FFF

D SA7 32K 38000 - 3FFFF

D SA8 32K 40000 - 47FFF

D SA9 32K 48000 - 4FFFF

D SA10 32K 50000 - 57FFF

D SA11 32K 58000 - 5FFFF

D SA12 32K 60000 - 67FFF

D SA13 32K 68000 - 6FFFF

D SA14 32K 70000 - 77FFF

D SA15 32K 78000 - 7FFFF

D SA16 32K 80000 - 87FFF

D SA17 32K 88000 - 8FFFF

D SA18 32K 90000 - 97FFF

D SA19 32K 98000 - 9FFFF

D SA20 32K A0000 - A7FFF

D SA21 32K A8000 - AFFFF

D SA22 32K B0000 - B7FFF

D SA23 32K B8000 - BFFFF

D SA24 32K C0000 - C7FFF

D SA25 32K C8000 - CFFFF

D SA26 32K D0000 - D7FFF

D SA27 32K D8000 - DFFFF

D SA28 32K E0000 - E7FFF

D SA29 32K E8000 - EFFFF

D SA30 32K F0000 - F7FFF

D SA31 32K F8000 - FFFFF

C SA32 32K 100000 - 107FFF

C SA33 32K 108000 - 10FFFF

C SA34 32K 110000 - 117FFF

C SA35 32K 118000 - 11FFFF

C SA36 32K 120000 - 127FFF

C SA37 32K 128000 - 12FFFF

C SA38 32K 130000 - 137FFF

C SA39 32K 138000 - 13FFFF

C SA40 32K 140000 - 147FFF

C SA41 32K 148000 - 14FFFF

C SA42 32K 150000 - 157FFF

C SA43 32K 158000 - 15FFFF

C SA44 32K 160000 - 167FFF

C SA45 32K 168000 - 16FFFF

C SA46 32K 170000 - 177FFF

C SA47 32K 178000 - 17FFFF

C SA48 32K 180000 - 187FFF

C SA49 32K 188000 - 18FFFF

C SA50 32K 190000 - 197FFF

C SA51 32K 198000 - 19FFFF

C SA52 32K 1A0000 - 1A7FFF

C SA53 32K 1A8000 - 1AFFFF

C SA54 32K 1B0000 - 1B7FFF

C SA55 32K 1B8000 - 1BFFFF

C SA56 32K 1C0000 - 1C7FFF

C SA57 32K 1C8000 - 1CFFFF

C SA58 32K 1D0000 - 1D7FFF

C SA59 32K 1D8000 - 1DFFFF

C SA60 32K 1E0000 - 1E7FFF

C SA61 32K 1E8000 - 1EFFFF

C SA62 32K 1F0000 - 1F7FFF

C SA63 32K 1F 8000 - 1FFF FF

B SA64 32K 200000 - 207FFF

B SA65 32K 208000 - 20FFFF

B SA66 32K 210000 - 217FFF

B SA67 32K 218000 - 21FFFF

B SA68 32K 220000 - 227FFF

B SA69 32K 228000 - 22FFFF

B SA70 32K 230000 - 237FFF

B SA71 32K 238000 - 23FFFF

B SA72 32K 240000 - 247FFF

B SA73 32K 248000 - 24FFFF

B SA74 32K 250000 - 257FFF

B SA75 32K 258000 - 25FFFF

B SA76 32K 260000 - 267FFF

B SA77 32K 268000 - 26FFFF

B SA78 32K 270000 - 277FFF

B SA79 32K 278000 - 27FFFF

B SA80 32K 280000 - 287FFF

B SA81 32K 288000 - 28FFFF

B SA82 32K 290000 - 297FFF

B SA83 32K 298000 -29FFFF

B SA84 32K 2A0000 - 2A7FFF

B SA85 32K 2A8000 - 2AF FFF

B SA86 32K 2B0000 - 2B7FFF

B SA87 32K 2B8000 - 2BF FFF

B SA88 32K 2C0000 - 2C7FFF

B SA89 32K 2C8000 - 2CFFFF

Memory Organiza tion – 64-Mbit Top Boot (Continued)

Plane Sector Size

(Words)

x16

Address Range

(A21 - A0)

AT52BR6408A(T)

3425A–STKD–1/04

B SA90 32K 2D0000 - 2D7FFF

B SA91 32K 2D8000 - 2DFFFF

B SA92 32K 2E0000 - 2E7FFF

B SA93 32K 2E8000 - 2EFFFF

B SA94 32K 2F0000 - 2F7FFF

B SA95 32K 2F8000 - 2FFFFF

A SA96 32K 300000 - 307FFF

A SA97 32K 308000 - 30FFFF

A SA98 32K 310000 - 317FFF

A SA99 32K 318000 - 31FFFF

A SA100 32K 320000 - 327FFF

A SA101 32K 328000 - 32FFFF

A SA102 32K 330000 - 337FFF

A SA103 32K 338000 - 33FFFF

A SA104 32K 340000 - 347FFF

A SA105 32K 348000 - 34FFFF

A SA106 32K 350000 - 357FFF

A SA107 32K 358000 - 35FFFF

A SA108 32K 360000 - 367FFF

A SA109 32K 368000 - 36FFFF

A SA110 32K 370000 - 377FFF

A SA111 32K 378000 - 37FFFF

A SA112 32K 380000 - 387FFF

Memory Organization – 64-Mbit Top Boot (Continued)

Plane Sector Size

(Words)

x16

Address Range

(A21 - A0) A SA113 32K 388000 - 38FFFF

A SA114 32K 390000 - 397FFF

A SA115 32K 398000 - 39F FFF

A SA116 32K 3A0000 - 3A7F FF

A SA117 32K 3A8000 - 3AFFFF

A SA118 32K 3B0000 - 3B7F FF

A SA119 32K 3B8000 - 3BFFFF

A SA120 32K 3C0000 - 3C7FFF

A SA121 32K 3C8000 - 3CFFFF

A SA122 32K 3D0000 - 3D7FFF

A SA123 32K 3D8000 - 3DFFFF

A SA124 32K 3E0000 - 3E7F FF

A SA125 32K 3E8000 - 3EFFFF

A SA126 32K 3F0000 - 3F7FFF

A SA127 4K 3F8000 - 3F8FF F

A SA128 4K 3F9000 - 3F9FF F

A SA129 4K 3FA000 - 3FAFFF

A SA130 4K 3FB000 - 3FBFFF

A SA131 4K 3F C000 - 3FCFFF

A SA132 4K 3F D000 - 3FDFFF

A SA133 4K 3FE000 - 3FEFFF

A SA134 4K 3FF000 - 3FFFFF

Memory Organization – 64-Mbit Top Boot (Continued)

Plane Sector Size

(Words)

x16

Address Range

(A21 - A0)

18 AT52BR6408A(T) 3425A–STKD–1/04

Notes: 1. X can be VIL or VIH.

2. Refer to AC programming waveforms.

3. Manufacturer Code: 001FH; Device Code: 00D6H – Bottom Boot; 00D2H – Top Boot.

4. See details under “Software Product Identification Entry/Exit” on page 24.

5. The VPP pin can be tied to VCC. For faster program/erase operations, VPP can be set to 12.0V ± 0.5V.

6. VIHPP (min) = 1.65V.

7. VILPP (max) = 0.8V.

DC and AC Operating Rang e

64-Mbit Device – 70, 85 ns

Operating Temperature (Case) Industrial -40°C - 85°C

VCC Power Supply 2.7V - 3.6V

Operating Modes

Mode CE OE WE RESET VPP(5) Ai I/O

Read VIL VIL VIH VIH XAi D

OUT

Burst Read VIL VIL VIH VIH XAi D

OUT

Program/Erase(3) VIL VIH VIL VIH VIHPP(6) Ai DIN

Standb y /Pro g r a m Inhibi t VIH X(1) XV

IH XX High Z

Program In hibit

XXV

IH VIH X

IL XV

IH X

XXX X V

ILPP(7)

Output Disable X VIH XV

IH XHigh Z

Reset XXX V

IL XX High Z

Product Identification

Software(4) VIH A0 = VIL, A1 - A21 = VIL Manufacturer Code(3)

A0 = VIH, A1 - A21 = VIL Device Code(3)

AT52BR6408A(T)

3425A–STKD–1/04

Note: 1. In the erase mode, ICC is 50 mA.

Input Test Waveforms and Measurement Level

tR, tF < 5 ns

Output Test Load

Note: 1. This parameter is characterized and is not 100% tested.

DC Characteristics

Symbol Parameter Condition Min Max Units

ILI Input Load Current VIN = 0V to VCC 1µA

ILO Output Leakage Current VI/O = 0V to VCC 1µA

ISB1 VCC Standby Current CMOS CE = VCCQ - 0.3V to VCC 10 µA

ICC(1) VCC Active Current f = 66 MHz; IOUT = 0 mA 30 mA

ICCRE VCC Read While Erase Current f = 66 MHz; IOUT = 0 mA 50 mA

ICCRW VCC Read While Write Current f = 66 MHz; IOUT = 0 mA 50 mA

VIL Input Low Voltage 0.6 V

VIH Input High Voltage 2.0 V

VOL Output Low Voltage IOL = 2.1 mA 0.45 V

VOH Output High Voltage IOH = -100 µA 2.5 V

IOH = -400 µA 2.4

DRIVING

LEVELS

2.0V

0.6V

1.5V AC

MEASUREMENT

LEVEL

1.8K

OUTPUT

30 pF

1.3K

Pin Capacitance

f = 1 MHz, T = 25°C(1)

Typ Max Units Conditions

CIN 46 pF V

IN = 0V

COUT 812 pF V

OUT = 0V

20 AT52BR6408A(T) 3425A–STKD–1/04

Asynchronous Read Cycle Waveform(1)(2)(3)

Notes: 1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC.

2. OE may be de layed up to tCE - tOE after the falling edge of CE witho u t im pa ct on tCE or by tACC - tOE after an address change

without impact on tACC.

3. tDF is specified from OE or CE, whichever occurs first (CL = 5 pF).

AC Asynchr o nous Read Timing Characteristi cs

Symbol Parameter

64-Mbit-70 64-Mbit-85

UnitsMinMaxMinMax

tACC Ac cess, Addres s to Data Valid 70 85 ns

tCE Access, CE to D a ta Valid 70 85 ns

tOE OE to Data Valid 20 20 ns

tDF CE, OE High to Data Float 25 25 ns

tRO RESET to Output Delay 150 150 ns

OUTPUT

VALID

I/O0 - I/O15 HIGH Z

RESET

OE tOE

tCE

ADDRESS VALID

tDF

tOH

tACC

tRO

A0 - A21

tRC

AT52BR6408A(T)

3425A–STKD–1/04

AC Word Load Waveforms

WE Controlled

CE Controlled

AC Word Load Characteristics

Symbol Parameter Min Max Units

tAS Address Setup Time to WE and CE Low 0 ns

tAH Address Hold Time 20 ns

tDS Data Setup Time 20 ns

tDH Data Hold Time 0 ns

tWP CE or WE Low Pulse Width 35 ns

tWPH CE or WE High Pulse Width 25 ns

tDS

tAH tDH

tWP

D AT A VALID

I/O0-I/O15

A0 -A21

WE tAS

tDS tDH

tWP

D AT A VALID

I/O0-I/O15

A0 -A21

tAS tAH

22 AT52BR6408A(T) 3425A–STKD–1/04

Program Cycle Waveforms

Sector, Plane or Chip Erase Cycl e Waveforms

Notes: 1. OE must be high only when WE and CE are both low.

2. For chip erase, the address should be 555. For plane or sector erase, the address depends on what plane or sector is to be

erased. (See note 4 and 6 under Command Definitions on page 12.)

3. For chip erase, t he d ata should be XX10 H , for pl ane er as e , the data should be XX2 0H , a nd for sector er as e , th e d ata should

be XX30H

4. The waveform s shown a bove use the WE controlled AC Word Load Waveforms.

Program Cyc le Characteristics

Symbol Parameter Min Typ Max Units

tBP Word Programming Time (Vpp = VCC)22µs

tBPVPP Word Programming Time (VPP > 11.5V) 10 µs

tSEC1 Sector Erase Cycle Time (4K word sectors) 100 ms

tSEC2 Sector Erase Cycle Time (32K word sectors) 500 ms

tES Erase Suspend Time 15 µs

tPS Program Suspend Time 10 µs

INPUT

DATA

XXAA

I/O0 -I/O15 XX55 XXA0

A0 -A21 ADDR

555 AAA 555

OE(1)

XXAA

I/O0 -I/O15 XX55 XX80

A0 -A21 555

555 AAA 555

XX55 Note3

AAA Note2

AT52BR6408A(T)

3425A–STKD–1/04

Notes: 1. These parameters are characterized and not 100% tested.

2. See tOE spec on page 20.

Data Polling Waveforms

Notes: 1. These parameters are characterized and not 100% tested.

2. See tOE spec on page 20.

Toggle Bit Wavefor ms(1)(2)(3)

Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit.

The tOEHP specification must be met by the toggling input(s).

2. Beginning and ending state of I/O6 will vary.

3. Any address location may be used but the address should not vary.

Data Polling Characteristics

Symbol Parameter Min Typ Max Units

tDH Data Hold Time 10 ns

tOEH OE Hold Time 10 ns

tOE OE to Output Delay(2) ns

tWR Write Recovery Time 0 ns

A0-A21

I/O7

Toggle Bit Characteristics(1)

Symbol Parameter Min Typ Max Units

tDH Data Hold Time 10 ns

tOEH OE Hold Time 10 ns

tOE OE to Output Delay(2) ns

tOEHP OE High Pulse 50 ns

tWR Write Recovery Time 0 ns

24 AT52BR6408A(T) 3425A–STKD–1/04

Software Pro duct Identification

Entry(1)

LOAD DATA AA

ADDRESS 555

LOAD DATA 55

ADDRESS AAA

LOAD DATA 90

ADDRESS xxx

(7)

ENTER PRODUCT

IDENTIFICATION

MODE

(2)(3)(5)

Software Product Identificatio n Exit(1)(6)

LOAD DATA AA

ADDRESS 555

LOAD DATA 55

ADDRESS AAA

LOAD DATA F0

ADDRESS 555

EXIT PRODUCT

IDENTIFICATION

MODE

(4)

OR LOAD DATA F0

ANY ADDRESS

EXIT PRODUCT

IDENTIFICATION

MODE

(4)

Notes: 1. Data Format: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0 (Hex) Address Format: A11 - A0 (Hex); A12 - A21 (Don’t Care).

2. A1 - A21 = VIL.

Manufacturer Code is read for A0 = VIL;

Device Code is read for A0 = VIH.

3. The device does not remain in identification mode if powered down.

4. The device returns to standard operation mode.

5. Manufactur er Code: 001FH

Device Code: 00D6H – Bottom Boot; 00D2H – Top Boot.

6. Either one of the Product ID Exit commands can be used.

7. For the 64-Mbit Bottom Boot: For the 64-Mbit Top Boot:

xxx = 0XX555 Status Read from Plane A xxx = 3XX555 Status Read from Plane A

xxx = 1XX555 Status Read from Plane B xxx = 2XX555 Status Read from Plane B

xxx = 2XX555 Status Read from Plane C xxx = 1XX555 Status Read from Plane C

xxx = 3XX555 Status Read from Plane D xxx = 0XX555 Status Read from Plane D

If a read status has been entered for a plane, any read from this plane will be a status read while any read of another plane

will be a memory read, either random or burst. Program or erase operations cannot be performed while one of the planes is

in the read status mode.

AT52BR6408A(T)

3425A–STKD–1/04

Table 4. Common Flash Interface Definition for 64-Mbit Device

Address 64-Mbit D evice Comments

10h 0051h “Q”

11h 0052h “R”

12h 0059h “Y”

13h 0002h

14h 0000h

15h 0041h

16h 0000h

17h 0000h

18h 0000h

19h 0000h

1Ah 0000h

1Bh 0027h VCC min write/erase

1Ch 0031h VCC max write/erase

1Dh 00B5h VPP min vo lta ge

1Eh 00C5h VPP max volt age

1Fh 0004h Typ word write – 16 µs

20h 0000h

21h 0009h Typ block erase – 500 ms

22h 0010h Typ chip erase, 64,300 ms

23h 0004h Max word write/typ time

24h 0000h n/a

25h 0003h Max block erase/typ block erase

26h 0003h Max chip erase/ typ chip erase

27h 0017h Device size

28h 000 1h x16 device

29h 000 0h x16 device

2Ah 0000h Multiple byte write not supported

2Bh 0000h Multiple byte write not supported

2Ch 0002h 2 regions, x = 2

2Dh 007Eh 64K bytes, Y = 126

2Eh 0000h 64K bytes, Y = 126

2Fh 0000h 64K bytes, Z = 256

30h 0001h 64K bytes, Z = 256

31h 0007h 8K bytes, Y = 7

32h 0000h 8K bytes, Y = 7

33h 0020h 8K bytes, Z = 32

34h 0000h 8K bytes, Z = 32

26 AT52BR6408A(T) 3425A–STKD–1/04

VENDOR SPECIFIC EXTENDED QUERY

41h 0050h “P”

42h 0052h “R”

43h 0049h “I”

44h 0031h Major version number, AS CII

45h 0030h Minor version number, ASCII

46h 008Fh Bit 0 – chip erase supported, 0 – no, 1 – yes

Bit 1 – erase suspend suppor ted, 0 – no, 1 – yes

Bit 2 – program suspend supported, 0 – no, 1 – yes

Bit 3 – simultaneous operations supported, 0 – no, 1 – yes

Bit 4 – burst mode read supported, 0 – no, 1 – yes

Bit 5 – page mode read supported, 0 – no, 1 – yes

Bit 6 – queued erase supported, 0 – no, 1 – yes

Bit 7 – protection bits supported, 0 – no, 1 – yes

47h 0000h Top Boot or 0001h

Bottom Boot Bit 0 – top (“0”) or bottom (“1”) boot block device

Undefi ned bits are “0”

48h 0000h Bit 0 – 4 word linear burst with wrap around, 0 – no, 1 – yes

Bit 1 – 8 word linear burst with wrap around, 0 – no, 1 – yes

Bit 2 – continuos burst, 0 – no, 1 – yes

Undefi ned bits are “0”

49h 0000h Bit 0 – 4 word page, 0 – no, 1 – yes

Bit 1 – 8 word page, 0 – no, 1 – yes

Undefi ned bits are “0”

4Ah 0080h Location of protection register lock byte, the section's first byte

4Bh 0003h # of bytes in the factory prog section of prot register – 2*n

4Ch 0003h # of bytes in the user prog section of prot register – 2*n

Table 4. Common Flash Interface Definition for 64-Mbit Device (Continued)

Address 64-Mbit D evice Comments

AT52BR6408A(T)

3425A–STKD–1/04

8-megabit SRAM

Description The 8-megabit SRAM is a high-speed, super low-power CMOS SRAM organized as

512K wor ds by 16 bits. The SRAM us es high- perform ance full CMOS proce ss techno l-

ogy and is de signed for high-spee d and low-power circuit technology. It is particularly

well-sui ted for the high-de nsity low- power sy stem applic ation. Th is devi ce has a data

retention mode that guarantees data to remain valid at a minimum power supply voltage

of 1.2V.

Features •Fully Static Operation and Tri-state Output

•TTL Compatible Inputs and Outputs

•Battery Backup

– 1.2V (Min) Data Retention

Block Diag ram

Voltage (V) Speed (ns)

Operation

Current/ICC (mA)

(Max)

Standby

Current (µA)

(Max) Temperature

(°C)

2.7 - 3.1 70 3 15 -40 - 85

MEMORY ARRAY

512K X 16

I/O0

SUB

SLB

SOE

SCS2

SCS1

SWE

DATA I/O BUFFER

SENSE AMP WRITE DRIVER

I/O7

I/O8

I/O15

ROW DECODER

COLUMN

DECODER

BLOCK

DECODER

PRE DECODER

ADD INPUT BUFFER

A18

28 AT52BR6408A(T) 3425A–STKD–1/04

Note: 1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause per manent damage to the device. This is

stress rating o nl y an d th e fu nct ion al opera tio n of t he d evice under the se o r any other con di tions abo ve thos e in di cat ed in the

operation of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may

affect reliability.

Notes: 1. H = VIH, L = VIL, X = Don't Care (VIL or VIH)

2. SUB, SLB (Upper, Lower Byte Enable). These active LOW inputs allow individual bytes to be written or read. When SLB is

LOW, data is written or read to the lower byte, I/O0 - I/O7. When SUB is LOW, data is written or read to the upper byte, I/O8

- I/O15.

Note: 1. Undershoot: VIL = -1.5V for pulse width less than 30 ns. Undershoot is sampled, not 100% tested.

Absolute Maxim u m Ratings(1)

Symbol Parameter Rating Unit

VIN, VOUT Input/Output Voltage -0.3 to 3.6 V

VCC Power Supply -0.3 to 3.6 V

TAOperating Temperature -40 to 85 °C

TSTG Storage Te mperature -55 to 150 °C

PDPower Dissipation 1.0 W

Truth Table

SCS1 SCS2 SWE SOE SLB(2) SUB(2) Mode

I/O Pin

PowerI/O0 - I/O7 I/O8 - I/O15

H(1) X

XXXXDeselected High-Z High-Z StandbyX(1) L

XX HH

L(1) HHH

Output Disabled High-Z High-Z ActiveHL

LHLX

Write

DIN High-Z

Active

HL High-Z D

LL DIN DIN

DIN High-Z

LHHL

Read

DOUT High-Z

Active

HL High-Z D

OUT

LL DOUT DOUT

DOUT High-Z

Recommended DC Operating Condition

Symbol Parameter Min Typ Max Unit

VCC Supply Voltage 2.7 3.0 3.1 V

VSS Ground 0 0 0 V

VIH Input High Voltage 2.2 VCC + 0.3 V

VIL(1) Input Low Voltage -0.3(1) 0.6 V

AT52BR6408A(T)

3425A–STKD–1/04

Note: 1. These parameters are sampled and not 100% tested.

DC Electrical Characteristics

TA = -40°C to 85°C

Symbol Parameter Test Condition Min Max Unit

ILI Input Leakage Current VSS < VIN < VCC -1 1 µA

ILO Output Leakage Current VSS < VOUT < VCC,

SCS1 = VIH or SCS2=VIL or

SOE = VIH or SWE = VIL or

SUB = VIH, SLB = VIH

-1 1 µA

ICC Operating Power Supply Current SCS1 = VIL, SCS2=VIH,

VIN = VIH or VIL, II/O = 0 mA 3mA

ICC1 Average Operating Current SCS1 = VIL, SCS2 = VIH,

VIN = VIH or VIL, Cycle Time = Min

100% Duty, II/O = 0 mA

15 mA

SCS1 < 0.2V, SCS2 > VCC - 0.2V

VIN < 0.2V or VIN > VCC - 0.2V,

Cycle Time = 1 µs

100% Duty, II/O = 0 mA

2mA

ISB Standby Current (TTL Input) SCS1 = VIH or SCS2 = VIL or

SUB, SLB = VIH

VIN = VIH or VIL

0.3 mA

ISB1 Standby Current (CMOS Input) SCS1 > VCC - 0.2V or

SCS2 < VSS + 0.2V or

SUB, SLB > VCC - 0.2V

VIN > VCC - 0.2V or

VIN < VSS + 0.2V

15 µA

VOL Output Low IOL = 2.1 mA 0.4 V

VOH Output High IOH = -1.0 mA 2.4 V

Capacitance(1)

(Temp = 25°C, f = 1.0 MHz)

Symbol Parameter Condition Max Unit

CIN Input Capacitance (Add, SCS1,

SCS2, SLB, SUB, SWE, SOE)VIN = 0 V 8 p F

COUT Output Capacitance (I/O) VI/O = 0 V 10 pF

30 AT52BR6408A(T) 3425A–STKD–1/04

AC Characteristics

TA = -40°C to 85°C, Unless Otherwise Specified

# Symbol Parameter

70 ns

UnitMin Max

RC Read Cycle Time 70 ns

AA Address Access Time 70 ns

ACS Chip Select Access Time 70 ns

OE Output Enable to Output Valid 35 ns

BA SLB, SUB Access Time 70 ns

CLZ Chip Select to Output in Low Z 10 ns

OLZ Output Enable to Output in Low Z 5 ns

BLZ SLB, SUB Enable to Output in Low Z 10 ns

CHZ Chip Deselection to Output in High Z 0 25 ns

10 tOHZ Out Disable to Output in High Z 0 25 ns

11 tBHZ SLB, SUB Disable to Output in High Z 0 25 ns

12 tOH Output Hold from Address Change 10 ns

13 tWC Write Cycle Time 70 ns

14 tCW Chip Selection to End of Write 60 ns

15 tAW Address Valid to End of Write 60 ns

16 tBW SLB, SUB Valid to End of Write 60 ns

17 tAS Address Setup Time 0 ns

18 tWP Write Pulse Width 50 ns

19 tWR Write Recovery Time 0 ns

20 tWHZ Write to Output in High Z 0 20 ns

21 tDW Data to Write Time Overlap 30 ns

22 tDH Data Hold from Write Time 0 ns

23 tOW Output Active from End of Write 5 ns

AC Test Conditions

TA = -40°C to 85°C, Unless Otherwise Specified

Parameter Value

Input Pulse Level 0.4V to 2.2V

Input Rise and Fall Time 5 ns

Input and Output Timing Reference Level 1.5V

Output Loa d tCLZ, tOLZ, tBLZ, tCHZ, tOHZ, tBHZ, tWHZ, tOW CL = 5 pF + 1 TTL Load

Ot hers CL = 30 pF + 1 TTL Load

AT52BR6408A(T)

3425A–STKD–1/04

AC Test Loads

Note: Including jig and scope capacitance.

DOUT

1728 Ohm

1029 Ohm

VTM = 2.8V

(1)

32 AT52BR6408A(T) 3425A–STKD–1/04

Timing Diagrams

Read Cycle 1(1),(4)

Read Cycle 2(1),(2),(4)

Read Cycle 3(1),(2),(4)

Notes: 1. Read Cycle occurs whenever a high on the SWE and SOE is low, while SUB and/or SLB and SCS1 and SCS2 are in active

status.

2. SOE = VIL.

3. Transition is measured ± 200 mV from steady state voltage. This parameter is sampled and not 100% tested.

4. SCS1 in high for the standby, low for active. SCS2 in low for the standby, high for active. SUB and SLB in high for the

st andby, low for active.

ADDRESS

SOE

SUB, SLB

SCS1

SCS2

DATA OUT HIGH-Z DATA VALID

tAA

tRC

tBA

tACS

tOE

tOLZ

tBLZ

tCLZ

tBHZ

tCHZ

tOH

tOHZ

(3)

DATA OUT

ADDRESS tAA

PREVIOUS DATA

tOH

DATA VALID

tOH

tRC

SUB, SLB

SCS1

SCS2

DATA OUT

ACS

CLZ(3)

DATA VALID

CHZ(3)

AT52BR6408A(T)

3425A–STKD–1/04

Writ e Cy cle 1 (SWE Controlled)(1),(4),(8)

Writ e Cy cle 2 (SCS1, SCS2 Controlled)(1),(4),(8)

Notes: 1. A write occurs during the overlap of a low SWE, a low SCS1, a high SCS2 and a low SUB and/or SLB.

2. tWR is measured from the earlier of SCS1, SLB, SUB, or SWE going high or SCS2 going low to the end of write cycle.

3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the output must not be

applied.

4. If the SCS1, SLB and SUB low transitio n an d SC S2 hi gh transition o ccur s im u lta neo us ly wi th the SWE low trans it ion or after

the SWE transition, outputs remain in a high impedance state.

5. Q (data out) is the same phase with the write data of this write cycle.

6. Q (data out) is the read data of the next address.

7. Transition is measured ± 200 mV from steady state. This parameter is sampled and not 100% tested.

8. SCS1 in hig h f or the s tandb y, low f or acti v e SCS2 in lo w f or th e stand b y, high for act iv e . SUB and SLB in high for the standb y,

low for active.

ADDRESS

SWE

SUB, SLB

DATA IN

SCS1

SCS2

DATA OUT

tWC

tCW

tAW

tBW

tWP

tAS

tWHZ

tWR

tDW tDH

tOW

DATA VALID

HIGH-Z

tAS

(2)

(5) (5)

(3)(7)

ADDRESS

SWE

SUB, SLB

DATA IN

SCS1

SCS2

DATA OUT

tWC

tCW

tAW

tBW

tWP

tAS tWR

tDW tDH

DATA VALID

HIGH-Z

(2)

HIGH-Z

34 AT52BR6408A(T) 3425A–STKD–1/04

Notes: 1. Typical values are under the condition of TA = 25°C. Typical values are sampled and not 100% tested.

2. tRC is read cycle time.

Data Retention Timing Diagram 1

Data Retention Timing Diagram 2

Data Retention Electri c Character istic

TA = -4 0 °C to 85°C

Symbol Parameter Test Condition Min Typ Max Unit

VDR VCC for Data Retention SCS1 > VCC - 0.2V or

SCS2 < VSS + 0.2V or

SUB, SLB > VCC - 0.2V

VIN > VCC - 0.2V or

VIN < VSS + 0.2V

1.2 3.3 V

ICCDR Data Retention Current VCC = 3V,

SCS1 > VCC - 0.2V or

SCS2 < VSS + 0.2V or

SUB, SLB > VCC - 0.2V

VIN > VCC - 0.2V or

VIN < VSS + 0.2V

18µA

tCDR Chip Deselect to Data

Retention Time See Data Retention Timing Diagram 0 ns

tROperat ing Recovery Time tRC ns

DATA RETENTION MODE

tCDR

VCC

SCS1 > VCC - 0.2V

2.7V

VDR

SCS1

VSS

VCC

2.7V

VDR

SCS2

VSS

0.4V

DATA RETENTION MODE

tCDR

SCS2 < 0.2V

AT52BR6408A(T)

3425A–STKD–1/04

Ordering Information

tACC

(ns) Ordering Code Flash Boot

Block SRAM Package Operation Range

70 AT52BR6408A-70CI Bottom 512K x 16 66C4 Industrial

(-40° to 85°C)

AT52BR6408AT-70CI Top 512K x 16 66C4 Industrial

(-40° to 85°C)

85 AT52BR6408A-85CI Bottom 512K x 16 66C4 Industrial

(-40° to 85°C)

AT52BR6408AT-85CI Top 512K x 16 66C4 Industrial

(-40° to 85°C)

Package Type

66C4 66-ball, Plastic Chip-size Ball Grid Array Package (CBGA)

36 AT52BR6408A(T) 3425A–STKD–1/04

Packagi ng Informat ion

66C4 – CBGA

2325 Orchard Parkway

San Jose, CA 95131

TITLE DRAWING NO.

REV.

66C4, 66-ball (12 x 8 Array), 11 x 8 x 1.2 mm Body, 0.8 mm Ball

Pitch Chip-scale Ball Grid Array Package (CBGA) A

66C4

08/29/01

Side View

T op View

Bottom View

1.20 REF

1.10 REF

101112

Marked A1 Identifier

Øb

0.12

Seating Plane

A1 Ball Corner

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL MIN NOM MAX NOTE

A – – 1.20

A1 0.25 – –

D 10.90 11.00 11.10

D1 8.80 TYP

E 7.90 8.00 8.10

E1 5.60 TYP

e 0.80 TYP

b 0.40 TYP

Printed on recycled paper.

3425A–STKD–1/04 xM

Disclaimer: Atmel Cor poration makes no warranty for the use of its produc ts, other than those expressly contained in the Comp any’s standard

warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any

errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and

does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are

granted by the Company in connection with the s ale of Atmel produc ts, expressly or by implication. Atmel’s products are not aut horized for use

as critical components in life suppor t devices or systems.

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