Freescale Semiconductor, Inc. SEMICONDUCTOR TECHNICAL DATA Dual 1:10 Low-Voltage Differential ECL/PECL Clock Driver Freescale Semiconductor, Inc... The MC100EP220 is a dual low skew 1-to-10 differential driver, designed with clock distribution in mind. The VBB output provides a DC threshold bias for single ended sources. The VBB can be connected to the true input or the complementary input, the latter will produce an inverted output. If used, the VBB output should be bypassed to ground. * * * * * * * 225ps Max. Part-to-Part Skew Order this document by MC100EP220/D DATA SHEET !! MC100EP220 LOW-VOLTAGE DUAL 1:10 DIFFERENTIAL ECL/PECL CLOCK DRIVER 60ps Output-to-Output Skew Differential Design VBB Output Voltage and Temperature Compensated Outputs Low Voltage VEE Range of -2.375 to -3.8V 65k Input Pulldown Resistors The EP220 is specifically designed, modeled and produced with low TB SUFFIX skew as the key goal. Optimal design and layout serve to minimize gate- 52-LEAD LQFP PACKAGE to-gate skew within a device, and empirical modeling is used to EXPOSED PAD determine process control limits that ensure consistent tpd distributions CASE 1336 from lot to lot. The net result is a dependable, guaranteed low skew device. To ensure that the tight skew specification is met it is necessary that both pairs of the differential outputs are terminated into 50, even if only one side is being used. In applications which do not use all of the outputs, it is best to leave unused pairs open to minimize power consumption in the device. The MC100EP220, as with most other ECL devices, can be operated from a positive VCC supply in PECL mode. This allows the EP220 to be used for high performance clock distribution in +3.3V or +2.5V systems. Designers can take advantage of the EP220's performance to distribute low skew clocks across the backplane. In a PECL environment, series or Thevenin line terminations are typically used as they require no additional power supplies. For more information on using PECL, designers should refer to Motorola Application Note AN1406/D. 09/01 IDTTM Low-Voltage Dual 1:10 Differential ECL/PECL Clock Driver REV 1 Motorola, Inc. 2001 For1 More Information On This Product, Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc Go to: www.freescale.com 1 MC100EP220 MC100EP220 Freescale Semiconductor, MC100EP220 Low-Voltage Dual 1:10 Differential ECL/PECL Clock Driver NETCOM MC100EP220 Freescale Semiconductor, Inc... Inc. Pinout: 52-Lead LQFP (Top View) LOGIC SYMBOL W W W W W W IDTTM Low-Voltage Dual 1:10 Differential ECL/PECL Clock Driver MOTOROLA 2 For acquired More Information On This Product, Freescale Timing Solutions Organization has been by Integrated Device Technology, Inc Go to: www.freescale.com 2 MC100EP220 TIMING SOLUTIONS MC100EP220 Freescale Semiconductor, Low-Voltage Dual 1:10 Differential ECL/PECL Clock Driver Inc. MC100EP220 NETCOM Table 1: PIN CONFIGURATION Pin I/O Type Function CLKA, CLKA Input ECL/LVPECL Differential reference clock signal input for fanout buffer A CLKB, CLKB Input ECL/LVPECL Differential reference clock signal input for fanout buffer B Q[0-19], Q[0-19] Output LVPECL Differential clock outputs VEEa Supply Negative power supply VCC, VCCO Supply Positive power supply. All VCC and VCCO pins must be connected to the positive power supply for correct DC and AC operation VBB Output DC bias output for single ended input operation a. In ECL mode (negative power supply mode), VEE is either -3.3V or -2.5V and VCC is connected to GND (0V). In PECL mode (positive power supply mode), VEE is connected to GND (0V) and VCC is either +3.3V or +2.5V. In both modes, the input and output levels are referrenced to the most positive supply (VCC). Freescale Semiconductor, Inc... Table 2: ABSOLUTE MAXIMUM RATINGSa Symbol Min Max Unit VCC Supply Voltage -0.3 4.6 V VIN DC Input Voltage -0.3 VCC+0.3 V DC Output Voltage -0.3 VCC+0.3 V DC Input Current 20 mA DC Output Current 50 mA 125 C VOUT IIN IOUT TS Characteristics Storage temperature -65 Condition a. Absolute maximum continuos ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied. Table 3: GENERAL SPECIFICATIONS Symbol Characteristics VTT Output termination voltage MM ESD Protection (Machine model) HBM CDM LU Min VCC - Max 2a Unit Condition V 75 V ESD Protection (Human body model) 1500 V ESD Protection (Charged device model) 500 V Latch-up immunity 200 CIN a. b. Typ mA 4.0 JA Thermal resistance junction to ambient See application JC Thermal resistance junction to case See application information pF Inputs informationb Output termination voltage VTT = 0V for VCC=2.5V operation is supported but the power consumption of the device will increase. Proper thermal management is critical for reliable system operation. This especially true for high-fanout and high drive capability products. Thermal package information and exposed pad land pattern design recommendations are available in the applications section of this datasheet. In addition, the means of calculating die power consumption, the corresponding die temperature and the relationship to long-term reliability is addressed in the Motorola application note AN1545. Thermal modeling is recommended for the MC100EP220. IDTTM Low-Voltage Dual 1:10 Differential ECL/PECL Clock Driver TIMING SOLUTIONS 3 For acquired More Information On This Product, Freescale Timing Solutions Organization has been by Integrated Device Technology, Inc Go to: www.freescale.com 3 MC100EP220 MOTOROLA MC100EP220 Freescale Semiconductor, MC100EP220 Low-Voltage Dual 1:10 Differential ECL/PECL Clock Driver Inc. NETCOM Table 4: PECL DC Characteristics (VCCO = VCC = 2.375V to 3.8V, VEE = GND) Symbol y TA = -40C Characteristics Min TA = 25C Max Min TA = 85C Max Min Unit Condition Max Clock input pair CLKA, CLKA, CLKB, CLKB (LVPECL differential signals) VPP VCMR Differential input voltagea VCC=3.3V VCC=2.5V 0.10 0.15 Differential cross point CLKA, CLKB voltageb 1.0 0.10 0.15 VCC-0.4 0.10 0.15 1.0 VCC-0.4 V V 1.0 VCC-0.4 V All inputs (LVPECL single ended signals) VIH Input high voltage VIL Input low voltage IIH Input Current VCC-1.14 VCC-1.14 VCC-1.14 V VCC-1.46 VCC-1.46 VCC-1.46 V 150 150 150 A VIN = VCC to VEE Freescale Semiconductor, Inc... LVPECL clock outputs (Q0-19, Q0-19) VOH Output High Voltage VCC-1.20 VCC-0.82 VCC-1.15 VCC-0.82 VCC-1.15 VCC-0.82 V IOH= -30mAc VOL Output Low Voltage VCC-1.90 VCC-1.40 VCC-1.90 VCC-1.40 VCC-1.9 VCC-1.40 V IOL= -5mAc Supply current and VBB IEE Max. Supply Current 190 190 190 mA VEE pin ICC Max. Supply Currentd 750 750 750 mA VCC pins VCC-1.24 V VBB a. b. c. d. e. Output reference voltagee VCC-1.36 VCC-1.24 VCC-1.36 VCC-1.24 VCC-1.36 VPP is the minimum differential input voltage swing required to maintain device functionality. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR (DC) range and the input swing lies within the VPP (DC) specification. Equivalent to an output termination of 50 to VTT. ICC includes current through the output resistors (all outputs terminated 50W to VTT). VBB output can be used to bias the complementary input when the device is used with single ended clock signals. VBB can sink max. 0.3 mA DC current. Table 5: ECL DC Characteristics (VCC = VCCO = GND, VEE = -3.8V to -2.375V) Symbol y Characteristics TA = -40C Min TA = 25C Max Min Max TA = 85C Min Unit Condition Max Clock input pair CLKA, CLKA, CLKB, CLKB for ECL differential signals VPP VCMR Differential input voltagea VEE=-3.3V VEE=-2.5V Differential cross point voltageb 0.10 0.15 VEE+1.0 0.10 0.15 -0.4 VEE+1.0 0.10 0.15 -0.4 VEE+1.0 V V -0.4 V All inputs ECL single ended signals VIH Input high voltage VIL Input low voltage IIH Input Current -1.14 -1.14 -1.14 V -1.46 -1.46 -1.46 V 150 150 150 A VIN = VEE to VCC LVPECL clock outputs (Q0-19, Q0-19) VOH Output High Voltage -1.20 -0.82 -1.15 -0.82 -1.15 -0.82 V IOH= -30 mAc VOL Output Low Voltage -1.90 -1.40 -1.90 -1.40 -1.90 -1.40 V IOL= -5 mAc Supply current and VBB a. b. c. d. e. IEE Max. Supply Current 190 190 190 mA VEE pin ICC Max. Supply Currentd 750 750 750 mA VCC Pins VBB Output reference voltagee -1.24 V -1.36 -1.24 -1.36 -1.24 -1.36 VPP is the minimum differential input voltage swing required to maintain device functionality. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR (DC) range and the input swing lies within the VPP (DC) specification. Equivalent to an output termination of 50 to VTT. ICC includes current through the output resistors (all outputs terminated 50W to VTT). VBB output can be used to bias the complementary input when the device is used with single ended clock signals. VBB can sink max. 0.3 mA DC current. IDTTM Low-Voltage Dual 1:10 Differential ECL/PECL Clock Driver MOTOROLA 4 For acquired More Information On This Product, Freescale Timing Solutions Organization has been by Integrated Device Technology, Inc Go to: www.freescale.com 4 MC100EP220 TIMING SOLUTIONS MC100EP220 Freescale Semiconductor, Low-Voltage Dual 1:10 Differential ECL/PECL Clock Driver Inc. MC100EP220 NETCOM Table 6: PECL/ECL AC Characteristicsa (VCC = VCCO = 2.375V to 3.8V, VEE = GND) or (VEE = -3.8V to -2.375V, VCC = VCCO = GND) Symbol y TA = -40C Characteristics Min Typ TA = 25C Max Min Typ TA = 85C Max Min Typ Unit Max Conditi tion Clock input pair CLKA, CLKA, CLKB, CLKB for PECL differential signals VPP VCMR fCLK Differential input voltageb (peak-to-peak) Differential cross point voltagec Input Frequency (PECL) 0.4 1.0 0.4 1.0 0.4 1.0 V 1.0 VCC-0.4 1.0 VCC-0.4 1.0 VCC-0.4 V 0 1.0 0 1.0 0 1.0 GHz V Clock input pair CLKA, CLKA, CLKB, CLKB for ECL differential signals Freescale Semiconductor, Inc... VPP Differential input voltage (peak-to-peak) 0.4 1.0 0.4 1.0 0.4 1.0 VCMR Differential cross point voltage VEE+1.0 -0.4 VEE+1.0 -0.4 VEE+1.0 -0.4 V fCLK Input Frequency (ECL) 0 1.0 0 1.0 0 1.0 GHz 500 350 450 550 425 535 650 ps 500 700 500 700 PECL/ECL clock outputs (Q0-19, Q0-19) tPD Propagation Delay CLKA or CLKB to Qx 300 400 VO(P-P) Differential output voltage (peak-to-peak) 450 700 tsk(O) Output-to-output skew (within device) tsk(PP) Output-to-output skew (part-to-part) tJIT(CC) Output cycle-to-cycle jitter (RMS) DCO Positive output pulse width tp - 50 tr, tf Output Rise/Fall Time 100 a. b. c. 35 60 35 200 35 200 TBD tp 60 TBD tp + 50 tp - 50 500 100 tp mV tp + 50 tp - 50 500 100 tp 60 ps Diff. 225 ps Diff. TBD ps tp + 50 ps tp input positive pulse width 500 ps 20% to 80% AC characteristics apply for parallel output termination of 50 to VTT. VPP (AC) is the minimum differential input voltage swing required to maintain AC characteristics including tpd and device-to-device skew. VCMR (AC) is the crosspoint of the differential input signal. AC operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (AC) specification. Violation of VCMR (AC) or VPP (AC) impacts the device propagation delay and part-to-part skew. $ % ! "# $ % W &' % $ % (' ) &' % '' '' Figure 1. MC100EP220 AC test reference +0 %/ )&%. / +0 , , *+ # # ,- Figure 2. MC100EP220 AC reference measurement waveform IDTTM Low-Voltage Dual 1:10 Differential ECL/PECL Clock Driver TIMING SOLUTIONS 5 For acquired More Information On This Product, Freescale Timing Solutions Organization has been by Integrated Device Technology, Inc Go to: www.freescale.com 5 MC100EP220 MOTOROLA MC100EP220 Freescale Semiconductor, MC100EP220 Low-Voltage Dual 1:10 Differential ECL/PECL Clock Driver Inc. NETCOM APPLICATIONS INFORMATION IIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I IIIIIIII I IIIIII II IIIIIIII I I IIIIII II I IIIIII II I IIIIIIII IIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIII ! 22 '12 3 4 * 5 -0 / 22 6710 / 22 82 56#!8 68 8 6 Figure 1. Recommended thermal land pattern The via diameter is should be approx. 0.3 mm with 1 oz. copper via barrel plating. Solder wicking inside the via resulting in voids during the solder process must be avoided. If the copper plating does not plug the vias, stencil print solder paste onto the printed circuit pad. This will supply enough solder paste to fill those vias and not starve the solder joints. The attachment process for exposed pad package is equivalent to standard surface mount packages. Figure 2. "Recommended solder mask openings" shows a recommend solder mask opening with respect to the recommended 5 x 5 thermal via array. Because a large solder mask opening may result in a poor release, the opening should be subdivided as shown in Figure 2. For the nominal package standoff 0.1 mm, a stencil thickness of 5 to 8 mils should be considered. IIIIIIIIIIIIII IIIIIIIIIIIIII II IIIIIIIIIIIIII II IIIIIIIIIIIIII IIIIIIIIIIIIII IIIIIIIIIIIIII IIII IIIIIIIIII IIIIIIIIIIIIII IIIIIIIIIIIII II I II I II I IIIIIIIIII ! 22 / / / / The MC100EP220 uses a thermally enhanced exposed pad (EP) 52 lead LQFP package. The package is molded so that the leadframe is exposed at the surface of the package bottom side. The exposed metal pad will provide the low thermal impedance that supports the power consumption of the MC100EP220 high-speed bipolar integrated circuit and eases the power management task for the system design. A thermal land pattern on the printed circuit board and thermal vias are recommended in order to take advantage of the enhanced thermal capabilities of the MC100EP220. Direct soldering of the exposed pad to the thermal land will provide an efficient thermal path. In multilayer board designs, thermal vias thermally connect the exposed pad to internal copper planes. Number of vias, spacing, via diameters and land pattern design depend on the application and the amount of heat to be removed from the package. A nine thermal via array, arranged in a 3 x 3 array and using a 1.2 mm pitch in the center of the thermal land is the absolute minimum requirement for MC100EP220 applications on multi-layer boards. The recommended thermal land design comprises a 5 x 5 t h e r m a l v i a a r r a y a s s h o w n i n F i g u r e 1. "Recommended thermal land pattern", providing an efficient heat removal path. Freescale Semiconductor, Inc... Using the thermally enhanced package of the MC100EP220 '12 3 4 * 5 -0 / 22 6710 / 22 82 56#!8 68 8 6 Figure 2. Recommended solder mask openings For thermal system analysis and junction temperature calculation the thermal resistance parameters of the package is provided. For thermal system analysis and junction temperature calculation the thermal resistance parameters of the package is provided: Table 7: Thermal Resistancea ConvectionLFPM RTHJAb C/W RTHJAc C/W Natural 57.1 24.9 100 50.0 21.3 200 46.9 20.0 400 43.4 18.7 800 38.6 16.9 RTHJCd C/W RTHJBe C/W 15.8 9.7 a. Thermal data pattern with a 3 x 3 thermal via array on 2S2P boards (based on empirical results) b. Junction to ambient, single layer test board, per JESD51-6 c. Junction to ambient, four conductor layer test board (2S2P), per JES51-6 d. Junction to case, per MIL-SPEC 883E, method 1012.1 e. Junction to board, four conductor layer test board (2S2P) per JESD 51-8 It is recommended that users employ thermal modeling analysis to assist in applying the general recommendations to their particular application. The exposed pad of the MC100EP220 package does not have an electrical low impedance path to the substrate of the integrated circuit and its terminals. The thermal land should be connected to GND through connection of internal board layers. IDTTM Low-Voltage Dual 1:10 Differential ECL/PECL Clock Driver MOTOROLA 6 For acquired More Information On This Product, Freescale Timing Solutions Organization has been by Integrated Device Technology, Inc Go to: www.freescale.com 6 MC100EP220 TIMING SOLUTIONS MC100EP220 Freescale Semiconductor, Low-Voltage Dual 1:10 Differential ECL/PECL Clock Driver Inc. MC100EP220 NETCOM OUTLINE DIMENSIONS TB SUFFIX PLASTIC LQFP PACKAGE CASE 1336-01 ISSUE O 4X / > +C AB 4X 13 TIPS X=A, B OR D X / +C D AB 52 40 1 39 Freescale Semiconductor, Inc... e 48X B VIEW Y VIEW Y E1 E b1 PLATING A E1/2 13 14 CCC EEEE EEEE CCC E/2 8 27 BASE METAL 8 c c1 26 8 b 8 D1/2 SECTION AB-AB ROTATED 90 CLOCKWISE D/2 D1 D H / J b +C 52X C 52X Z2 4X A SEATING PLANE / ) 4X J Z3 VIEW AA S Z1 R1 A2 Z R2 A1 G L L1 VIEW AA F EXPOSED PAD VIEW J-J 9':; / + <)9:<9: +& <9 )<<)'&:/ / <9'&&' <)9:<9: +9 '&+9: & +:) = / )0 / / +'(): +0 +9 ' '&)<9 +' +'() +9 >/ / <)9:<9: +9 ' '&)<9 +' :+'<9" +9 / / <)9:<9 : 9' <9( +)+& &'&(:<9/ +?+ +)+& &'&(:<9 :>+ 9' +(: '> + ?<'> ' , '> )+,<)() <)9:<9 = )& '>+9 / 22/ +)+& +99' +' 9 '> ?& &+<(: & '> @'/ )<9<)() :+ '?9 &'&(:<9 +9 +A+9' + & &'&(:<9 / 22/ / <)9:<9: +9 9' <9( ) &'&(:<9/ +?+ &'&(:<9 <: / 22 & :</ +9 +& )+,<)() +:'< = :<$ <)9:<9: <9(<9" ) )<:)+'>/ / ,+' :>+ @ +> &9& <: '<9+/ / '>: <)9:<9: += ' '> @+' :'<9 @ '> + '?9 / 22 +9 / 22 @&) '> + '</ DIM A A1 A2 b b1 c c1 D D1 e E E1 L L1 R1 R2 S F G Z Z1 Z2 Z3 IDTTM Low-Voltage Dual 1:10 Differential ECL/PECL Clock Driver TIMING SOLUTIONS 7 For acquired More Information On This Product, Freescale Timing Solutions Organization has been by Integrated Device Technology, Inc Go to: www.freescale.com 7 MILLIMETERS MIN MAX CCC / / / / / / / / / / / / / /B: /B: / B: /B: /B: / / /B&@ / CCC / / / CCC / / / / CCC MC100EP220 MOTOROLA MC100EP220 MPC92459 PART NUMBERS 900 Low-Voltage MHzPRODUCT LowDual Voltage 1:10 LVDS Differential Clock Synthesizer ECL/PECL Clock Driver INSERT NAME AND DOCUMENT TITLE NETCOM NETCOM Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support 800-345-7015 408-284-8200 Fax: 408-284-2775 netcom@idt.com 480-763-2056 Corporate Headquarters Asia Pacific and Japan Europe Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) Integrated Device Technology Singapore (1997) Pte. Ltd. Reg. No. 199707558G 435 Orchard Road #20-03 Wisma Atria Singapore 238877 +65 6 887 5505 IDT Europe, Limited Prime House Barnett Wood Lane Leatherhead, Surrey United Kingdom KT22 7DE +44 1372 363 339 (c) 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. 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