R2A20158NP - Renesas Electronics

New Product

R03DS0015EJ0100

Rev.1.00

2011.09.05

Page 1 of 8

R03DS0015EJ0100 Rev.1.00

2010.09.05

8-bit 8ch D/A Converter with Buffer Amplifiers for I2C BUS (Corresponds to Fast mode)

R2A20158NP

Description

The R2A20158NP is an integrated circuit semiconductor of CMOS structure with 8 channels of built in D/A

converters with output buffer operational amplifiers. It is the electrical characteristic improvement version

of the M62393.

The input is 2-wires serial method is used for the transfer format of digital data to allow connection with a

microcomputer with minimum wiring. This IC corresponds to Fast mode of I2C BUS standard.

The output buffer operational amplifier employs AB class output circuit with sync and source drive capacity of

1.0mA or more, and it operates in the whole voltage range from Vcc to ground.

Maximum 8 ICs can be connected to a bus by using 3-chip select pins, so that it is possible to handle up to

64 channels analog data.

Features

Guarantee Differential nonlinearity error : +/-0.7LSB, Nonlinearity error : +/-1.0LSB

Digital data transfer format: I2C BUS serial data method (corresponds to Fast mode: 400kHz)

Output buffer operational amplifier

It operates in the whole range from Vcc to ground.

High output current drive capacity: 1mA over

The very small size (4mmX4mm) QFN-20 package is added to the lineup.

Application

Conversion from digital data to analog control data for home-use and industrial equipment.

Signal gain control or automatic adjustment of LCD-TV, PDP-TV or LCD display-monitor.

Blurring correction control or various control of the interchangeable lens of digital camera

Block Diagram

8-bit upper

segment R-2R

8-bit latch

8-bit upper

segment R-2R

8-bit latch

8-bit upper

segment R-2R

8-bit latch

8-bit upper

segment R-2R

8-bit latch

Channel

decoder

Chip select

VDD

GNDAo5 Ao6 Ao7 Ao8 VrefU1

I2C BUS TRANCEIVER

CS0 CS1 CS2 Ao1 Ao2 Ao3 Ao4 VccVrefU2

VrefL

SDASCL

8-bit upper

segment R-2R

8-bit latch

8-bit upper

segment R-2R

8-bit latch

8-bit upper

segment R-2R

8-bit latch

8-bit upper

segment R-2R

8-bit latch

754321 61920

9141011121316 1518 17

RESET

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R2A20158NP

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R03DS0015EJ0100 Rev.1.00

2010.09.05

Pin Arrangement

Pin Description

Ao413

Ao52

Ao63

Serial clock input terminalSCL20

8-bit resolution D/A converter output terminal

(After power on, analog output of every channel is set in DAC data “00h”)

Ao312

D/A converter low level reference voltage input terminalVrefL

D/A converter high level reference voltage input terminal 1 (for ch5 to ch8)VrefU1

D/A converter high level reference voltage input terminal 2 (for ch1 to ch4)VrefU2

Chip select data input terminal 2 *1CS216

Chip select data input terminal 1 *1CS117

Serial data input terminalSDA1

Reset signal input terminal. A low state of RESET clear the all 8-bit latches.

RESET19

Ao74

Ao85

Analog power supply terminalVcc14

Ao110

Ao211

Chip select data input terminal 0 *1CS018

Analog and digital common GNDGND8

Digital power supply terminalVDD

FunctionPin NamePin No.

Outline: PWQN0020KB-A [NP]

R2A20158NP (Top view)

SDA

Ao5 Vcc

Ao4

VrefU2

Ao6

Ao7

VrefL

VDD

CS0

R2A20158NP

CS1

Ao8

Ao1

11 Ao2

10 CS2

Ao3

SCL

VrefU1 RESET

GND

*1 : This IC can be accessed only when the slave address (A0 to A2) coincides

with the chip select input (CS0 to CS2).

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R2A20158NP

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R03DS0015EJ0100 Rev.1.00

2010.09.05

-0.3 to VDD+0.3 6.5

VIN DDigital input voltage

mW/deg7.25Ta> +25degK thetaThermal derating factor

Tstg

Topr

IAO

VrefU1, VrefU2

VDD

Vcc

Symbol

Ta= +85deg

Continuous

Conditions

290Power dissipation

V-0.3 to < 6.5Upper reference voltage of D/A *1

mA-2.0 to +2.0Buffer amplifier output current

deg-40 to +125Storage temperature deg-30 to +85Operating temperature

V-0.3 to < 6.5Digital Supply voltage V-0.3 to +6.5Analog Supply voltage UnitRatingsItem

Absolute Maximum Ratings

Electrical Characteristics

*2 : The output does not necessary be the value with the reference voltage setting range.

The output value is determined by the buffer amplifier output voltage range (VAO).

VDD VrefU1, VrefU2

« Digital Part »

V0.4--IOL = 3 mAVOLOutput low voltage (SDA) VIN = 0 to Vcc

CLK = 500kHz operation, IAO =0 µA

Test conditions

V--0.8VDD

VIHInput high voltage V0.2VDD

--VILInput low voltage

µA10--10IILKInput leak current mA1.0--IDDSupply current V5.55.02.7VDDSupply voltage

Unit

MaxTypMin

SymbolItem Limits

« Analog Part »

VVcc-0.7Vcc

VrefU1,

VrefU2

D-A converter high level

reference voltage range *2

V0.3Vcc-GNDVrefL

D-A converter low level

reference voltage range *2

Buffer amplifier output impedance

Output capacitative load

Full scale error

Zero code error

Nonlinearity error

Differential nonlinearity error

Buffer amplifier output

current range

Buffer amplifier output

voltage range

D-A converter high level

reference voltage input current

Supply current

Supply Voltage

Item

VrefU1,VrefU2 = 4.79V,

VrefL = 0.95V,

Vcc = 5.5V (15mV/LSB),

Without load (IAO = 0µA)

Upper side saturation voltage = 0.3V,

Lower side saturation voltage = 0.2V

IAO = +/- 500 µA

IAO = +/- 100 µA

VtefU = 5V, VrefL = 0V,

Data condition: at maximum current

for each terminal

CLK=500kHz operation, IAO = 0µA

Test conditions

mA1.20.6-IrefU1, 2

V5.5-2.7Vcc

LSB0.7--0.7SDL

LSB1.0--1.0SL

LSB2.0--2.0SZERO

LSB2.0--2.0SFULL

ohm-5.0-Rp

µF0.1--Co

VVcc-0.2-0.2

mA1.0--1.0IAO

VVcc-0.1-0.1

VAO

mA1.20.4-Icc

Unit

MaxTypMin

Symbol Limits

(Vcc,VDD,VrefU1,V1refU2 = +5V +/-10%, Vcc VrefU1,VrefU2, GND=VrefL=0V, Ta=-30 to +85deg unless otherwise noted)

*1 VDD VrefU1, VrefU2

(Ta = 25 deg unless otherwise noted)

New Product

R2A20158NP

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R03DS0015EJ0100 Rev.1.00

2010.09.05

Timing Chart

SDA

VIH

VIL

SCL

VIH

VIL

Start Start StartStop

tR, tFtBUF

tHD:STA tSU:DAT tHD:DAT tSU:ST0

tLOW tHIGH

tsu:STA

tSU:STO

tSU:DAT

tHD:DAT

tSU:STA

tHIGH

tLOW

tHD:STA

tBUF

fSCL

Symbol Max.Min.

4.0

250

4.7

4.0

4.7

4.0

4.7

STANDARD MODE

400

300

1000

3.45

100

µs-0.6

Set-up time for START condition.

Only relevant for a repeated START condition.

ns300-Fall time of SDA and SCL signals

µs-0.6High perio d o f th e cl ock µs-1.3Low period of the clock

kHz4000SCL clock frequency

µs-1.3

Free time: the bus must be free before a new

transmission can start

µs-0.6

Hold time START condition after this period,

the first clock pulse is generated

µs0.90Data Hold time

pF400-Capacitive load of bus line

ns300-Rise time of SDA and SCL signals

µs-0.6Set-up time for STOP con dition

ns-100Data Set-up time

Max.Min. Unit

FAST MODE

Item

All of above value are corresponds to VIHmin and VILmax.

I2C BUS Line Characteristics

New Product

R2A20158NP

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R03DS0015EJ0100 Rev.1.00

2010.09.05

I2C BUS Format

STA STPAAAWSlave address Sub address DAC data

Note: STA: start condition, A: acknowledge bit, W: write (SDA=Low), STP: stop condition

A1 A0A21001

Slave address

S2 S1 S0S3XXXX

Sub address

Channel select data

ch8 selection0001 Don’t car e1001

::::

ch7 selection1110

ch3 selection1100 ch4 selection0010 ch5 selection1010 ch6 selection0110

S1 Don’t car e00 ch1 selection10

Don’t car e1

ch2 selection0

Channel selectionS0

Don’t care Channel select data

D2 D1 D0D3D4D5D6D7

DAC data

First

MSB Last

LSB

(VrefU –VrefL) / 256 x 3 + VrefL0000000

VrefU1111111 (VrefU –VrefL) / 256 x 255 + VrefL0111111

:::::::

(VrefU –VrefL) / 256 x 4 + VrefL1000000

(VrefU –VrefL) / 256 x 2 + VrefL1000000 (VrefU –VrefL) / 256 x 1 + VrefL0000000 DAC outputD0D2D3D4D5D6D7

Note: This IC can be accessed only when the lower

3 bits data of slave address (A0 to A2) coincide

with the input data of CS0 to CS2.

(L=Low, H=High)

::::::

LHL010

CS2

HH111

HL100 LL000

CS0CS1A0A1A2

First

MSB Last

LSB

First

MSB Last

LSB

(Slave address) Chip select data

Chip select data

DAC data

New Product

R2A20158NP

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R03DS0015EJ0100 Rev.1.00

2010.09.05

Data Timing Chart SCL and SDA (Model)

< Start condition to slave address bit >

SDA

SCL

D/A

output

< Sub address bit >

SDA

SCL

D/A

output

Start condition

123 WA

123456

78A

SDA

SCL

D/A

output

123456

78A

< DAC data bit to stop c ondition >

Stop

condition

Start condition With SCL at High, SDA line goes from High to Low

Stop condition With SCL at High, SDA line goes from Low to High

( Under normal circumstance, SDA is changed when SCL is Low )

Acknowledge bit The receiving IC has to pull down SDA line whenever receive slave data.

( The transmitting IC releases the SDA line just then transmit 8-bit data. )

456

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R2A20158NP

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R03DS0015EJ0100 Rev.1.00

2010.09.05

Digital Data Format

ADAC data 1ASub address 1AWSlave addressSTA

ADAC data 2ASub address 2 Sub address n STPADAC data nA

After the Start condition, the transmitting IC accesses the slave IC by Slave address, and transmits the

data to each channel by two bites (Sub address and DAC data).

If ripple or spike is input to D/A converter upper reference voltage terminal (VrefU1,2), accuracy of D/A

converter is down, So, when use this device, please connect capacitor among Vcc to GND for stable D/A

conversion.

This IC’s output amplifier has an advantage to capacitive load, So, it’s no problem at device action when

connect capacitor ( 0.1 µF Max ) among output to GND for every noise elimination.

Application Example

Precaution For use

Analog output

terminals

MCU

R2A20158NP

SCL

SDA

GND

VDD

Vcc

+10µF

10µF

VrefL

+10µF

Ao1

Ao2

Ao3

Ao4

Ao5

Ao6

Ao7

Ao8

7VrefU1

10µF

9VrefU2

10µF

16 CS2

17 CS1

18 CS0

Chip select data

19 RESET

RESET signal

New Product

R2A20158NP

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R03DS0015EJ0100 Rev.1.00

2010.09.05

Package Dimensions

PWQN0020KB-A [NP]

Ordering Information

Embossed Taping/2,500 pcs.NPPWQN0020KB-AQFN-20R2A20158NP

Packing/QuantityPackage type No.Package CodePackage NameOrder part No.

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