TSC2008
1
FEATURES APPLICATIONS
DESCRIPTION
PENIRQ
SPI
Serial
Interface
and
Control
CS
SDI
X+
X-
Y+
Y-
AUX
TEMP
Mux
VDD/REF
GND
SAR
ADC
Internal
Clock
Touch
Screen
Sensor
Drivers
Preprocessing
SCLK
SDO
TSC2008
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.......................................................................................................................................................... SBAS406B – JUNE 2008 – REVISED MARCH 2009
1.2V to 3.6V, 12-Bit, Nanopower, 4-WireMicro TOUCH SCREEN CONTROLLER with SPI™
•Cellular Phones234
•4-Wire Touch Screen Interface
•PDA, GPS, and Media Players•Single 1.2V to 3.6V Supply/Reference
•Portable Instruments•Ratiometric Conversion
•Point-of-Sale Terminals•Effective Throughput Rate:
•Multi-Screen Touch Control Systems– Up to 20kHz (8-Bit) or 10kHz (12-Bit)•Preprocessing to Reduce Bus Activity•High-Speed SPI (up to 25MHz)
The TSC2008 is a very low-power touch screen•Simple Command-Based User Interface:
controller designed to work with power-sensitive,–TSC2046 Compatible
handheld applications that are based on advancedlow-voltage processors. It works with a supply voltage– 8- or 12-Bit Resolution
as low as 1.2V, which can be supplied by a•On-Chip Temperature Measurement
single-cell battery. It contains a complete, ultra-low•Touch Pressure Measurement
power, 12-bit, analog-to-digital (A/D) resistive touchscreen converter, including drivers and the control•Digital Buffered PENIRQ
logic to measure touch pressure.•On-Chip, Programmable PENIRQ Pull-up
In addition to these standard features, the TSC2008•Auto Power-Down Control
offers preprocessing of the touch screen•Low Power (12-Bit, 8.2kHz Eq Rate):
measurements to reduce bus loading, thus reducing– 30.4 µA at 1.2V, f
SCLK
= 5MHz
the consumption of host processor resources that canthen be redirected to more critical functions.– 35.5 µA at 1.8V, f
SCLK
= 10MHz– 44.6 µA at 2.7V, f
SCLK
= 10MHz
The TSC2008 supports an SPI serial bus and datatransmission. It offers programmable resolution of 8•Power-On, Software, and SureSet™ Resets
or 12 bits to accommodate different screen sizes and•Enhanced ESD Protection:
performance needs.– ± 8kV HBM
The TSC2008 is available in a 12-lead,– ± 1kV CDM
(1,555 ± 0,055mm) x (2,055 ± 0,055mm) 3 x 4 array,– ± 25kV Air Gap Discharge
wafer chip-scale package (WCSP), and a 16-pin,4 x 4 QFN package. The TSC2008 is characterized– ± 15kV Contact Discharge
for the – 40 ° C to +85 ° C industrial temperature range.•1.5 x 2 WCSP-12 and 4 x 4 QFN-16 PackagesU.S. Patent No. 6246394; other patents pending.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2SureSet is a trademark of Texas Instruments.3SPI is a trademark of Motorola Inc.4All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2008 – 2009, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
ABSOLUTE MAXIMUM RATINGS
(1)
TSC2008
SBAS406B – JUNE 2008 – REVISED MARCH 2009 ..........................................................................................................................................................
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled withappropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be moresusceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION
(1)
TYPICAL TYPICAL NO MISSINGINTEGRAL GAIN CODES SPECIFIED TRANSPORTLINEARITY ERROR RESOLUTION PACKAGE PACKAGE TEMPERATURE PACKAGE ORDERING MEDIA,PRODUCT (LSB) (LSB) (BITS) TYPE DESIGNATOR RANGE MARKING NUMBER QUANTITY
Small TapeTSC2008IRGVT16-Pin,
and Reel, 2504 x 4 RGV – 40 ° C to +85 ° C TSC2008I
Tape andQFN
TSC2008IRGVR
Reel, 2500TSC2008 ± 1.5 0.7 11
Small Tape12-Pin,
TSC2008IYZGT
and Reel, 2503 x 4 Matrix,
YZG – 40 ° C to +85 ° C TSC2008I1.5 x 2
Tape andTSC2008IYZGRWCSP
Reel, 3000
(1) For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet, or seethe TI website at www.ti.com .
Over operating free-air temperature range (unless otherwise noted).
PARAMETER TSC2008 UNIT
Analog input X+, Y+, AUX to GND – 0.4 to VDD + 0.1 VVoltage
Analog input X – , Y – to GND – 0.4 to VDD + 0.1 VVoltage range VDD to GND – 0.3 to +5 VDigital input voltage to GND – 0.3 to VDD + 0.3 VDigital output voltage to GND – 0.3 to VDD + 0.3 VPower dissipation (T
J
Max - T
A
)/ θ
JA
QFN package 47 ° C/WThermal impedance, θ
JA
Low-K 113 ° C/WWCSP
High-K 62 ° C/WOperating free-air temperature range, T
A
– 40 to +85 ° CStorage temperature range, T
STG
– 65 to +150 ° CJunction temperature, T
J
Max +150 ° CVapor phase (60 sec) +215 ° CLead temperature
Infrared (15 sec) +220 ° CIEC contact discharge
(2)
X+, X – , Y+, Y – ± 15 kVIEC air discharge
(2)
X+, X – , Y+, Y – ± 25 kV
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure toabsolute-maximum rated conditions for extended periods may affect device reliability.(2) Test method based on IEC standard 61000-4-2. Device powered by battery. Contact Texas Instruments for test details.
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ELECTRICAL CHARACTERISTICS
TSC2008
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.......................................................................................................................................................... SBAS406B – JUNE 2008 – REVISED MARCH 2009
At T
A
= – 40 ° C to +85 ° C, V
DD
= +1.2V to +3.6V, unless otherwise noted.
TSC2008
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
AUXILIARY ANALOG INPUT
Input voltage range 0 V
DD
V
Input capacitance 12 pF
Input leakage current – 1 +1 µA
A/D CONVERTER
Resolution Programmable: 8 or 12 bits 12 Bits
No missing codes 12-bit resolution 11 Bits
Integral linearity ± 1.5 LSB
(1)
Differential linearity ± 1 LSB
V
DD
= 1.8V – 1.2 LSBOffset error
V
DD
= 3.0V – 3.1 LSB
V
DD
= 1.8V 0.7 LSBGain error
V
DD
= 3.0V 0.1 LSB
TOUCH SENSORS
T
A
= +25 ° C, V
DD
= 1.8V, setup command ' 10100000 ' 50 k ΩPENIRQ pull-up resistor, R
IRQ
T
A
= +25 ° C, V
DD
= 1.8V, setup command ' 10101000 ' 90 k Ω
Y+, X+ 6 ΩSwitch
on-resistance
Y – , X – 5 Ω
Switch drivers drive current
(2)
100ms duration 50 mA
INTERNAL TEMPERATURE SENSOR
Temperature range – 40 +85 ° C
V
DD
= 3V 1.94 ° C/LSBDifferential
method
(3)
V
DD
= 1.6V 1.04 ° C/LSBResolution
V
DD
= 3V 0.35 ° C/LSBTEMP1
(4)
V
DD
= 1.6V 0.19 ° C/LSB
V
DD
= 3V ± 2 ° C/LSBDifferential
method
(3)
V
DD
= 1.6V ± 2 ° C/LSBAccuracy
V
DD
= 3V ± 3 ° C/LSBTEMP1
(4)
V
DD
= 1.6V ± 3 ° C/LSB
INTERNAL OSCILLATOR
V
DD
= 1.2V 3.19 MHz
V
DD
= 1.8V 3.66 MHz8-bit
V
DD
= 2.7V 3.78 MHz
V
DD
= 3.6V 3.82 MHzInternal clock frequency, f
CCLK
V
DD
= 1.2V 1.6 MHz
V
DD
= 1.8V 1.83 MHz12-bit
V
DD
= 2.7V 1.88 MHz
V
DD
= 3.6V 1.91 MHz
V
DD
= 1.6V 0.0056 %/ ° CFrequency drift
V
DD
= 3.0V 0.012 %/ ° C
(1) LSB means least significant bit. With V
DD
(REF) = +2.5V, 1LSB is 610 µV.(2) Assured by design, but not production tested. Exceeding 50mA source current may result in device degradation.(3) Difference between TEMP1 and TEMP2 measurement; no calibration necessary.(4) Temperature drift is – 2.1mV/ ° C.
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TSC2008
SBAS406B – JUNE 2008 – REVISED MARCH 2009 ..........................................................................................................................................................
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ELECTRICAL CHARACTERISTICS (continued)At T
A
= – 40 ° C to +85 ° C, V
DD
= +1.2V to +3.6V, unless otherwise noted.
TSC2008
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DIGITAL INPUT/OUTPUT
Logic family CMOS
V
IH
1.2V ≤V
DD
< 3.6V 0.7 × V
DD
V
DD
+ 0.3 V
1.2V ≤V
DD
< 1.6V – 0.3 0.2 × V
DD
VV
IL
1.6V ≤V
DD
≤3.6V – 0.3 0.3 × V
DD
V
I
IL
CS, SCLK, and SDI pins – 1 1 µA
Logic level C
IN
CS, SCLK, and SDI pins 10 pF
V
OH
I
OH
= 2 TTL loads V
DD
– 0.2 V
DD
V
V
OL
I
OL
= 2 TTL loads 0 0.2 V
I
LEAK
Floating output – 1 1 µA
C
OUT
Floating output 10 pF
Data format Straight Binary
POWER SUPPLY REQUIREMENTS
Power-supply voltage
V
DD
Specified performance 1.2 3.6 V
12-bit, 69.6k eq rate
(5)
285.0 320.0 µAf
SCLK
= 5MHz,
V
DD
= 1.2Vf
ADC
= 2MHz,
8.2k eq rate
(5)
30.4 37.7 µAPD[1:0] = 0,0Quiescent supply current
82.6k eq rate
(5)
344.0 425.0 µA(V
DD
with sensor off)
V
DD
= 1.8V12-bit,
8.2k eq rate
(5)
34.5 42.2 µAf
SCLK
= 10MHz,f
ADC
= 2MHz,
84.8k eq rate
(5)
461.0 570.0 µAPD[1:0] = 0,0
V
DD
= 2.7V
8.2k eq rate
(5)
44.6 55.1 µA
Power-down supply current CS = 1, SDI = SCLK = 1, PENIRQ = 1, PD[1:0] = 0,0 0 0.8 µA
POWER ON/OFF SLOPE REQUIREMENTS (see Figure 37 )
t
VDD_OFF_RAMP
T
A
= – 40 ° C to +85 ° C 2 kV/s
T
A
= – 40 ° C to +85 ° C, VDD = 0V 1 st
VDD_OFF
T
A
= – 20 ° C to +85 ° C, VDD = 0V 0.3 s
t
VDD_ON_RAMP
T
A
= – 40 ° C to +85 ° C 12 kV/s
t
DEVICE_READY
T
A
= – 40 ° C to +85 ° C 2 ms
(5) See the Throughput Rate and SPI Bus Traffic section for calculation information.
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PIN CONFIGURATION
1 2 3 4
NC
NC
PENIRQ
SDO
X-
Y+
X+
VDD/REF
13
14
15
16
8
7
6
5
TSC2008
ThermalPad
AUX
GND
Y-
NC
SDI
CS
SCLK
12 11 10 9
NC
C lumnso
(FRONTVIEW)
A CB D
Y-
GND AUXSCLK
X-X+VDD/REF
3
2
1
PENIRQSDO
CS
Rows
Y+
SDI
TSC2008
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.......................................................................................................................................................... SBAS406B – JUNE 2008 – REVISED MARCH 2009
RGV PACKAGE
(1)
YZG PACKAGE4 x 4 QFN-16
WCSP-12(TOP VIEW)
(TOP VIEW, SOLDER BUMPS ON BOTTOM SIDE)
(1) The thermal pad is internally connected tothe substrate. The thermal pad can beconnected to the analog ground or leftfloating. Keep the thermal pad separatefrom the digital ground, if possible.
PIN ASSIGNMENTSPIN NO.
PINQFN WCSP NAME I/O A/D DESCRIPTION
1 — NC No connection
2 B1 SDI I D Serial data input
3 A1 CS I D Chip select
4 A2 SCLK I D Serial clock input
5 A3 VDD/REF Supply voltage and external reference input
6 B3 X+ I A X+ channel input
7 C3 Y+ I A Y+ channel input
8 D3 X – I A X – channel input
9 D2 Y – I A Y – channel input
10 B2 GND Ground
11 — NC No connection
12 C2 AUX I A Auxiliary channel input. If not used, this input should be grounded.
13 — NC No connection
14 — NC No connection
Pen touch interrupt output. Active low when pen is touched. The output remains low until conversion is15 D1 PENIRQ O D
complete or pen touch is released. The rising edge signals the end of conversion (EOC).
16 C1 SDO O D Serial data output
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TIMING INFORMATION
BIT0
tDIS(CSR-SDOZ)
tH(SDI-SCLKR)
NOTE: CPOL=0,CPHA=0,Byte0cyclerequires24SCLKs,andByte1cyclerequires8SCLKs.
tH(SCLKF-SDOVALID)
tSU(SDI-SCLKR)
tD(CSF-SDOVALID)
tSU(SCLKF-CSR)
tWH(CS)
tC(SCLK)
tSU(CSF-SCLK1R)
tFtR
tWL(SCLK)
tWH(SCLK)
BIT1
MSBIN
MSBOUT
CS SS( )
SCLK
SDO(MISO)
SDI(MOSI)
BIT0BIT1
CS
SCLK
PENIRQ/BUSY
(TSC2008)
tD(SCLKR-PENIRQF)
tSU(PENIRQR-SCLKR)
tD(SCLKF-PENIRQF)
TSC2008
SBAS406B – JUNE 2008 – REVISED MARCH 2009 ..........................................................................................................................................................
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The TSC2008 supports SPI programming in mode CPOL = 0 and CPHA = 0. The falling edge of SCLK is used tochange the output (MISO) data, and the rising edge is used to latch the input (MOSI) data. Eight SCLKs arerequired to complete the command byte cycle, and an additional eight or 16 SCLKs are required for the data tobe read, depending on the mode used.
Figure 1. Detailed I/O Timing
Figure 2. PENIRQ Timing
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TIMING REQUIREMENTS
(1)
TSC2008
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.......................................................................................................................................................... SBAS406B – JUNE 2008 – REVISED MARCH 2009
All specifications typical at – 40 ° C to +85 ° C, VDD = 1.6V, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN MAX UNIT
1.2V ≤VDD < 1.6V, 40% to 60% duty cycle 182 ns
t
C(SCLK)
SPI serial clock cycle time 1.6 ≤VDD < 2.7V, 40% to 60% duty cycle 62.5 ns
2.7V ≤VDD ≤3.6V, 40% to 60% duty cycle 40 ns
1.2V ≤VDD < 1.6V, 10pF load 5.5 MHz
f
SCLK
SPI serial clock frequency 1.6 ≤VDD < 2.7V, 10pF load 16 MHz
2.7V ≤VDD ≤3.6V, 10pF load 25 MHz
t
WH(SCLK)
SPI serial clock high time 0.4 × t
C(SCLK)
0.6 × t
C(SCLK)
ns
t
WL(SCLK)
SPI serial clock low time 0.4 × t
C(SCLK)
0.6 × t
C(SCLK)
ns
1.2V ≤VDD < 1.6V 22 nst
SU(CSF-SCLK1R)
Enable lead time
1.6 ≤VDD < 3.6V 14 ns
1.2V ≤VDD < 1.6V 55 nst
D(CSF-SDOVALID)
Slave access time
1.6 ≤VDD < 3.6V 25 ns
1.2V ≤VDD < 1.6V 40 80 nst
H(SCLKF-SDOVALID)
MISO data hold time
1.6 ≤VDD < 3.6V 6 30 ns
1.2V ≤VDD < 1.6V 50 nst
WH(CS)
Sequential transfer delay
1.6 ≤VDD < 3.6V 20 ns
1.2V ≤VDD < 1.6V 25 nst
SU(SDI-SCLKR)
MOSI data setup time
1.6 ≤VDD < 3.6V 10 ns
t
H(SDI-SCLKR)
MOSI data hold time 5 ns
1.2V ≤VDD < 1.6V 55 nst
DIS(CSR-SDOZ)
Slave MISO disable time
1.6 ≤VDD < 3.6V 25 ns
1.2V ≤VDD < 1.6V 50 nst
SU(SCLKF-CSR)
Enable lag time
1.6 ≤VDD < 3.6V 20 ns
1.2V ≤VDD < 1.6V 55 nsPENIRQ (used as BUSY)t
D(SCLKR-PENIRQF)
delay from SCLK rising edge
1.6 ≤VDD < 3.6V 25 ns
Setup time from PENIRQ 1.2V ≤VDD < 1.6V 50 nst
SU(PENIRQR-SCLKR)
(used as BUSY) to the rising
1.6 ≤VDD < 3.6V 20 nsedge of SCLK
t
D(RESET)
Reset period requirement 200 ns
t
R
Rise time VDD = 3V, f
SCLK
= 25MHz 3 ns
t
F
Fall time VDD = 3V, f
SCLK
= 25MHz 3 ns
(1) All input signals are specified with t
R
= t
F
= 5ns (10% to 90% of VDD) and timed from a voltage level of (V
IL
+ V
IH
)/2.
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TYPICAL CHARACTERISTICS
-40 -20 0 20 40 60 80 100
Temperature( C)°
450
400
350
300
250
200
SupplyCurrent( A)m
SPI=2.5MHz
SPI=10MHz
SPI=5MHz
-40 -20 0 20 40 60 80 100
Temperature(°C)
Power-DownSupplyCurrent(nA)
100
80
60
40
20
0
VDD=1.6V
VDD=3.6V VDD=3.0V
-40 -20 0 20 40 60 80 100
Temperature( C)°
30
25
20
15
10
5
0
SupplyCurrent( A)m
SPI=2.5MHz
SPI=10MHz
SPI=5MHz
TSC2008
SBAS406B – JUNE 2008 – REVISED MARCH 2009 ..........................................................................................................................................................
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At T
A
= – 40 ° C to +85 ° C, VDD = +1.2V to +3.6V, PD1 = PD0 = 0, f
SCLK
= 10MHz, f
ADC
= f
OSC
/2 = 2MHz, 12-bit mode,non-continuous AUX measurement, and MAV filter enabled (see MAV Filter section), unless otherwise noted.
POWER-DOWN SUPPLY CURRENT SUPPLY CURRENTvs TEMPERATURE vs TEMPERATURE
Figure 3. Figure 4.
SUPPLY CURRENT SUPPLY CURRENTAUX CONVERSION vs SUPPLY VOLTAGE
Figure 5. Figure 6.
SUPPLY CURRENT (Part Not Addressed) SUPPLY CURRENT (Part Not Addressed)vs TEMPERATURE vs SUPPLY VOLTAGE
Figure 7. Figure 8.
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-40 -20 0 20 40 60 80 100
Temperature( C)°
2
1
0
-1
-2
Deltafrom+25 C(LSB)°
VDD=1.8V
-40 -20 0 20 40 60 80 100
T C)emperature(°
2
1
0
-1
-2
Deltafrom+25 C(LSB)°
VDD=1.8V
VDD(V)
1.2 1.6 2.0 2.4 2.8 3.2
11
10
9
8
7
6
5
4
3
3.6
R ( )W
ON
X+
Y+
Y-
X-
-40 -20 0 20 40 60 80 100
Temperature( C)°
6
5
4
3
2
RON (W)
X+,Y+:VDD=3.0VtoPin
X- -,Y :PintoGND X+
Y+
Y-
X-
-40 -20 0 20 40 60 80 100
Temperature( C)°
8
7
6
5
4
3
2
RON ()
W
X+,Y+:VDD=1.8VtoPin
X-,Y :PintoGND-
X+
Y+
Y-
X-
-40 -20 0 20 40 60 80 100
Temperature( C)°
850
800
750
700
650
600
550
500
450
400
TEMPDiodeVoltage(mV)
VDD=1.8V
95.7mV
TEMP1
MeasurementIncludes
A/DConverterOffset
andGainErrors
136mV
TEMP2
TSC2008
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.......................................................................................................................................................... SBAS406B – JUNE 2008 – REVISED MARCH 2009
TYPICAL CHARACTERISTICS (continued)At T
A
= – 40 ° C to +85 ° C, VDD = +1.2V to +3.6V, PD1 = PD0 = 0, f
SCLK
= 10MHz, f
ADC
= f
OSC
/2 = 2MHz, 12-bit mode,non-continuous AUX measurement, and MAV filter enabled (see MAV Filter section), unless otherwise noted.
CHANGE IN GAIN CHANGE IN OFFSETvs TEMPERATURE vs TEMPERATURE
Figure 9. Figure 10.
SWITCH ON-RESISTANCE SWITCH ON-RESISTANCEvs SUPPLY VOLTAGE vs TEMPERATURE
Figure 11. Figure 12.
SWITCH ON-RESISTANCE TEMP DIODE VOLTAGEvs TEMPERATURE vs TEMPERATURE
Figure 13. Figure 14.
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VDD(V)
1.2 1.6 2.0 2.4 2.8 3.2
588
586
584
582
580
578
576
574
3.6
TEMP1DiodeVoltage(mV)
VDD=V =1.8V
REF
MeasurementIncludes
A/DConverterOffset
andGainErrors
VDD(V)
1.2 1.6 2.0 2.4 2.8 3.2
704
702
700
698
696
694
692
690
3.6
TEMP2DiodeVoltage(mV)
VDD=V =1.8V
REF
MeasurementIncludes
A/DConverterOffset
andGainErrors
Temperature( C)°
InternalOscillatorClockFrequency(MHz)
-40 -20
3.40
3.30
3.20
3.10
3.00
2.90
2.80
2.70
0 20 40 60 80 100
VDD=1.2V
Temperature( C)°
InternalOscillatorClockFrequency(MHz)
-40 -20
3.70
3.69
3.68
3.67
3.66
3.65
3.64
3.63
3.62
3.61
3.60
0 20 40 60 80 100
VDD=1.8V
Temperature( C)°
InternalOscillatorClockFrequency(MHz)
-40 -20
3.90
3.85
3.80
3.75
3.70
0 20 40 60 80 100
VDD=3.0V
TSC2008
SBAS406B – JUNE 2008 – REVISED MARCH 2009 ..........................................................................................................................................................
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TYPICAL CHARACTERISTICS (continued)At T
A
= – 40 ° C to +85 ° C, VDD = +1.2V to +3.6V, PD1 = PD0 = 0, f
SCLK
= 10MHz, f
ADC
= f
OSC
/2 = 2MHz, 12-bit mode,non-continuous AUX measurement, and MAV filter enabled (see MAV Filter section), unless otherwise noted.
TEMP1 DIODE VOLTAGE TEMP2 DIODE VOLTAGEvs SUPPLY VOLTAGE vs SUPPLY VOLTAGE
Figure 15. Figure 16.
INTERNAL OSCILLATOR CLOCK FREQUENCY INTERNAL OSCILLATOR CLOCK FREQUENCYvs TEMPERATURE vs TEMPERATURE
Figure 17. Figure 18.
INTERNAL OSCILLATOR CLOCK FREQUENCYvs TEMPERATURE
Figure 19.
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Product Folder Link(s): TSC2008
OVERVIEW
X+
Y+
X-
Y-
AuxilaryInput GND
TSC2008
GND
1 Fto
10 F
m
m
0.1 Fm
Touch
Screen
GPIO
SDI
SCLK
Host
Processor
PENIRQ
SDO
SCLK
VDD/REF
AUX
GND
1.8VDC
GPIO
SDO
CS
SDI
TSC2008
www.ti.com
.......................................................................................................................................................... SBAS406B – JUNE 2008 – REVISED MARCH 2009
The TSC2008 is an analog interface circuit for a human interface touch screen device. All peripheral functionsare controlled through the command byte and onboard state machines. While maintaining similarity in hardware,command, and software to its predecessor, the TSC2046 (or TSC2046E), the TSC2008 includes significantimprovements such as:•Much stronger and more comprehensive electrostatic discharge (ESD) protection•Uses only 1/13 power for equivalent performance•1/7 bus traffic•3/16 size•Direct 1.8V interface•Prudent reset scheme•Saves 1/7 power if 8-bit SDO adjusted output mode used
The TSC2008 consists of the following blocks (refer to the block diagram on the front page):•Touch Screen Sensor Drivers•Auxiliary Input (AUX)•Temperature Sensor•Acquisition Activity Preprocessing•Internal Conversion Clock•SPI Interface
Communication with the TSC2008 is done via an SPI serial interface. The TSC2008 is an SPI slave device;therefore, data are shifted into or out of the TSC2008 under the control of the host microprocessor, which alsoprovides the serial data clock.
Control of the TSC2008 and its functions is accomplished by writing to the command register of an internal statemachine. A simple command protocol (compatible with SPI) is used to address this register.
A typical application of the TSC2008 is shown in Figure 20 .
Figure 20. Typical Circuit Configuration
Copyright © 2008 – 2009, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Link(s): TSC2008
TOUCH SCREEN OPERATION
4-WIRE TOUCH SCREEN COORDINATE PAIR MEASUREMENT
ConductiveBar
InsulatingMaterial(Glass)
Silver
Ink
TransparentConductor(ITO)
BottomSide
Transparent
Conductor(ITO)
TopSide
X+
X-
Y+
Y-
ITO=IndiumTinOxide
RTOUCH +RX−plate @XPostition
4096 ǒZ2
Z1*1Ǔ
(1)
TSC2008
SBAS406B – JUNE 2008 – REVISED MARCH 2009 ..........................................................................................................................................................
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A resistive touch screen operates by applying a voltage across a resistor network and measuring the change inresistance at a given point on the matrix where the screen is touched by an input (stylus, pen, or finger). Thechange in the resistance ratio marks the location on the touch screen.
The TSC2008 supports resistive 4-wire configurations, as shown in Figure 21 . The circuit determines location intwo coordinate pair dimensions, although a third dimension can be added for measuring pressure.
A 4-wire touch screen is typically constructed as shown in Figure 21 . It consists of two transparent resistivelayers separated by insulating spacers.
Figure 21. 4-Wire Touch Screen Construction
The 4-wire touch screen panel works by applying a voltage across the vertical or horizontal resistive network.The A/D converter converts the voltage measured at the point where the panel is touched. A measurement of theY position of the pointing device is made by connecting the X+ input to a data converter chip, turning on the Y+and Y – drivers, and digitizing the voltage seen at the X+ input. The voltage measured is determined by thevoltage divider developed at the point of touch. For this measurement, the horizontal panel resistance in the X+lead does not affect the conversion because of the high input impedance of the A/D converter.
Voltage is then applied to the other axis, and the A/D converter converts the voltage representing the X positionon the screen. This process provides the X and Y coordinates to the associated processor.
Measuring touch pressure (Z) can also be done with the TSC2008. To determine pen or finger touch, thepressure of the touch must be determined. Generally, it is not necessary to have very high performance for thistest; therefore, 8-bit resolution mode may be sufficient (however, data sheet calculations are shown using 12-bitresolution mode). There are several different ways of performing this measurement. The TSC2008 supports twomethods. The first method requires knowing the X-plate resistance, the measurement of the X-Position, and twoadditional cross panel measurements (Z
2
and Z
1
) of the touch screen (see Figure 22 ). Equation 1 calculates thetouch resistance:
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Product Folder Link(s): TSC2008
RTOUCH +RX−plate @XPostition
4096 ǒ4096
Z1*1Ǔ*RY−plate @ǒ1*YPosition
4096 Ǔ
(2)
X-Position
MeasureX-Position
MeasureZ -Position
1
Touch
X+ Y+
X-Y-
Z -Position
1
Touch
X+ Y+
Y-X-
MeasureZ -Position
2
Z -Position
2
Touch
X+ Y+
Y-X-
TSC2008
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.......................................................................................................................................................... SBAS406B – JUNE 2008 – REVISED MARCH 2009
The second method requires knowing both the X-plate and Y-plate resistance, measurement of X-Position andY-Position, and Z
1
.Equation 2 also calculates the touch resistance:
Figure 22. Pressure Measurement
When the touch panel is pressed or touched and the drivers to the panel are turned on, the voltage across thetouch panel will often overshoot and then slowly settle down (decay) to a stable dc value. This effect is a result ofmechanical bouncing caused by vibration of the top layer sheet of the touch panel when the panel is pressed.This settling time must be accounted for, or else the converted value is incorrect. Therefore, a delay must beintroduced between the time the driver for a particular measurement is turned on, and the time a measurement ismade.
In some applications, external capacitors may be required across the touch screen for filtering noise picked up bythe touch screen (for example, noise generated by the LCD panel or back-light circuitry). The value of thesecapacitors provides a low-pass filter to reduce the noise, but creates an additional settling time requirement whenthe panel is touched. The settling time typically shows up as gain error. The TSC2008 has a built-in noise filter(see the Preprocessing section). These capacitors can be reduced to minimal value or not installed.
The TSC2008 touch screen interface can measure position (X,Y) and pressure (Z).
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INTERNAL TEMPERATURE SENSOR
Converter
GND
VDD
TEMP1
TEMP2
+IN
-IN
GND
REF
DV+kT
q@ln(N)
(3)
T+q@DV
k@ln(N)
(4)
TSC2008
SBAS406B – JUNE 2008 – REVISED MARCH 2009 ..........................................................................................................................................................
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In some applications, such as battery recharging, an ambient temperature measurement is required. Thetemperature measurement technique used in the TSC2008 relies on the characteristics of a semiconductorjunction operating at a fixed current level. The forward diode voltage (V
BE
) has a well-defined characteristicversus temperature. The ambient temperature can be predicted in applications by knowing the +25 ° C value ofthe V
BE
voltage and then monitoring the delta of that voltage as the temperature changes.
The TSC2008 offers two modes of temperature measurement. The first mode requires calibration at a knowntemperature, but only requires a single reading to predict the ambient temperature. The TEMP1 diode, shown inFigure 23 , is used during this measurement cycle. This voltage is typically 580mV at +25 ° C with a 10 µA current.The absolute value of this diode voltage can vary by a few millivolts; the temperature coefficient (T
C
) of thisvoltage is very consistent at – 2.1mV/ ° C. During the final test of the end product, the diode voltage is stored at aknown room temperature, in system memory, for calibration purposes by the user. The result is an equivalenttemperature measurement resolution of 0.3 ° C/LSB (1LSB = 610 µV with V
REF
= 2.5V).
Figure 23. Functional Block Diagram of Temperature Measurement Mode
The second mode does not require a test temperature calibration, but uses a two-measurement (differential)method to eliminate the need for absolute temperature calibration and for achieving 2 ° C/LSB accuracy. Thismode requires a second conversion of the voltage across the TEMP2 diode with a resistance 91 times largerthan the TEMP1 diode. The voltage difference between the first (TEMP1) and second (TEMP2) conversion isrepresented by:
Where:
N = the resistance ratio = 91.k = Boltzmann's constant = 1.3807 × 10
– 23
J/K (joules/kelvins).q = the electron charge = 1.6022 × 10
– 19
C (coulombs).T = the temperature in kelvins (K).
This method can provide much improved absolute temperature measurement, but a lower resolution of1.6 ° C/LSB. The resulting equation to solve for T is:
Where:
ΔV = V
BE
(TEMP2) – V
BE
(TEMP1) (in mV).
∴T = 2.573 ⋅ΔV (in K),
or T = 2.573 ⋅ΔV – 273 (in ° C).
Temperature 1 and/or temperature 2 measurements have the same timing as shown in Figure 30 to Figure 33 .
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Product Folder Link(s): TSC2008
ANALOG-TO-DIGITAL CONVERTER
Converter
-REF
+REF
+IN
-IN
PenTouch
Control
Logic
A[2:0]
MedianValueFilter
and
AveragingFilter
(MAV)
VDD
GND
GND
TEMP1
TEMP2
RIRQ 90kW50kW
AUX
GND
X+
X-
Y+
Y-
VDD/REF PENIRQ
Reference
TSC2008
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.......................................................................................................................................................... SBAS406B – JUNE 2008 – REVISED MARCH 2009
Figure 24 shows the analog inputs of the TSC2008. The analog inputs (X, Y, and Z touch panel coordinates, chiptemperature and auxiliary inputs) are provided via a multiplexer to the Successive Approximation Register (SAR)analog-to-digital converter (ADC). The A/D architecture is based on capacitive redistribution architecture, whichinherently includes a sample-and-hold function.
Figure 24. Analog Input Section (Simplified Diagram)
A unique configuration of low on-resistance switches allows an unselected A/D converter input channel toprovide power and an accompanying pin to provide ground for driving the touch panel. By maintaining adifferential input to the converter and a differential reference input architecture, it is possible to negate errorscaused by the driver switch on-resistance.
The TSC2008 uses an external voltage reference applied to the VDD/REF pin. The upper reference voltagerange is the same as the supply voltage range, which allows for simple, 1.2V to 3.6V single-supply operation ofthe chip.
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Product Folder Link(s): TSC2008
Reference Mode
Converter
+IN +REF
Y+
VDD/REF
X+
Y-
GND
-REF
-IN
Converter
+IN +REF
Y+
VDD/REF
X+
Y-
GND
-REF
-IN
TSC2008
SBAS406B – JUNE 2008 – REVISED MARCH 2009 ..........................................................................................................................................................
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There is a critical item regarding the reference when making measurements while the switch drivers are on. Forthis discussion, it is useful to consider the basic operation of the TSC2008 (see Figure 20 ). This particularapplication shows the device being used to digitize a resistive touch screen. A measurement of the current Yposition of the pointing device is made by connecting the X+ input to the A/D converter, turning on the Y+ and Y –drivers, and digitizing the voltage on X+, as shown in Figure 25 . For this measurement, the resistance in the X+lead does not affect the conversion; it does affect the settling time, but the resistance is usually small enoughthat this is not a concern. However, because the resistance between Y+ and Y – is fairly low, the on-resistance ofthe Y drivers does make a small difference. Under the situation outlined so far, it would not be possible toachieve a 0V input or a full-scale input regardless of where the pointing device is on the touch screen becausesome voltage is lost across the internal switches. In addition, the internal switch resistance is unlikely to track theresistance of the touch screen, providing an additional source of error.
Figure 25. Simplified Diagram of Single-Ended Reference
This situation is resolved, as shown in Figure 26 , by using the differential mode; the +REF and – REF inputs areconnected directly to Y+ and Y – , respectively. This mode makes the A/D converter ratiometric. The result of theconversion is always a percentage of the external reference, regardless of how it changes in relation to theon-resistance of the internal switches. Note that there is an important consideration regarding power dissipationwhen using the ratiometric mode of operation (see the Power Dissipation section for more details).
Figure 26. Simplified Diagram of Differential Reference(Both Y Switches are Enabled, and X+ is the Analog Input)
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Product Folder Link(s): TSC2008
Touch Screen Settling
Touch Detect
TSC2008
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.......................................................................................................................................................... SBAS406B – JUNE 2008 – REVISED MARCH 2009
In some applications, external capacitors may be required across the touch screen to filter noise picked up by thetouch screen (that is, noise generated by the LCD panel or backlight circuitry). These capacitors provide alow-pass filter to reduce the noise, but they also cause a settling time requirement when the panel is touched.The settling time typically shows up as a gain error. The problem is that the input and/or reference has notsettled to its final steady-state value before the A/D converter samples the input(s) and provides the digitaloutput. Additionally, the reference voltage may continue to change during the measurement cycle.
There are two ways to resolve this issue. Option 1 is to stop or slow down the TSC2008 SCLK for the requiredtouch screen settling time. This option allows the input and reference to have stable values for the Acquire period(three clock cycles of the TSC2008; see Figure 30 ). This option works for both the single-ended and thedifferential modes. Option 2 is to operate the TSC2008 in the differential mode only for the touch screenmeasurements and command the TSC2008 to remain on (touch screen drivers ON) and not go into power-down(PD0 = 1). Several conversions are made, depending on the settling time required and the TSC2008 data rate.Once the required number of conversions have been made, the processor commands the TSC2008 to go into itspower-down state on the last measurement. This process is required for X-Position, Y-Position, and Z-Positionmeasurements.
The PENIRQ can be used as an interrupt to the host. R
IRQ
is an internal pull-up resistor with a programmablevalue of either 50k Ω(default) or 90k Ω(which allows the total resistance from X+ to Y – to be as high as 30k Ω).Write command '1010' (setup command) followed by data '1xx0' sets the pull-up resistor to 90k Ω.NOTE: Thefirst three bits must be '0's and the select bit is the last bit. To change the pull-up resistor back to 50k Ω, issuewrite command '1010' followed by data '0xx0'.
An example for the Y-position measurement is detailed in Figure 27 . The PENIRQ output is pulled high by aninternal pull-up resistor. While in power-down mode with PD0 = 0, the Y – driver is on and connected to GND,and the PENIRQ output is connected to the X+ input. When the panel is touched, the X+ input is pulled to groundthrough the touch screen, and PENIRQ output goes low because of the current path through the panel to GND,initiating an interrupt to the processor. During the measurement cycle for X-, Y-, and Z-Position, the X+ input isdisconnected from the PENIRQ pull-down transistor to eliminate any pull-up resistor leakage current from flowingthrough the touch screen, thus causing no errors.
If the last command byte written to the TSC2008 contains PD0 = 1, the pen-interrupt output function is disabledand cannot detect when the panel is touched. In order to re-enable the pen-interrupt output function under thesecircumstances, a command byte must be written to the TSC2008 with PD0 = 0.
If the last command byte contains PD0 = 0, then the pen-interrupt function is enabled at the end of a conversion.The end of conversion (EOC) occurs on the rising edge of PENIRQ.
In both cases previously listed, it is recommended that whenever the host writes to the TSC2008, the masterprocessor masks the interrupt associated to PENIRQ. This masking prevents false triggering of interrupts whenthe PENIRQ line is disabled in the cases previously listed.
Copyright © 2008 – 2009, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Link(s): TSC2008
GND
TEMP1
TEMP2
VDD
PenTouch
X+
Y+
Y-
HighwhentheX+orY+
driverison,orwhenany
sensorconnection/short-
circuittestsareactivated.
GND
ON
Sense
Viasgotosystemanaloggroundplane.
GND
Highwhen
theX+orY+
driverison.
Control
Logic
RIRQ
VDD/REF
PENIRQ
Connectto
AnalogSupply
Preprocessing
7Acquired
Data
7
7m asue rementsinput
intotemporaryarray
Sortby
descendingorder
7
Averagingoutp tu
fromwindowof3
3
TSC2008
SBAS406B – JUNE 2008 – REVISED MARCH 2009 ..........................................................................................................................................................
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Figure 27. Example of a Pen-Touch Induced Interrupt via the PENIRQ Pin
The TSC2008 has a fixed combined MAV filter (median value filter and averaging filter).
MAV Filter
If the acquired signal source is noisy because of the digital switching circuit, it may necessary to evaluate thedata without noise. In this case, the median value filter operation helps remove the noise. The array of sevenconverted results is sorted first. The middle three values are then averaged to produce the output value of theMAV filter.
The MAV filter is applied to all measurements for all analog inputs including the touch screen inputs, temperaturemeasurements TEMP1 and TEMP2, and auxiliary input AUX. To shorten the conversion time, the MAV filter maybe bypassed though the setup command; see Table 2 and Table 4 .
Figure 28. MAV Filter Operation (Patent Pending)
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Product Folder Link(s): TSC2008
DIGITAL INTERFACE
TSC2008
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.......................................................................................................................................................... SBAS406B – JUNE 2008 – REVISED MARCH 2009
The TSC2008 communicates through a standard SPI bus. The SPI allows full-duplex, synchronous, serialcommunication between a host processor (the master) and peripheral devices (slaves). The SPI mastergenerates the synchronizing clock and initiates transmissions. The SPI slave devices depend on a master to startand synchronize transmissions.
A transmission begins when initiated by a master SPI. The byte from the master SPI begins shifting in on theslave SDI (MOSI — master out, slave in) pin under the control of the master serial clock. As the byte shifts in onthe SDI (MOSI) pin, a byte shifts out on the SDO (MISO — master in, slave out) pin to the master shift register.
The idle state of the TSC2008 serial clock is logic low, which corresponds to a clock polarity setting of 0 (typicalmicroprocessor SPI control bit CPOL = 0). The TSC2008 interface is designed so that with a clock phase bitsetting of 0 (typical microprocessor SPI control bit CPHA = 0), the master begins driving its MOSI pin and theslave begins driving its MISO pin half an SCLK before the first serial clock edge. The CS ( SS, slave select) pincan remain low between transmissions.
Table 1. Standard SPI Signal Names vs Common Serial Interface Signal Names
SPI SIGNAL NAMES COMMON SERIAL INTERFACE NAMES
SS (Slave Select) CS (Chip Select)MISO (Master In Slave Out) SDO (Serial Data Out)MOSI (Master Out Slave In) SDI (Serial Data In)
As a comparison to the popular TSC2046 timing characteristics, a few differences between the interfaces areworth notice:
1. Unlike the TSC2046, there is not a 15 SCLK cycle for the TSC2008.2. There is an adjusted SDO timing that allows an 8-bit, back-to-back cycle.3. The TSC2008 uses an internal conversion clock; therefore, the SPI serial clock (SCLK) can only affect theacquiring period and I/O transfer.4. The TSC2008 uses an internal clock to perform the conversion. PENIRQ rises when the conversion iscomplete. If the host issues an SCLK before the conversion is complete, PENIRQ also rises, but theconversion result is invalid.5. If a new command is issued before a conversion is complete (indicated by EOC), then the conversion isaborted.
6. Releasing the SPI bus (by raising CS) during the conversion is OK, but releasing the SPI during the I/Otransfer (for example, read result) aborts the data transfer.
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Product Folder Link(s): TSC2008
CONTROL BYTE
TSC2008
SBAS406B – JUNE 2008 – REVISED MARCH 2009 ..........................................................................................................................................................
www.ti.com
The control byte (on SDI), as shown in Table 2 , provides the start conversion, addressing, A/D converterresolution, configuration, and power-down of the TSC2008. Figure 30 ,Table 2 , and Table 3 give detailedinformation regarding the order and description of these control bits within the control byte.
Table 2. Order of the Control Bits in the Control Byte
BIT 7 BIT 0(MSB) BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 (LSB) COMMENT
S A2 A1 A0 MODE SER/ DFR PD1 PD0 Excludes setup commandS 0 1 0 Pull-up Bypass Timing Reset Setup command
Table 3. Description of the Control Bits in the Control Byte
BIT DESCRIPTION
Start Bit. When this bit = '1', it indicates this is one of the user commands. A new control byte can start every 16th clock cycle in7
12-bit conversion mode or every 12th clock cycle in 8-bit conversion mode (see Figure 30 through Figure 33 ).Bit[6:4] = A[2:0]. Channel select command if A[2:0] ≠'010'.
These channel select bits, along with the SER/ DFR bit,6-4 Bit[6:4] = A[2:0]. Setup command if A[2:0] = '010'.control the setting of the multiplexer input, touch driverswitches, and reference inputs (see Table 4 andFigure 30 through Figure 33 ).Mode Select Bit. This bit controls the number of bits for
Pull-up Resistor Select Bit
(1)
.the next conversion.3 0: 50k ΩPENIRQ pull-up resistor (default).0: 12 bits (low)
1: 90k ΩPENIRQ pull-up resistor.1: 8 bits (high).Single-Ended/Differential Reference Select Bit
Bypass Noise Filter Bit
(1)
.(SER/ DFR). Along with the channel select bits, A[2:0],2 0: MAV noise filter enabled (default).this bit controls the setting of the multiplexer input, touch
1: MAV noise filter bypassed.driver switches, and reference inputs (see Table 4 ).
Bit 1: Timing Select Bit
(1)
.0: TSC2046-compatible timing for SDO during data read (default)1: Adjusted SDO timing; MSB appears before 1st rising clock edge.Bit[1:0] = PD[1:0]. Power Down Mode Select Bits.1-0
See Table 5 for details.
Bit 0: Software Reset Bit.0: Nothing happens (default).1: Software reset.
(1) These bits configure the pull-up resistor value, control the filter bypass, and select the SDO output timing. The bits are static and thevalues are stored in register bits that will only be reset to default by a reset condition (power-on reset, software reset, or SureSet) orchanged with the setup command.
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Product Folder Link(s): TSC2008
TSC2008
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.......................................................................................................................................................... SBAS406B – JUNE 2008 – REVISED MARCH 2009
The control byte begins with a start bit followed by seven control bits. For the command to be valid, the start bitmust be '1'. Do not use '0' for the start bit; it is reserved for factory use.
Initiate Start— The first bit is the start bit (S), and must always be high to initiate the start of a user-controllablecontrol byte. When the start bit = '0', it is reserved for factory use.
Addressing and Command Decoding— The next three bits in the control byte following the start bit are threeaddressing bits A[2:0] used to select the active input channel(s) of the input multiplexer (see Table 4 andFigure 24 ), enable the touch screen drivers, select the reference inputs, or decode other commands.
Bit[6:4] = '010' is the setup command that is used to configure the TSC.
Bit[3:0] followed by the setup command are the configuration bits and are used to select the pull-up resistorvalue, bypass the noise filter (in the preprocessing unit), select the SDO output timing, and perform the softwarereset. Bit[3:1] are static — that is, they do not change once programmed unless either the device is powered off,one of the reset conditions occur (power-on reset, software reset, or SureSet), or unless changed with the setupcommand. Note that if any reset occurs, bit[3:1] is set to the default values listed in Table 3 . Any functiondecoded as shown in Table 4 (excluding the setup command) has no access to these four configuration bits.
Table 4. Converter Function Select (CFS) Information
BIT 2
(1)
INPUT TOA[2:0] SER/ DFR +REF – REF = – IN ADC = +IN X-DRIVERS Y-DRIVERS DESCRIPTION
0h Don't care VDD GND TEMP1 All OFF All OFF Measure TEMP11h 1 (single-ended) VDD GND X+ All OFF All ON Measure Y position1h 0 (differential mode) Y+ Y – X+ All OFF All ON Measure Y positionUsed as noise filter2h — — — All OFF All OFF Setup command
(2)bypass3h 1 (single-ended) VDD GND X+ X – ON Y+ ON Measure Z1 position3h 0 (differential mode) Y+ X – X+ X – ON Y+ ON Measure Z1 position4h 1 (single-ended) VDD GND Y – X – ON Y+ ON Measure Z2 position4h 0 (differential mode) Y+ X – Y – X – ON Y+ ON Measure Z2 position5h 1 (single-ended) VDD GND Y+ All ON All OFF Measure X position5h 0 (differential mode) X+ X – Y+ All ON All OFF Measure X position6h Don't care VDD GND AUX All OFF All OFF Measure AUX7h Don't care VDD GND TEMP2 All OFF All OFF Measure TEMP2
(1) Bit 2 is the SER/ DFR control bit for all commands except for the setup command.(2) Use the setup command to configure the touch screen controller or access the software reset function.
MODE— The mode bit sets the resolution of the A/D converter. With this bit low, the next conversion has 12 bitsof resolution; with this bit high, the next conversion has eight bits of resolution.
SER/ DFR— The SER/DFR bit controls the reference mode: either single-ended (high) or differential (low). Thedifferential mode is also referred to as the ratiometric conversion mode and is preferred for X-Position,Y-Position, and Pressure-Touch measurements for optimum performance. The reference is derived from thevoltage at the switch drivers, which is almost the same as the voltage to the touch screen. In this case, areference voltage is not needed because the reference voltage to the A/D converter is the same as the voltageacross the touch screen. In single-ended mode, the converter reference voltage is always the difference betweenthe VREF and GND pins (see Table 4 and Figure 24 through Figure 26 , for further information).
If X-Position, Y-Position, and Pressure-Touch are measured in the single-ended mode, then VDD is used as thereference.
NOTE: The differential mode can only be used for X-Position, Y-Position, and Pressure-Touch measurements.All other measurements require the single-ended mode.
Copyright © 2008 – 2009, Texas Instruments Incorporated Submit Documentation Feedback 21
Product Folder Link(s): TSC2008
Variable Resolution
8- and 12-Bit Conversion
Conversion Clock and Conversion Time
TSC2008
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PD0 and PD1— The power-down bits select the power-down mode that the TSC2008 will be in after the currentcommand completes, as shown in Table 5 .
It is recommended to set PD0 = '0' in each command byte to get the lowest power consumption possible. Ifmultiple X-, Y-, and Z-position measurements are performed sequentially (such as when averaging),PD0 = '1' leaves the touch screen drivers on at the end of each conversion cycle.
Table 5. Power-Down and Internal Reference Selection
PD1 PD0 PENIRQ DESCRIPTION
Power-Down Between Conversions. When each conversion is finished, theconverter enters a low-power mode. At the start of the next conversion, the0 0 Enabled device instantly powers up to full power. There is no need for additional delays toensure full operation, and the very first conversion is valid. The Y – switch is onwhen in power-down.0 1 Disabled A/D converter on. PENIRQ disabled.1 0 Enabled A/D converter off. PENIRQ enabled.1 1 Disabled A/D converter on. PENIRQ disabled.
The TSC2008 provides either 8-bit or 12-bit resolution for the A/D converter. Lower resolution is often practicalfor measuring slow changing signals such as touch pressure. Performing the conversions at lower resolutionreduces the amount of time it takes for the A/D converter to complete its conversion process, which also lowerspower consumption.
The TSC2008 provides both 12-bit or 8-bit conversion modes.
The 12-bit conversion mode can be done in 24 SCLKs per cycle or 16 SCLKs per cycle timing; see Figure 30and Figure 31 for details. The 8-bit conversion can be done in 24 SCLKs per cycle (although this mode isunlikely to be selected), 16 SCLKs per cycle, or even 8 SCLKs per cycle (when adjusted SDO timing is selected);see Figure 32 and Figure 33 for details.
The 8-bit mode can be used when faster throughput is needed and the digital result is not as critical. Byswitching to the 8-bit conversion mode, a conversion is complete four internal conversion clock cycles earlier andalso takes less time to transfer the result. The internal conversion clock runs at twice the speed (4MHz typical)than the 12-bit conversion mode. This faster conversion and transfer saves power.
The TSC2008 contains an internal clock that drives the state machines that perform the many functions of thedevice. This clock is divided down to provide a clock that runs the A/D converter. The 8-bit ADC mode uses a4MHz clock and the 12-bit ADC mode uses a 2MHz clock. The actual frequency of this internal clock is slowerthan the name suggests, and varies with the supply voltage.
22 Submit Documentation Feedback Copyright © 2008 – 2009, Texas Instruments Incorporated
Product Folder Link(s): TSC2008
Data Format
OutputCode
0V
FS=Full-ScaleVoltage=VREF
(1)
1LSB=V /4096
REF
(1)
FS 1LSB-
11...111
11...110
11...101
00...010
00...001
00...000
1LSB
InputVoltage (V)
(2)
TSC2008
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.......................................................................................................................................................... SBAS406B – JUNE 2008 – REVISED MARCH 2009
The TSC2008 output data are in Straight Binary format as shown in Figure 29 . This figure shows the ideal outputcode for the given input voltage and does not include the effects of offset, gain, or noise.
(1) Reference voltage at converter: +REF – ( – REF). See Figure 24 .(2) Input voltage at converter, after multiplexer: +IN – ( – IN). See Figure 24 .
Figure 29. Ideal Input Voltages and Output Codes
Copyright © 2008 – 2009, Texas Instruments Incorporated Submit Documentation Feedback 23
Product Folder Link(s): TSC2008
12-BIT OPERATION TIMING
tACQ
Idle Acquire Conv
10
Idle
1SCLK
CS
8 1
11SDO
Drivers1and2(1)
(SER/DFRHigh)
Drivers1and2(1, 2)
(SER/DFRLow)
(MSB)
(START)
(LSB)
A2S
On
On
Off Off
Off Off
SDI A1 A0 MODE SER/
DFR PD1 PD0
10 9 8 7 6 5 4 3 2 1 0 ZeroFilled...
8 1 8
NOTES: (1)ForY-Position,Driver1isonX+isselected,andDriver2isoff.ForX-Position,Driver1isoff,Y+isselected,andDriver2ison.Y willturnon-
whenpower-downmodeisenteredandPD0=0.
(2)DriverswillremainonifPD0=1(nopowerdown)untilselectedinputchannel,orpower ishigh.-downmodeischanged,or CS
PENIRQ
HIGH: Disableor(EnableandNotTouched)
New DefinitionPENIRQ
LOW: EnableandTouched
HIGH: Disableor
(EnableandNotTouched)
LOW: EnableandTouched
1
SCLK
CS
8 1
SDO
PENIRQ
SSDI
ControlBits
S
ControlBits
HIGH: Disableor(EnableandNotTouched)
NewPENIRQDefinition
LOW: EnableandTouched
8 1 18
11 10 9 8 7 6 5 4 3 2 1 0 11 10 9
A2
1 1
A1 A0
MODE
SER/
DFR PD1 PD0 A2 A1 A0
MODE
SER/
DFR PD1 PD0
n n +1
n n +1
HIGH: Disableor
(EnableandNotTouched)
LOW: EnableandTouched
Idle Acquire Conv Idle Acquire Conv Idle
TSC2008
SBAS406B – JUNE 2008 – REVISED MARCH 2009 ..........................................................................................................................................................
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A single touch result can be easily achieved using 24 SCLKs per cycle operation when the 12-bit ADC mode isused, as shown in Figure 30 . However, because this operation uses slightly more bus bandwidth, a more efficientmethod is to overlap the control bytes with the conversion result using 16 SCLKs per cycle operation; seeFigure 31 .
Figure 30. Conversion Timing — 12-Bit Mode, 24 SCLKs per Cycle, 8-Bit Bus Interface
The control bits for conversion n+ 1 can be overlapped with conversion nto allow for a conversion every 16clock cycles, as shown in Figure 31 . After submitting the control bits, the TSC2008 uses the internal clock toacquire data from seven conversions (see Figure 28 ). Deselecting the TSC2008 ( CS = '1') during this time periodallows the host to communicate with the other peripherals using the same SPI bus before reading out the ADCdata.
Figure 31. Conversion Timing — 12-Bit Mode, 16 SCLKs per Cycle, 8-Bit Bus Interface, with Earliest Startof New Command
24 Submit Documentation Feedback Copyright © 2008 – 2009, Texas Instruments Incorporated
Product Folder Link(s): TSC2008
8-BIT OPERATION TIMING
1
SCLK
CS
8 1
1 1
SDO
PENIRQ
SSDI
ControlBits
S
ControlBits
HIGH: Disableor(EnableandNotTouched)
New DefinitionPENIRQ
LOW: EnableandTouched
7 6 5 7 6 54 3 2 1 0
8 1 18
A2 A1 A0
MODE
SER/
DFR PD1 PD0 A2 A1 A0
MODE
SER/
DFR PD1 PD0
n n +1
n n +1
HIGH: Disableor
(EnableandNotTouched)
LOW: EnableandTouched
Idle Acquire Conv Idle Acquire Conv Idle
New DefPENIRQ
1
SCLK
CS
8 1
SDO
PENIRQ
SSDI
ControlBits
S
1 1
ControlBits
HIGH: Disableor(EnableandNotTouched)
LOW: EnableandTouched
7 6 5 7 6 5 44 3 2 1 0
8 1
A2 A1 A0
MODE
SER/
DFR PD1 PD0 A2 A1 A0
MODE
SER/
DFR PD1 PD0
n n +1
n n +1
HIGH: Disableor
(EnableandNotTouched)
LOW: EnableandTouched
Idle Acquire Conv Idle Acquire Conv Idle
TSC2008
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.......................................................................................................................................................... SBAS406B – JUNE 2008 – REVISED MARCH 2009
If the 8-bit ADC mode produces an acceptable result, then 16 SCLKs per cycle operation can also be used, asshown in Figure 32 . If SDO is released one-half SCLK cycle earlier (with the SDO adjusted option), the fastesttransfer (eight SCLKs per cycle) is achievable; see Figure 33 .
Figure 32. Conversion Timing — 8-Bit Mode, 16 SCLKs per Cycle, 8-Bit Bus Interface, without AdjustedSDO Timing (TSC2046 -Compatible)
Figure 33. Conversion Timing — 8-Bit Mode, 8 SCLKs per Cycle, 8-Bit Bus Interface, with Adjusted SDOTiming
Copyright © 2008 – 2009, Texas Instruments Incorporated Submit Documentation Feedback 25
Product Folder Link(s): TSC2008
POWER DISSIPATION
0 2 4 6 8 10 12 14
SampleOutputRate(kHz)
400
350
300
250
200
150
100
50
0
SupplyCurrent( A)m
12-BitAUXConversionwithMAV
SCLK=16MHz
VDD=1.8V
T =+25 C
A°
0 10 20 30 40 50 60 70 80 90
SampleOutputRate(kHz)
400
350
300
250
200
150
100
50
0
SupplyCurrent( A)m
12-BitAUXConversionwithoutMAV
SCLK=16MHz
VDD=1.8V
T =+25 C
A°
THROUGHPUT RATE AND SPI BUS TRAFFIC
TSC2008
SBAS406B – JUNE 2008 – REVISED MARCH 2009 ..........................................................................................................................................................
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There are two major power modes for the TSC2008: full-power (PD0 = '1') and auto power-down (PD0 = '0').Unlike its predecessor, the TSC2046/2046E (where operation is synchronous to SCLK and therefore powerdepends on the SCLK frequency), the TSC2008 uses an internal clock for conversion and is asynchronous toSCLK. TSC2008 power consumption depends on the sample rate and is minimally affected by the SCLKfrequency. Figure 30 shows a timing example using 12-bit resolution and 24 SCLKs per cycle. There areapproximately 2.5 SCLKs of acquisition time used at the end of the 8-bit command cycle. When thepreprocessing filter is on, the next six acquisition cycles are controlled by the internal conversion clock instead ofrelying on the external SCLK. A conversion time follows each acquisition time. Because there are six moreconversions to be completed, and also because of the power used from preprocessing, the power consumptionwhen the filter is on is higher than the power consumed without the filter at the same output rate, as shown inFigure 34 . This timing sequence also applies to Figure 31 to Figure 33 . Thus, using the TSC2008, powerconsumption can be very low, even with a low SCLK frequency.
Figure 34. Sample Output Rate vs Supply Current (with and without MAV filter)
Another important consideration for power dissipation is the reference mode of the converter. In the single-endedreference mode, the touch panel drivers are on only when the analog input voltage is being acquired (seeFigure 30 and Table 4 ). The external device (for example, a resistive touch screen), therefore, is only poweredduring the acquisition period. In the differential reference mode, the external device must be powered throughoutthe acquisition and conversion periods (see Figure 30 ). If the conversion rate is high, using this mode couldsubstantially increase power dissipation.
Although the internal A/D converter has a sample rate of up to 200kSPS, the throughput presented at the bus ismuch lower. The rate is reduced because preprocessing manages the redundant work of filtering out noise. Thethroughput is further limited by the SPI bus bandwidth, which is determined by the supply voltage and what thehost processor can support. The effective throughput is approximately 20kSPS at 8-bit resolution, or 10kSPS at12-bit resolution. The preprocessing saves a large portion of the SPI bandwidth for the system to use on otherdevices.
Each sample and conversion takes 19 CCLK cycles (12-bit), or 16 CCLK cycles (8-bit). The TSC2008 containsan internal clock that drives the state machines that perform the many functions of the device. This clock isdivided down to provide a clock that runs the A/D converter. The 8-bit ADC mode uses a 4MHz clock and the12-bit ADC mode uses a 2MHz clock. The actual frequency of this internal clock is slower than the namesuggests, and varies with the supply voltage. For a typical internal 4MHz OSC clock, the frequency actuallyranges from 3.66MHz to 3.82MHz. For VDD = 1.2V, the frequency reduces to 3.19MHz, which gives a3.19MHz/16 = 199kSPS raw A/D converter sample rate.
26 Submit Documentation Feedback Copyright © 2008 – 2009, Texas Instruments Incorporated
Product Folder Link(s): TSC2008
12-Bit Operation
8-Bit Operation
TSC2008
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.......................................................................................................................................................... SBAS406B – JUNE 2008 – REVISED MARCH 2009
For 12-bit operation, sending the conversion result across the SPI bus takes 16 or 24 bus clocks (SCLK clock);see Figure 31 and Figure 30 . There is an additional SCLK to be added to accommodate the cycle overhead (timebetween consecutive cycles) so that the total bus cycle time used for calculating the throughput is actually 17 or25 bus clocks (SCLK clock), respectively. Using a TSC2046-compatible SDO output mode or an SDO-adjustedoutput mode does not affect the transmission time.
Seven sample-and-conversions take (19 x 7) internal clocks to complete. The MAV filter loop requires 19 internalclocks. For VDD = 1.2V, the complete processed data cycle time calculations are shown in Table 6 . Because thefirst acquisition cycle overlaps with the I/O cycle, four CCLKs must be deducted from the total CCLK cycles. Thetotal time required is (19 × 7 + 19) – 4 = 148 CCLKs plus I/O.
For 8-bit operation, sending the conversion result across the SPI bus takes 8, 16, or 24 bus clocks (SCLK clock);see Figure 33 ,Figure 32 , and Figure 30 . There is an additional SCLK to be added to accommodate the cycleoverhead (time between consecutive cycles) so that the total bus cycle time used for calculating the throughput isactually 9, 17, or 25 bus clocks (SCLK clock), respectively. Sending the conversion result takes 17 or 25 SCLKsusing 8-bit resolution and a TSC2046-compatible SDO output mode. If an SDO-adjusted output mode is usedwith 8-bit resolution, it takes only 9 or 17 SCLKs to send the result back to host.
Seven sample-and-conversions take (16 x 7) internal clocks to complete. The MAV filter loop takes 19 internalclocks. For VDD = 1.2V, the complete processed data cycle time calculations are shown in Table 6 . Because thefirst acquisition cycle is overlapped with the I/O cycle, four CCLKs must be deducted from the total CCLK cycles.The total time required is (16 × 7 + 19) – 4 = 127 CCLKs plus I/O.
Table 6. Measurement Cycle Time Calculations
(1) (2)
f
SCLK
= 100kHz (Period = 10 µs)
8-Bit 17 × 10 µs + 127 × 322.6ns = 211.0 µs12-Bit 25 × 10 µs + 148 × 645.2ns = 345.5 µs
f
SCLK
= 1MHz (Period = 1 µs)
8-Bit 17 × 1 µs + 127 × 322.6ns = 58.0 µs12-Bit 25 × 1 µs + 148 × 645.2ns = 120.5 µs
f
SCLK
= 2MHz (Period = 500ns)
8-Bit 17 × 500ns + 127 × 322.6ns = 49.5 µs12-Bit 25 × 500ns + 148 × 645.2ns = 108.0 µs
f
SCLK
= 2.5MHz (Period = 400ns)
8-Bit 17 × 400ns + 127 × 322.6ns = 47.8 µs12-Bit 25 × 400ns + 148 × 645.2ns = 105.5 µs
f
SCLK
= 4MHz (Period = 250ns)
8-Bit 17 × 250ns + 127 × 322.6ns = 45.2 µs12-Bit 25 × 250ns + 148 × 645.2ns = 101.7 µs
f
SCLK
= 10MHz (Period = 100ns)
8-Bit 17 × 100ns + 127 × 322.6ns = 42.7 µs12-Bit 25 × 100ns + 148 × 645.2ns = 98.0 µs
f
SCLK
= 16MHz (Period = 62.5ns)
8-Bit 17 × 62.5ns + 127 × 322.6ns = 42.0 µs12-Bit 25 × 62.5ns + 148 × 645.2ns = 97.1 µs
f
SCLK
= 25MHz (Period = 40ns)
8-Bit 17 × 40ns + 127 × 322.6ns = 41.7 µs12-Bit 25 × 40ns + 148 × 645.2ns = 96.5 µs
(1) 8-bit mode cycle time is calculated based on SDO-adjusted output mode.(2) CCLK period used for calculation is worst-case at 1.2V supply, 322.6ns.
Copyright © 2008 – 2009, Texas Instruments Incorporated Submit Documentation Feedback 27
Product Folder Link(s): TSC2008
TSC2008
SBAS406B – JUNE 2008 – REVISED MARCH 2009 ..........................................................................................................................................................
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As an example, use V
DD
= 1.2V and 12-bit mode with 2MHz SPI clock (f
SCLK
= 2MHz). The equivalent TSCthroughput is at least seven times faster than the effective throughput across the bus (9.26k x 7 = 64.82kSPS).The supply current to the TSC for this rate and configuration is 240.08 µA. To achieve an equivalent samplethroughput of 8.2kSPS using the device without preprocessing, the TSC2008 consumes only (8.2/64.82) ×240.08 µA = 30.37 µA.
Table 7. Effective and Equivalent Throughput RatesTSCCONVERSION EFFECTIVE EQUIVALENT NO. NO. CCLKSUPPLY SPI BUS CYCLE TIME THROUGHPUT THROUGHPUT OF OF f
CCLK
PERIODSVOLTAGE SPEED (f
SCLK
) RESOLUTION ( µs) (kSPS) (kSPS) SCL CCLK (kHz) (ns)
8-bit 204.3 4.89 34.26 17 127 3700 270.3100kHz
12-bit 330.0 3.03 21.21 25 148 1850 540.5
8-bit 51.3 19.48 136.39 17 127 3700 270.31MHz
12-bit 105.0 9.52 66.67 25 148 1850 540.5
8-bit 42.8 23.35 163.46 17 127 3700 270.32MHz
12-bit 92.5 10.81 75.68 25 148 1850 540.5
8-bit 41.1 24.32 170.22 17 127 3700 270.32.5MHz
12-bit 90.0 11.11 77.78 25 148 1850 540.52.7V
8-bit 38.6 25.92 181.47 17 127 3700 270.34MHz
12-bit 86.3 11.59 81.16 25 148 1850 540.5
8-bit 36.0 27.76 194.31 17 127 3700 270.310MHz
12-bit 82.5 12.12 84.85 25 148 1850 540.5
8-bit 35.4 28.26 197.81 17 127 3700 270.316MHz
12-bit 81.6 12.26 85.82 25 148 1850 540.5
8-bit 35.0 28.57 199.98 17 127 3700 270.325MHz
12-bit 81.0 12.35 86.42 25 148 1850 540.5
8-bit 205.3 4.87 34.10 17 127 3600 277.8100kHz
12-bit 332.2 3.01 21.07 25 148 1800 555.6
8-bit 52.3 19.13 133.90 17 127 3600 277.81MHz
12-bit 107.2 9.33 65.28 25 148 1800 555.6
8-bit 43.8 22.84 159.90 17 127 3600 277.82MHz
12-bit 94.7 10.56 73.90 25 148 1800 555.6
8-bit 42.1 23.77 166.36 17 127 3600 277.81.8V 2.5MHz
12-bit 92.2 10.84 75.90 25 148 1800 555.6
8-bit 39.5 25.30 177.09 17 127 3600 277.84MHz
12-bit 88.5 11.30 79.12 25 148 1800 555.6
8-bit 37.0 27.04 189.30 17 127 3600 277.810MHz
12-bit 84.7 11.80 82.62 25 148 1800 555.6
8-bit 36.3 27.52 192.62 17 127 3600 277.816MHz
12-bit 83.8 11.94 83.55 25 148 1800 555.6
8-bit 211.0 4.74 33.18 17 127 3100 322.5100kHz
12-bit 345.5 2.89 20.26 25 148 1550 645.2
8-bit 58.0 17.25 120.76 17 127 3100 322.51MHz
12-bit 120.5 8.3 58.10 25 148 1550 645.2
8-bit 49.5 20.22 141.51 17 127 3100 322.52MHz
12-bit 108.0 9.26 64.82 25 148 1550 645.21.2V
8-bit 47.8 20.93 146.54 17 127 3100 322.52.5MHz
12-bit 105.5 9.48 66.36 25 148 1550 645.2
8-bit 45.2 22.12 154.81 17 127 3100 322.54MHz
12-bit 101.7 9.83 68.81 25 148 1550 645.2
8-bit 44.4 22.54 157.77 17 127 3100 322.55MHz
12-bit 100.5 9.95 69.66 25 148 1550 645.2
28 Submit Documentation Feedback Copyright © 2008 – 2009, Texas Instruments Incorporated
Product Folder Link(s): TSC2008
RESET
Software Reset
1
SCLK
CS
8 1
S 0 0 X X X1 1SDI
ControlBits
S
ControlBits
8
tD(RESET)
tSU(SCLKF-CSR) tSU(CSF-SCLK1R)
A2 A1 A0
MODE
SER/
DFR PD1 PD0
SureSet
01
0000 0
1
SPILockup 24-BitSureSetSequence
CS
SCLK
SDI 1
00
1
Reset NormalOperation
TSC2008
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.......................................................................................................................................................... SBAS406B – JUNE 2008 – REVISED MARCH 2009
The TSC2008 can be reset with three different methods: power-on reset (POR), software reset, and theproprietary SureSet function. The configuration bits (see Table 3 , bit[3:1]) accessible through the setup command('010') are reset to the respective default values listed in Table 3 after any reset occurs (POR, software reset, orSureSet).
The TSC2008 has a software reset command that can be issued by submitting the 8-bit command '1010 0001'via the SPI, as shown in Figure 35 . This command resets the device to the default configuration. All the settingsin the control byte are reset to default values (see Table 2 and Table 3 ).
Figure 35. Software Reset Timing
Table 8. Timing Requirements for Figure 35PARAMETER TEST CONDITIONS MIN MAX UNIT
1.2V ≤VDD < 1.6V 22 nst
SU(CSF-SCLK1R)
Enable lead time
1.6 ≤VDD < 3.6V 14 ns
1.2V ≤VDD < 1.6V 50 nst
SU(SCLKF-CSR)
Enable lag time
1.6 ≤VDD < 3.6V 20 ns
t
D(RESET)
Reset period requirement 200 ns
The TSC2008 uses SureSet, a unique reset function. SureSet works in the same way as a hardware resetexcept that it does not require a dedicated reset pin on the device. SureSet works independently from thesoftware reset and power-on reset. For example, the software reset works only after the interface (internal statemachine) is fully functional, whereas SureSet works without the interface. In the unlikely event that the hostbecomes out-of-sync with the TSC2008, and forcing CS high does not reset the state machine, the host cansubmit a 24-bit sequence (0x06D926) that resets the device to a default state (the same as the power-up state),as shown in Figure 36 . In order to reset the TSC2008, the device must be selected ( CS low) before submittingthis sequence.
Figure 36. SureSet Timing
Copyright © 2008 – 2009, Texas Instruments Incorporated Submit Documentation Feedback 29
Product Folder Link(s): TSC2008
Power-On Reset
tDEVICE_READY
1.2Vto3.6V
0.9V
0.3V
0V
VDD
tVDD_OFF_RAMP
tVDD_OFF
tVDD_ON_RAMP
Temperature( C)°
V OffTimeforValidPOR(s)
DD
-40 -20
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
0 20 40 60 80 100
RecommendedV OffTime
forT = 40 Cto+85 C- ° °
DD
A
TypicalV OffTimeforVariousTemperatures
DD
TSC2008
SBAS406B – JUNE 2008 – REVISED MARCH 2009 ..........................................................................................................................................................
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During TSC2008 power up, an internal power-on reset (POR) is triggered if the power-supply ramping meets thetiming requirements shown in Figure 37 and listed in Table 9 . The recommended and typical V
DD
off times areshown in Figure 38 . The POR brings the TSC2008 to the default working condition. If the system is not able tomeet the power ramping timing requirements, or if the system is not properly reset (even after a POR), thenincluding the SureSet reset in the initialization routine is recommended.
Figure 37. Power-On Reset Timing
Table 9. Timing Requirements for Figure 37PARAMETER TEST CONDITIONS MIN MAX UNIT
t
VDD_OFF_RAMP
T
A
= – 40 ° C to +85 ° C 2 kV/s
T
A
= – 40 ° C to +85 ° C 1 st
VDD_OFF
T
A
= – 20 ° C to +85 ° C 0.3 s
t
VDD_ON_RAMP
T
A
= – 40 ° C to +85 ° C 12 kV/s
t
DEVICE_READY
T
A
= – 40 ° C to +85 ° C 2 ms
Figure 38. V
DD
Off Time vs Temperature
30 Submit Documentation Feedback Copyright © 2008 – 2009, Texas Instruments Incorporated
Product Folder Link(s): TSC2008
LAYOUT
TSC2008
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.......................................................................................................................................................... SBAS406B – JUNE 2008 – REVISED MARCH 2009
The following layout suggestions should obtain optimum performance from the TSC2008. Keep in mind thatmany portable applications have conflicting requirements for power, cost, size, and weight. In general, mostportable devices have fairly clean power and grounds because most of the internal components are very lowpower. This situation would mean less bypassing for the converter power and less concern regarding grounding.However, each situation is unique and the following suggestions should be reviewed carefully.
For optimum performance, care should be taken with the physical layout of the TSC2008 circuitry. The basicSAR architecture is sensitive to glitches or sudden changes on the power supply, reference, ground connections,and digital inputs that occur just before latching the output of the analog comparator. Therefore, during any singleconversion for an n-bit SAR converter, there are nwindows in which large external transient voltages can easilyaffect the conversion result. Such glitches might originate from switching power supplies, nearby digital logic, andhigh power devices. The degree of error in the digital output depends on the reference voltage, layout, and theexact timing of the external event. The error can change if the external event changes in time with respect to theSCLK input.
With this in mind, power to the TSC2008 should be clean and well-bypassed. A 0.1 µF ceramic bypass capacitorshould be placed as close to the device as possible. In addition, a 1 µF to 10 µF capacitor may also be needed ifthe impedance of the connection between VDD/REF and the power supply is high.
A bypass capacitor is generally not needed on the VDD/REF pin because the internal reference is buffered by aninternal op amp. If an external reference voltage originates from an op amp, make sure that it can drive anybypass capacitor that is used without oscillation.
The TSC2008 architecture offers no inherent rejection of noise or voltage variation with regard to using anexternal reference input, which is of particular concern when the reference input is tied to the power supply. Anynoise and ripple from the supply appear directly in the digital results. While high-frequency noise can be filteredout, voltage variation as a result of line frequency (50Hz or 60Hz) can be difficult to remove. Some packageoptions have pins labeled as VOID. Avoid any active trace going under any pin marked as VOID unless it isshielded by a ground or power plane.
The GND pin should be connected to a clean ground point. In many cases, this point is the analog ground. Avoidconnections that are too near the grounding point of a microcontroller or digital signal processor. If needed, run aground trace directly from the converter to the power-supply entry or battery connection point. The ideal layoutincludes an analog ground plane dedicated to the converter and associated analog circuitry.
In the specific case of use with a resistive touch screen, care should be taken with the connection between theconverter and the touch screen. Because resistive touch screens have fairly low resistance, the interconnectionshould be as short and robust as possible. Loose connections can be a source of error when the contactresistance changes with flexing or vibrations.
As indicated previously, noise can be a major source of error in touch-screen applications (for example,applications that require a back-lit LCD panel). This electromagnetic interference (EMI) noise can be coupledthrough the LCD panel to the touch screen and cause flickering of the converted A/D converter data. Severalthings can be done to reduce this error, such as using a touch screen with a bottom-side metal layer connectedto ground, which couples the majority of noise to ground. Additionally, filtering capacitors, from Y+, Y – , X+, andX – to ground, can also help. Note, however, that the use of these capacitors increases screen settling time andrequires a longer time for panel voltages to stabilize. The resistor value varies depending on the touch screensensor used. The PENIRQ pull-up resistor (R
IRQ
) may be adequate for most of sensors. If not used, thegeneral-purpose analog input to the converter (AUX) should be connected to the analog ground plane.
Copyright © 2008 – 2009, Texas Instruments Incorporated Submit Documentation Feedback 31
Product Folder Link(s): TSC2008
TSC2008
SBAS406B – JUNE 2008 – REVISED MARCH 2009 ..........................................................................................................................................................
www.ti.com
Revision HistoryNOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (December 2008) to Revision B ........................................................................................... Page
•Deleted QFN (RGV) package availability status .................................................................................................................... 1•Changed product name in Ordering Information table from TSC2008I to TSC2008 ............................................................. 2•Added " I " to QFN package ordering numbers in Ordering Information table ........................................................................ 2•Changed Power On/Off Slope Requirements parameter names .......................................................................................... 4•Changed V
DD
off time test condition from – 21 ° C to +85 ° C .................................................................................................. 4•Changed and moved Power-On Reset section ................................................................................................................... 30
32 Submit Documentation Feedback Copyright © 2008 – 2009, Texas Instruments Incorporated
Product Folder Link(s): TSC2008
PACKAGE OPTION ADDENDUM
www.ti.com 15-Apr-2011
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TSC2008IRGVR ACTIVE VQFN RGV 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Add to cart
TSC2008IRGVT ACTIVE VQFN RGV 16 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Add to cart
TSC2008IYZGR ACTIVE DSBGA YZG 12 3000 Green (RoHS
& no Sb/Br) Call TI Level-1-260C-UNLIM Add to cart
TSC2008IYZGT ACTIVE DSBGA YZG 12 250 Green (RoHS
& no Sb/Br) Call TI Level-1-260C-UNLIM Add to cart
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TSC2008IRGVR VQFN RGV 16 2500 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
TSC2008IRGVT VQFN RGV 16 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
TSC2008IYZGR DSBGA YZG 12 3000 180.0 8.4 1.75 2.25 0.81 4.0 8.0 Q1
TSC2008IYZGT DSBGA YZG 12 250 180.0 8.4 1.75 2.25 0.81 4.0 8.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TSC2008IRGVR VQFN RGV 16 2500 367.0 367.0 35.0
TSC2008IRGVT VQFN RGV 16 250 210.0 185.0 35.0
TSC2008IYZGR DSBGA YZG 12 3000 210.0 185.0 35.0
TSC2008IYZGT DSBGA YZG 12 250 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
D: Max =
E: Max =
2.1 mm, Min =
1.6 mm, Min =
2.04 mm
1.539 mm
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