TSC2008 TS C20 08 www.ti.com.......................................................................................................................................................... SBAS406B - JUNE 2008 - REVISED MARCH 2009 1.2V to 3.6V, 12-Bit, Nanopower, 4-Wire Micro TOUCH SCREEN CONTROLLER with SPITM FEATURES APPLICATIONS * * * * * * * * * 1 234 * * * * * * * * * * * * 4-Wire Touch Screen Interface Single 1.2V to 3.6V Supply/Reference Ratiometric Conversion Effective Throughput Rate: - Up to 20kHz (8-Bit) or 10kHz (12-Bit) Preprocessing to Reduce Bus Activity High-Speed SPI (up to 25MHz) Simple Command-Based User Interface: - TSC2046 Compatible - 8- or 12-Bit Resolution On-Chip Temperature Measurement Touch Pressure Measurement Digital Buffered PENIRQ On-Chip, Programmable PENIRQ Pull-up Auto Power-Down Control Low Power (12-Bit, 8.2kHz Eq Rate): - 30.4A at 1.2V, fSCLK = 5MHz - 35.5A at 1.8V, fSCLK = 10MHz - 44.6A at 2.7V, fSCLK = 10MHz Power-On, Software, and SureSetTM Resets Enhanced ESD Protection: - 8kV HBM - 1kV CDM - 25kV Air Gap Discharge - 15kV Contact Discharge 1.5 x 2 WCSP-12 and 4 x 4 QFN-16 Packages Cellular Phones PDA, GPS, and Media Players Portable Instruments Point-of-Sale Terminals Multi-Screen Touch Control Systems DESCRIPTION The TSC2008 is a very low-power touch screen controller designed to work with power-sensitive, handheld applications that are based on advanced low-voltage processors. It works with a supply voltage as low as 1.2V, which can be supplied by a single-cell battery. It contains a complete, ultra-low power, 12-bit, analog-to-digital (A/D) resistive touch screen converter, including drivers and the control logic to measure touch pressure. In addition to these standard features, the TSC2008 offers preprocessing of the touch screen measurements to reduce bus loading, thus reducing the consumption of host processor resources that can then be redirected to more critical functions. The TSC2008 supports an SPI serial bus and data transmission. It offers programmable resolution of 8 or 12 bits to accommodate different screen sizes and performance needs. The TSC2008 is available in a 12-lead, (1,555 0,055mm) x (2,055 0,055mm) 3 x 4 array, wafer chip-scale package (WCSP), and a 16-pin, 4 x 4 QFN package. The TSC2008 is characterized for the -40C to +85C industrial temperature range. U.S. Patent No. 6246394; other patents pending. VDD/REF X+ XY+ Y- Touch Screen Sensor Drivers Mux SAR ADC TEMP AUX Internal Clock Preprocessing PENIRQ SPI Serial Interface and Control CS SCLK SDI SDO GND 1 2 3 4 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SureSet is a trademark of Texas Instruments. SPI is a trademark of Motorola Inc. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2008-2009, Texas Instruments Incorporated TSC2008 SBAS406B - JUNE 2008 - REVISED MARCH 2009.......................................................................................................................................................... www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) PRODUCT TYPICAL INTEGRAL LINEARITY (LSB) TSC2008 (1) TYPICAL GAIN ERROR (LSB) 1.5 NO MISSING CODES RESOLUTION (BITS) 0.7 PACKAGE TYPE PACKAGE DESIGNATOR SPECIFIED TEMPERATURE RANGE PACKAGE MARKING 16-Pin, 4x4 QFN RGV -40C to +85C TSC2008I 12-Pin, 3 x 4 Matrix, 1.5 x 2 WCSP YZG ORDERING NUMBER TSC2008IRGVT Small Tape and Reel, 250 TSC2008IRGVR Tape and Reel, 2500 TSC2008IYZGT Small Tape and Reel, 250 TSC2008IYZGR Tape and Reel, 3000 11 -40C to +85C TRANSPORT MEDIA, QUANTITY TSC2008I For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet, or see the TI website at www.ti.com. ABSOLUTE MAXIMUM RATINGS (1) Over operating free-air temperature range (unless otherwise noted). PARAMETER TSC2008 UNIT Analog input X+, Y+, AUX to GND -0.4 to VDD + 0.1 V Analog input X-, Y- to GND -0.4 to VDD + 0.1 V -0.3 to +5 V Digital input voltage to GND -0.3 to VDD + 0.3 V Digital output voltage to GND -0.3 to VDD + 0.3 V Power dissipation (TJ Max - TA)/JA Voltage Voltage range VDD to GND QFN package Thermal impedance, JA WCSP Low-K High-K 47 C/W 113 C/W 62 C/W Operating free-air temperature range, TA -40 to +85 C Storage temperature range, TSTG -65 to +150 C Junction temperature, TJ Max Lead temperature IEC contact discharge (2) IEC air discharge (2) (1) (2) 2 +150 C Vapor phase (60 sec) +215 C Infrared (15 sec) +220 C X+, X-, Y+, Y- 15 kV X+, X-, Y+, Y- 25 kV Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to absolute-maximum rated conditions for extended periods may affect device reliability. Test method based on IEC standard 61000-4-2. Device powered by battery. Contact Texas Instruments for test details. Submit Documentation Feedback Copyright (c) 2008-2009, Texas Instruments Incorporated Product Folder Link(s): TSC2008 TSC2008 www.ti.com.......................................................................................................................................................... SBAS406B - JUNE 2008 - REVISED MARCH 2009 ELECTRICAL CHARACTERISTICS At TA = -40C to +85C, VDD = +1.2V to +3.6V, unless otherwise noted. TSC2008 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT AUXILIARY ANALOG INPUT Input voltage range 0 Input capacitance VDD 12 Input leakage current -1 V pF +1 A 12 Bits A/D CONVERTER Resolution Programmable: 8 or 12 bits No missing codes 12-bit resolution 11 Integral linearity Bits LSB (1) 1.5 Differential linearity Offset error Gain error 1 LSB VDD = 1.8V -1.2 LSB VDD = 3.0V -3.1 LSB VDD = 1.8V 0.7 LSB VDD = 3.0V 0.1 LSB TA = +25C, VDD = 1.8V, setup command '10100000' 50 k TA = +25C, VDD = 1.8V, setup command '10101000' 90 k 6 TOUCH SENSORS PENIRQ pull-up resistor, RIRQ Switch on-resistance Y+, X+ Y-, X- Switch drivers drive current (2) 5 100ms duration 50 mA INTERNAL TEMPERATURE SENSOR Temperature range -40 Differential method (3) Resolution TEMP1 (4) Differential method (3) Accuracy TEMP1 (4) +85 C VDD = 3V 1.94 C/LSB VDD = 1.6V 1.04 C/LSB VDD = 3V 0.35 C/LSB VDD = 1.6V 0.19 C/LSB VDD = 3V 2 C/LSB VDD = 1.6V 2 C/LSB VDD = 3V 3 C/LSB VDD = 1.6V 3 C/LSB VDD = 1.2V 3.19 MHz VDD = 1.8V 3.66 MHz VDD = 2.7V 3.78 MHz VDD = 3.6V 3.82 MHz VDD = 1.2V 1.6 MHz VDD = 1.8V 1.83 MHz VDD = 2.7V 1.88 MHz INTERNAL OSCILLATOR 8-bit Internal clock frequency, fCCLK 12-bit VDD = 3.6V Frequency drift (1) (2) (3) (4) 1.91 MHz VDD = 1.6V 0.0056 %/C VDD = 3.0V 0.012 %/C LSB means least significant bit. With VDD (REF) = +2.5V, 1LSB is 610V. Assured by design, but not production tested. Exceeding 50mA source current may result in device degradation. Difference between TEMP1 and TEMP2 measurement; no calibration necessary. Temperature drift is -2.1mV/C. Submit Documentation Feedback Copyright (c) 2008-2009, Texas Instruments Incorporated Product Folder Link(s): TSC2008 3 TSC2008 SBAS406B - JUNE 2008 - REVISED MARCH 2009.......................................................................................................................................................... www.ti.com ELECTRICAL CHARACTERISTICS (continued) At TA = -40C to +85C, VDD = +1.2V to +3.6V, unless otherwise noted. TSC2008 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DIGITAL INPUT/OUTPUT Logic family CMOS VIH VIL Logic level 1.2V VDD < 3.6V 0.7 x VDD VDD + 0.3 V 1.2V VDD < 1.6V -0.3 0.2 x VDD V 1.6V VDD 3.6V -0.3 0.3 x VDD V -1 1 A IIL CS, SCLK, and SDI pins CIN CS, SCLK, and SDI pins 10 pF VOH IOH = 2 TTL loads VDD - 0.2 VDD V VOL IOL = 2 TTL loads 0 0.2 V ILEAK Floating output -1 1 A COUT Floating output 10 pF Data format Straight Binary POWER SUPPLY REQUIREMENTS Power-supply voltage VDD Specified performance 12-bit, fSCLK = 5MHz, fADC = 2MHz, PD[1:0] = 0,0 Quiescent supply current (VDD with sensor off) Power-down supply current 12-bit, fSCLK = 10MHz, fADC = 2MHz, PD[1:0] = 0,0 VDD = 1.2V VDD = 1.8V 3.6 V 69.6k eq rate (5) 1.2 285.0 320.0 A 8.2k eq rate (5) 30.4 37.7 A 82.6k eq rate (5) 344.0 425.0 A 34.5 42.2 A 84.8k eq rate (5) 461.0 570.0 A 8.2k eq rate (5) 44.6 55.1 A CS = 1, SDI = SCLK = 1, PENIRQ = 1, PD[1:0] = 0,0 0 0.8 A VDD = 2.7V 8.2k eq rate (5) POWER ON/OFF SLOPE REQUIREMENTS (see Figure 37) tVDD_OFF_RAMP TA = -40C to +85C 2 kV/s TA = -40C to +85C, VDD = 0V 1 s TA = -20C to +85C, VDD = 0V 0.3 s tVDD_ON_RAMP TA = -40C to +85C 12 kV/s tDEVICE_READY TA = -40C to +85C 2 ms tVDD_OFF (5) 4 See the Throughput Rate and SPI Bus Traffic section for calculation information. Submit Documentation Feedback Copyright (c) 2008-2009, Texas Instruments Incorporated Product Folder Link(s): TSC2008 TSC2008 www.ti.com.......................................................................................................................................................... SBAS406B - JUNE 2008 - REVISED MARCH 2009 PIN CONFIGURATION YZG PACKAGE WCSP-12 (TOP VIEW, SOLDER BUMPS ON BOTTOM SIDE) Y- GND NC AUX RGV PACKAGE(1) 4 x 4 QFN-16 (TOP VIEW) VDD/REF X+ Y+ X- SCLK GND AUX Y- CS SDI SDO PENIRQ A B C D 3 NC 13 NC 14 11 10 9 Rows 12 8 X- 7 Y+ 6 X+ 5 VDD/REF TSC2008 PENIRQ 15 SDO 16 Thermal Pad 2 1 Columns (1) 3 4 SCLK (FRONT VIEW) CS 2 SDI NC 1 The thermal pad is internally connected to the substrate. The thermal pad can be connected to the analog ground or left floating. Keep the thermal pad separate from the digital ground, if possible. PIN ASSIGNMENTS PIN NO. QFN WCSP PIN NAME 1 -- NC 2 B1 3 I/O A/D DESCRIPTION SDI I D Serial data input A1 CS I D Chip select 4 A2 SCLK I D Serial clock input 5 A3 VDD/REF 6 B3 X+ I A X+ channel input 7 C3 Y+ I A Y+ channel input 8 D3 X- I A X- channel input 9 D2 Y- I A Y- channel input 10 B2 GND 11 -- NC 12 C2 AUX 13 -- NC No connection 14 -- NC No connection 15 D1 PENIRQ O D Pen touch interrupt output. Active low when pen is touched. The output remains low until conversion is complete or pen touch is released. The rising edge signals the end of conversion (EOC). 16 C1 SDO O D Serial data output No connection Supply voltage and external reference input Ground No connection I A Auxiliary channel input. If not used, this input should be grounded. Submit Documentation Feedback Copyright (c) 2008-2009, Texas Instruments Incorporated Product Folder Link(s): TSC2008 5 TSC2008 SBAS406B - JUNE 2008 - REVISED MARCH 2009.......................................................................................................................................................... www.ti.com TIMING INFORMATION The TSC2008 supports SPI programming in mode CPOL = 0 and CPHA = 0. The falling edge of SCLK is used to change the output (MISO) data, and the rising edge is used to latch the input (MOSI) data. Eight SCLKs are required to complete the command byte cycle, and an additional eight or 16 SCLKs are required for the data to be read, depending on the mode used. CS (SS) tC(SCLK) tWH(SCLK) tF tR tWL(SCLK) SCLK tWH(CS) tSU(SCLKF-CSR) tSU(CSF-SCLK1R) tH(SCLKF-SDOVALID) SDO (MISO) MSB OUT tDIS(CSR-SDOZ) BIT 1 BIT 0 BIT 1 BIT 0 tD(CSF-SDOVALID) tSU(SDI-SCLKR) tH(SDI-SCLKR) SDI (MOSI) MSB IN NOTE: CPOL = 0, CPHA = 0, Byte 0 cycle requires 24 SCLKs, and Byte 1 cycle requires 8 SCLKs. Figure 1. Detailed I/O Timing CS SCLK tD(SCLKF-PENIRQF) PENIRQ/BUSY (TSC2008) tSU(PENIRQR-SCLKR) tD(SCLKR -PENIRQF) Figure 2. PENIRQ Timing 6 Submit Documentation Feedback Copyright (c) 2008-2009, Texas Instruments Incorporated Product Folder Link(s): TSC2008 TSC2008 www.ti.com.......................................................................................................................................................... SBAS406B - JUNE 2008 - REVISED MARCH 2009 TIMING REQUIREMENTS (1) All specifications typical at -40C to +85C, VDD = 1.6V, unless otherwise noted. PARAMETER tC(SCLK) SPI serial clock cycle time TEST CONDITIONS SPI serial clock frequency MAX UNIT 182 ns 1.6 VDD < 2.7V, 40% to 60% duty cycle 62.5 ns 2.7V VDD 3.6V, 40% to 60% duty cycle fSCLK MIN 1.2V VDD < 1.6V, 40% to 60% duty cycle 40 ns 1.2V VDD < 1.6V, 10pF load 5.5 MHz 1.6 VDD < 2.7V, 10pF load 16 MHz 2.7V VDD 3.6V, 10pF load 25 MHz tWH(SCLK) SPI serial clock high time 0.4 x tC(SCLK) 0.6 x tC(SCLK) ns tWL(SCLK) SPI serial clock low time 0.4 x tC(SCLK) 0.6 x tC(SCLK) ns tSU(CSF-SCLK1R) tD(CSF-SDOVALID) tH(SCLKF-SDOVALID) tWH(CS) Enable lead time Slave access time MISO data hold time Sequential transfer delay tSU(SDI-SCLKR) MOSI data setup time tH(SDI-SCLKR) MOSI data hold time tDIS(CSR-SDOZ) Slave MISO disable time 1.2V VDD < 1.6V 22 1.6 VDD < 3.6V 14 ns ns 1.2V VDD < 1.6V 55 ns 1.6 VDD < 3.6V 25 ns 40 80 ns 6 30 ns 1.2V VDD < 1.6V 1.6 VDD < 3.6V 1.2V VDD < 1.6V 50 ns 1.6 VDD < 3.6V 20 ns 1.2V VDD < 1.6V 25 ns 1.6 VDD < 3.6V 10 ns 5 ns 1.2V VDD < 1.6V 55 ns 1.6 VDD < 3.6V 25 ns 1.2V VDD < 1.6V 50 1.6 VDD < 3.6V 20 ns tSU(SCLKF-CSR) Enable lag time tD(SCLKR-PENIRQF) 1.2V VDD < 1.6V PENIRQ (used as BUSY) delay from SCLK rising edge 1.6 VDD < 3.6V tSU(PENIRQR-SCLKR) Setup time from PENIRQ 1.2V VDD < 1.6V (used as BUSY) to the rising 1.6 VDD < 3.6V edge of SCLK tD(RESET) Reset period requirement tR Rise time VDD = 3V, fSCLK = 25MHz 3 ns tF Fall time VDD = 3V, fSCLK = 25MHz 3 ns (1) ns 55 ns 25 ns 50 ns 20 ns 200 ns All input signals are specified with tR = tF = 5ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. Submit Documentation Feedback Copyright (c) 2008-2009, Texas Instruments Incorporated Product Folder Link(s): TSC2008 7 TSC2008 SBAS406B - JUNE 2008 - REVISED MARCH 2009.......................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS At TA = -40C to +85C, VDD = +1.2V to +3.6V, PD1 = PD0 = 0, fSCLK = 10MHz, fADC = fOSC/2 = 2MHz, 12-bit mode, non-continuous AUX measurement, and MAV filter enabled (see MAV Filter section), unless otherwise noted. POWER-DOWN SUPPLY CURRENT vs TEMPERATURE SUPPLY CURRENT vs TEMPERATURE 450 VDD = 3.0V VDD = 3.6V 60 40 VDD = 1.6V SPI = 5MHz 350 SPI = 2.5MHz 300 250 20 200 0 -40 -20 0 20 40 60 80 100 Temperature (C) 20 40 Temperature (C) Figure 3. Figure 4. SUPPLY CURRENT AUX CONVERSION SUPPLY CURRENT vs SUPPLY VOLTAGE -40 650 0 -20 200 Supply Current (mA) 550 500 SPI = 10MHz 450 400 SPI = 5MHz 350 SPI = 2.5MHz 300 250 150 X,Y, Z Conversion at 200SSPS Touch Sensor Modeled By: 2kW for X-Plane 2kW for Y-Plane 1kW for Z (Touch Resistance) TA = +25C 100 With MAV, SPI = 5MHz 50 MAV Bypassed, SPI = 5MHz 150 0 1.2 1.6 2.0 2.4 VDD (V) 2.8 3.2 1.2 3.6 1.6 2.0 2.4 VDD (V) 2.8 3.2 Figure 5. Figure 6. SUPPLY CURRENT (Part Not Addressed) vs TEMPERATURE SUPPLY CURRENT (Part Not Addressed) vs SUPPLY VOLTAGE 30 3.6 100 90 25 SPI = 10MHz 80 SPI = 10MHz Supply Current (mA) Supply Current (mA) 80 100 200 20 15 SPI = 5MHz 10 70 60 50 SPI = 5MHz 40 30 SPI = 2.5MHz 20 5 SPI = 2.5MHz 10 0 0 -40 -20 0 20 40 Temperature (C) 60 80 100 1.2 Figure 7. 8 60 250 600 Supply Current (mA) SPI = 10MHz 400 80 Supply Current (mA) Power-Down Supply Current (nA) 100 1.6 2.0 2.4 VDD (V) 2.8 3.2 3.6 Figure 8. Submit Documentation Feedback Copyright (c) 2008-2009, Texas Instruments Incorporated Product Folder Link(s): TSC2008 TSC2008 www.ti.com.......................................................................................................................................................... SBAS406B - JUNE 2008 - REVISED MARCH 2009 TYPICAL CHARACTERISTICS (continued) At TA = -40C to +85C, VDD = +1.2V to +3.6V, PD1 = PD0 = 0, fSCLK = 10MHz, fADC = fOSC/2 = 2MHz, 12-bit mode, non-continuous AUX measurement, and MAV filter enabled (see MAV Filter section), unless otherwise noted. CHANGE IN GAIN vs TEMPERATURE CHANGE IN OFFSET vs TEMPERATURE 2 2 VDD = 1.8V Delta from +25C (LSB) Delta from +25C (LSB) VDD = 1.8V 1 0 -1 -2 1 0 -1 -2 -40 0 -20 20 40 Temperature (C) 60 80 100 -40 20 40 Temperature (C) 60 80 Figure 9. Figure 10. SWITCH ON-RESISTANCE vs SUPPLY VOLTAGE SWITCH ON-RESISTANCE vs TEMPERATURE 100 6 11 X+, Y+: VDD = 3.0V to Pin X-, Y-: Pin to GND 10 Y+ X+ 5 9 Y+ 8 RON (W) RON (W) 0 -20 X+ 7 YX- 4 6 Y- 5 3 X- 4 2 3 8 7 1.6 2.0 2.4 VDD (V) 2.8 3.2 3.6 -20 0 20 40 Temperature (C) 60 Figure 11. Figure 12. SWITCH ON-RESISTANCE vs TEMPERATURE TEMP DIODE VOLTAGE vs TEMPERATURE 850 X+, Y+: VDD = 1.8V to Pin X-, Y-: Pin to GND X+ YX- 5 4 3 750 80 100 Measurement Includes A/D Converter Offset and Gain Errors 800 Y+ 6 RON (W) -40 TEMP Diode Voltage (mV) 1.2 95.7mV TEMP2 700 650 600 TEMP1 550 136mV 500 450 VDD = 1.8V 400 2 -40 -20 0 20 40 Temperature (C) 60 80 100 -40 Figure 13. -20 0 20 40 Temperature (C) 60 80 100 Figure 14. Submit Documentation Feedback Copyright (c) 2008-2009, Texas Instruments Incorporated Product Folder Link(s): TSC2008 9 TSC2008 SBAS406B - JUNE 2008 - REVISED MARCH 2009.......................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = -40C to +85C, VDD = +1.2V to +3.6V, PD1 = PD0 = 0, fSCLK = 10MHz, fADC = fOSC/2 = 2MHz, 12-bit mode, non-continuous AUX measurement, and MAV filter enabled (see MAV Filter section), unless otherwise noted. TEMP1 DIODE VOLTAGE vs SUPPLY VOLTAGE TEMP2 DIODE VOLTAGE vs SUPPLY VOLTAGE 704 586 584 582 580 578 576 VDD = VREF = 1.8V 574 1.2 Internal Oscillator Clock Frequency (MHz) TEMP2 Diode Voltage (mV) Measurement Includes A/D Converter Offset and Gain Errors 1.6 2.0 Measurement Includes A/D Converter Offset and Gain Errors 702 700 698 696 694 692 VDD = VREF = 1.8V 690 2.4 VDD (V) 2.8 3.2 1.2 3.6 1.6 2.0 2.4 VDD (V) 2.8 3.2 3.6 Figure 15. Figure 16. INTERNAL OSCILLATOR CLOCK FREQUENCY vs TEMPERATURE INTERNAL OSCILLATOR CLOCK FREQUENCY vs TEMPERATURE 3.40 Internal Oscillator Clock Frequency (MHz) TEMP1 Diode Voltage (mV) 588 3.30 3.20 3.10 3.00 2.90 2.80 VDD = 1.2V 2.70 -40 -20 0 20 40 Temperature (C) 60 80 3.70 3.69 3.68 3.67 3.66 3.65 3.64 3.63 3.62 3.61 VDD = 1.8V 3.60 100 -40 -20 0 Figure 17. 20 40 Temperature (C) 60 80 100 Figure 18. Internal Oscillator Clock Frequency (MHz) INTERNAL OSCILLATOR CLOCK FREQUENCY vs TEMPERATURE 3.90 3.85 3.80 3.75 VDD = 3.0V 3.70 -40 -20 0 20 40 Temperature (C) 60 80 100 Figure 19. 10 Submit Documentation Feedback Copyright (c) 2008-2009, Texas Instruments Incorporated Product Folder Link(s): TSC2008 TSC2008 www.ti.com.......................................................................................................................................................... SBAS406B - JUNE 2008 - REVISED MARCH 2009 OVERVIEW The TSC2008 is an analog interface circuit for a human interface touch screen device. All peripheral functions are controlled through the command byte and onboard state machines. While maintaining similarity in hardware, command, and software to its predecessor, the TSC2046 (or TSC2046E), the TSC2008 includes significant improvements such as: * Much stronger and more comprehensive electrostatic discharge (ESD) protection * Uses only 1/13 power for equivalent performance * 1/7 bus traffic * 3/16 size * Direct 1.8V interface * Prudent reset scheme * Saves 1/7 power if 8-bit SDO adjusted output mode used The TSC2008 consists of the following blocks (refer to the block diagram on the front page): * Touch Screen Sensor Drivers * Auxiliary Input (AUX) * Temperature Sensor * Acquisition Activity Preprocessing * Internal Conversion Clock * SPI Interface Communication with the TSC2008 is done via an SPI serial interface. The TSC2008 is an SPI slave device; therefore, data are shifted into or out of the TSC2008 under the control of the host microprocessor, which also provides the serial data clock. Control of the TSC2008 and its functions is accomplished by writing to the command register of an internal state machine. A simple command protocol (compatible with SPI) is used to address this register. A typical application of the TSC2008 is shown in Figure 20. 1.8VDC 1mF to 10mF 0.1mF Host Processor X+ VDD/REF GND PENIRQ SDO Y+ TSC2008 X- CS Y- Auxilary Input SDI SCLK GPIO SDO GND SDI AUX Touch Screen SCLK GPIO GND Figure 20. Typical Circuit Configuration Submit Documentation Feedback Copyright (c) 2008-2009, Texas Instruments Incorporated Product Folder Link(s): TSC2008 11 TSC2008 SBAS406B - JUNE 2008 - REVISED MARCH 2009.......................................................................................................................................................... www.ti.com TOUCH SCREEN OPERATION A resistive touch screen operates by applying a voltage across a resistor network and measuring the change in resistance at a given point on the matrix where the screen is touched by an input (stylus, pen, or finger). The change in the resistance ratio marks the location on the touch screen. The TSC2008 supports resistive 4-wire configurations, as shown in Figure 21. The circuit determines location in two coordinate pair dimensions, although a third dimension can be added for measuring pressure. 4-WIRE TOUCH SCREEN COORDINATE PAIR MEASUREMENT A 4-wire touch screen is typically constructed as shown in Figure 21. It consists of two transparent resistive layers separated by insulating spacers. Conductive Bar Transparent Conductor (ITO) Bottom Side Y+ X+ Silver Ink Transparent Conductor (ITO) Top Side XY- ITO = Indium Tin Oxide Insulating Material (Glass) Figure 21. 4-Wire Touch Screen Construction The 4-wire touch screen panel works by applying a voltage across the vertical or horizontal resistive network. The A/D converter converts the voltage measured at the point where the panel is touched. A measurement of the Y position of the pointing device is made by connecting the X+ input to a data converter chip, turning on the Y+ and Y- drivers, and digitizing the voltage seen at the X+ input. The voltage measured is determined by the voltage divider developed at the point of touch. For this measurement, the horizontal panel resistance in the X+ lead does not affect the conversion because of the high input impedance of the A/D converter. Voltage is then applied to the other axis, and the A/D converter converts the voltage representing the X position on the screen. This process provides the X and Y coordinates to the associated processor. Measuring touch pressure (Z) can also be done with the TSC2008. To determine pen or finger touch, the pressure of the touch must be determined. Generally, it is not necessary to have very high performance for this test; therefore, 8-bit resolution mode may be sufficient (however, data sheet calculations are shown using 12-bit resolution mode). There are several different ways of performing this measurement. The TSC2008 supports two methods. The first method requires knowing the X-plate resistance, the measurement of the X-Position, and two additional cross panel measurements (Z2 and Z1) of the touch screen (see Figure 22). Equation 1 calculates the touch resistance: R TOUCH + RX-plate @ 12 XPostition Z 2 *1 4096 Z 1 (1) Submit Documentation Feedback Copyright (c) 2008-2009, Texas Instruments Incorporated Product Folder Link(s): TSC2008 TSC2008 www.ti.com.......................................................................................................................................................... SBAS406B - JUNE 2008 - REVISED MARCH 2009 The second method requires knowing both the X-plate and Y-plate resistance, measurement of X-Position and Y-Position, and Z1. Equation 2 also calculates the touch resistance: RX-plate @ XPostition 4096 Y R TOUCH + *1 *R Y-plate @ 1* Position 4096 4096 Z1 (2) Measure X-Position X+ Y+ Touch X-Position Y- X- Measure Z1-Position Y+ X+ Touch Z1-Position Y- X- Y+ X+ Touch Z2-Position X- YMeasure Z2-Position Figure 22. Pressure Measurement When the touch panel is pressed or touched and the drivers to the panel are turned on, the voltage across the touch panel will often overshoot and then slowly settle down (decay) to a stable dc value. This effect is a result of mechanical bouncing caused by vibration of the top layer sheet of the touch panel when the panel is pressed. This settling time must be accounted for, or else the converted value is incorrect. Therefore, a delay must be introduced between the time the driver for a particular measurement is turned on, and the time a measurement is made. In some applications, external capacitors may be required across the touch screen for filtering noise picked up by the touch screen (for example, noise generated by the LCD panel or back-light circuitry). The value of these capacitors provides a low-pass filter to reduce the noise, but creates an additional settling time requirement when the panel is touched. The settling time typically shows up as gain error. The TSC2008 has a built-in noise filter (see the Preprocessing section). These capacitors can be reduced to minimal value or not installed. The TSC2008 touch screen interface can measure position (X,Y) and pressure (Z). Submit Documentation Feedback Copyright (c) 2008-2009, Texas Instruments Incorporated Product Folder Link(s): TSC2008 13 TSC2008 SBAS406B - JUNE 2008 - REVISED MARCH 2009.......................................................................................................................................................... www.ti.com INTERNAL TEMPERATURE SENSOR In some applications, such as battery recharging, an ambient temperature measurement is required. The temperature measurement technique used in the TSC2008 relies on the characteristics of a semiconductor junction operating at a fixed current level. The forward diode voltage (VBE) has a well-defined characteristic versus temperature. The ambient temperature can be predicted in applications by knowing the +25C value of the VBE voltage and then monitoring the delta of that voltage as the temperature changes. The TSC2008 offers two modes of temperature measurement. The first mode requires calibration at a known temperature, but only requires a single reading to predict the ambient temperature. The TEMP1 diode, shown in Figure 23, is used during this measurement cycle. This voltage is typically 580mV at +25C with a 10A current. The absolute value of this diode voltage can vary by a few millivolts; the temperature coefficient (TC) of this voltage is very consistent at -2.1mV/C. During the final test of the end product, the diode voltage is stored at a known room temperature, in system memory, for calibration purposes by the user. The result is an equivalent temperature measurement resolution of 0.3C/LSB (1LSB = 610V with VREF = 2.5V). VDD TEMP2 TEMP1 +IN GND REF Converter -IN GND Figure 23. Functional Block Diagram of Temperature Measurement Mode The second mode does not require a test temperature calibration, but uses a two-measurement (differential) method to eliminate the need for absolute temperature calibration and for achieving 2C/LSB accuracy. This mode requires a second conversion of the voltage across the TEMP2 diode with a resistance 91 times larger than the TEMP1 diode. The voltage difference between the first (TEMP1) and second (TEMP2) conversion is represented by: DV + kT q @ ln(N) (3) Where: N = the resistance ratio = 91. k = Boltzmann's constant = 1.3807 x 10-23 J/K (joules/kelvins). q = the electron charge = 1.6022 x 10-19 C (coulombs). T = the temperature in kelvins (K). This method can provide much improved absolute temperature measurement, but a lower resolution of 1.6C/LSB. The resulting equation to solve for T is: q @ DV T+ k @ ln(N) (4) Where: V = VBE (TEMP2) - VBE(TEMP1) (in mV). T = 2.573 V (in K), or T = 2.573 V - 273 (in C). Temperature 1 and/or temperature 2 measurements have the same timing as shown in Figure 30 to Figure 33. 14 Submit Documentation Feedback Copyright (c) 2008-2009, Texas Instruments Incorporated Product Folder Link(s): TSC2008 TSC2008 www.ti.com.......................................................................................................................................................... SBAS406B - JUNE 2008 - REVISED MARCH 2009 ANALOG-TO-DIGITAL CONVERTER Figure 24 shows the analog inputs of the TSC2008. The analog inputs (X, Y, and Z touch panel coordinates, chip temperature and auxiliary inputs) are provided via a multiplexer to the Successive Approximation Register (SAR) analog-to-digital converter (ADC). The A/D architecture is based on capacitive redistribution architecture, which inherently includes a sample-and-hold function. VDD/REF 50kW RIRQ PENIRQ 90kW Pen Touch Median Value Filter and Averaging Filter (MAV) X+ TEMP2 TEMP1 Control Logic A[2:0] GND X- VDD Y+ +IN Y- +REF Converter -IN -REF GND AUX GND Figure 24. Analog Input Section (Simplified Diagram) A unique configuration of low on-resistance switches allows an unselected A/D converter input channel to provide power and an accompanying pin to provide ground for driving the touch panel. By maintaining a differential input to the converter and a differential reference input architecture, it is possible to negate errors caused by the driver switch on-resistance. Reference The TSC2008 uses an external voltage reference applied to the VDD/REF pin. The upper reference voltage range is the same as the supply voltage range, which allows for simple, 1.2V to 3.6V single-supply operation of the chip. Submit Documentation Feedback Copyright (c) 2008-2009, Texas Instruments Incorporated Product Folder Link(s): TSC2008 15 TSC2008 SBAS406B - JUNE 2008 - REVISED MARCH 2009.......................................................................................................................................................... www.ti.com Reference Mode There is a critical item regarding the reference when making measurements while the switch drivers are on. For this discussion, it is useful to consider the basic operation of the TSC2008 (see Figure 20). This particular application shows the device being used to digitize a resistive touch screen. A measurement of the current Y position of the pointing device is made by connecting the X+ input to the A/D converter, turning on the Y+ and Y- drivers, and digitizing the voltage on X+, as shown in Figure 25. For this measurement, the resistance in the X+ lead does not affect the conversion; it does affect the settling time, but the resistance is usually small enough that this is not a concern. However, because the resistance between Y+ and Y- is fairly low, the on-resistance of the Y drivers does make a small difference. Under the situation outlined so far, it would not be possible to achieve a 0V input or a full-scale input regardless of where the pointing device is on the touch screen because some voltage is lost across the internal switches. In addition, the internal switch resistance is unlikely to track the resistance of the touch screen, providing an additional source of error. VDD/REF Y+ +IN X+ +REF Converter -IN -REF Y- GND Figure 25. Simplified Diagram of Single-Ended Reference This situation is resolved, as shown in Figure 26, by using the differential mode; the +REF and -REF inputs are connected directly to Y+ and Y-, respectively. This mode makes the A/D converter ratiometric. The result of the conversion is always a percentage of the external reference, regardless of how it changes in relation to the on-resistance of the internal switches. Note that there is an important consideration regarding power dissipation when using the ratiometric mode of operation (see the Power Dissipation section for more details). VDD/REF Y+ +IN X+ +REF Converter -IN -REF Y- GND Figure 26. Simplified Diagram of Differential Reference (Both Y Switches are Enabled, and X+ is the Analog Input) 16 Submit Documentation Feedback Copyright (c) 2008-2009, Texas Instruments Incorporated Product Folder Link(s): TSC2008 TSC2008 www.ti.com.......................................................................................................................................................... SBAS406B - JUNE 2008 - REVISED MARCH 2009 Touch Screen Settling In some applications, external capacitors may be required across the touch screen to filter noise picked up by the touch screen (that is, noise generated by the LCD panel or backlight circuitry). These capacitors provide a low-pass filter to reduce the noise, but they also cause a settling time requirement when the panel is touched. The settling time typically shows up as a gain error. The problem is that the input and/or reference has not settled to its final steady-state value before the A/D converter samples the input(s) and provides the digital output. Additionally, the reference voltage may continue to change during the measurement cycle. There are two ways to resolve this issue. Option 1 is to stop or slow down the TSC2008 SCLK for the required touch screen settling time. This option allows the input and reference to have stable values for the Acquire period (three clock cycles of the TSC2008; see Figure 30). This option works for both the single-ended and the differential modes. Option 2 is to operate the TSC2008 in the differential mode only for the touch screen measurements and command the TSC2008 to remain on (touch screen drivers ON) and not go into power-down (PD0 = 1). Several conversions are made, depending on the settling time required and the TSC2008 data rate. Once the required number of conversions have been made, the processor commands the TSC2008 to go into its power-down state on the last measurement. This process is required for X-Position, Y-Position, and Z-Position measurements. Touch Detect The PENIRQ can be used as an interrupt to the host. RIRQ is an internal pull-up resistor with a programmable value of either 50k (default) or 90k (which allows the total resistance from X+ to Y- to be as high as 30k). Write command '1010' (setup command) followed by data '1xx0' sets the pull-up resistor to 90k. NOTE: The first three bits must be '0's and the select bit is the last bit. To change the pull-up resistor back to 50k, issue write command '1010' followed by data '0xx0'. An example for the Y-position measurement is detailed in Figure 27. The PENIRQ output is pulled high by an internal pull-up resistor. While in power-down mode with PD0 = 0, the Y- driver is on and connected to GND, and the PENIRQ output is connected to the X+ input. When the panel is touched, the X+ input is pulled to ground through the touch screen, and PENIRQ output goes low because of the current path through the panel to GND, initiating an interrupt to the processor. During the measurement cycle for X-, Y-, and Z-Position, the X+ input is disconnected from the PENIRQ pull-down transistor to eliminate any pull-up resistor leakage current from flowing through the touch screen, thus causing no errors. If the last command byte written to the TSC2008 contains PD0 = 1, the pen-interrupt output function is disabled and cannot detect when the panel is touched. In order to re-enable the pen-interrupt output function under these circumstances, a command byte must be written to the TSC2008 with PD0 = 0. If the last command byte contains PD0 = 0, then the pen-interrupt function is enabled at the end of a conversion. The end of conversion (EOC) occurs on the rising edge of PENIRQ. In both cases previously listed, it is recommended that whenever the host writes to the TSC2008, the master processor masks the interrupt associated to PENIRQ. This masking prevents false triggering of interrupts when the PENIRQ line is disabled in the cases previously listed. Submit Documentation Feedback Copyright (c) 2008-2009, Texas Instruments Incorporated Product Folder Link(s): TSC2008 17 TSC2008 SBAS406B - JUNE 2008 - REVISED MARCH 2009.......................................................................................................................................................... www.ti.com Connect to Analog Supply VDD/REF PENIRQ VDD RIRQ Pen Touch Control Logic TEMP1 High when the X+ or Y+ driver is on. X+ TEMP2 Y+ Sense GND Y- High when the X+ or Y+ driver is on, or when any sensor connection/shortcircuit tests are activated. ON Vias go to system analog ground plane. GND GND Figure 27. Example of a Pen-Touch Induced Interrupt via the PENIRQ Pin Preprocessing The TSC2008 has a fixed combined MAV filter (median value filter and averaging filter). MAV Filter If the acquired signal source is noisy because of the digital switching circuit, it may necessary to evaluate the data without noise. In this case, the median value filter operation helps remove the noise. The array of seven converted results is sorted first. The middle three values are then averaged to produce the output value of the MAV filter. The MAV filter is applied to all measurements for all analog inputs including the touch screen inputs, temperature measurements TEMP1 and TEMP2, and auxiliary input AUX. To shorten the conversion time, the MAV filter may be bypassed though the setup command; see Table 2 and Table 4. 7 measurements input into temporary array 7 7 Acquired Data Sort by descending order Averaging output from window of 3 7 3 Figure 28. MAV Filter Operation (Patent Pending) 18 Submit Documentation Feedback Copyright (c) 2008-2009, Texas Instruments Incorporated Product Folder Link(s): TSC2008 TSC2008 www.ti.com.......................................................................................................................................................... SBAS406B - JUNE 2008 - REVISED MARCH 2009 DIGITAL INTERFACE The TSC2008 communicates through a standard SPI bus. The SPI allows full-duplex, synchronous, serial communication between a host processor (the master) and peripheral devices (slaves). The SPI master generates the synchronizing clock and initiates transmissions. The SPI slave devices depend on a master to start and synchronize transmissions. A transmission begins when initiated by a master SPI. The byte from the master SPI begins shifting in on the slave SDI (MOSI--master out, slave in) pin under the control of the master serial clock. As the byte shifts in on the SDI (MOSI) pin, a byte shifts out on the SDO (MISO--master in, slave out) pin to the master shift register. The idle state of the TSC2008 serial clock is logic low, which corresponds to a clock polarity setting of 0 (typical microprocessor SPI control bit CPOL = 0). The TSC2008 interface is designed so that with a clock phase bit setting of 0 (typical microprocessor SPI control bit CPHA = 0), the master begins driving its MOSI pin and the slave begins driving its MISO pin half an SCLK before the first serial clock edge. The CS (SS, slave select) pin can remain low between transmissions. Table 1. Standard SPI Signal Names vs Common Serial Interface Signal Names SPI SIGNAL NAMES COMMON SERIAL INTERFACE NAMES SS (Slave Select) CS (Chip Select) MISO (Master In Slave Out) SDO (Serial Data Out) MOSI (Master Out Slave In) SDI (Serial Data In) As a comparison to the popular TSC2046 timing characteristics, a few differences between the interfaces are worth notice: 1. Unlike the TSC2046, there is not a 15 SCLK cycle for the TSC2008. 2. There is an adjusted SDO timing that allows an 8-bit, back-to-back cycle. 3. The TSC2008 uses an internal conversion clock; therefore, the SPI serial clock (SCLK) can only affect the acquiring period and I/O transfer. 4. The TSC2008 uses an internal clock to perform the conversion. PENIRQ rises when the conversion is complete. If the host issues an SCLK before the conversion is complete, PENIRQ also rises, but the conversion result is invalid. 5. If a new command is issued before a conversion is complete (indicated by EOC), then the conversion is aborted. 6. Releasing the SPI bus (by raising CS) during the conversion is OK, but releasing the SPI during the I/O transfer (for example, read result) aborts the data transfer. Submit Documentation Feedback Copyright (c) 2008-2009, Texas Instruments Incorporated Product Folder Link(s): TSC2008 19 TSC2008 SBAS406B - JUNE 2008 - REVISED MARCH 2009.......................................................................................................................................................... www.ti.com CONTROL BYTE The control byte (on SDI), as shown in Table 2, provides the start conversion, addressing, A/D converter resolution, configuration, and power-down of the TSC2008. Figure 30, Table 2, and Table 3 give detailed information regarding the order and description of these control bits within the control byte. Table 2. Order of the Control Bits in the Control Byte BIT 7 (MSB) BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 (LSB) COMMENT S A2 A1 A0 MODE SER/DFR PD1 PD0 Excludes setup command S 0 1 0 Pull-up Bypass Timing Reset Setup command Table 3. Description of the Control Bits in the Control Byte BIT DESCRIPTION 7 Start Bit. When this bit = '1', it indicates this is one of the user commands. A new control byte can start every 16th clock cycle in 12-bit conversion mode or every 12th clock cycle in 8-bit conversion mode (see Figure 30 through Figure 33). 6-4 Bit[6:4] = A[2:0]. Channel select command if A[2:0] '010'. These channel select bits, along with the SER/DFR bit, control the setting of the multiplexer input, touch driver switches, and reference inputs (see Table 4 and Figure 30 through Figure 33). Bit[6:4] = A[2:0]. Setup command if A[2:0] = '010'. 3 Mode Select Bit. This bit controls the number of bits for the next conversion. 0: 12 bits (low) 1: 8 bits (high). Pull-up Resistor Select Bit (1). 0: 50k PENIRQ pull-up resistor (default). 1: 90k PENIRQ pull-up resistor. 2 Single-Ended/Differential Reference Select Bit (SER/DFR). Along with the channel select bits, A[2:0], this bit controls the setting of the multiplexer input, touch driver switches, and reference inputs (see Table 4). Bypass Noise Filter Bit (1). 0: MAV noise filter enabled (default). 1: MAV noise filter bypassed. 1-0 (1) 20 Bit[1:0] = PD[1:0]. Power Down Mode Select Bits. See Table 5 for details. Bit 1: Timing Select Bit (1). 0: TSC2046-compatible timing for SDO during data read (default) 1: Adjusted SDO timing; MSB appears before 1st rising clock edge. Bit 0: Software Reset Bit. 0: Nothing happens (default). 1: Software reset. These bits configure the pull-up resistor value, control the filter bypass, and select the SDO output timing. The bits are static and the values are stored in register bits that will only be reset to default by a reset condition (power-on reset, software reset, or SureSet) or changed with the setup command. Submit Documentation Feedback Copyright (c) 2008-2009, Texas Instruments Incorporated Product Folder Link(s): TSC2008 TSC2008 www.ti.com.......................................................................................................................................................... SBAS406B - JUNE 2008 - REVISED MARCH 2009 The control byte begins with a start bit followed by seven control bits. For the command to be valid, the start bit must be '1'. Do not use '0' for the start bit; it is reserved for factory use. Initiate Start--The first bit is the start bit (S), and must always be high to initiate the start of a user-controllable control byte. When the start bit = '0', it is reserved for factory use. Addressing and Command Decoding--The next three bits in the control byte following the start bit are three addressing bits A[2:0] used to select the active input channel(s) of the input multiplexer (see Table 4 and Figure 24), enable the touch screen drivers, select the reference inputs, or decode other commands. Bit[6:4] = '010' is the setup command that is used to configure the TSC. Bit[3:0] followed by the setup command are the configuration bits and are used to select the pull-up resistor value, bypass the noise filter (in the preprocessing unit), select the SDO output timing, and perform the software reset. Bit[3:1] are static--that is, they do not change once programmed unless either the device is powered off, one of the reset conditions occur (power-on reset, software reset, or SureSet), or unless changed with the setup command. Note that if any reset occurs, bit[3:1] is set to the default values listed in Table 3. Any function decoded as shown in Table 4 (excluding the setup command) has no access to these four configuration bits. Table 4. Converter Function Select (CFS) Information (1) A[2:0] BIT 2 SER/DFR +REF -REF = -IN INPUT TO ADC = +IN X-DRIVERS Y-DRIVERS DESCRIPTION 0h Don't care VDD GND TEMP1 All OFF All OFF Measure TEMP1 1h 1 (single-ended) VDD GND X+ All OFF All ON Measure Y position 1h 0 (differential mode) Y+ Y- X+ All OFF All ON Measure Y position 2h Used as noise filter bypass -- -- -- All OFF All OFF Setup command (2) 3h 1 (single-ended) VDD GND X+ X- ON Y+ ON Measure Z1 position 3h 0 (differential mode) Y+ X- X+ X- ON Y+ ON Measure Z1 position 4h 1 (single-ended) VDD GND Y- X- ON Y+ ON Measure Z2 position 4h 0 (differential mode) Y+ X- Y- X- ON Y+ ON Measure Z2 position 5h 1 (single-ended) VDD GND Y+ All ON All OFF Measure X position 5h 0 (differential mode) X+ X- Y+ All ON All OFF Measure X position 6h Don't care VDD GND AUX All OFF All OFF Measure AUX 7h Don't care VDD GND TEMP2 All OFF All OFF Measure TEMP2 (1) (2) Bit 2 is the SER/DFR control bit for all commands except for the setup command. Use the setup command to configure the touch screen controller or access the software reset function. MODE--The mode bit sets the resolution of the A/D converter. With this bit low, the next conversion has 12 bits of resolution; with this bit high, the next conversion has eight bits of resolution. SER/DFR--The SER/DFR bit controls the reference mode: either single-ended (high) or differential (low). The differential mode is also referred to as the ratiometric conversion mode and is preferred for X-Position, Y-Position, and Pressure-Touch measurements for optimum performance. The reference is derived from the voltage at the switch drivers, which is almost the same as the voltage to the touch screen. In this case, a reference voltage is not needed because the reference voltage to the A/D converter is the same as the voltage across the touch screen. In single-ended mode, the converter reference voltage is always the difference between the VREF and GND pins (see Table 4 and Figure 24 through Figure 26, for further information). If X-Position, Y-Position, and Pressure-Touch are measured in the single-ended mode, then VDD is used as the reference. NOTE: The differential mode can only be used for X-Position, Y-Position, and Pressure-Touch measurements. All other measurements require the single-ended mode. Submit Documentation Feedback Copyright (c) 2008-2009, Texas Instruments Incorporated Product Folder Link(s): TSC2008 21 TSC2008 SBAS406B - JUNE 2008 - REVISED MARCH 2009.......................................................................................................................................................... www.ti.com PD0 and PD1--The power-down bits select the power-down mode that the TSC2008 will be in after the current command completes, as shown in Table 5. It is recommended to set PD0 = '0' in each command byte to get the lowest power consumption possible. If multiple X-, Y-, and Z-position measurements are performed sequentially (such as when averaging), PD0 = '1' leaves the touch screen drivers on at the end of each conversion cycle. Table 5. Power-Down and Internal Reference Selection PD1 PD0 PENIRQ DESCRIPTION 0 0 Enabled Power-Down Between Conversions. When each conversion is finished, the converter enters a low-power mode. At the start of the next conversion, the device instantly powers up to full power. There is no need for additional delays to ensure full operation, and the very first conversion is valid. The Y- switch is on when in power-down. 0 1 Disabled A/D converter on. PENIRQ disabled. 1 0 Enabled A/D converter off. PENIRQ enabled. 1 1 Disabled A/D converter on. PENIRQ disabled. Variable Resolution The TSC2008 provides either 8-bit or 12-bit resolution for the A/D converter. Lower resolution is often practical for measuring slow changing signals such as touch pressure. Performing the conversions at lower resolution reduces the amount of time it takes for the A/D converter to complete its conversion process, which also lowers power consumption. 8- and 12-Bit Conversion The TSC2008 provides both 12-bit or 8-bit conversion modes. The 12-bit conversion mode can be done in 24 SCLKs per cycle or 16 SCLKs per cycle timing; see Figure 30 and Figure 31 for details. The 8-bit conversion can be done in 24 SCLKs per cycle (although this mode is unlikely to be selected), 16 SCLKs per cycle, or even 8 SCLKs per cycle (when adjusted SDO timing is selected); see Figure 32 and Figure 33 for details. The 8-bit mode can be used when faster throughput is needed and the digital result is not as critical. By switching to the 8-bit conversion mode, a conversion is complete four internal conversion clock cycles earlier and also takes less time to transfer the result. The internal conversion clock runs at twice the speed (4MHz typical) than the 12-bit conversion mode. This faster conversion and transfer saves power. Conversion Clock and Conversion Time The TSC2008 contains an internal clock that drives the state machines that perform the many functions of the device. This clock is divided down to provide a clock that runs the A/D converter. The 8-bit ADC mode uses a 4MHz clock and the 12-bit ADC mode uses a 2MHz clock. The actual frequency of this internal clock is slower than the name suggests, and varies with the supply voltage. 22 Submit Documentation Feedback Copyright (c) 2008-2009, Texas Instruments Incorporated Product Folder Link(s): TSC2008 TSC2008 www.ti.com.......................................................................................................................................................... SBAS406B - JUNE 2008 - REVISED MARCH 2009 Data Format The TSC2008 output data are in Straight Binary format as shown in Figure 29. This figure shows the ideal output code for the given input voltage and does not include the effects of offset, gain, or noise. FS = Full-Scale Voltage = VREF(1) 1LSB = VREF(1)/4096 1LSB 11...111 Output Code 11...110 11...101 00...010 00...001 00...000 0V Input Voltage (2) FS - 1LSB (V) (1) Reference voltage at converter: +REF - (-REF). See Figure 24. (2) Input voltage at converter, after multiplexer: +IN - (-IN). See Figure 24. Figure 29. Ideal Input Voltages and Output Codes Submit Documentation Feedback Copyright (c) 2008-2009, Texas Instruments Incorporated Product Folder Link(s): TSC2008 23 TSC2008 SBAS406B - JUNE 2008 - REVISED MARCH 2009.......................................................................................................................................................... www.ti.com 12-BIT OPERATION TIMING A single touch result can be easily achieved using 24 SCLKs per cycle operation when the 12-bit ADC mode is used, as shown in Figure 30. However, because this operation uses slightly more bus bandwidth, a more efficient method is to overlap the control bytes with the conversion result using 16 SCLKs per cycle operation; see Figure 31. CS tACQ SCLK SDI 1 S 8 A2 A1 A0 SER/ MODE DFR 1 8 PD1 PD0 (START) Idle 8 1 Conv Acquire Idle HIGH: Disable or (Enable and Not Touched) HIGH: Disable or (Enable and Not Touched) 0 PENIRQ 1 New PENIRQ Definition LOW: Enable and Touched LOW: Enable and Touched SDO 10 11 9 8 7 6 5 4 3 2 1 (MSB) 0 Zero Filled... (LSB) (1) Drivers 1 and 2 (SER/DFR High) Off On Off (1, 2) Drivers 1 and 2 (SER/DFR Low) Off On Off NOTES: (1) For Y-Position, Driver 1 is on X+ is selected, and Driver 2 is off. For X-Position, Driver 1 is off, Y+ is selected, and Driver 2 is on. Y- will turn on when power-down mode is entered and PD0 = 0. (2) Drivers will remain on if PD0 = 1 (no power down) until selected input channel, or power-down mode is changed, or CS is high. Figure 30. Conversion Timing--12-Bit Mode, 24 SCLKs per Cycle, 8-Bit Bus Interface The control bits for conversion n + 1 can be overlapped with conversion n to allow for a conversion every 16 clock cycles, as shown in Figure 31. After submitting the control bits, the TSC2008 uses the internal clock to acquire data from seven conversions (see Figure 28). Deselecting the TSC2008 (CS = '1') during this time period allows the host to communicate with the other peripherals using the same SPI bus before reading out the ADC data. CS SCLK 1 8 8 1 1 8 n SDI S A2 A1 A0 SER/ MODE DFR S A2 A1 A0 PD1 PD0 Control Bits Idle 1 n+1 SER/ MODE DFR PD1 PD0 Control Bits Acquire Conv HIGH: Disable or (Enable and Not Touched) LOW: Enable and Touched New PENIRQ Definition 1 LOW: Enable and Touched n SDO Idle HIGH: Disable or (Enable and Not Touched) 1 PENIRQ Acquire Conv Idle 11 10 9 8 7 6 5 n+1 4 3 2 1 0 11 10 9 Figure 31. Conversion Timing--12-Bit Mode, 16 SCLKs per Cycle, 8-Bit Bus Interface, with Earliest Start of New Command 24 Submit Documentation Feedback Copyright (c) 2008-2009, Texas Instruments Incorporated Product Folder Link(s): TSC2008 TSC2008 www.ti.com.......................................................................................................................................................... SBAS406B - JUNE 2008 - REVISED MARCH 2009 8-BIT OPERATION TIMING If the 8-bit ADC mode produces an acceptable result, then 16 SCLKs per cycle operation can also be used, as shown in Figure 32. If SDO is released one-half SCLK cycle earlier (with the SDO adjusted option), the fastest transfer (eight SCLKs per cycle) is achievable; see Figure 33. CS SCLK 1 8 1 8 1 n SDI S A2 A1 A0 SER/ MODE DFR S A2 A1 A0 PD1 PD0 Control Bits 1 SER/ MODE DFR PD1 PD0 Control Bits Acquire Conv Idle 8 n+1 Acquire Conv Idle HIGH: Disable or (Enable and Not Touched) Idle HIGH: Disable or (Enable and Not Touched) New PENIRQ Definition 1 PENIRQ 1 LOW: Enable and Touched n LOW: Enable and Touched SDO 7 6 5 4 3 2 n+1 1 0 7 6 5 Figure 32. Conversion Timing--8-Bit Mode, 16 SCLKs per Cycle, 8-Bit Bus Interface, without Adjusted SDO Timing (TSC2046-Compatible) CS SCLK 1 8 1 8 n SDI S A2 A1 A0 SER/ MODE DFR Control Bits Idle PD1 PD0 S A2 A1 A0 Acquire Conv PD1 PD0 Acquire Idle Conv Idle HIGH: Disable or (Enable and Not Touched) 1 LOW: Enable and Touched SDO SER/ MODE DFR Control Bits HIGH: Disable or (Enable and Not Touched) PENIRQ 1 n+1 New PENIRQ Def 1 LOW: Enable and Touched n 7 6 5 4 3 2 1 0 n+1 7 6 5 4 Figure 33. Conversion Timing--8-Bit Mode, 8 SCLKs per Cycle, 8-Bit Bus Interface, with Adjusted SDO Timing Submit Documentation Feedback Copyright (c) 2008-2009, Texas Instruments Incorporated Product Folder Link(s): TSC2008 25 TSC2008 SBAS406B - JUNE 2008 - REVISED MARCH 2009.......................................................................................................................................................... www.ti.com POWER DISSIPATION There are two major power modes for the TSC2008: full-power (PD0 = '1') and auto power-down (PD0 = '0'). Unlike its predecessor, the TSC2046/2046E (where operation is synchronous to SCLK and therefore power depends on the SCLK frequency), the TSC2008 uses an internal clock for conversion and is asynchronous to SCLK. TSC2008 power consumption depends on the sample rate and is minimally affected by the SCLK frequency. Figure 30 shows a timing example using 12-bit resolution and 24 SCLKs per cycle. There are approximately 2.5 SCLKs of acquisition time used at the end of the 8-bit command cycle. When the preprocessing filter is on, the next six acquisition cycles are controlled by the internal conversion clock instead of relying on the external SCLK. A conversion time follows each acquisition time. Because there are six more conversions to be completed, and also because of the power used from preprocessing, the power consumption when the filter is on is higher than the power consumed without the filter at the same output rate, as shown in Figure 34. This timing sequence also applies to Figure 31 to Figure 33. Thus, using the TSC2008, power consumption can be very low, even with a low SCLK frequency. 400 400 12-Bit AUX Conversion with MAV SCLK = 16MHz VDD = 1.8V TA = +25C 300 12-Bit AUX Conversion without MAV SCLK = 16MHz VDD = 1.8V TA = +25C 350 Supply Current (mA) Supply Current (mA) 350 250 200 150 100 300 250 200 150 100 50 50 0 0 0 2 4 6 8 10 Sample Output Rate (kHz) 12 14 0 10 20 30 40 50 60 70 Sample Output Rate (kHz) 80 90 Figure 34. Sample Output Rate vs Supply Current (with and without MAV filter) Another important consideration for power dissipation is the reference mode of the converter. In the single-ended reference mode, the touch panel drivers are on only when the analog input voltage is being acquired (see Figure 30 and Table 4). The external device (for example, a resistive touch screen), therefore, is only powered during the acquisition period. In the differential reference mode, the external device must be powered throughout the acquisition and conversion periods (see Figure 30). If the conversion rate is high, using this mode could substantially increase power dissipation. THROUGHPUT RATE AND SPI BUS TRAFFIC Although the internal A/D converter has a sample rate of up to 200kSPS, the throughput presented at the bus is much lower. The rate is reduced because preprocessing manages the redundant work of filtering out noise. The throughput is further limited by the SPI bus bandwidth, which is determined by the supply voltage and what the host processor can support. The effective throughput is approximately 20kSPS at 8-bit resolution, or 10kSPS at 12-bit resolution. The preprocessing saves a large portion of the SPI bandwidth for the system to use on other devices. Each sample and conversion takes 19 CCLK cycles (12-bit), or 16 CCLK cycles (8-bit). The TSC2008 contains an internal clock that drives the state machines that perform the many functions of the device. This clock is divided down to provide a clock that runs the A/D converter. The 8-bit ADC mode uses a 4MHz clock and the 12-bit ADC mode uses a 2MHz clock. The actual frequency of this internal clock is slower than the name suggests, and varies with the supply voltage. For a typical internal 4MHz OSC clock, the frequency actually ranges from 3.66MHz to 3.82MHz. For VDD = 1.2V, the frequency reduces to 3.19MHz, which gives a 3.19MHz/16 = 199kSPS raw A/D converter sample rate. 26 Submit Documentation Feedback Copyright (c) 2008-2009, Texas Instruments Incorporated Product Folder Link(s): TSC2008 TSC2008 www.ti.com.......................................................................................................................................................... SBAS406B - JUNE 2008 - REVISED MARCH 2009 12-Bit Operation For 12-bit operation, sending the conversion result across the SPI bus takes 16 or 24 bus clocks (SCLK clock); see Figure 31 and Figure 30. There is an additional SCLK to be added to accommodate the cycle overhead (time between consecutive cycles) so that the total bus cycle time used for calculating the throughput is actually 17 or 25 bus clocks (SCLK clock), respectively. Using a TSC2046-compatible SDO output mode or an SDO-adjusted output mode does not affect the transmission time. Seven sample-and-conversions take (19 x 7) internal clocks to complete. The MAV filter loop requires 19 internal clocks. For VDD = 1.2V, the complete processed data cycle time calculations are shown in Table 6. Because the first acquisition cycle overlaps with the I/O cycle, four CCLKs must be deducted from the total CCLK cycles. The total time required is (19 x 7 + 19) - 4 = 148 CCLKs plus I/O. 8-Bit Operation For 8-bit operation, sending the conversion result across the SPI bus takes 8, 16, or 24 bus clocks (SCLK clock); see Figure 33, Figure 32, and Figure 30. There is an additional SCLK to be added to accommodate the cycle overhead (time between consecutive cycles) so that the total bus cycle time used for calculating the throughput is actually 9, 17, or 25 bus clocks (SCLK clock), respectively. Sending the conversion result takes 17 or 25 SCLKs using 8-bit resolution and a TSC2046-compatible SDO output mode. If an SDO-adjusted output mode is used with 8-bit resolution, it takes only 9 or 17 SCLKs to send the result back to host. Seven sample-and-conversions take (16 x 7) internal clocks to complete. The MAV filter loop takes 19 internal clocks. For VDD = 1.2V, the complete processed data cycle time calculations are shown in Table 6. Because the first acquisition cycle is overlapped with the I/O cycle, four CCLKs must be deducted from the total CCLK cycles. The total time required is (16 x 7 + 19) - 4 = 127 CCLKs plus I/O. Table 6. Measurement Cycle Time Calculations (1) (2) fSCLK = 100kHz (Period = 10s) 8-Bit 17 x 10s + 127 x 322.6ns = 211.0s 12-Bit 25 x 10s + 148 x 645.2ns = 345.5s fSCLK = 1MHz (Period = 1s) 8-Bit 17 x 1s + 127 x 322.6ns = 58.0s 12-Bit 25 x 1s + 148 x 645.2ns = 120.5s fSCLK = 2MHz (Period = 500ns) 8-Bit 17 x 500ns + 127 x 322.6ns = 49.5s 12-Bit 25 x 500ns + 148 x 645.2ns = 108.0s fSCLK = 2.5MHz (Period = 400ns) 8-Bit 17 x 400ns + 127 x 322.6ns = 47.8s 12-Bit 25 x 400ns + 148 x 645.2ns = 105.5s fSCLK = 4MHz (Period = 250ns) 8-Bit 17 x 250ns + 127 x 322.6ns = 45.2s 12-Bit 25 x 250ns + 148 x 645.2ns = 101.7s fSCLK = 10MHz (Period = 100ns) 8-Bit 17 x 100ns + 127 x 322.6ns = 42.7s 12-Bit 25 x 100ns + 148 x 645.2ns = 98.0s fSCLK = 16MHz (Period = 62.5ns) 8-Bit 17 x 62.5ns + 127 x 322.6ns = 42.0s 12-Bit 25 x 62.5ns + 148 x 645.2ns = 97.1s fSCLK = 25MHz (Period = 40ns) (1) (2) 8-Bit 17 x 40ns + 127 x 322.6ns = 41.7s 12-Bit 25 x 40ns + 148 x 645.2ns = 96.5s 8-bit mode cycle time is calculated based on SDO-adjusted output mode. CCLK period used for calculation is worst-case at 1.2V supply, 322.6ns. Submit Documentation Feedback Copyright (c) 2008-2009, Texas Instruments Incorporated Product Folder Link(s): TSC2008 27 TSC2008 SBAS406B - JUNE 2008 - REVISED MARCH 2009.......................................................................................................................................................... www.ti.com As an example, use VDD = 1.2V and 12-bit mode with 2MHz SPI clock (fSCLK = 2MHz). The equivalent TSC throughput is at least seven times faster than the effective throughput across the bus (9.26k x 7 = 64.82kSPS). The supply current to the TSC for this rate and configuration is 240.08A. To achieve an equivalent sample throughput of 8.2kSPS using the device without preprocessing, the TSC2008 consumes only (8.2/64.82) x 240.08A = 30.37A. Table 7. Effective and Equivalent Throughput Rates SUPPLY VOLTAGE SPI BUS SPEED (fSCLK) 100kHz 1MHz 2MHz 2.5MHz 2.7V 4MHz 10MHz 16MHz 25MHz 100kHz 1MHz 2MHz 1.8V 2.5MHz 4MHz 10MHz 16MHz 100kHz 1MHz 2MHz 1.2V 2.5MHz 4MHz 5MHz 28 RESOLUTION TSC CONVERSION CYCLE TIME (s) EFFECTIVE THROUGHPUT (kSPS) EQUIVALENT THROUGHPUT (kSPS) NO. OF SCL NO. OF CCLK fCCLK (kHz) CCLK PERIODS (ns) 8-bit 204.3 4.89 34.26 17 127 3700 270.3 12-bit 330.0 3.03 21.21 25 148 1850 540.5 8-bit 51.3 19.48 136.39 17 127 3700 270.3 12-bit 105.0 9.52 66.67 25 148 1850 540.5 8-bit 42.8 23.35 163.46 17 127 3700 270.3 12-bit 92.5 10.81 75.68 25 148 1850 540.5 8-bit 41.1 24.32 170.22 17 127 3700 270.3 12-bit 90.0 11.11 77.78 25 148 1850 540.5 8-bit 38.6 25.92 181.47 17 127 3700 270.3 12-bit 86.3 11.59 81.16 25 148 1850 540.5 8-bit 36.0 27.76 194.31 17 127 3700 270.3 12-bit 82.5 12.12 84.85 25 148 1850 540.5 8-bit 35.4 28.26 197.81 17 127 3700 270.3 12-bit 81.6 12.26 85.82 25 148 1850 540.5 8-bit 35.0 28.57 199.98 17 127 3700 270.3 12-bit 81.0 12.35 86.42 25 148 1850 540.5 8-bit 205.3 4.87 34.10 17 127 3600 277.8 12-bit 332.2 3.01 21.07 25 148 1800 555.6 8-bit 52.3 19.13 133.90 17 127 3600 277.8 12-bit 107.2 9.33 65.28 25 148 1800 555.6 8-bit 43.8 22.84 159.90 17 127 3600 277.8 12-bit 94.7 10.56 73.90 25 148 1800 555.6 8-bit 42.1 23.77 166.36 17 127 3600 277.8 12-bit 92.2 10.84 75.90 25 148 1800 555.6 8-bit 39.5 25.30 177.09 17 127 3600 277.8 12-bit 88.5 11.30 79.12 25 148 1800 555.6 8-bit 37.0 27.04 189.30 17 127 3600 277.8 12-bit 84.7 11.80 82.62 25 148 1800 555.6 8-bit 36.3 27.52 192.62 17 127 3600 277.8 12-bit 83.8 11.94 83.55 25 148 1800 555.6 8-bit 211.0 4.74 33.18 17 127 3100 322.5 12-bit 345.5 2.89 20.26 25 148 1550 645.2 8-bit 58.0 17.25 120.76 17 127 3100 322.5 12-bit 120.5 8.3 58.10 25 148 1550 645.2 8-bit 49.5 20.22 141.51 17 127 3100 322.5 12-bit 108.0 9.26 64.82 25 148 1550 645.2 8-bit 47.8 20.93 146.54 17 127 3100 322.5 12-bit 105.5 9.48 66.36 25 148 1550 645.2 8-bit 45.2 22.12 154.81 17 127 3100 322.5 12-bit 101.7 9.83 68.81 25 148 1550 645.2 8-bit 44.4 22.54 157.77 17 127 3100 322.5 12-bit 100.5 9.95 69.66 25 148 1550 645.2 Submit Documentation Feedback Copyright (c) 2008-2009, Texas Instruments Incorporated Product Folder Link(s): TSC2008 TSC2008 www.ti.com.......................................................................................................................................................... SBAS406B - JUNE 2008 - REVISED MARCH 2009 RESET The TSC2008 can be reset with three different methods: power-on reset (POR), software reset, and the proprietary SureSet function. The configuration bits (see Table 3, bit[3:1]) accessible through the setup command ('010') are reset to the respective default values listed in Table 3 after any reset occurs (POR, software reset, or SureSet). Software Reset The TSC2008 has a software reset command that can be issued by submitting the 8-bit command '1010 0001' via the SPI, as shown in Figure 35. This command resets the device to the default configuration. All the settings in the control byte are reset to default values (see Table 2 and Table 3). tSU(CSF-SCLK1R) tSU(SCLKF-CSR) CS tD(RESET) SCLK 1 SDI S 8 0 1 0 X X X 1 8 S A2 A1 A0 1 Control Bits SER/ MODE DFR PD1 PD0 Control Bits Figure 35. Software Reset Timing Table 8. Timing Requirements for Figure 35 PARAMETER tSU(CSF-SCLK1R) TEST CONDITIONS Enable lead time tSU(SCLKF-CSR) Enable lag time tD(RESET) Reset period requirement MIN MAX UNIT 1.2V VDD < 1.6V 22 ns 1.6 VDD < 3.6V 14 ns 1.2V VDD < 1.6V 50 ns 1.6 VDD < 3.6V 20 ns 200 ns SureSet The TSC2008 uses SureSet, a unique reset function. SureSet works in the same way as a hardware reset except that it does not require a dedicated reset pin on the device. SureSet works independently from the software reset and power-on reset. For example, the software reset works only after the interface (internal state machine) is fully functional, whereas SureSet works without the interface. In the unlikely event that the host becomes out-of-sync with the TSC2008, and forcing CS high does not reset the state machine, the host can submit a 24-bit sequence (0x06D926) that resets the device to a default state (the same as the power-up state), as shown in Figure 36. In order to reset the TSC2008, the device must be selected (CS low) before submitting this sequence. CS SCLK 0 SDI 0 SPI Lockup 0 0 0 1 1 0 0 24-Bit SureSet Sequence 1 1 0 Reset Normal Operation Figure 36. SureSet Timing Submit Documentation Feedback Copyright (c) 2008-2009, Texas Instruments Incorporated Product Folder Link(s): TSC2008 29 TSC2008 SBAS406B - JUNE 2008 - REVISED MARCH 2009.......................................................................................................................................................... www.ti.com Power-On Reset During TSC2008 power up, an internal power-on reset (POR) is triggered if the power-supply ramping meets the timing requirements shown in Figure 37 and listed in Table 9. The recommended and typical VDD off times are shown in Figure 38. The POR brings the TSC2008 to the default working condition. If the system is not able to meet the power ramping timing requirements, or if the system is not properly reset (even after a POR), then including the SureSet reset in the initialization routine is recommended. tVDD_ON_RAMP tVDD_OFF_RAMP 1.2V to 3.6V 0.9V tDEVICE_READY VDD 0.3V 0V tVDD_OFF Figure 37. Power-On Reset Timing Table 9. Timing Requirements for Figure 37 PARAMETER TEST CONDITIONS tVDD_OFF_RAMP MIN MAX UNIT TA = -40C to +85C 2 kV/s TA = -40C to +85C 1 s TA = -20C to +85C 0.3 s tVDD_ON_RAMP TA = -40C to +85C 12 kV/s tDEVICE_READY TA = -40C to +85C 2 ms tVDD_OFF VDD Off Time for Valid POR (s) 1.4 1.2 1.0 Recommended VDD Off Time for TA = -40C to +85C 0.8 0.6 0.4 0.2 0 Typical VDD Off Time for Various Temperatures -40 -20 0 20 40 Temperature (C) 60 80 100 Figure 38. VDD Off Time vs Temperature 30 Submit Documentation Feedback Copyright (c) 2008-2009, Texas Instruments Incorporated Product Folder Link(s): TSC2008 TSC2008 www.ti.com.......................................................................................................................................................... SBAS406B - JUNE 2008 - REVISED MARCH 2009 LAYOUT The following layout suggestions should obtain optimum performance from the TSC2008. Keep in mind that many portable applications have conflicting requirements for power, cost, size, and weight. In general, most portable devices have fairly clean power and grounds because most of the internal components are very low power. This situation would mean less bypassing for the converter power and less concern regarding grounding. However, each situation is unique and the following suggestions should be reviewed carefully. For optimum performance, care should be taken with the physical layout of the TSC2008 circuitry. The basic SAR architecture is sensitive to glitches or sudden changes on the power supply, reference, ground connections, and digital inputs that occur just before latching the output of the analog comparator. Therefore, during any single conversion for an n-bit SAR converter, there are n windows in which large external transient voltages can easily affect the conversion result. Such glitches might originate from switching power supplies, nearby digital logic, and high power devices. The degree of error in the digital output depends on the reference voltage, layout, and the exact timing of the external event. The error can change if the external event changes in time with respect to the SCLK input. With this in mind, power to the TSC2008 should be clean and well-bypassed. A 0.1F ceramic bypass capacitor should be placed as close to the device as possible. In addition, a 1F to 10F capacitor may also be needed if the impedance of the connection between VDD/REF and the power supply is high. A bypass capacitor is generally not needed on the VDD/REF pin because the internal reference is buffered by an internal op amp. If an external reference voltage originates from an op amp, make sure that it can drive any bypass capacitor that is used without oscillation. The TSC2008 architecture offers no inherent rejection of noise or voltage variation with regard to using an external reference input, which is of particular concern when the reference input is tied to the power supply. Any noise and ripple from the supply appear directly in the digital results. While high-frequency noise can be filtered out, voltage variation as a result of line frequency (50Hz or 60Hz) can be difficult to remove. Some package options have pins labeled as VOID. Avoid any active trace going under any pin marked as VOID unless it is shielded by a ground or power plane. The GND pin should be connected to a clean ground point. In many cases, this point is the analog ground. Avoid connections that are too near the grounding point of a microcontroller or digital signal processor. If needed, run a ground trace directly from the converter to the power-supply entry or battery connection point. The ideal layout includes an analog ground plane dedicated to the converter and associated analog circuitry. In the specific case of use with a resistive touch screen, care should be taken with the connection between the converter and the touch screen. Because resistive touch screens have fairly low resistance, the interconnection should be as short and robust as possible. Loose connections can be a source of error when the contact resistance changes with flexing or vibrations. As indicated previously, noise can be a major source of error in touch-screen applications (for example, applications that require a back-lit LCD panel). This electromagnetic interference (EMI) noise can be coupled through the LCD panel to the touch screen and cause flickering of the converted A/D converter data. Several things can be done to reduce this error, such as using a touch screen with a bottom-side metal layer connected to ground, which couples the majority of noise to ground. Additionally, filtering capacitors, from Y+, Y-, X+, and X- to ground, can also help. Note, however, that the use of these capacitors increases screen settling time and requires a longer time for panel voltages to stabilize. The resistor value varies depending on the touch screen sensor used. The PENIRQ pull-up resistor (RIRQ) may be adequate for most of sensors. If not used, the general-purpose analog input to the converter (AUX) should be connected to the analog ground plane. Submit Documentation Feedback Copyright (c) 2008-2009, Texas Instruments Incorporated Product Folder Link(s): TSC2008 31 TSC2008 SBAS406B - JUNE 2008 - REVISED MARCH 2009.......................................................................................................................................................... www.ti.com Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (December 2008) to Revision B ........................................................................................... Page * * * * * * 32 Deleted QFN (RGV) package availability status.................................................................................................................... 1 Changed product name in Ordering Information table from TSC2008I to TSC2008............................................................. 2 Added "I" to QFN package ordering numbers in Ordering Information table ........................................................................ 2 Changed Power On/Off Slope Requirements parameter names .......................................................................................... 4 Changed VDD off time test condition from -21C to +85C .................................................................................................. 4 Changed and moved Power-On Reset section ................................................................................................................... 30 Submit Documentation Feedback Copyright (c) 2008-2009, Texas Instruments Incorporated Product Folder Link(s): TSC2008 PACKAGE OPTION ADDENDUM www.ti.com 15-Apr-2011 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) TSC2008IRGVR ACTIVE VQFN RGV 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Add to cart TSC2008IRGVT ACTIVE VQFN RGV 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Add to cart TSC2008IYZGR ACTIVE DSBGA YZG 12 3000 Green (RoHS & no Sb/Br) Call TI Level-1-260C-UNLIM Add to cart TSC2008IYZGT ACTIVE DSBGA YZG 12 250 Green (RoHS & no Sb/Br) Call TI Level-1-260C-UNLIM Add to cart (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device TSC2008IRGVR Package Package Pins Type Drawing VQFN RGV 16 TSC2008IRGVT VQFN RGV TSC2008IYZGR DSBGA YZG TSC2008IYZGT DSBGA YZG SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 2500 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 16 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 12 3000 180.0 8.4 1.75 2.25 0.81 4.0 8.0 Q1 12 250 180.0 8.4 1.75 2.25 0.81 4.0 8.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TSC2008IRGVR VQFN RGV 16 2500 367.0 367.0 35.0 TSC2008IRGVT VQFN RGV 16 250 210.0 185.0 35.0 TSC2008IYZGR DSBGA YZG 12 3000 210.0 185.0 35.0 TSC2008IYZGT DSBGA YZG 12 250 210.0 185.0 35.0 Pack Materials-Page 2 D: Max = 2.1 mm, Min = 2.04 mm E: Max = 1.6 mm, Min = 1.539 mm IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. 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