TEA19161CT/1Y - NXP SEMICONDUCTORS

TEA19162T/3

PFC controller

Rev. 3 — 7 May 2018 Product data sheet

1 General description

The TEA19162T and TEA19161T are combined controller (combo) ICs for resonant

topologies including PFC. They provide high efficiency at all power levels. Together

with the TEA1995T dual LLC resonant SR controller, a cost-effective resonant power

supply can be built. This power supply meets the efficiency regulations of Energy Star,

the Department of Energy (DoE), the Eco-design Directive of the European Union, the

European Code of Conduct, and other guidelines.

The TEA19162T is a Power Factor Correction (PFC) controller. The IC communicates

with the TEA19161T on start-up sequence and protections. It also enables a fast latch

reset mechanism. To maximize the overall system efficiency, the TEA19161T allows

setting the TEA19161T PFC to burst mode at a low output power level.

Using the TEA19161T and TEA19162T combo together with the TEA1995T secondary

synchronous rectifier controller, a highly efficient and reliable power supply can be

designed with a minimum of external components. The target output power is between

90 W and 500 W.

The system provides a very low no-load input power (< 75 mW; total system including the

TEA19161T/TEA19162T combo and theTEA1995T) and high efficiency from minimum to

maximum load. So, no additional low-power supply is required.

NXP Semiconductors TEA19162T/3

PFC controller

Product data sheet Rev. 3 — 7 May 2018

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2 Features and benefits

2.1 Distinctive features

•Complete functionality as TEA19161T/TEA19162T combo

•Integrated X-capacitor discharge without additional external components

•Universal mains supply operation (70 V (AC) to 276 V (AC))

•Integrated soft start and soft stop

•Accurate boost voltage regulation

2.2 Green features

•Valley/zero voltage switching for minimum switching losses

•Frequency limitation to reduce switching losses

•Reduced supply current (200 µA) when in burst mode

2.3 Protection features

•Safe restart mode for system fault conditions

•Continuous mode protection with demagnetization detection

•Accurate OverVoltage Protection (OVP)

•Open-Loop Protection (OLP)

•Short-Circuit Protection (SCP)

•Internal and external IC OverTemperature Protection (OTP)

•Low and adjustable OverCurrent Protection (OCP) trip level

•Adjustable brownin/brownout protection

•Supply UnderVoltage Protection (UVP)

3 Applications

•Desktop and all-in-one PCs

•LCD television

•Notebook adapter

•Printers

•Gaming console power supplies

NXP Semiconductors TEA19162T/3

PFC controller

Product data sheet Rev. 3 — 7 May 2018

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4 Ordering information

Table 1. Ordering information

PackageType number

Name Description Version

TEA19162T/3 SO8 plastic small outline package; 8 leads; body width 3.9 mm SOT96-1

5 Marking

Table 2. Marking codes

Type number Marking code

TEA19162T/3 EA19162

NXP Semiconductors TEA19162T/3

PFC controller

Product data sheet Rev. 3 — 7 May 2018

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6 Block diagram

X-CAP

DISCHARGE

CONTROL

reset

+9.45 V

+0.7 V

DEMAGNETIZATION AND VALLEY DETECTION

SUPPLY

TIMER 44.5 µs

TIMER 50 ms UVPMains

StartMains

StartXCapDis

MAINS

CURRENT

TRACKING

DELAY

100 µs

current

comparator

TIMER

118 ms

TIMER

4 ms

GATE

SENSING

SENSE

RESISTOR

SENSING

DRIVER

GatePfc

TIMER 3.8 µs

VALLEY

DETECTION

ZERO

CURRENT

SIGNAL INTERNAL

SUPPLIES

Rd Q

MAINS SENSING

CONTROL

OVP

control

TEMPERATURE

SENSING

PFC

OSCILLATOR

GatePfc

demag

ExtOTP

NTCMeasure

Ext-OTP

MAINS

SENSING

-90 mV

+2 V

+0.25 V

SNSAUX

SUPIC

SNSMAINS

aaa-017283

200 µA

210 µA

Gm amplifier

5 µA

+2.63 V OVBoost

SoftStop

soft stop

+0.4 V OLP

+2 V

SNSBOOST

100 µA

ResetFastLatch

BOOST

VOLTAGE SENSING

ON-TIME

CONTROL

EndFastLatch

+3.23 V

+2.8 V

ProtActive

SoftStop

NTC

measure

26 µA

+13 V StartSUPIC StartMains

ProtActive SNSCUR

GATEPFC

OCP +0.5 V

C Qn

D Q

RResetFastLatch

EnablePfc

ProtActive

IntOTP

UVPSUPIC

Start-SUPIC

OVP

EndFastLatch

ProtActive

StartMains

EnablePfc

TOnPassed

OCP

UVPmains

Int/ExtOTP

OLP

+9 V UVPSUPIC

+5 V Ana

+5 V Dig

+11 V

PROTECTIONS

CURRENT SENSING

GATE CONTROL

STARTUP

CONTROL

OTP

X-CAP

DISCHARGE

mains

compensation

+3.5 V

GatePfc

TOnPassed

OVP

OVBoost

+2.5 V

enable

PFC

+3.8 V

+3.5 V

+1.23 V

PFCCOMP GND

32 µA

+10.5 mV

+50 mV

SNSCUR

Figure 1. Block diagram

NXP Semiconductors TEA19162T/3

PFC controller

Product data sheet Rev. 3 — 7 May 2018

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7 Pinning information

7.1 Pinning

GATEPFC SNSAUX

GND PFCCOMP

SNSCUR SNSMAINS

SUPIC SNSBOOST

aaa-017287

Figure 2. Pin configuration

7.2 Pin description

Table 3. Pin description

Symbol Pin Description

GATEPFC 1 gate driver output for PFC

GND 2 ground

SNSCUR 3 programmable current sense input for PFC

SUPIC 4 supply voltage

SNSBOOST 5 sense input for PFC output voltage

SNSMAINS 6 sense input for mains voltage

PFCCOMP 7 frequency compensation pin for PFC

SNSAUX 8 input from auxiliary winding for demagnetization timing and valley

detection for PFC

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PFC controller

Product data sheet Rev. 3 — 7 May 2018

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8 Functional description

8.1 General control

The TEA19162T is a controller for a power factor correction circuit. Figure 3 shows a

typical configuration.

aaa-018105

LLC

resonant converter

PFC

SNSAUX GATEPFC

SNSMAINS SNSCUR

SUPIC

Vmains-L

Vmains-N

Rmains

GND SNSBOOST

Vboost

Cboost

PFCCOMP

Raux

RSNSCUR

Rsense

RSNSBOOST

CSUPIC

Figure 3. TEA19162T typical configuration

8.2 Supply voltage and start-up

When using the TEA19162T (PFC) together with the TEA19161T (LLC), connect the

SUPIC pin of the TEA19162T to the SUPIC pin of the TEA19161T. The LLC controller

then supplies the PFC either via the high-voltage supply pin of the TEA19161T (SUPHV)

or via the primary auxiliary winding.

To enable the PFC, the SUPIC voltage must exceed the Vstart(SUPIC) level (13 V typical).

Although the Vstart(SUPIC) level of the LLC is higher than the Vstart(SUPIC) level of the PFC,

the system ensures that both converters (PFC and LLC) start up at the same time.

Therefore, the LLC initially pulls down the SNSBOOST pin, disabling the PFC until the

SUPIC voltage reaches the Vstart(SUPIC) level of the LLC.

When both conditions are met and the SNSMAINS is above the brownin level, the PFC

starts up via an internal soft start (see Figure 4).

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PFC controller

Product data sheet Rev. 3 — 7 May 2018

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aaa-020197

td(start)

VSNSBOOST

VSUPIC LLCPFC

Vboost

Vstart(SNSBOOST) 2.3 V

Vreg(SNSBOOST) 2.5 V

Vpu(rst)SNSBOOST 2.0 V

Vscp(stop) 0.4 V

Vuvp(SUPIC) 9 V

Vstart(SUPIC) 13.0 V

Vbrownin

mains voltage

Vrst(SUPIC) 3.5 V

Vuvp(SUPIC) 13.2 V

Vstart(hys)SUPIC 0.7 V

Vstart(SUPIC) 19.2 V

VGATEPFC

UVP SCP ONwait

PFC mode of operation

Figure 4. Start-up of the PFC and LLC

The exact start-up sequence of the PFC depends on the availability of start-up conditions

(brownin level, Vstart(SUPIC) of the PFC, and Ien(PFC)).

Before t1, the SUPIC voltage is below the UVP level of the PFC and LLC. When the LLC

reaches a minimum supply voltage level (t1), the LLC pulls down the SNSBOOST pin to

disable the PFC.

At t2, the SUPIC voltage reaches the start level of the PFC converter. However, as

the LLC pulls low the SNSBOOST to below the PFC short protection level, the PFC is

still off. When the mains voltage exceeds the brownin level, the PFC resets its latched

protection by pulling VSNSBOOST to the Vpu(rst)SNSBOOST level (t3). However, the LLC

returns it to the protection mode. When at t4 the SUPIC voltage reaches the start level

of the LLC, the SNSBOOST is released. The SNSBOOST voltage increases because

of the resistive divider which is connected to the PFC bus voltage. To ensure that this

voltage is representative of the Vboost voltage before the system actually starts to switch,

an additional delay (td(start); 3.62 ms) is active before the PFC starts switching (t5).

Another important condition for the PFC start is a precharge of the compensation circuitry

connected to the PFCCOMP pin. This condition is met when the current out of the

PFCCOMP pin < |Ien(PFCCOMP)|.

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PFC controller

Product data sheet Rev. 3 — 7 May 2018

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When at t6 the SNSBOOST voltage reaches the start level of the LLC (Vstart(SNSBOOST)),

the LLC converter starts to switch.

When VSUPIC < Vuvp(SUPIC), the PFC controller stops switching immediately.

8.3 Protections

Table 4 gives an overview of the available protections.

Table 4. Protections overview

Protection Description Action LLC[1]

UVP-SUPIC undervoltage protection SUPIC PFC = off; restart when

VSUPIC > Vstart(SUPIC); SNSBOOST

pulled low, disabling the LLC.

off Section 8.2

OTP-internal internal overtemperature protection latched; SNSBOOST pulled low,

disabling the LLC.

off Section 8.3.1

OTP-external external overtemperature protection latched; SNSBOOST pulled low,

disabling the LLC.

off Section 8.3.2

brownout-mains undervoltage protection mains PFC = off; restart when

ISNSMAINS > Ibi

[2] -Section 8.3.2

SoftStop-OVP-

SNSBOOST

overvoltage protection boost voltage

followed by a soft stop

PFC = off via soft stop; restart when

VSNSBOOST < Vovp(start)

-Section 8.3.3

OVP-SNSBOOST overvoltage protection boost voltage PFC = off; restart when

VSNSBOOST < Vovp(SNSBOOST)

-Section 8.3.4

SCP-SNSBOOST short-circuit protection PFC = off; restart when

VSNSBOOST > Vscp(start)

-Section 8.3.5

OLP-PFC open-loop protection PFC = off; restart when

VSNSBOOST > Vscp(start)

-Section 8.3.5

OCP overcurrent protection PFC MOSFET switched off,

continue operation

-Section 8.3.6

[1] Some protections also disable the LLC (see Section 8.5.1).

[2] At start-up, the PFC disables the LLC converter until the mains voltage exceeds the brownin level.

8.3.1 Internal OverTemperature Protection (OTP)

An accurate internal temperature protection is provided in the circuit. When the junction

temperature exceeds the thermal shutdown temperature (Tpl(IC)), the IC stops switching.

The internal overtemperature protection is a latched protection. It also disables the LLC

converter by pulling down the SNSBOOST pin.

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PFC controller

Product data sheet Rev. 3 — 7 May 2018

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8.3.2 Brownin/brownout and external overtemperature protection

On the TEA19162T, the mains measurement and external temperature are combined at

the SNSMAINS pin (see Figure 5).

aaa-018107

t1 t4t2

t3 t5

mains - L

mains - N

VSNSMAINS 2 V

250 mV

ISNSMAINS

-200 µA

Figure 5. Mains and external OTP measurement

At t1, the voltage at the SNSMAINS pin is internally regulated to Vregd(SNSMAINS)

(250 mV). The current into the SNSMAINS pin is a measure of the system input mains

voltage. The TEA19162T continuously measures the SNSMAINS current and waits until

it detects a peak in the measured current (t2). This peak current value is internally stored

and used as an input for the brownout/brownin detection and the mains compensation.

When, at t3, the current into the SNSMAINS pin is well below the brownin level

(< Ien(NTC)), the controller starts to measure the value of the external NTC. The external

NTC is measured by sourcing a current (Io(SNSMAINS)) out of the SNSMAINS pin. When,

after a maximum measuring time of tdet(NTC)max (1 ms), the voltage remains below

Vdet(SNSMAINS) during four consecutive NTC measurements, the OTP protection is

triggered (t5).

To prevent the PFC from operating at very low mains input voltages, the PFC stops

switching when the measured peak current drops to below Ibo. When the measured

current exceeds Ibi, the PFC restarts with a soft start.

8.3.3 Soft stop overvoltage protection (SNSBOOST pin)

When the SNSBOOST voltage is between the Vdet(L)SNSBOOST and Vdet(H)SNSBOOST, the

TEA19162T stops switching via a soft stop. The TEA19161T uses this function to force

the TEA19162T to operate in burst mode with a specific duty cycle (see Section 8.5.2).

Audible noise is avoided because at the end of a switching period, the PFC stops via a

soft stop. After an OVP event, the system always starts via a soft start.

NXP Semiconductors TEA19162T/3

PFC controller

Product data sheet Rev. 3 — 7 May 2018

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8.3.4 Overvoltage protection (SNSBOOST pin)

To prevent output overvoltage during load steps and mains transients, an overvoltage

protection circuit is built in.

When the voltage on the SNSBOOST pin exceeds the Vovp(stop) level and is outside the

Vdet(L)SNSBOOST and Vdet(H)SNSBOOST window for a minimum period of td(ovp) (100 µs),

switching of the power factor correction circuit is inhibited. When the SNSBOOST pin

voltage drops to below the Vovp(start) (Vovp(stop) − Vhys(ovp)) level again, the switching of the

PFC recommences. The IC always restarts with a soft start (see Section 8.4.1).

8.3.5 PFC open-loop protection (SNSBOOST pin)

The PFC does not start switching until the voltage on the SNSBOOST pin exceeds

Vscp(start). This function acts as short circuit protection for the boost voltage (SCP-

SNSBOOST; see Table 4).

8.3.6 Overcurrent protection (SNSCUR pin)

Sensing the voltage across an external sense resistor, Rsense, on the source of the

external MOSFET, limits the maximum peak current cycle-by-cycle. The voltage is

measured via the SNSCUR pin.

8.3.7 Fast latch reset

The restart of the system after a protection is triggered depends on the type of protection.

In a safe restart protection (only applicable for the LLC), the system typically restarts after

the restart delay time (1 s).

It is different for latched protections. Typically, in a latched protection, the SUPIC must

reach the undervoltage protection level to release the protection mode and to restart the

system. The release/restart can only be achieved by disconnecting the mains.

In the protection mode, the TEA19161T regulates the voltage of the SUPIC pin to its

start level. The PFC output capacitor supplies the SUPIC pin via the SUPHV pin of the

TEA19161T. So it takes a long time before the voltage of the SUPIC pin drops below its

undervoltage level after the mains is disconnected. To prevent this delay, a special fast

latch reset function is implemented in the TEA19162T, which also releases the protection

mode when the mains is reconnected.

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PFC controller

Product data sheet Rev. 3 — 7 May 2018

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aaa-018109

td(start)

td(main)bo

LLC

Vstart(SUPIC) = 19.2 V

Vstart(hys)SUPIC = 0.7 V

VSUPIC

VSNSBOOST

PFC

off wait

protection on

UVPSNSBOOST

PFC

LLC

Vout

mains

brownout on

brownin

brownout

Vreg(SNSBOOST) = 2.5 V

Vscp(stop) = 0.4 V

Vpu(rst)SNSBOOST = 2.0 V

Vstart(SNSBOOST) = 2.3 V

Vuvp(SNSBOOST) = 1.6 V

Figure 6. Fast latch reset

Before t1, the LLC (and/or PFC) is in a (latched) protection and pulls down the

SNSBOOST pin, which also disables the PFC.

When the mains voltage drops to below the brownout level (Ibo) and the time td(det)bo

(50 ms) expires (t1), the PFC enters the brownout protection mode. When, in the

brownout protection mode, the mains voltage increases again and exceeds the brownin

level (Ibi; t2), the PFC pulls up the SNSBOOST voltage to the Vpu(rst)SNSBOOST level

(see Figure 6). Because the Vpu(rst)SNSBOOST level of the PFC exceeds the Vuvp(SNSBOOST)

level of the LLC, the LLC converter resets the protection mode. However, switching is still

inhibited as the SNSBOOST voltage remains below the start level (Vstart(SNSBOOST)) of the

LLC. The SUPIC voltage is still regulated to the Vstart(SUPIC) level of the LLC converter.

To ensure that the voltage at the SNSBOOST pin accurately reflects the output voltage

of the PFC, the PFC converter starts after a delay time (td(start)) (t3). The start of the PFC

converter is followed by a start-up of the LLC converter (t4).

8.4 Power factor correction regulation

The power factor correction circuit operates in quasi-resonant or discontinuous

conduction mode with valley switching. The next primary stroke is only started when the

previous secondary stroke has ended and the voltage across the PFC MOSFET has

reached a minimum value. To detect transformer demagnetization and the minimum

voltage across the external PFC MOSFET switch, the voltage on the SNSAUX pin is

used.

NXP Semiconductors TEA19162T/3

PFC controller

Product data sheet Rev. 3 — 7 May 2018

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8.4.1 Soft start (SNSCUR pin)

To prevent audible transformer noise at start-up or during hiccup, the soft start function

slowly increases the transformer peak current (see Figure 7).

SNSBOOST

Vstart(soft)init

GATEPFC

Vreg(oc)

SNSCUR

aaa-018110

tstart(soft)

Figure 7. PFC start-up

At t1, all conditions to start up the PFC are fulfilled. The maximum voltage on the

SNSCUR pin is limited to Vstart(soft)init (125 mV). When the PFC starts switching, the

maximum SNSCUR voltage is increased to Vreg(oc) within a time period of tstart(soft)

(3.62 ms) or until the ton regulation limits the on-time of the PFC external MOSFET.

8.4.2 ton control

The power factor correction circuit is operated in ton control. The resulting mains

harmonic reduction of a typical application is well within the class-D requirements.

The following circuits determine the on-time of the external PFC MOSFET:

•The error amplifier and the loop compensation which define the voltage on the

PFCCOMP pin. At Vtonzero(PFCCOMP) (3.5 V), the on-time is reduced to zero. At

Vtonmax(PFCCOMP) (1.23 V), the on-time is at a maximum.

•Mains compensation which uses the current through the SNSMAINS pin to represent

the mains input voltage level.

8.4.3 PFC error amplifier (PFCCOMP and SNSBOOST pins)

The boost voltage is divided using a high-ohmic resistive divider and is supplied to the

SNSBOOST pin. The transconductance error amplifier, which compares the SNSBOOST

voltage with an accurate trimmed reference voltage (Vreg(SNSBOOST)) is connected to this

pin. The external loop compensation network on the PFCCOMP pin filters the output

current. In a typical application, a resistor and two capacitors set the regulation loop

bandwidth.

NXP Semiconductors TEA19162T/3

PFC controller

Product data sheet Rev. 3 — 7 May 2018

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The transconductance of the error amplifier is not constant. To avoid triggering the OVP

during start-up and during a converter transient response, the transconductance is

increased to a level of gm(high) starting at Vgm(high)start (see Figure 8).

aaa-020217

gm(high)

40 mV

Vgm(high)start

Vovp(stop)

2.0

lPFCCOMP

(µA)

VSNSBOOST (V)

lsink(PFCCOMP)

2.5 2.6

2.63

Figure 8. Transconductance of the PFC error amplifier

8.4.4 Valley switching and demagnetization (SNSAUX pin)

To ensure that the TEA19162T operates in discontinuous or quasi-resonant mode, the

PFC MOSFET is switched on after the transformer is demagnetized. To reduce switching

losses and ElectroMagnetic Interference (EMI), the next stroke is started when the PFC

MOSFET drain-source voltage is at its minimum (valley switching). The demagnetization

and valley detection are measured via the SNSAUX pin.

If no demagnetization signal is detected on the SNSAUX pin, the controller generates a

demagnetization signal (tto(demag); 44.5 µs typical) after the external MOSFET is switched

off.

If no valley signal is detected on the PFCAUX pin, the controller generates a valley signal

(tto(vrec); 3.8 µs typical) after demagnetization is detected.

To protect the internal circuitry, for example during lightning events, connect a 5 kΩ

series resistor (Raux; see Figure 13) to the SNSAUX pin. Also connect a 1 kΩ (typical)

external sense resistor (RSNSCUR; see Figure 13) to the SNSCUR pin. To prevent

incorrect switching due to external disturbance, place the resistors close to the IC.

8.4.5 Frequency limitation

To optimize the transformer and minimize switching losses, the switching frequency

is limited to fsw(PFC)max. If the frequency for quasi-resonant operation exceeds the

fsw(PFC)max limit, the system enters Discontinuous Conduction Mode (DCM). When the

system is in DCM, the PFC MOSFET switches on at a minimum voltage across the

switch (valley switching).

To ensure correct control of the PFC MOSFET under all circumstances, the minimum off-

time is limited at toff(PFC)min.

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PFC controller

Product data sheet Rev. 3 — 7 May 2018

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8.4.6 Mains voltage compensation (SNSMAINS pin)

The equation for the transfer function of a power factor corrector contains the square

of the mains input voltage. In a typical application, the result is a low bandwidth for low

mains input voltages. At high mains input voltages, the Mains Harmonic Reduction

(MHR) requirements may be hard to meet.

To compensate for the mains input voltage influence, the TEA19162T contains

a correction circuit. The input voltage is measured via the SNSMAINS pin

(see Section 8.3.2) and the information is fed to an internal mains compensation

circuit (see Figure 1). With this compensation, it is possible to keep the regulation loop

bandwidth constant over the full mains input range. The result is that a mains voltage

independent transient response on load steps is yielded, while still complying with class-

D MHR requirements.

In a typical application, an external circuitry at the PFCCOMP pin (see Section 8.4.3) sets

the bandwidth of the regulation loop.

8.4.7 Active X-capacitor discharge

The TEA19162T provides an active X-capacitor discharge after the mains voltage is

disconnected. When the mains input voltage (and so also the measured current into the

SNSMAINS pin) increases (see Figure 9, t2 - t1), the system assumes the presence of a

mains voltage. When the mains voltage does not increase for a minimum period of td(dch),

the active X-capacitor discharge is activated (t3).

When the active X-capacitor discharge function is activated, the X-capacitor is

discharged via the external PFC MOSFET (see Figure 10). To avoid any increase of the

PFC output voltage, the external PFC MOSFET is slowly turned on until a small current

is detected via the SNSCUR pin (see Figure 9, t4). A slow increase of the GATEPFC

voltage is achieved via a current source (Ich(GATEPFC)) that slowly charges the external

gate-source capacitance of the external MOSFET.

When the voltage at the SNSCUR exceeds Vch(stop)SNSCUR level (10.5 mV), the voltage

at the GATEPFC pin slowly decreases by activating a current sink (Idch(GATEPFC)). As a

result, the gate-source capacitance of the external MOSFET is discharged. When the

voltage on the GATEPFC pin drops to below Vdch(stop)GATEPFC level (0.7 V), the current

sink is switched off. The charge/discharge cycle is repeated after the period toff(dch)

(t5). As for a typical power MOSFET the duration of charge/discharge pulses on the

GATEPFC pin is shorter than 2 ms, Tp (4 ms typical) defines the pulse repetition time.

When the voltage on the GATEPFC pin exceeds Vdch(GATEPFC) while the voltage on

the SNSCUR pin is still below Vch(stop)SNSCUR, the system assumes a full discharge

of the X-capacitor. It starts to ramp down the GATEPFC voltage. Unless the mains

is reconnected, the next active X-capacitor discharge cycle is started after td(dch).

Reconnecting the mains is detected via a positive dI/dt at the SNSMAINS pin.

While the GATEPFC pin discharges the X-capacitor, the mains can be reconnected.

In that case, the current through the external MOSFET increases rapidly. If the voltage

on the SNSCUR pin exceeds Vdch(SNSCUR), the internal driver stage rapidly turns off the

GATEPFC pin. When the mains is disconnected again (measured via the SNSMAINS

pin), the next active X-capacitor discharge cycle starts, followed by a delay of td(dch).

NXP Semiconductors TEA19162T/3

PFC controller

Product data sheet Rev. 3 — 7 May 2018

15 / 30

aaa-018129t4t1 t2

td(dch)

toff(dch)

Vdch(stop)GATEPFC

Vch(stop)SNSCUR

mains - L

mains - N

Ich(GATEPFC)

IGATEPFC

Idch(GATEPFC)

VGATEPFC

VSNSCUR

Figure 9. TEA19162T active X-capacitor discharge

NXP Semiconductors TEA19162T/3

PFC controller

Product data sheet Rev. 3 — 7 May 2018

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aaa-020234

GATEPFC

charge

Cboost

Rsense

Vdis(dch)GATEPFC

Ich(GATEPFC)

Idch(GATEPFC)

Vdch(stop)GATEPFC

X-CAPACITOR

DISCHARGE

CONTROL

enable tristate

GateDig

UVP SUPIC

mains-L

mains-N

driver

TIMER

td(dch)

TIMER

toff(dch)

reset

Vch(stop)SNSCUR

Vdis(dch)SNSCUR

SNSCUR

Figure 10. TEA19162T active X-capacitor discharge block diagram

8.5 PFC-LLC communication protocol

The TEA19162T (PFC controller) is designed to cooperate with the TEA19161T (LLC

controller) in one system. Both controllers can be seen as a combo IC, split up into

two packages. All required functionality between the TEA19162T and TEA19161T is

arranged via the combined SUPIC and SNSBOOST pins.

Both controllers are supplied via the SUPIC pin (see Section 8.2). The SNSBOOST pin

is used to communicate about the protection states of both controllers. The TEA19161T

forces the TEA19162T to enter burst mode also using the SNSBOOST pin.

8.5.1 Protections

When a protection is triggered in the PFC or the LLC, it can also disable the other

converter. For example, if an OVP is detected at the LLC, both converters are stopped.

Also, at initial start-up, the PFC disables the LLC converter until the brownin level of the

mains voltage is detected.

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PFC controller

Product data sheet Rev. 3 — 7 May 2018

17 / 30

The SNSBOOST pin is used for the communication about such protection states. By

pulling down the SNSBOOST pin below the Vuvp(SNSBOOST) level of the LLC converter,

the PFC can disable the LLC converter. Similarly, by pulling down the SNSBOOST pin

below the short protection level Vscp(stop) of the PFC converter, the LLC can disable the

PFC.

Table 4 in Section 8.3 gives an overview of all protections in the PFC converter. The PFC

protections that also disable the LLC are listed in the LLC-column.

When the mains voltage initially drops to below the brownout level and then increases

to above the brownin level, all protections of the PFC and the LLC are reset. A reset

of all protections is also communicated via the SNSBOOST pin by pulling it up to the

Vpu(rst)SNSBOOST level (see Section 8.3.7).

The IC starts and remains in the protection mode until the mains brownin level is

reached. The IC current consumption is then at power-saving level.

8.5.2 PFC burst mode

Based on the output power level of the LLC converter, the LLC determines when the

PFC enters burst mode. During the burst mode, the LLC converter disables the PFC

by increasing the SNSBOOST voltage to between Vdet(L)SNSBOOST and Vdet(H)SNSBOOST

(see Figure 11). It ensures a soft start and a soft stop at the start and the end of a

switching period, respectively. This increase in the voltage on the SNSBOOST pin is

achieved by an additional current out of the LLC converter towards the SNSBOOST pin.

The additional current creates a positive voltage shift because of the external resistive

network at the SNSBOOST pin.

NXP Semiconductors TEA19162T/3

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aaa-020102

GM AMPLIFIER

soft stop

PFC LLC

SNSBOOST

PFC burst mode

VSNSBOOST > 2.37 V

100 kΩ

100 µs

DELAY

3.23 V

2.8 V

3.8 V

2.63 V

OVP

PFCCOMP

Ioff(burst) = 6.4 µA

Ich(stop)soft = 32 µA

Voff(burst)

RESET

MAX.

VALUE

a. Block diagram

Voff(burst) = -75 mV

Von(burst)max = 2.37 V

Ioff(burst)

aaa-020103

OFF OFF ONON

Vdet(H)SNSBOOST = 3.23 V

PFC LLC

Vdet(L)SNSBOOST = 2.8 V

Vovp(stop) = 2.63 V

Vreg(SNSBOOST) = 2.5 V

Vclamp(PFCCOMP) = 3.80 V

Vtonzero(PFCCOMP) = 3.5 V

VSNSBOOST t4

VPFCCOMP

VGATEPFC

b. Timing diagram

Figure 11. PFC burst mode

At t1, the current out of the LLC SNSBOOST pin (Ioff(burst)) is activated and the voltage

on the SNSBOOST pin increases. When a 100 kΩ external resistor RSNSBOOST between

the SNSBOOST pin and GND pin is used (see Figure 11), the SNSBOOST voltage

increase is about 640 mV (= Ioff(burst)SNSBOOST * RSNSBOOST). As due to this increase

the SNSBOOST voltage is between Vdet(L)SNSBOOST and Vdet(H)SNSBOOST levels (t2), the

soft stop of the PFC converter is started. In the soft stop state, the current out of the

PFCCOMP pin (Ich(stop)soft) is activated. At the end of the soft stop, the PFC enters the

energy safe state and stops switching (t3). The voltage at the PFCCOMP pin is clamped

at Vtonzero(PFCCOMP) (3.5 V). It remains at this level during the energy safe state. As the

LLC converter operates continuously, even when the PFC is stopped, the PFC output

capacitor discharges.

When the PFC boost capacitor is discharged so much that the voltage on the

SNSBOOST pin drops by 75 mV (ΔVoff(burst); t4), the internal current source in the LLC

converter is switched off. Because of the negative voltage drop at the SNSBOOST pin,

the SNSBOOST voltage drops below the regulation level (Vreg(SNSBOOST); t5). The PFC

starts switching again (t6). When VSNSBOOST exceeds the LLC Von(burst)max level (2.37 V)

again, the internal current is reactivated and the PFC stops switching again.

The TEA19162T current consumption in the burst mode depends on whether the IC

is switching or not. During burst mode on-time and burst mode off-time, the current

consumption is at operating level and power-saving level, respectively.

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8.5.3 Soft stop

A soft stop always precedes the PFC burst mode. It reduces audible noise of the

converter.

The internal current source activated in the LLC converter (see Figure 11) pulls up the

voltage at the PFC SNSBOOST pin. When the SNSBOOST pin voltage is between

Vdet(L)SNSBOOST (2.8 V) and Vdet(H)SNSBOOST (3.23 V), the PFC soft stop begins. Then,

a PFC internal current source Ich(stop)soft is activated and the transconductance error

amplifier in the PFC control loop is switched off (see Figure 11).

The activated current source provides a current of 32 µA (Ich(stop)soft) out of the

PFCCOMP pin. This current slowly increases the voltage of the PFCCOMP pin, gradually

reducing the converter switching on-time. When the zero on-time is reached, the soft stop

ends. The zero on-time corresponds with the PFCCOMP pin voltage of Vtonzero(PFCCOMP)

(3.5 V).

The detection of the overvoltage on the SNSBOOST pin at the normal OVP level

(Vovp(stop)) is delayed for the time td(ovp) (100 µs). This additional delay is required to

verify if the system should stop immediately because of an OVP or via a soft stop when

activating the burst mode.

8.6 Driver (pin GATEPFC)

The driver circuit to the gate of the power MOSFET has a current sourcing capability of

600 mA and a current sink capability of 1.4 A typical. These capabilities allow a fast turn-

on and turn-off of the power MOSFET, ensuring efficient operation.

When the SUPIC voltage is below its start level, the internal keep-off circuitry of the PFC

driver pulls down the GATEPFC pin. The pulling down of the GATEPFC pin prevents that

an external power MOSFET is activated when the IC power supply is absent or when the

VSUPIC < Vstart(SUPIC). The keep-off circuitry (see Figure 12) is supplied via the GATEPFC

pin. So, if the actual IC supply is absent or too low (VSUPIC < Vstart(SUPIC)), the circuit

works correctly.

driver GATEPFC

UVP-SUPIC

aaa-021332

Figure 12. Keep-off circuitry at the GATEPFC pin

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Product data sheet Rev. 3 — 7 May 2018

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9 Limiting values

Table 5. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

Voltages

VSUPIC voltage on pin SUPIC −0.4 +38 V

VSNSMAINS voltage on pin

SNSMAINS

current limited −0.4 +12 V

VPFCCOMP voltage on pin

PFCCOMP

current limited −0.4 +12 V

VSNSAUX voltage on pin

SNSAUX

current limited −25 +25 V

VSNSCUR voltage on pin

SNSCUR

current limited −0.4 +12 V

VSNSBOOST voltage on pin

SNSBOOST

current limited −0.4 +12 V

VGATEPFC voltage on pin

GATEPFC

current limited −0.4 +12 V

General

Ptot total power dissipation Tamb < 75 °C - 0.45 W

Tstg storage temperature −55 +150 °C

Tjjunction temperature −40 +150 °C

ESD

human body model [1] −2000 +2000 VVESD electrostatic discharge

voltage charged device

model

[2] −500 +500 V

[1] Equivalent to discharging a 100 pF capacitor through a 1.5 kΩ series resistor.

[2] Equivalent to discharging a 200 pF capacitor through a 0.75 µH coil and a 10 Ω resistor.

10 Thermal characteristics

Table 6. Thermal characteristics

Symbol Parameter Conditions Typ Unit

Rth(j-a) thermal resistance from

junction to ambient

in free air; JEDEC test board 150 K/W

Rth(j-c) thermal resistance from

junction to case

in free air; JEDEC test board 90

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Product data sheet Rev. 3 — 7 May 2018

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11 Characteristics

Table 7. Characteristics

Tamb =25 °C; VSUPIC = 20 V; all voltages are measured with respect to ground (pin 2); currents are positive when flowing into

the IC; unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Unit

Supply (SUPIC pin)

Vstart(SUPIC) start voltage on pin SUPIC 12.35 13 13.65 V

Vuvp(SUPIC) undervoltage protection voltage

on pin SUPIC

8.55 9 9.45 V

operating mode; fsw = 100 kHz;

pin GATEPFC = floating;

VSNSBOOST = 2.2 V

- - 0.80 mAICC supply current

power-save mode; pin

PFCCOMP = floating;

VSNSBOOST = 2.7 V

- - 0.20 mA

Gate driver output (GATEPFC pin)

Isource(GATEPFC) source current on pin

GATEPFC

VGATEPFC = 2 V; VSUPIC ≥ 13 V - −0.6 - A

VGATEPFC = 2 V; VSUPIC ≥ 13 V - 0.6 - AIsink(GATEPFC) sink current on pin GATEPFC

VGATEPFC = 10 V; VSUPIC ≥ 13 V - 1.4 - A

Vo(max)GATEPFC maximum output voltage on pin

GATEPFC

10.0 11.0 12.0 V

Mains voltage sensing (SNSMAINS pin)

Ibi brownin current 5.35 5.75 6.15 µA

Ibo brownout current 4.65 5.00 5.35 µA

Ibo(hys) hysteresis of brownout current Ibi − Ibo 640 750 820 nA

td(det)bo brownout detection delay time 45.2 50 55.5 ms

Vregd(SNSMAINS) regulated voltage on pin

SNSMAINS

mains detection period;

no current at SNSMAINS;

Cmax(SNSMAINS) = 100 pF

230 250 270 mV

X-capacitor discharge (SNSCUR and GATEPFC pins)

td(dch) discharge delay time x-capacitor discharge 109 118 128 ms

Ich(GATEPFC) charge current on pin

GATEPFC

x-capacitor discharge −29 −26 −23 µA

Idch(GATEPFC) discharge current on pin

GATEPFC

x-capacitor discharge 23 26 29 µA

Vch(stop)SNSCUR stop charge voltage on pin

SNSCUR

x-capacitor discharge; stop of

external MOST gate charge;

dV/dt = 0

8.00 10.50 12.50 mV

Vdch(stop)GATEPFC stop discharge voltage on pin

GATEPFC

x-capacitor discharge; stop of

external MOST gate discharge

0.3 0.7 1.1 V

toff(dch) discharge off-time x-capacitor; time between

discharge/charge pulses;

GATEPFC pin

1.88 - 6.40 ms

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Product data sheet Rev. 3 — 7 May 2018

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Symbol Parameter Conditions Min Typ Max Unit

Tppulse period x-capacitor discharge;

pulse duration < 2 ms (typical);

GATEPFC pin

3.76 4.00 4.27 ms

Vdis(dch)GATEPFC disable discharge voltage on

pin GATEPFC

x-capacitor discharge 9.00 9.45 9.90 V

Vdis(dch)SNSCUR disable discharge voltage on

pin SNSCUR

x-capacitor discharge 44 50 56 mV

Output voltage sensing, regulation and compensation (SNSBOOST and PFCCOMP pins)

Vreg(SNSBOOST) regulation voltage on pin

SNSBOOST

IPFCCOMP = 0 A 2.475 2.500 2.525 V

gmtransconductance error amplifier;

VSNSBOOST to IPFCCOMP;

|VSNSBOOST − Vintregd(SNSBOOST)|

< 40 mV

−90 −75 −60 µA/V

Isink(PFCCOMP) sink current on pin PFCCOMP VSNSBOOST = 2 V;

VPFCCOMP = 2.75 V

30.0 35.5 41.0 µA

gm(high) high transconductance error amplifier;

VSNSBOOST to IPFCCOMP;

Vstart(gm)high ≤ VSNSBOOST

< Vstop(ovp)

- −1.26 - mA/V

Vgm(high)start start high transconductance

voltage

pin SNSBOOST 2.56 2.60 2.63 V

Iclamp(max) maximum clamp current pin PFCCOMP; energy save

mode; PFC off; VPFCCOMP = 0 V

−260 −220 −190 µA

Ien(PFC) PFC enable current pin PFCCOMP −15 −11.5 −8 µA

bidirectional clamp; energy

save mode; PFC off

3.40 3.50 3.60 V

upper clamp voltage;

unidirectional clamp;

operating mode; PFC on;

IPFCCOMP = 120 µA

3.70 3.80 3.90 V

Vclamp(PFCCOMP) clamp voltage on pin

PFCCOMP

lower clamp voltage;

unidirectional clamp;

operating mode; PFC

on; VSNSBOOST = 2.5 V;

IPFCCOMP = 30 µA

Vtonmax(PFCCOMP) V

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Product data sheet Rev. 3 — 7 May 2018

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Symbol Parameter Conditions Min Typ Max Unit

Mains compensation

minimum mains voltage

compensation current;

VPFCCOMP = 1.25 V;

VSNSBOOST = 2.5 V;

Imvc(SNSMAINS) = 5.25 µA

30 37.5 45 µston(PFC) PFC on-time

maximum mains voltage

compensation current;

VPFCCOMP = 1.25 V;

VSNSBOOST = 2.5 V;

Imvc(SNSMAINS) = Imvc(max)SNSMAINS

1.5 3 4.5 µs

Imvc(max)SNSMAINS maximum mains voltage

compensation current on pin

SNSMAINS

18 20 22 µA

PFC on-timer (PFCCOMP pin)

Vtonzero(PFCCOMP) zero on-time voltage on pin

PFCCOMP

3.40 3.50 3.60 V

Vtonmax(PFCCOMP) maximum on-time voltage on

pin PFCCOMP

1.18 1.23 1.28 V

fsw(PFC)max maximum PFC switching

frequency

120 134 148 kHz

toff(PFC)min minimum PFC off-time 1.25 1.55 1.85 µs

Demagnetization sensing (pin SNSAUX)

Vdet(demag)SNSAUX demagnetization detection

voltage on pin SNSAUX

−125 −90 −55 mV

tto(demag) demagnetization time-out time 37 44.5 52 µs

Iprot(SNSAUX) protection current on pin

SNSAUX

pin SNSAUX = open;

VSNSAUX = 50 mV

- −40 - nA

Valley sensing (SNSAUX pin)

(ΔV/Δt)vrec(min) minimum valley recognition

voltage change with time

- 1.7 V/µs

tto(vrec) valley recognition time-out time 3.0 3.8 4.6 µs

Output current sensing (SNSCUR pin)

Vreg(oc) overcurrent regulation voltage dV/dt = 0 0.48 0.50 0.52 V

td(swoff)driver driver switch-off delay time pin GATEPFC - 80 - ns

tleb leading edge blanking time VSNSCUR = 0.75 V 240 300 360 ns

Iprot(SNSCUR) protection current on pin

SNSCUR

pin SNSCUR = open - −50 - nA

Output voltage protection sensing (pin SNSBOOST)

Ipd(SNSBOOST) pull-down current on pin

SNSBOOST

protection active;

VSNSBOOST = 1.0 V;

85 100 115 µA

Vscp(stop) stop short-circuit protection

voltage

0.35 0.40 0.45 V

NXP Semiconductors TEA19162T/3

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Product data sheet Rev. 3 — 7 May 2018

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Symbol Parameter Conditions Min Typ Max Unit

Vscp(start) start short-circuit protection

voltage

0.45 0.50 0.55 V

td(start) start delay time after short-circuit protection

removed

3.30 3.62 4.00 ms

Ipu(rst)SNSBOOST reset pull-up current on pin

SNSBOOST

fast latch reset;

VSNSBOOST = 1.5 V

−245 −210 −175 µA

Vpu(rst)SNSBOOST reset pull-up voltage on pin

SNSBOOST

fast latch reset 1.94 2.00 2.06 V

Iprot(SNSBOOST) protection current on open pin

SNSBOOST

pin SNSBOOST = open - 35 - nA

Vovp(stop) stop overvoltage protection

voltage

2.59 2.63 2.67 V

Vovp(start) start overvoltage protection

voltage

2.47 2.53 2.59 V

Vhys(ovp) overvoltage protection

hysteresis voltage on pin

SNSBOOST

Vovp(stop) − Vovp(start) 0.07 0.10 0.13 V

Soft start (pin SNSCUR)

tstart(soft) soft start time 3.30 3.62 4.00 ms

Vstart(soft)init initial soft start voltage 100 125 155 mV

Soft stop (pins SNSBOOST and PFCCOMP)

Vdet(L)SNSBOOST LOW-level detection voltage on

pin SNSBOOST

soft stop 2.74 2.80 2.86 V

Vdet(H)SNSBOOST HIGH-level detection voltage on

pin SNSBOOST

soft stop 3.17 3.23 3.29 V

Ich(stop)soft soft stop charge current pin PFCCOMP −36 −32 −28 µA

td(ovp) overvoltage protection delay

time

pin SNSBOOST 80 100 120 µs

External and internal overtemperature measurement

Ien(NTC) NTC enable current pin SNSMAINS; NTC

measurement; mains

measurement period; falling

slope

2.0 2.5 3.0 µA

Io(SNSMAINS) output current on pin

SNSMAINS

−214 −200 −186 µA

tdet(NTC)max maximum NTC detection time 0.92 1.00 1.08 ms

Vdet(SNSMAINS) detection voltage on pin

SNSMAINS

NTC measurement;

ISNSMAINS = −200 A

1.95 2.00 2.05 V

Tpl(IC) IC protection level temperature 130 150 160 °C

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12 Application information

Capacitor CSUPIC filters the IC supply voltage, which must be supplied externally.

Sense resistor Rsense converts the current through the MOSFET M1 to a voltage on

the SNSCUR pin. The Rsense value determines the maximum primary peak current in

MOSFET M1.

To limit the current into the SNSCUR pin due to negative voltage spikes across the sense

resistor, resistor RSNSCUR is added.

To protect the IC from damage during lightning events, resistor Raux is added.

aaa-018105

LLC

resonant converter

PFC

SNSAUX GATEPFC

SNSMAINS SNSCUR

SUPIC

Vmains-L

Vmains-N

Rmains

GND SNSBOOST

Vboost

Cboost

PFCCOMP

Raux

RSNSCUR

Rsense

RSNSBOOST

CSUPIC

Figure 13. Application diagram

NXP Semiconductors TEA19162T/3

PFC controller

Product data sheet Rev. 3 — 7 May 2018

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13 Package outline

UNIT A

max. A1A2A3bpc D(1) E(2) (1)

e HEL LpQ Zywv θ

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

inches

1.75 0.25

0.10

1.45

1.25 0.25 0.49

0.36

0.25

0.19

5.0

4.8

4.0

3.8 1.27 6.2

5.8 1.05 0.7

0.6

0.7

0.3 8

0.25 0.10.25

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Notes

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

1.0

0.4

SOT96-1

detail X

vMA

(A )

pin 1 index

076E03 MS-012

0.069 0.010

0.004

0.057

0.049 0.01 0.019

0.014

0.0100

0.0075

0.20

0.19

0.16

0.15 0.05 0.244

0.228

0.028

0.024

0.028

0.012

0.010.010.041 0.004

0.039

0.016

0 2.5 5 mm

scale

SO8: plastic small outline package; 8 leads; body width 3.9 mm SOT96-1

99-12-27

03-02-18

Figure 14. Package outline SOT096-1 (SO8)

NXP Semiconductors TEA19162T/3

PFC controller

Product data sheet Rev. 3 — 7 May 2018

27 / 30

14 Revision history

Table 8. Revision history

Document ID Release date Data sheet status Change notice Supersedes

TEA19162T v.3 20180507 Product data sheet - TEA19162T v.2.0

Modifications: •Section 5, Marking, has been added to the data sheet.

•Figure 4, Start-up of the PFC and LLC, has been updated.

•Figure 11, PFC burst mode, has been updated.

•Section 10, Thermal characteristics, has been updated.

TEA19162T v.2 20160413 Product data sheet - TEA19162T v.1.0

Modifications: •Text and graphics have been updated throughout the data sheet.

TEA19162T v.1 20160310 Product data sheet - -

NXP Semiconductors TEA19162T/3

PFC controller

Product data sheet Rev. 3 — 7 May 2018

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15 Legal information

15.1 Data sheet status

Document status[1][2] Product status[3] Definition

Objective [short] data sheet Development This document contains data from the objective specification for product

development.

Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.

Product [short] data sheet Production This document contains the product specification.

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term 'short data sheet' is explained in section "Definitions".

[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple

devices. The latest product status information is available on the Internet at URL http://www.nxp.com.

15.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences

of use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

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intended for quick reference only and should not be relied upon to contain

detailed and full information. For detailed and full information see the

relevant full data sheet, which is available on request via the local NXP

Semiconductors sales office. In case of any inconsistency or conflict with the

short data sheet, the full data sheet shall prevail.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

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Product data sheet.

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Limited warranty and liability — Information in this document is believed

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Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

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Characteristics sections of this document is not warranted. Constant or

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Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

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purchase of NXP Semiconductors products by customer.

NXP Semiconductors TEA19162T/3

PFC controller

Product data sheet Rev. 3 — 7 May 2018

29 / 30

No offer to sell or license — Nothing in this document may be interpreted

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the grant, conveyance or implication of any license under any copyrights,

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NXP Semiconductors accepts no liability for inclusion and/or use of non-

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of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specifications.

Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

15.4 Trademarks

Notice: All referenced brands, product names, service names and

trademarks are the property of their respective owners.

GreenChip — is a trademark of NXP B.V.

NXP Semiconductors TEA19162T/3

PFC controller

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section 'Legal information'.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 7 May 2018

Document identifier: TEA19162T

Contents

1 General description ............................................ 1

2 Features and benefits .........................................2

2.1 Distinctive features ............................................ 2

2.2 Green features ...................................................2

2.3 Protection features .............................................2

3 Applications .........................................................2

4 Ordering information .......................................... 3

5 Marking .................................................................3

6 Block diagram ..................................................... 4

7 Pinning information ............................................ 5

7.1 Pinning ...............................................................5

7.2 Pin description ................................................... 5

8 Functional description ........................................6

8.1 General control .................................................. 6

8.2 Supply voltage and start-up ...............................6

8.3 Protections ......................................................... 8

8.3.1 Internal OverTemperature Protection (OTP) ......8

8.3.2 Brownin/brownout and external

overtemperature protection ................................9

8.3.3 Soft stop overvoltage protection

(SNSBOOST pin) ...............................................9

8.3.4 Overvoltage protection (SNSBOOST pin) ........10

8.3.5 PFC open-loop protection (SNSBOOST pin) ... 10

8.3.6 Overcurrent protection (SNSCUR pin) .............10

8.3.7 Fast latch reset ................................................10

8.4 Power factor correction regulation ................... 11

8.4.1 Soft start (SNSCUR pin) ..................................12

8.4.2 ton control ........................................................12

8.4.3 PFC error amplifier (PFCCOMP and

SNSBOOST pins) ............................................ 12

8.4.4 Valley switching and demagnetization

(SNSAUX pin) ..................................................13

8.4.5 Frequency limitation .........................................13

8.4.6 Mains voltage compensation (SNSMAINS

pin) ................................................................... 14

8.4.7 Active X-capacitor discharge ........................... 14

8.5 PFC-LLC communication protocol ................... 16

8.5.1 Protections ....................................................... 16

8.5.2 PFC burst mode .............................................. 17

8.5.3 Soft stop .......................................................... 19

8.6 Driver (pin GATEPFC) .....................................19

9 Limiting values .................................................. 20

10 Thermal characteristics ....................................20

11 Characteristics .................................................. 21

12 Application information .................................... 25

13 Package outline .................................................26

14 Revision history ................................................ 27

15 Legal information .............................................. 28