AS7C33128PFS16B AS7C33128PFS18B October 2003 (R) 3.3V 128K x 16/18 pipeline burst synchronous SRAM Features *Byte write enables *Multiple chip enables for easy expansion *3.3V core power supply *2.5V or 3.3V I/O operation with separate VDDQ *30 mW typical standby power in power down mode *NTDTM1 pipeline architecture available (AS7C33128NTD16B/AS7C33128NTD18B) *Organization: 131,072 words x 16 or 18 bits *Fast clock speeds to 200 MHz in LVTTL/LVCMOS *Fast clock to data access: 3.0/3.5/4.0 ns *Fast OE access time: 3.0/3.5/4.0 ns *Fully synchronous register-to-register operation *"Flow-through" or "Pipeline" mode *Single-cycle deselect Dual-cycle deselect also available (AS7C33128PFD16B/ AS7C33128PFD18B) 1. Pentium(R) is a registered trademark of Intel Corporation. NTDTM is a trademark of Alliance Semiconductor Corporation. All trademarks mentioned in this document are the property of their respective owners. *Pentium(R)1 compatible architecture and timing *Asynchronous output enable control *Economical 100-pin TQFP package Pin arrangement CLK CS CLR CLK ADV ADSC ADSP 17 A[16:0] Burst logic Q D Address register CS 17 15 NC NC NC 128K x 16/18 Memory array 17 VDDQ VSSQ NC NC DQb DQb VSSQ VDDQ DQb DQb FT VDD NC VSS DQb DQb VDDQ VSSQ DQb DQb DQpb/NC NC VSSQ VDDQ NC NC NC CLK 16/18 GWE BWb D DQb 16/18 Q Byte Write registers BWE CLK D DQa Q 2 Byte Write registers BWa CLK D EnableQ register CE CLK ZZ Power down D OE Input registers CLK CLK Output registers Q Enable delay register CLK OE FT TQFP 14 x 20mm 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 A NC NC VDDQ VSSQ NC DQpa/NC DQa DQa VSSQ VDDQ DQa DQa VSS NC VDD ZZ DQa DQa VDDQ VSSQ DQa DQa NC NC VSSQ VDDQ NC NC NC LBO A A A A A1 A0 NC NC VSS VDD NC NC A A A A A A NC CE0 CE1 CE2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 LBO 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 A A CE0 CE1 NC NC BWb BWa CE2 VDD VSS CLK GWE BWE OE ADSC ADSP ADV A A Logic block diagram 16/18 DQ [a,b] Note: pins 24, 74 are NC for x16. Selection guide -200 -166 -133 5 6 7.5 Maximum pipelined clock frequency 200 166 133 Maximum pipelined clock access time 3 3.5 4 Maximum operating current 400 350 325 mA Maximum standby current 120 100 90 mA Maximum CMOS standby current (DC) 30 30 30 mA Minimum cycle time 10/29/03; v.1.0 Alliance Semiconductor Units ns MHz ns P. 1 of 14 Copyright (c) Alliance Semiconductor. All rights reserved. AS7C33128PFS16B AS7C33128PFS18B (R) Functional description The AS7C33128PFS16B and AS7C33128PFS18B are high performance CMOS 2 Mbit synchronous Static Random Access Memory (SRAM) devices organized as 131,072 words x 16 or 18 bits and incorporate a pipeline for highest frequency on any given technology. Timing for this device is compatible with existing Pentium(R) synchronous cache specifications. This architecture is suited for ASIC, DSP (TMS320C6X), and PowerPCTM1-based systems in computing, datacom, instrumentation, and telecommunications systems. Fast cycle times of 5.0/6.0/7.5 ns with clock access times (tCD) of 3.0/3.5/4.0 ns enable 200, 166 and 133 MHz bus frequencies. Three chip enable inputs permit easy memory expansion. Burst operation is initiated in one of two ways: the controller address strobe (ADSC), or the processor address strobe (ADSP). The burst advance pin (ADV) allows subsequent internally generated burst addresses. Read cycles are initiated with ADSP (regardless of WE and ADSC) using the new external address clocked into the on-chip address register. When ADSP is sampled LOW, the chip enables are sampled active, and the output buffer is enabled with OE. In a read operation the data accessed by the current address, registered in the address registers by the positive edge of CLK, are carried to the data-out registers and driven on the output pins on the next positive edge of CLK. ADV is ignored on the clock edge that samples ADSP asserted but is sampled on all subsequent clock edges. Address is incremented internally for the next access of the burst when ADV is sampled LOW and both address strobes are HIGH. Burst mode is selectable with the LBO input. With LBO unconnected or driven HIGH, burst operations use a Pentium(R) count sequence. With LBO driven LOW the device uses a linear count sequence suitable for PowerPCTM and many other applications. Write cycles are performed by disabling the output buffers with OE and asserting a write command. A global write enable GWE writes all 16/18 bits regardless of the state of individual BW[a:b] inputs. Alternately, when GWE is HIGH, one or more bytes may be written by asserting BWE and the appropriate individual byte BWn signal(s). BWn is ignored on the clock edge that samples ADSP LOW, but is sampled on all subsequent clock edges. Output buffers are disabled when BWn is sampled LOW (regardless of OE). Data is clocked into the data input register when BWn is sampled LOW. Address is incremented internally to the next burst address if BWn and ADV are sampled LOW. Read or write cycles may also be initiated with ADSC instead of ADSP. The differences between cycles initiated with ADSC and ADSP follow. ADSP must be sampled HIGH when ADSC is sampled LOW to initiate a cycle with ADSC. WE signals are sampled on the clock edge that samples ADSC LOW (and ADSP HIGH). Master chip select CE0 blocks ADSP, but not ADSC. The AS7C33128PFS16B and AS7C33128PFS18B operate from a 3.3V supply. I/Os use a separate power supply that can operate at 2.5V or 3.3V. These devices are available in a 100-pin 14x20 mm TQFP packaging. 1. PowerPCTM is a trademark International Business Machines Corporation 10/29/03; v.1.0 Alliance Semiconductor P. 2 of 14 AS7C33128PFS16B AS7C33128PFS18B (R) Capacitance Parameter Input capacitance I/O capacitance Symbol CIN CI/O Signals Address and control pins I/O pins Test conditions VIN = 0V VIN = VOUT = 0V Max 5 7 Unit pF pF Write enable truth table (per byte) GWE L H H H BWE X L H L BWn X L X H WEn T T F* F* Key: *= valid read; n = a,b X = Don't Care, L = Low, H = High, T=True, F=False; WE, WEn = internal write signal. Burst Order Starting Address First increment Second increment Third increment 10/29/03; v.1.0 Interleaved Burst Order Linear Burst Order LBO=1 01 10 00 11 11 00 10 01 LBO=0 01 10 10 11 11 00 00 01 00 01 10 11 11 10 01 00 Starting Address First increment Second increment Third increment Alliance Semiconductor 00 01 10 11 11 00 01 10 P. 3 of 14 AS7C33128PFS16B AS7C33128PFS18B (R) Signal descriptions Signal CLK I/O I Properties CLOCK A0-A16 I SYNC DQ[a,b] I/O SYNC CE0 I SYNC CE1, CE2 I SYNC ADSP I SYNC ADSC I SYNC ADV I SYNC GWE I SYNC BWE I SYNC BW[a,b] I SYNC OE I ASYNC LBO I STATIC FT I STATIC ZZ I ASYNC Description Clock. All inputs except OE, FT, ZZ, LBO are synchronous to this clock. Address. Sampled when all chip enables are active and ADSC or ADSP are asserted. Data. Driven as output when the chip is enabled and OE is active. Master chip enable. Sampled on clock edges when ADSP or ADSC is active. When CE0 is inactive, ADSP is blocked. Refer to the Synchronous Truth Table for more information. Synchronous chip enables. Active HIGH and active LOW, respectively. Sampled on clock edges when ADSC is active or when CE0 and ADSP are active. Address strobe (processor). Asserted LOW to load a new address or to enter standby mode. Address strobe (controller). Asserted LOW to load a new address or to enter standby mode. Burst advance. Asserted LOW to continue burst read/write. Global write enable. Asserted LOW to write all 16/18 bits. When HIGH, BWE and BW[a,b] control write enable. Byte write enable. Asserted LOW with GWE = HIGH to enable effect of BW[a,b] inputs. Write enables. Used to control write of individual bytes when GWE = HIGH and BWE = LOW. If any of BW[a,b] is active with GWE = HIGH and BWE = LOW the cycle is a write cycle. If all BW[a,b] are inactive, the cycle is a read cycle. Asynchronous output enable. I/O pins are driven when OE is active and the chip is in read mode. Selects Burst mode. When tied to VDD or left floating, device follows interleaved Burst order. When driven Low, device follows linear Burst order. This signal is internally pulled High. Selects Pipeline or Flow-through mode.When tied to VDD or left floating, enables Pipeline mode. When driven Low, enables single register Flow-through mode. This signal is internally pulled High. Snooze. Places device in low power mode; data is retained. Connect to GND if unused. Absolute maximum ratings Parameter Power supply voltage relative to GND Input voltage relative to GND (input pins) Input voltage relative to GND (I/O pins) Power dissipation DC output current Storage temperature (plastic) Temperature under bias Symbol VDD, VDDQ VIN VIN PD IOUT Tstg Tbias Min -0.5 -0.5 -0.5 - - -65 -65 Max +4.6 VDD + 0.5 VDDQ + 0.5 1.8 50 +150 +135 Unit V V V W mA C C Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect reliability. 10/29/03; v.1.0 Alliance Semiconductor P. 4 of 14 AS7C33128PFS16B AS7C33128PFS18B (R) Synchronous truth table CE0 H L L L L L L L L X X X X H H H H L X H X H CE1 X L L X X H H H H X X X X X X X X H X X X X CE2 X X X H H L L L L X X X X X X X X L X X X X ADSP X L H L H L L H H H H H H X X X X H H X H X ADSC L X L X L X X L L H H H H H H H H L H H H H ADV X X X X X X X X X L L H H L L H H X L L H H WEn1 X X X X X X X F F F F F F F F F F T T T T T OE X X X X X L H L H L H L H L H L H X X X X X Address accessed NA NA NA NA NA External External External External Next Next Current Current Next Next Current Current External Next Next Current Current CLK L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H Operation Deselect Deselect Deselect Deselect Deselect Begin read Begin read Begin read Begin read Cont. read Cont. read Suspend read Suspend read Cont. read Cont. read Suspend read Suspend read Begin write Cont. write Cont. write Suspend write Suspend write DQ Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z2 Hi-Z Hi-Z2 Hi-Z Q Hi-Z Q Hi-Z Q Hi-Z Q Hi-Z D3 D D D D Key: X = Don't Care, L = Low, H = High. 1See "Write enable truth table" on page 3 for more information. 2 Q in flow through mode 3 For write operation following a READ, OE must be HIGH before the input data set up time and held HIGH throughout the input hold time. Recommended operating conditions Parameter Supply voltage 3.3V I/O supply voltage 2.5V I/O supply voltage Input voltages 1 Ambient operating temperature Symbol VDD VSS VDDQ VSSQ VDDQ VSSQ VIH VIL VIH VIL Min 3.135 0.0 3.135 0.0 2.35 0.0 2.0 -0.52 2.0 -0.52 Nominal 3.3 0.0 3.3 0.0 2.5 0.0 - - - - Max 3.6 0.0 3.6 0.0 2.9 0.0 VDD + 0.3 0.8 VDDQ + 0.3 0.8 Unit TA 0 - 70 C V V V V V 1 Input voltage ranges apply to 3.3V I/O operation. For 2.5V I/O operation, contact factory for input specifications. 2 VIL min = -2.0V for pulse width less than 0.2 x tRC. 10/29/03; v.1.0 Alliance Semiconductor P. 5 of 14 AS7C33128PFS16B AS7C33128PFS18B (R) TQFP thermal resistance Description Thermal resistance (junction to ambient)1 Thermal resistance (junction to top of case)1 Conditions Symbol Typical Units JA 46 C/W JC 2.8 C/W -200 Min Max -166 Min Max -133 Min Max Unit 2 - 2 - 2 A - 2 - 2 - 2 A - 400 - 350 - 325 mA - 120 - 100 - 90 - 30 - 30 - 30 - 30 - 30 - 30 - 2.4 0.4 - - 2.4 0.4 - - 2.4 0.4 - Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51 1 This parameter is sampled. DC electrical characteristics Parameter Input leakage current1 Output leakage current Operating power supply current Symbol |ILI| |ILO| ICC2 ISB Standby power supply current ISB1 ISB2 Output voltage VOL VOH Test conditions VDD = Max, VIN = GND to VDD - OE VIH, VDD = Max, VOUT = GND to VDD CE0 = VIL, CE1 = VIH, CE2 = VIL, f = fMax, IOUT = 0 mA Deselected, f = fMax, ZZ VIL Deselected, f = 0, ZZ 0.2V all VIN 0.2V or VDD - 0.2V Deselected, f = fMax, ZZ VDD - 0.2V All VIN VIL or VIH IOL = 8 mA IOH = -4 mA mA V 1 LBO pin has an internal pull-up and input leakage = 10 A. 2 ICC give with no output loading. ICC increases with faster cycle times and greater output loading. DC electrical characteristics for 2.5V I/O operation -200 -166 -133 Parameter Symbol Test conditions Min Max Min Max Min Max Unit Output leakage current |ILO| OE >VIH, VDD = Max, VOUT = GND to VDD -1 1 -1 1 -1 1 A VOL IOL = 2 mA - 0.7 - 0.7 - 0.7 VOH IOH = -2 mA 1.7 - 1.7 - 1.7 - Output voltage 10/29/03; v.1.0 Alliance Semiconductor P. 6 of 14 V AS7C33128PFS16B AS7C33128PFS18B (R) Timing characteristics over operating range Parameter Clock frequency Cycle time (pipelined mode) Cycle time (flow-through mode) Clock access time (pipelined mode) Clock access time (flow-through mode) Output enable LOW to data valid Sym fMax tCYC tCYCF tCD tCDF tOE tLZC Data output invalid from clock HIGH tOH Output enable LOW to output Low Z tLZOE Output enable HIGH to output High Z tHZOE Clock HIGH to output High Z tHZC Output enable HIGH to invalid output tOHOE Clock HIGH pulse width tCH Clock LOW pulse width tCL Address setup to clock HIGH tAS Data setup to clock HIGH tDS Write setup to clock HIGH tWS Chip select setup to clock HIGH tCSS Address hold from clock HIGH tAH Data hold from clock HIGH tDH Write hold from clock HIGH tWH Chip select hold from clock HIGH tCSH ADV setup to clock HIGH tADVS ADSP setup to clock HIGH tADSPS ADSC setup to clock HIGH tADSCS ADV hold from clock HIGH tADVH ADSP hold from clock HIGH tADSPH ADSC hold from clock HIGH tADSCH Clock HIGH to output Low Z -200 Min Max - 200 5 - 7.5 - - 3.0 -166 Min Max - 166 6 - 9 - - 3.5 -133 Min Max - 133 7.5 - 12 - - 4.0 Unit MHz ns ns ns - 6.5 - 8.0 - 10 ns - 0 1.5 0 - - 0 2.2 2.2 1.4 1.4 1.4 1.4 0.4 0.4 0.4 0.4 1.4 1.4 1.4 0.4 0.4 0.4 3.0 - - - 3.0 3.0 - - - - - - - - - - - - - - - - - - 0 1.5 0 - - 0 2.4 2.4 1.5 1.5 1.5 1.5 0.5 0.5 0.5 0.5 1.5 1.5 1.5 0.5 0.5 0.5 3.5 - - - 3.5 3.5 - - - - - - - - - - - - - - - - - - 0 1.5 0 - - 0 2.5 2.5 1.5 1.5 1.5 1.5 0.5 0.5 0.5 0.5 1.5 1.5 1.5 0.5 0.5 0.5 4.0 - - - 4.0 4.0 - - - - - - - - - - - - - - - - - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Notes1 2,3,4 2 2,3,4 2,3,4 2,3,4 5 5 6 6 6,7 6,8 6 6 6,7 6,8 6 6 6 6 6 6 1 See "Notes" on page 11.. 10/29/03; v.1.0 Alliance Semiconductor P. 7 of 14 AS7C33128PFS16B AS7C33128PFS18B (R) Key to switching waveforms Rising input Falling input Undefined/don't care Timing waveform of read cycle tCH tCYC tCL CLK tADSPS tADSPH ADSP tADSCS tADSCH ADSC tAS LOAD NEW ADDRESS tAH A1 Address A2 A3 tWS tWH GWE, BWE tCSS tCSH CE0, CE2 CE1 tADVS tADVH ADV OE tCD tHZOE tOH DOUT (pipelined mode) tLZOE Q(A1) Q(A2) ADV INSERTS WAIT STATES Q(A2Y01) Q(A2Y10) Q(A2Y11) Q(A3) tHZC Q(A3Y01) Q(A3Y10) tOE DOUT (flow-through mode) Q(A1) Q(A2Y01) Q(A2Y10) Q(A2Y11) Q(A3) Q(A3Y01) Q(A3Y10) Q(A3Y11) tHZC Note: Y = XOR when LBO = HIGH/No Connect; Y = ADD when LBO = LOW. BW[a:b] is don't care. 10/29/03; v.1.0 Alliance Semiconductor P. 8 of 14 AS7C33128PFS16B AS7C33128PFS18B (R) Timing waveform of write cycle tCYC tCH tCL CLK tADSPS tADSPH ADSP tADSCS tADSCH ADSC ADSC LOADS NEW ADDRESS tAS tAH Address A1 A3 A2 tWS tWH BWE BWa,b tCSS tCSH CE0, CE2 CE1 tADVS ADV SUSPENDS BURST tADVH ADV OE tDS tDH Data In D(A1) D(A2) D(A2Y01) D(A2Y01) D(A2Y10) D(A2Y11) D(A3) D(A3Y01) D(A3Y10) Note: Y = XOR when LBO = HIGH/No Connect; Y = ADD when LBO = LOW. 10/29/03; v.1.0 Alliance Semiconductor P. 9 of 14 AS7C33128PFS16B AS7C33128PFS18B (R) Timing waveform of read/write cycle tCYC tCH tCL CLK tADSPS tADSPH ADSP tAS tAH Address A2 A1 A3 tWS tWH GWE CE0, CE2 CE1 tADVS tADVH ADV OE tDS tDH D(A2) DIN tLZC tHZOE tCD Q(A1) DOUT (pipeline mode) tOH tLZOE tOE Q(A3) Q(A3Y01) Q(A3Y10) Q(A3Y11) tCDF DOUT (flow-through mode) Q(A1) Q(A3Y01) Q(A3Y10) Q(A3Y11) Note: Y = XOR when LBO = HIGH/No Connect; Y = ADD when LBO = LOW. 10/29/03; v.1.0 Alliance Semiconductor P. 10 of 14 AS7C33128PFS16B AS7C33128PFS18B (R) AC test conditions * Output load: see Figure B, except for tLZC, tLZOE, tHZOE, tHZC, see Figure C. * Input pulse level: GND to 3V. See Figure A. Thevenin equivalent: * Input rise and fall time (measured at 0.3V and 2.7V): 2 ns. See Figure A. +3.0V 90% 10% GND 90% 10% Figure A: Input waveform DOUT Z0 = 50 50 VL = 1.5V for 3.3V I/O; 30 pF* = V DDQ/2 for 2.5V I/O Figure B: Output load (A) +3.3V for 3.3V I/O; /+2.5V for 2.5V I/O DOUT 353 / 1538 319 / 1667 5 pF* GND *including scope and jig capacitanc Figure C: Output load (B) Notes 1 For test conditions, see AC Test Conditions, Figures A, B, C. 2 This parameter measured with output load condition in Figure C. 3 This parameter is sampled, but not 100% tested. 4 tHZOE is less than tLZOE; and tHZC is less than tLZC at any given temperature and voltage. 5 tCH measured as HIGH above VIH and tCL measured as LOW below VIL. 6 This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK. All other synchronous inputs must meet the setup and hold times for all rising edges of CLK when chip is enabled. 7 Write refers to GWE, BWE, BW[a,b]. 8 Chip select refers to CE0, CE1, CE2 10/29/03; v.1.0 Alliance Semiconductor P. 11 of 14 AS7C33128PFS16B AS7C33128PFS18B (R) Package Dimensions 100-pin quad flat pack (TQFP) Hd D c L1 L b A1 A2 e TQFP Min Max A1 0.05 A2 1.35 1.45 b 0.22 0.38 0.15 c 0.09 0.20 D 13.90 14.10 E 19.90 20.10 e He E 0.65 nominal Hd 15.85 16.15 He 21.80 22.20 L 0.45 0.75 L1 1.00 nominal 0 7 Dimensions in millimeters 10/29/03; v.1.0 Alliance Semiconductor P. 12 of 14 AS7C33128PFS16B AS7C33128PFS18B (R) Ordering information Package TQFP TQFP TQFP TQFP Width x16 x16 x18 x18 -200 MHz -166 MHz AS7C33128PFS16B-200TQC AS7C33128PFS16B-166TQC AS7C33128PFS16B-200TQI AS7C33128PFS16B-166TQI AS7C33128PFS18B-200TQC AS7C33128PFS18B-166TQC AS7C33128PFS18B-200TQI AS7C33128PFS18B-166TQI -133 MHz AS7C33128PFS16B-133TQC AS7C33128PFS16B-133TQI AS7C33128PFS18B-133TQC AS7C33128PFS18B-133TQI Part numbering guide AS7C 1 33 2 128 3 PF 4 S 5 16/18 6 B 7 -XXX 8 TQ 9 C/I 10 1. Alliance Semiconductor SRAM Prefix 2.Operating voltage: 33=3.3V 3.Organization: 128=128K 4.Pipeline-Flowthrough (each device works in both modes) 5.Deselect: S=Single cycle deselect 6.Organization: 16=x16; 18=x18 7.Production version: B= product revision 8.Clock speed (MHz) 9.Package type: TQ=TQFP 10.Operating temperature: C=Commercial (0 C to 70 C); I=Industrial (-40 C to 85 C) 10/29/03; v.1.0 Alliance Semiconductor P. 13 of 14 AS7C33128PFS16B AS7C33128PFS18B (R) (R) Alliance Semiconductor Corporation 2575, Augustine Drive, Santa Clara, CA 95054 Tel: 408 - 855 - 4900 Fax: 408 - 855 - 4999 www.alsc.com Copyright (c) Alliance Semiconductor All Rights Reserved Part Number: AS7C33128PFS16B-18B Document Version: v.1.0 (c) Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. 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