ADC14155WRQV - Texas Instruments High-Performance Analog

ADC14155QML

ADC14155QML 14-Bit, 155 MSPS, 1.1 GHz Bandwidth A/D Converter

Literature Number: SNAS378H

ADC14155QML

July 16, 2010

14-Bit, 155 MSPS, 1.1 GHz Bandwidth A/D Converter

General Description

The ADC14155 is a high-performance CMOS analog-to-dig-

ital converter capable of converting analog input signals into

14-bit digital words at rates up to 155 Mega Samples Per

Second (MSPS). This converter uses a differential, pipelined

architecture with digital error correction and an on-chip sam-

ple-and-hold circuit to minimize power consumption and the

external component count, while providing excellent dynamic

performance. A unique sample-and-hold stage yields a full-

power bandwidth of 1.1 GHz. The ADC14155 operates from

dual +3.3V and +1.8V power supplies and consumes 967 mW

of power at 155 MSPS.

The separate +1.8V supply for the digital output interface al-

lows lower power operation with reduced noise. A power-

down feature reduces the power consumption to 5 mW with

the clock input disabled, while still allowing fast wake-up time

to full operation.

The differential inputs provide a full scale differential input

swing equal to 2 times the reference voltage. A stable 1.0V

internal voltage reference is provided, or the ADC14155 can

be operated with an external reference.

The Clock mode (differential versus single-ended) and output

data format (offset binary versus 2's complement) are pin-se-

lectable. A duty cycle stabilizer maintains performance over

a wide range of clock duty cycles.

The ADC14155 is available in a 48-lead thermally ehanced

mult-layer ceramic quad package and operates over the mil-

itary temperature range of -55°C to +125°C.

Features

■Total Ionizing Dose 100 krad(Si)

■Single Event Latch-up 120 MeV-cm2/mg

■1.1 GHz Full Power Bandwidth

■Internal sample-and-hold circuit

■Low power consumption

■Internal precision 1.0V reference

■Single-ended or Differential clock modes

■Data Ready output clock

■Clock Duty Cycle Stabilizer

■Dual +3.3V and +1.8V supply operation (+/- 10%)

■Power-down mode

■Offset binary or 2's complement output data format

■48-pin Cer Quad package, (11.5mm x 11.5mm, 0.635mm

pin-pitch)

Key Specifications

■Resolution 14 Bits

■Conversion Rate 155 MSPS

■SNR (fIN = 70 MHz) 70.1 dBFS (typ)

■SFDR (fIN = 70 MHz) 82.3 dBFS (typ)

■ENOB (fIN = 70 MHz) 11.3 bits (typ)

■Full Power Bandwidth 1.1 GHz (typ)

■Power Consumption 967 mW (typ)

Applications

■High IF Sampling Receivers

■Power Amplifier Linearization

■Multi-carrier, Multi-mode Receivers

■Test and Measurement Equipment

■Communications Instrumentation

■Radar Systems

Ordering Information

NS Part Number SMD Part Number NS Package Number Package Description

ADC14155W-MLS

Flight Part

EL48A 48L Cer Quad

ADC14155WRQV

Flight Part TBD EL48A 48L Cer Quad

ADC14155W-MPR

Pre-Flight Prototype EL48A 48L Cer Quad

ADC14155LCVAL

Low Frequency Ceramic

Evaluation Board

48L Cer Quad

on Evaluation Board

ADC14155HCVAL

High Frequency Ceramic

Evaluation Board

48L Cer Quad

on Evaluation Board

ADC14155QML 14-Bit, 155 MSPS, 1.1 GHz Bandwidth A/D Converter

Block Diagram

20210702

Connection Diagram

20210714

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ADC14155QML

Pin Descriptions and Equivalent Circuits

Pin No. Symbol Equivalent Circuit Description

ANALOG I/O

4VIN−Differential analog input pins. The differential full-scale input signal

level is two times the reference voltage with each input pin signal

centered on a common mode voltage, VCM.

5VIN+

42, 43 VRP

These pins should each be bypassed to AGND with a low ESL

(equivalent series inductance) 0.1 µF capacitor placed very close

to the pin to minimize stray inductance. A 0.1 µF capacitor should

be placed between VRP and VRN as close to the pins as possible,

and a 10 µF capacitor should be placed in parallel.

VRP and VRN should not be loaded. VRM may be loaded to 1mA for

use as a temperature stable 1.5V reference.

It is recommended to use VRM to provide the common mode

voltage, VCM, for the differential analog inputs, VIN+ and VIN−.

46, 47 VRM

44, 45 VRN

48 VREF

This pin can be used as either the +1.0V internal reference voltage

output (internal reference operation) or as the external reference

voltage input (external reference operation).

To use the internal reference, VREF should be decoupled to AGND

with a 0.1 µF, low equivalent series inductance (ESL) capacitor. In

this mode, VREF defaults as the output for the internal 1.0V

reference.

To use an external reference, overdrive this pin with a low noise

external reference voltage. The output impedance of the internal

reference at this pin is 9kΩ. Therefore, to overdrive this pin, the

impedance of the external reference source should be << 9kΩ.

This pin should not be used to source or sink current.

The full scale differential input voltage range is 2 * VREF.

DIGITAL I/O

11 CLK+ The clock input pins can be configured to accept either a single-

ended or a differential clock input signal.

When the single-ended clock mode is selected through CLK_SEL/

DF (pin 8), connect the clock input signal to the CLK+ pin and

connect the CLK− pin to AGND.

When the differential clock mode is selected through CLK_SEL/DF

(pin 8), connect the positive and negative clock inputs to the CLK

+ and CLK− pins, respectively.

The analog input is sampled on the falling edge of the clock input.

12 CLK−

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ADC14155QML

Pin No. Symbol Equivalent Circuit Description

8 CLK_SEL/DF

This is a four-state pin controlling the input clock mode and output

data format.

CLK_SEL/DF = VA, CLK+ and CLK− are configured as a

differential clock input. The output data format is 2's complement.

CLK_SEL/DF = (2/3)*VA, CLK+ and CLK− are configured as a

differential clock input. The output data format is offset binary.

CLK_SEL/DF = (1/3)*VA, CLK+ is configured as a single-ended

clock input and CLK− should be tied to AGND. The output data

format is 2's complement.

CLK_SEL/DF = AGND, CLK+ is configured as a single-ended clock

input and CLK− should be tied to AGND. The output data format is

offset binary.

7 PD

This is a two-state input controlling Power Down.

PD = VA, Power Down is enabled. In the Power Down state only

the reference voltage circuitry remains active and power

dissipation is reduced.

PD = AGND, Normal operation.

17-24,

27-32 D0–D13

Digital data output pins that make up the 14-bit conversion result.

D0 (pin 17) is the LSB, while D13 (pin 32) is the MSB of the output

word. Output levels are CMOS compatible.

33 OVR Over-Range Indicator. This output is set HIGH when the input

amplitude exceeds the 14-bit conversion range (0 to 16383).

34 DRDY

Data Ready Strobe. This pin is used to clock the output data. It has

the same frequency as the sampling clock. One word of data is

output in each cycle of this signal. The rising edge of this signal

should be used to capture the output data.

ANALOG POWER

2, 9, 37, 40,

41 VA

Positive analog supply pins. These pins should be connected to a

quiet +3.3V source and be bypassed to AGND with 100 pF and 0.1

µF capacitors located close to the power pins.

1, 3, 6, 10, 38,

39 AGND The ground return for the analog supply.

DIGITAL POWER

13 VD

Positive digital supply pin. This pin should be connected to a quiet

+3.3V source and be bypassed to DGND with a 100 pF and 0.1 µF

capacitor located close to the power pin.

14 DGND The ground return for the digital supply.

16, 25, 26, 36 VDR

Positive driver supply pin for the output drivers. This pin should be

connected to a quiet voltage source of +1.8V and be bypassed to

DRGND with 100 pF and 0.1 µF capacitors located close to the

power pins.

15, 35 DRGND

The ground return for the digital output driver supply. These pins

should be connected to the system digital ground. See Section 7.0

(Layout and Grounding) for more details.

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ADC14155QML

Absolute Maximum Ratings

(Note 1, Note 2)

Supply Voltage (VA, VD) −0.3V to 4.2V

Supply Voltage (VDR) −0.3V to 2.35V

|VA–VD|≤ 100 mV

Voltage on Any Input Pin

(Not to exceed 4.2V)

−0.3V to (VA +0.3V)

Voltage on Any Output Pin

(Not to exceed 2.35V)

-0.3V to (VDR +0.2V)

Input Current at Any Pin other

than Supply Pins (Note 3)

±5 mA

Package Input Current (Note 3) ±50 mA

Max Junction Temp (TJ) +150°C

ESD Rating

Human Body Model (Note 5) Class 2 (2500V)

Storage Temperature −65°C to +150°C

Operating Ratings (Note 1, Note 2)

Operating Temperature -55°C ≤ TA ≤ +125°C

Supply Voltage (VA, VD) +3.0V to +3.6V

Output Driver Supply (VDR)+1.6V to +2.0V

CLK −0.05V to (VA + 0.05V)

Clock Duty Cycle 30/70 %

Analog Input Pins 0V to 2.6V

VCM 1.4V to 1.6V

|AGND-DGND| ≤100mV

Package Thermal Resistance

Package θJA (°C/W) θJC (°C/W)

(Heat Sink)

θJ-T (°C/W)

(Top of Package)

48L Cer

Quad

21.8 0.68 1.86

Quality Conformance Inspection

MIL-STD-883, Method 5005 - Group A

Subgroup Description Temp (°C)

1 Static tests at +25

2 Static tests at +125

3 Static tests at -55

4 Dynamic tests at +25

5 Dynamic tests at +125

6 Dynamic tests at -55

7 Functional tests at +25

8A Functional tests at +125

8B Functional tests at -55

9 Switching tests at +25

10 Switching tests at +125

11 Switching tests at -55

12 Setting time at +25

13 Setting time at +125

14 Setting time at -55

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ADC14155QML

ADC14155 Converter Electrical Characteristics

DC Parameters (Note 15)

Unless otherwise specified, the following specifications apply: AGND = DGND = DRGND = 0V, VA = VD = +3.3V, VDR = +1.8V,

Internal VREF = +1.0V, fCLK = 155 MHz, VCM = VRM, CL = 5 pF/pin, Differential Analog Input, Single-Ended Clock Mode, Offset Binary

Format. Typical values are for TA = 25°C. Boldface limits apply for TMIN ≤ TA ≤ TMAX. All other limits apply for TA = 25°C (Note

6, Note 7, Note 8)

Symbol Parameter Conditions Notes Typical

(Note 9)Min Max Units Sub-

groups

STATIC CONVERTER CHARACTERISTICS

Resolution with No Missing

Codes

14 Bits

INL Integral Non Linearity (Note

10)2.3 -5.0 +5.0 LSB 1, 2, 3

DNL Differential Non Linearity ±0.5 -0.9 +1.1 LSB 1, 2, 3

PGE Maximum Positive Gain

Error +0.1 -3.3 +3.5 %FS 1, 2, 3

NGE Maximum Negative Gain

Error +0.3 -3.3 +3.9 %FS 1, 2, 3

TC GE Gain Error Tempco -55°C ≤ TA ≤ +125°C 0.007 Δ%FS/°C

VOFF Offset Error (VIN+ = VIN−) -0.1 +0.7 -0.9 %FS 1, 2, 3

TC VOFF Offset Error Tempco -55°C ≤ TA ≤ +125°C 0.0001 Δ%FS/°C

Under Range Output Code 0 0 0

Over Range Output Code 16383 16383 16383

REFERENCE AND ANALOG INPUT CHARACTERISTICS

VCM

Common Mode Input

Voltage 1.5 V

VRM

Reference Ladder Midpoint

Output Voltage Output load = 1 mA 1.5 V

CIN

VIN Input Capacitance

(each pin to GND)

VIN = 1.5 Vdc ± 0.5 V(CLK LOW) (Note

11)9 pF

VIN = 1.5 Vdc ± 0.5 V(CLK HIGH) (Note

11)6 pF

VREF Reference Voltage (Note

12)1.00 V

Reference Input

Resistance 9 kΩ

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ADC14155QML

ADC14155 Converter Electrical Characteristics (Continued)

DYNAMIC Parameters (Note 15)

Unless otherwise specified, the following specifications apply: AGND = DGND = DRGND = 0V, VA = VD = +3.3V, VDR = +1.8V,

Internal VREF = +1.0V, fCLK = 155 MHz, VCM = VRM, CL = 5 pF/pin, Differential Analog Input, Single-Ended Clock Mode, Offset Binary

Format. Typical values are for TA = 25°C. Boldface limits apply for TMIN ≤ TA ≤ TMAX. All other limits apply for TA = 25°C (Note

6, Note 7, Note 8)

Symbol Parameter Conditions Notes Typical

(Note 9)Min Max Units Sub-

groups

DYNAMIC CONVERTER CHARACTERISTICS, AIN = -1dBFS

FPBW Full Power Bandwidth -1dBFS Input, -3 dB Corner 1.1 GHz

SNR Signal-to-Noise Ratio

fIN = 10 MHz 69 dBFS

fIN = 70 MHz 70.1 66.5 dBFS 4, 5, 6

fIN = 169 MHz 68.5 dBFS

fIN = 238 MHz 68.5 dBFS

fIN = 398 MHz 66.4 dBFS

SFDR Spurious Free Dynamic

Range

fIN = 10 MHz 82 dBFS

fIN = 70 MHz 82.3 68 dBFS 4, 5, 6

fIN = 169 MHz 80.5 dBFS

fIN = 238 MHz 77.3 dBFS

fIN = 398 MHz 63.5 dBFS

ENOB Effective Number of Bits

fIN = 10 MHz 11.3 Bits

fIN = 70 MHz 11.3 10.7 Bits 4, 5, 6

fIN = 169 MHz 11.0 Bits

fIN = 238 MHz 11.0 Bits

fIN = 398 MHz 10.0 Bits

THD Total Harmonic Disortion

fIN = 10 MHz -81 dBFS

fIN = 70 MHz -79.9 -67 dBFS 4, 5, 6

fIN = 169 MHz -82.4 dBFS

fIN = 238 MHz -76.6 dBFS

fIN = 398 MHz -63.2 dBFS

H2 Second Harmonic

Distortion

fIN = 10 MHz -95.4 dBFS

fIN = 70 MHz -88.5 -70 dBFS 4, 5, 6

fIN = 169 MHz -88.3 dBFS

fIN = 238 MHz -77.3 dBFS

fIN = 398 MHz -60.9 dBFS

H3 Third Harmonic Distortion

fIN = 10 MHz -81.6 dBFS

fIN = 70 MHz -82.3 -68 dBFS 4, 5, 6

fIN = 169 MHz -86.4 dBFS

fIN = 238 MHz -89.0 dBFS

fIN = 398 MHz -80.5 dBFS

SINAD Signal-to-Noise and

Distortion Ratio

fIN = 10 MHz 68.2 dBFS

fIN = 70 MHz 69.9 66.2 dBFS 4, 5, 6

fIN = 169 MHz 68.3 dBFS

fIN = 238 MHz 67.8 dBFS

fIN = 398 MHz 61.5 dBFS

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ADC14155QML

DYNAMIC Parameters (Note 15)

Unless otherwise specified, the following specifications apply: AGND = DGND = DRGND = 0V, VA = VD = +3.3V, VDR = +1.8V,

Internal VREF = +1.0V, fCLK = 155 MHz, VCM = VRM, CL = 5 pF/pin, Differential Analog Input, Differential Clock Mode, Offset Binary

Format. Typical values are for TA = 25°C. Boldface limits apply for TMIN ≤ TA ≤ TMAX. All other limits apply for TA = 25°C (Note

6, Note 7, Note 8)

Symbol Parameter Conditions Notes Typical

(Note 9)Min Max Units Sub-

groups

DYNAMIC CONVERTER CHARACTERISTICS, AIN = -1dBFS

SNR Signal-to-Noise Ratio fIN = 70 MHz (Note

16)70.4 66.7 dBFS

fIN = 169 MHz 68.8 dBFS

SFDR Spurious Free Dynamic

Range

fIN = 70 MHz (Note

16)80.3 68.2 dBFS

fIN = 169 MHz 80.3 dBFS

ENOB Effective Number of Bits fIN = 70 MHz (Note

16)11.3 10.5 Bits

fIN = 169 MHz 11.0 Bits

THD Total Harmonic Disortion fIN = 70 MHz (Note

16)-78.4 -65.2 dBFS

fIN = 169 MHz -78.8 dBFS

SINAD Signal-to-Noise and

Distortion Ratio

fIN = 70 MHz (Note

16)69.7 65 dBFS

fIN = 169 MHz 68.3 dBFS

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ADC14155QML

Logic and Power Supply Electrical Characteristics (Note 15)

Unless otherwise specified, the following specifications apply: AGND = DGND = DRGND = 0V, VA = VD = +3.3V, VDR = +1.8V,

Internal VREF = +1.0V, fCLK = 155 MHz, VCM = VRM, CL = 5 pF/pin, Differential Analog Input, Single-Ended Clock Mode, Offset Binary

Format. Typical values are for TA = 25°C. Timing measurements are taken at 50% of the signal amplitude. Boldface limits apply

for TMIN ≤ TA ≤ TMAX. All other limits apply for TA = 25°C (Note 6, Note 7, Note 8)

Symbol Parameter Conditions Notes Typical

(Note 9)Min Max Units Sub-

groups

DIGITAL INPUT CHARACTERISTICS (CLK, PD/DCS, CLK_SEL/DF)

VIN(1) Logical “1” Input Voltage VD = 3.6V (Note

16) 2.0 V

VIN(0) Logical “0” Input Voltage VD = 3.0V 0.8 V (max)

IIN(1) Logical “1” Input Current VIN = 3.3V (Note

14)10 µA

IIN(0) Logical “0” Input Current VIN = 0V (Note

14)-10 µA

CIN Digital Input Capacitance 5 pF

DIGITAL OUTPUT CHARACTERISTICS (D0–D13, DRDY, OVR)

VOH Output Logic High IOUT = −0.5 mA , VDR = 1.8V (Note

16)1.55 1.2 V

VOL Output Logic Low IOUT = 1.6 mA, VDR = 1.8V (Note

16)0.15 0.4 V

+ISC

Output Short Circuit Source

Current VOUT = 0V (Note

14)-10 mA

−ISC

Output Short Circuit Sink

Current VOUT = VDR

(Note

14)10 mA

COUT Digital Output Capacitance 5 pF

POWER SUPPLY CHARACTERISTICS

IAAnalog Supply Current Full Operation 283 350 mA 1, 2, 3

IDDigital Supply Current Full Operation 10 11 mA 1, 2, 3

IDR

Digital Output Supply

Current

Full Operation (Note

13)

15 mA

Power Consumption Excludes IDR 967 1170 mW 1, 2, 3

Power Down Power

Consumption

Clock disabled 5 mW

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ADC14155QML

Timing and AC Characteristics (Note 15)

Unless otherwise specified, the following specifications apply: AGND = DGND = DRGND = 0V, VA = VD = +3.3V, VDR = +1.8V,

Internal VREF = +1.0V, fCLK = 155 MHz, VCM = VRM, CL = 5 pF/pin, Differential Analog Input, Single-Ended Clock Mode, Offset Binary

Format. Typical values are for TA = 25°C. Timing measurements are taken at 50% of the signal amplitude. Boldface limits apply

for TMIN ≤ TA ≤ TMAX. All other limits apply for TA = 25°C (Note 6, Note 7, Note 8)

Symbol Parameter Conditions Notes Typical

(Note 9)Min Max Units Sub-

groups

Maximum Clock Frequency 155 MHz 7, 8A, 8B

Minimum Clock Frequency (Note

14)5 MHz (min)

Clock High Time 3.0 ns

Clock Low Time 3.0 ns

Conversion Latency (Note

17) 8Clock

Cycles

tOD

Output Delay of CLK to

DATA Relative to falling edge of CLK 2.0 ns

tSU Data Output Setup Time Relative to DRDY (Note

16)2.1 1.22 ns

tHData Output Hold Time Relative to DRDY (Note

16)2.1 1.83 ns

tAD Aperture Delay 0.5 ns

tAJ Aperture Jitter 0.08 ps rms

Power Down Recovery

Time

0.1 µF to GND on pins 43, 44; 10

µF and 0.1 µF between pins 43,

44; 0.1 µF and 10 µF to GND on

pins 47, 48

3.0 ms

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ADC14155QML

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is

guaranteed to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics.

The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under

the listed test conditions. Operation of the device beyond the maximum Operating Ratings is not recommended.

Note 2: All voltages are measured with respect to GND = AGND = DGND = DRGND = 0V, unless otherwise specified.

Note 3: When the input voltage at any pin exceeds the power supplies (that is, VIN < AGND, or VIN > VA), the current at that pin should be limited to ±5 mA. The

±50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of ±5 mA to 10.

Note 4: The maximum allowable power dissipation is dictated by TJ,max, the junction-to-ambient thermal resistance, (θJA), and the ambient temperature, (TA), and

can be calculated using the formula PD,max = (TJ,max - TA )/θJA. The values for maximum power dissipation listed above will be reached only when the device is

operated in a severe fault condition (e.g. when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed). Such

conditions should always be avoided.

Note 5: Human Body Model is 100 pF discharged through a 1.5 kΩ resistor.

Note 6: The inputs are protected as shown below. Input voltage magnitudes above VA or below GND will not damage this device, provided current is limited per

(Note 3). However, errors in the A/D conversion can occur if the input goes above 2.6V or below GND as described in the Operating Ratings section.

20210711

Note 7: To guarantee accuracy, it is required that |VA–VD| ≤ 100 mV and separate bypass capacitors are used at each power supply pin.

Note 8: With the test condition for VREF = +1.0V (2VP-P differential input), the 14-bit LSB is 122.1 µV.

Note 9: Typical figures are at TA = 25°C and represent most likely parametric norms at the time of product characterization. The typical specifications are not

guaranteed.

Note 10: Integral Non Linearity is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes through positive and negative

full-scale.

Note 11: The input capacitance is the sum of the package/pin capacitance and the sample and hold circuit capacitance.

Note 12: Optimum performance will be obtained by keeping the reference input in the 0.9V to 1.1V range. The LM4051CIM3-ADJ (SOT-23 package) is

recommended for external reference applications.

Note 13: IDR is the current consumed by the switching of the output drivers and is primarily determined by load capacitance on the output pins, the supply voltage,

VDR, and the rate at which the outputs are switching (which is signal dependent). IDR=VDR(C0 x f0 + C1 x f1 +....C11 x f11) where VDR is the output driver power

supply voltage, Cn is total capacitance on the output pin, and fn is the average frequency at which that pin is toggling.

Note 14: Test at wafer sort only

Note 15: Pre and post irradiation limits are identical to those listed in the Electrical Characteristics tables. Radiation testing is performed per MIL-STD-883, Test

Method 1019.

Note 16: Guaranteed by characterization.

Note 17: Guaranteed by design.

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ADC14155QML

Specification Definitions

APERTURE DELAY is the time after the falling edge of the

clock to when the input signal is acquired or held for conver-

sion.

APERTURE JITTER (APERTURE UNCERTAINTY) is the

variation in aperture delay from sample to sample. Aperture

jitter manifests itself as noise in the output.

CLOCK DUTY CYCLE is the ratio of the time during one cycle

that a repetitive digital waveform is high to the total time of

one period. The specification here refers to the ADC clock

input signal.

COMMON MODE VOLTAGE (VCM) is the common DC volt-

age applied to both input terminals of the ADC.

CONVERSION LATENCY is the number of clock cycles be-

tween initiation of conversion and when that data is presented

to the output driver stage. Data for any given sample is avail-

able at the output pins the Pipeline Delay plus the Output

Delay after the sample is taken. New data is available at every

clock cycle, but the data lags the conversion by the pipeline

delay.

DIFFERENTIAL NON-LINEARITY (DNL) is the measure of

the maximum deviation from the ideal step size of 1 LSB.

EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE

BITS) is another method of specifying Signal-to-Noise and

Distortion Ratio or SINAD. ENOB is defined as (SINAD -

1.76) / 6.02 and says that the converter is equivalent to a

perfect ADC of this (ENOB) number of bits.

FULL POWER BANDWIDTH is a measure of the frequency

at which the reconstructed output fundamental drops 3 dB

below its low frequency value for a full scale input.

GAIN ERROR is the deviation from the ideal slope of the

transfer function. It can be calculated as:

Gain Error = Positive Full Scale Error − Negative Full Scale

Error

It can also be expressed as Positive Gain Error and Negative

Gain Error, which are calculated as:

PGE = Positive Full Scale Error - Offset Error

NGE = Offset Error - Negative Full Scale Error

INTEGRAL NON LINEARITY (INL) is a measure of the de-

viation of each individual code from a line drawn from negative

full scale (½ LSB below the first code transition) through pos-

itive full scale (½ LSB above the last code transition). The

deviation of any given code from this straight line is measured

from the center of that code value.

INTERMODULATION DISTORTION (IMD) is the creation of

additional spectral components as a result of two sinusoidal

frequencies being applied to the ADC input at the same time.

It is defined as the ratio of the power in the intermodulation

products to the total power in the original frequencies. IMD is

usually expressed in dBFS.

LSB (LEAST SIGNIFICANT BIT) is the bit that has the small-

est value or weight of all bits. This value is VFS/2n, where

“VFS” is the full scale input voltage and “n” is the ADC reso-

lution in bits.

MISSING CODES are those output codes that will never ap-

pear at the ADC outputs. The ADC14155QML is guaranteed

not to have any missing codes.

MSB (MOST SIGNIFICANT BIT) is the bit that has the largest

value or weight. Its value is one half of full scale.

NEGATIVE FULL SCALE ERROR is the difference between

the actual first code transition and its ideal value of ½ LSB

above negative full scale.

OFFSET ERROR is the difference between the two input

voltages [(VIN+) – (VIN-)] required to cause a transition from

code 8191 to 8192.

OUTPUT DELAY is the time delay after the falling edge of the

clock before the data update is presented at the output pins.

PIPELINE DELAY (LATENCY) See CONVERSION LATEN-

CY.

POSITIVE FULL SCALE ERROR is the difference between

the actual last code transition and its ideal value of 1½ LSB

below positive full scale.

POWER SUPPLY REJECTION RATIO (PSRR) is a measure

of how well the ADC rejects a change in the power supply

voltage. PSRR is the ratio of the Full-Scale output of the ADC

with the supply at the minimum DC supply limit to the Full-

Scale output of the ADC with the supply at the maximum DC

supply limit, expressed in dB.

SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in

dB, of the rms value of the input signal to the rms value of the

sum of all other spectral components below one-half the sam-

pling frequency, not including harmonics or DC.

SIGNAL TO NOISE PLUS DISTORTION (S/N+D or

SINAD) Is the ratio, expressed in dB, of the rms value of the

input signal to the rms value of all of the other spectral com-

ponents below half the clock frequency, including harmonics

but excluding d.c.

SPURIOUS FREE DYNAMIC RANGE (SFDR) is the differ-

ence, expressed in dB, between the rms values of the input

signal and the peak spurious signal, where a spurious signal

is any signal present in the output spectrum that is not present

at the input.

TOTAL HARMONIC DISTORTION (THD) is the ratio, ex-

pressed in dB, of the rms total of the first nine harmonic levels

at the output to the level of the fundamental at the output. THD

is calculated as

where f1 is the RMS power of the fundamental (output) fre-

quency and f2 through f10 are the RMS power of the first 9

harmonic frequencies in the output spectrum.

SECOND HARMONIC DISTORTION (2ND HARM) is the dif-

ference expressed in dB, between the RMS power in the input

frequency at the output and the power in its 2nd harmonic

level at the output.

THIRD HARMONIC DISTORTION (3RD HARM) is the dif-

ference, expressed in dB, between the RMS power in the

input frequency at the output and the power in its 3rd harmonic

level at the output.

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ADC14155QML

Timing Diagram

20210709

Output Timing

Transfer Characteristic

20210710

FIGURE 1. Transfer Characteristic

13 www.national.com

ADC14155QML

Typical Performance Characteristics, DNL, INL Unless otherwise specified, the following

specifications apply: AGND = DGND = DRGND = 0V, VA = VD = +3.3V, VDR = +1.8V, Internal VREF = +1.0V, fCLK = 155 MHz,

VCM = VRM, CL = 5 pF/pin, Differential Analog Input, Single-Ended Clock Mode, Offset Binary Format. Typical values are for TA =

25°C. Boldface limits apply for TMIN ≤ TA ≤ TMAX. All other limits apply for TA = 25°C (Note 6, Note 7, Note 8)

DNL

20210719

INL

20210720

Typical Performance Characteristics, Dynamic Performance Unless otherwise

specified, the following specifications apply: AGND = DGND = DRGND = 0V, VA = VD = +3.3V, VDR = +1.8V, Internal VREF = +1.0V,

fCLK = 155 MHz, VCM = VRM, CL = 5 pF/pin, Differential Analog Input, Single-Ended Clock Mode, Offset Binary Format. Typical

values are for TA = 25°C. Boldface limits apply for TMIN ≤ TA ≤ TMAX. All other limits apply for TA = 25°C

SFDR vs. fIN

20210721

SNR vs. fIN

20210722

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ADC14155QML

SNR, SINAD, SFDR vs. fIN

20210723

DISTORTION vs. fIN

20210724

SNR, SINAD, SFDR vs. VA

20210725

DISTORTION vs. VA

20210726

15 www.national.com

ADC14155QML

SNR, SINAD, SFDR vs. VDR

20210727

DISTORTION vs. VDR

20210728

SNR, SINAD, SFDR vs. VREF

20210729

DISTORTION vs. VREF

20210730

SNR, SINAD, SFDR vs. Temperature

20210731

DISTORTION vs. Temperature

20210732

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ADC14155QML

Spectral Response @ 70 MHz Input

20210733

Spectral Response @ 169 MHz Input

20210734

Spectral Response @ 238 MHz Input

20210735

17 www.national.com

ADC14155QML

Functional Description

Operating on dual +3.3V and +1.8V supplies, the ADC14155

digitizes a differential analog input signal to 14 bits, using a

differential pipelined architecture with error correction circuitry

and an on-chip sample-and-hold circuit to ensure maximum

performance.

The user has the choice of using an internal 1.0V stable ref-

erence, or using an external reference. The ADC14155 will

accept an external reference between 0.9V and 1.1V (1.0V

recommended) which is buffered on-chip to ease the task of

driving that pin. The +1.8V output driver supply reduces pow-

er consumption and decreases the noise at the output of the

converter.

The quad state function pin CLK_SEL/DF (pin 8) allows the

user to choose between using a single-ended or a differential

clock input and between offset binary or 2's complement out-

put data format. The digital outputs are CMOS compatible

signals that are clocked by a synchronous data ready output

signal (DRDY, pin 34) at the same rate as the clock input. For

the ADC14155 the clock frequency can be between 5 MSPS

and 155 MSPS (typical) with fully specified performance at

155 MSPS. The analog input is acquired at the falling edge of

the clock and the digital data for a given sample is output on

the falling edge of the DRDY signal and is delayed by the

pipeline for 8 clock cycles. The data should be captured on

the rising edge of the DRDY signal.

Power-down is selectable using the PD pin (pin 7). A logic

high on the PD pin disables everything except the voltage

reference circuitry and reduces the converter power con-

sumption to 5 mW with no clock running. For normal opera-

tion, the PD pin should be connected to the analog ground

(AGND). A duty cycle stabilizer maintains performance over

a wide range of clock duty cycles.

Applications Information

1.0 RADIATION ENVIRONMENTS

Careful consideration should be given to environmental con-

ditions when using a product in a radiation environment.

1.1 Total Ionizing Dose

Radiation hardness assured (RHA) products are those part

numbers with a total ionizing dose (TID) level specified in the

Ordering Information table on the front page. Testing and

qualification of these products is done on a wafer level ac-

cording to MIL-STD-883, Test Method 1019. Wafer level TID

data is available with lot shipments.

1.2 Single Event Effects

One time single event latch-up testing (SEL) was preformed

according to EIA/JEDEC Standard, EIA/JEDEC57. The linear

energy transfer threshold (LETth) shown in the Key Specifi-

cations table on the front page is the maximum LET tested. A

test report is available upon request.

2.0 OPERATING CONDITIONS

We recommend that the following conditions be observed for

operation of the ADC14155:

3.0V ≤ VA ≤ 3.6V

VD = VA

VDR = 1.8V

5 MHz ≤ fCLK ≤ 155 MHz

1.0V internal reference

0.9V ≤ VREF ≤ 1.1V (for an external reference)

VCM = 1.5V (from VRM)

3.0 ANALOG INPUTS

3.1 Signal Inputs

3.1.1 Differential Analog Input Pins

The ADC14155 has one pair of analog signal input pins, VIN

+ and VIN−, which form a differential input pair. The input sig-

nal, VIN, is defined as

VIN = (VIN+) – (VIN−)

Figure 2 shows the expected input signal range. Note that the

common mode input voltage, VCM, should be 1.5V. Using

VRM (pin 46 or 47) for VCM will ensure the proper input com-

mon mode level for the analog input signal. The peaks of the

individual input signals should each never exceed 2.6V. Each

analog input pin of the differential pair should have a peak-to-

peak voltage equal to the reference voltage, VREF, be 180°

out of phase with each other and be centered around

VCM.The peak-to-peak voltage swing at each analog input pin

should not exceed the value of the reference voltage or the

output data will be clipped.

20210715

FIGURE 2. Expected Input Signal Range

For single frequency sine waves the full scale error in LSB

can be described as approximately

EFS = 16384 ( 1 - sin (90° + dev))

Where dev is the angular difference in degrees between the

two signals having a 180° relative phase relationship to each

other (see Figure 3). For single frequency inputs, angular er-

rors result in a reduction of the effective full scale input. For

complex waveforms, however, angular errors will result in

distortion.

www.national.com 18

ADC14155QML

20210716

FIGURE 3. Angular Errors Between the Two Input Signals

Will Reduce the Output Level or Cause Distortion

It is recommended to drive the analog inputs with a source

impedance less than 100Ω. Matching the source impedance

for the differential inputs will improve even ordered harmonic

performance (particularly second harmonic).

Table 1 indicates the input to output relationship of the

ADC14155.

TABLE 1. Input to Output Relationship

VIN+VIN−Binary Output 2’s Complement Output

VCM − VREF/2 VCM + VREF/2 00 0000 0000 0000 10 0000 0000 0000 Negative Full-Scale

VCM − VREF/4 VCM + VREF/4 01 0000 0000 0000 11 0000 0000 0000

VCM VCM 10 0000 0000 0000 00 0000 0000 0000 Mid-Scale

VCM + VREF/4 VCM − VREF/4 11 0000 0000 0000 01 0000 0000 0000

VCM + VREF/2 VCM − VREF/2 11 1111 1111 1111 01 1111 1111 1111 Positive Full-Scale

3.1.2 Driving the Analog Inputs

The VIN+ and the VIN− inputs of the ADC14155 have an in-

ternal sample-and-hold circuit which consists of an analog

switch followed by a switched-capacitor amplifier. The analog

inputs are connected to the sampling capacitors through

NMOS switches, and each analog input has parasitic capac-

itances associated with it.

When the clock is high, the converter is in the sample phase.

The analog inputs are connected to the sampling capacitor

through the NMOS switches, which causes the capacitance

at the analog input pins to appear as the pin capacitance plus

the internal sample and hold circuit capacitance (approxi-

mately 9 pF). While the clock level remains high, the sampling

capacitor will track the changing analog input voltage. When

the clock transitions from high to low, the converter enters the

hold phase, during which the analog inputs are disconnected

from the sampling capacitor. The last voltage that appeared

at the analog input before the clock transition will be held on

the sampling capacitor and will be sent to the ADC core. The

capacitance seen at the analog input during the hold phase

appears as the sum of the pin capacitance and the parasitic

capacitances associated with the sample and hold circuit of

each analog input (approximately 6 pF). Once the clock signal

transitions from low to high, the analog inputs will be recon-

nected to the sampling capacitor to capture the next sample.

Usually, there will be a difference between the held voltage

on the sampling capacitor and the new voltage at the analog

input. This will cause a charging glitch that is proportional to

the voltage difference between the two samples to appear at

the analog input pin. The input circuitry must be fast enough

to allow the sampling capacitor to fully charge before the clock

signal goes high again, as incomplete settling can degrade

the SFDR performance.

A single-ended to differential conversion circuit is shown in

Figure 4. A transformer is preferred for high frequency input

signals. Terminating the transformer on the secondary side

provides two advantages. First, it presents a real broadband

impedance to the ADC inputs and second, it provides a com-

mon path for the charging glitches from each side of the

differential sample-and-hold circuit.

One short-coming of using a transformer to achieve the sin-

gle-ended to differential conversion is that most RF trans-

formers have poor low frequency performance. A differential

amplifier can be used to drive the analog inputs for low fre-

quency applications. The amplifier must be fast enough to

settle from the charging glitches on the analog input resulting

from the sample-and-hold operation before the clock goes

high and the sample is passed to the ADC core.

The SFDR performance of the converter depends on the ex-

ternal signal conditioning circuity used, as this affects how

quickly the sample-and-hold charging glitch will settle. An ex-

ternal resistor and capacitor network as shown in Figure 4

should be used to isolate the charging glitches at the ADC

input from the external driving circuit and to filter the wideband

noise at the converter input. These components should be

placed close to the ADC inputs because the analog input of

the ADC is the most sensitive part of the system, and this is

the last opportunity to filter that input. For Nyquist applications

the RC pole should be at the ADC sample rate. The ADC input

capacitance in the sample mode should be considered when

setting the RC pole. For wideband undersampling applica-

tions, the RC pole should be set at about 1.5 to 2 times the

maximum input frequency to maintain a linear delay re-

sponse.

3.1.3 Input Common Mode Voltage

The input common mode voltage, VCM, should be in the range

of 1.4V to 1.6V and be a value such that the peak excursions

of the analog signal do not go more negative than ground or

more positive than 2.6V. It is recommended to use VRM (pin

46 or 47) as the input common mode voltage.

3.2 Reference Pins

The ADC14155 is designed to operate with an internal 1.0V

reference, or an external 1.0V reference, but performs well

with external reference voltages in the range of 0.9V to 1.1V.

The internal 1.0 Volt reference is the default condition when

no external reference input is applied to the VREF pin. If a volt-

age in the range of 0.9V to 1.1V is applied to the VREF pin,

then that voltage is used for the reference. The VREF pin

should always be bypassed to ground with a 0.1 µF capacitor

close to the reference input pin. Lower reference voltages will

decrease the signal-to-noise ratio (SNR) of the ADC14155.

Increasing the reference voltage (and the input signal swing)

beyond 1.1V may degrade THD for a full-scale input, espe-

cially at higher input frequencies.

It is important that all grounds associated with the reference

voltage and the analog input signal make connection to the

19 www.national.com

ADC14155QML

ground plane at a single, quiet point to minimize the effects of

noise currents in the ground path.

The Reference Bypass Pins (VRP, VRM, and VRN) are made

available for bypass purposes. All these pins should each be

bypassed to ground with a 0.1 µF capacitor. A 0.1 µF and a

10 µF capacitor should be placed between the VRP and VRN

pins, as shown in Figure 4. This configuration is necessary to

avoid reference oscillation, which could result in reduced SF-

DR and/or SNR. VRM may be loaded to 1mA for use as a

temperature stable 1.5V reference. The remaining pins

should not be loaded.

Smaller capacitor values than those specified will allow faster

recovery from the power down mode, but may result in de-

graded noise performance. Loading any of these pins, other

than VRM, may result in performance degradation.

The nominal voltages for the reference bypass pins are as

follows:

VRM = 1.5 V

VRP = VRM + VREF / 2

VRN = VRM − VREF / 2

4.0 DIGITAL INPUTS

Digital CMOS compatible inputs consist of CLK+, CLK−, PD

and CLK_SEL/DF.

4.1 Clock Inputs

The CLK+ and CLK− signals control the timing of the sampling

process. The CLK_SEL/DF pin (pin 8) allows the user to con-

figure the ADC for either differential or single-ended clock

mode (see Section 3.3). In differential clock mode, the two

clock signals should be exactly 180° out of phase from each

other and of the same amplitude. In the single-ended clock

mode, the clock signal should be routed to the CLK+ input and

the CLK− input should be tied to AGND in combination with

the correct setting from Table 3.

To achieve the optimum noise performance, the clock inputs

should be driven with a stable, low jitter clock signal in the

range indicated in the Electrical Table. The clock input signal

should also have a short transition region. This can be

achieved by passing a low-jitter sinusoidal clock source

through a high speed buffer gate. This configuration is shown

in Figure 4. The trace carrying the clock signal should be as

short as possible and should not cross any other signal line,

analog or digital, not even at 90°. Figure 4 shows the recom-

mended clock input circuit.

The clock signal also drives an internal state machine. If the

clock is interrupted, or its frequency is too low, the charge on

the internal capacitors can dissipate to the point where the

accuracy of the output data will degrade. This is what limits

the minimum sample rate.

The clock line should be terminated at its source in the char-

acteristic impedance of that line. Take care to maintain a

constant clock line impedance throughout the length of the

line. Refer to Application Note AN-905 for information on set-

ting characteristic impedance.

It is highly desirable that the the source driving the ADC clock

pins only drive that pin. However, if that source is used to drive

other devices, then each driven pin should be AC terminated

with a series RC to ground, such that the resistor value is

equal to the characteristic impedance of the clock line and the

capacitor value is

where tPD is the signal propagation rate down the clock line,

"L" is the line length and ZO is the characteristic impedance

of the clock line. This termination should be as close as pos-

sible to the ADC clock pin but beyond it as seen from the clock

source. Typical tPD is about 150 ps/inch (60 ps/cm) on FR-4

board material. The units of "L" and tPD should be the same

(inches or centimeters).

The duty cycle of the clock signal can affect the performance

of the A/D Converter. Because achieving a precise duty cycle

is difficult, the ADC14155 has a Duty Cycle Stabilizer. It is

designed to maintain performance over a clock duty cycle

range of 30% to 70%.

4.2 Power-Down (PD)

Power-down can be enabled through this two-state input pin.

Table 2 shows how to power-down the ADC14155.

TABLE 2. Power Down Selection Table

PD Input Voltage Power State

VAPower-down

AGND On

The power-down mode allows the user to conserve power

when the converter is not being used. In the power-down state

all bias currents of the analog circuitry, excluding the refer-

ence are shut down which reduces the power consumption to

5 mW with no clock running. The output data pins are unde-

fined and the data in the pipeline is corrupted while in the

power-down mode.

The Power-down Mode Exit Cycle time is determined by the

value of the capacitors on the VRP (pin 42, 43), VRM (pin 46,

47) and VRN (pin 44, 45) reference bypass pins (pins 43, 44

and 45) and is about 3 ms with the recommended component

values. These capacitors lose their charge in the power-down

mode and must be recharged by on-chip circuitry before con-

versions can be accurate. Smaller capacitor values allow

slightly faster recovery from the power down mode, but can

result in a reduction in SNR, SINAD and ENOB performance.

4.3 Clock Mode Select/Data Format (CLK_SEL/DF)

Single-ended versus differential clock mode and output data

format are selectable using this quad-state function pin. Table

3 shows how to select between the clock modes and the out-

put data formats.

TABLE 3. Clock Mode and Data Format Selection Table

CLK_SEL/DF

Input Voltage Clock Mode Output Data

Format

VADifferential 2's Complement

(2/3) * VADifferential Offset Binary

(1/3) * VASingle-Ended 2's Complement

AGND Single-Ended Offset Binary

5.0 DIGITAL OUTPUTS

Digital outputs consist of the 1.8V CMOS signals D0-D13,

DRDY and OVR.

The ADC14155 has 16 CMOS compatible data output pins:

14 data output bits corresponding to the converted input val-

ue, a data ready (DRDY) signal that should be used to capture

the output data and an over-range indicator (OVR) which is

set high when the sample amplitude exceeds the 14-bit con-

version range. Valid data is present at these outputs while the

PD pin is low.

www.national.com 20

ADC14155QML

Data should be captured and latched with the rising edge of

the DRDY signal. Depending on the setup and hold time re-

quirements of the receiving circuit (ASIC), either the rising

edge or the falling edge of the DRDY signal can be used to

latch the data. Generally, rising-edge capture would maxi-

mize setup time with minimal hold time; while falling-edge-

capture would maximize hold time with minimal setup time.

However, actual timing for the falling-edge case depends

greatly on the CLK frequency and both cases also depend on

the delays inside the ASIC. Refer to the AC Electrical Char-

acterisitics table.

Be very careful when driving a high capacitance bus. The

more capacitance the output drivers must charge for each

conversion, the more instantaneous digital current flows

through VDR and DRGND. These large charging current

spikes can cause on-chip ground noise and couple into the

analog circuitry, degrading dynamic performance. Adequate

bypassing, limiting output capacitance and careful attention

to the ground plane will reduce this problem. Additionally, bus

capacitance beyond the specified 5 pF/pin will cause tOD to

increase, reducing the setup and hold time of the ADC output

data. The result could be an apparent reduction in dynamic

performance.

To minimize noise due to output switching, the load currents

at the digital outputs should be minimized. This can be done

by using a programmable logic device (PLD) such as the

LC4032V-25TN48C to level translate the ADC output data

from 1.8V to 3.3V for use by any other circuitry. Only one load

should be connected to each output pin. Additionally, insert-

ing series resistors of about 22Ω at the digital outputs, close

to the ADC pins, will isolate the outputs from trace and other

circuit capacitances and limit the output currents, which could

otherwise result in performance degradation. See Figure 4.

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ADC14155QML

20210736

FIGURE 4. Application Circuit using Transformer Drive Circuit

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ADC14155QML

6.0 POWER SUPPLY CONSIDERATIONS

The power supply pins should be bypassed with a 0.1 µF ca-

pacitor and with a 100 pF ceramic chip capacitor close to each

power pin. Leadless chip capacitors are preferred because

they have low series inductance.

As is the case with all high-speed converters, the ADC14155

is sensitive to power supply noise. Accordingly, the noise on

the analog supply pin should be kept below 100 mVP-P.

No pin should ever have a voltage on it that is in excess of the

supply voltages, not even on a transient basis. Be especially

careful of this during power turn on and turn off.

The VDR pin provides power for the output drivers and may be

operated from a supply in the range of 1.6V to 2.0V. This en-

ables lower power operation, reduces the noise coupling

effects from the digital outputs to the analog circuitry and sim-

plifies interfacing to lower voltage devices and systems. Note,

however, that tOD increases with reduced VDR. A level trans-

lator may be required to interface the digital output signals of

the ADC14155 to non-1.8V CMOS devices.

Care should be taken to avoid extremely rapid power supply

ramp up rate. Excessive power supply ramp up rate may

damage the device.

7.0 LAYOUT AND GROUNDING

For best dynamic performance, the center die attach pad of

the device should be connected to ground with low inductive

path.

Proper grounding and proper routing of all signals are essen-

tial to ensure accurate conversion. Maintaining separate ana-

log and digital areas of the board, with the ADC14155

between these areas, is required to achieve specified perfor-

mance.

The ground return for the data outputs (DRGND) carries the

ground current for the output drivers. The output current can

exhibit high transients that could add noise to the conversion

process. To prevent this from happening, it is recommended

to use a single common ground plane with managed return

current paths instead of a split ground plane. The key is to

make sure that the supply current in the ground plane does

not return under a sensitive node (e.g., caps to ground in the

analog input network). This is done by routing a trace from the

ADC to the regulator / bulk capacitor for the supply so that it

does not run under a critical node.

Capacitive coupling between the typically noisy digital circuit-

ry and the sensitive analog circuitry can lead to poor perfor-

mance. The solution is to keep the analog circuitry separated

from the digital circuitry, and to keep the clock line as short as

possible.

The effects of the noise generated from the ADC output

switching can be minimized through the use of 22Ω resistors

in series with each data output line. Locate these resistors as

close to the ADC output pins as possible.

Since digital switching transients are composed largely of

high frequency components, total ground plane copper

weight will have little effect upon the logic-generated noise.

This is because of the skin effect. Total surface area is more

important than is total ground plane area.

Generally, analog and digital lines should cross each other at

90° to avoid crosstalk. To maximize accuracy in high speed,

high resolution systems, however, avoid crossing analog and

digital lines altogether. It is important to keep clock lines as

short as possible and isolated from ALL other lines, including

other digital lines. Even the generally accepted 90° crossing

should be avoided with the clock line as even a little coupling

can cause problems at high frequencies. This is because oth-

er lines can introduce jitter into the clock line, which can lead

to degradation of SNR. Also, the high speed clock can intro-

duce noise into the analog chain.

Best performance at high frequencies and at high resolution

is obtained with a straight signal path. That is, the signal path

through all components should form a straight line wherever

possible.

Be especially careful with the layout of inductors and trans-

formers. Mutual inductance can change the characteristics of

the circuit in which they are used. Inductors and transformers

should not be placed side by side, even with just a small part

of their bodies beside each other. For instance, place trans-

formers for the analog input and the clock input at 90° to one

another to avoid magnetic coupling.

The analog input should be isolated from noisy signal traces

to avoid coupling of spurious signals into the input. Any ex-

ternal component (e.g., a filter capacitor) connected between

the converter's input pins and ground or to the reference input

pin and ground should be connected to a very clean point in

the ground plane.

All analog circuitry (input amplifiers, filters, reference compo-

nents, etc.) should be placed in the analog area of the board.

All digital circuitry and dynamic I/O lines should be placed in

the digital area of the board. The ADC14155 should be be-

tween these two areas. Furthermore, all components in the

reference circuitry and the input signal chain that are con-

nected to ground should be connected together with short

traces and enter the ground plane at a single, quiet point. All

ground connections should have a low inductance path to

ground.

8.0 DYNAMIC PERFORMANCE

To achieve the best dynamic performance, the clock source

driving the CLK input must have a sharp transition region and

be free of jitter. Isolate the ADC clock from any digital circuitry

with buffers, as with the clock tree shown in Figure 5 . The

gates used in the clock tree must be capable of operating at

frequencies much higher than those used if added jitter is to

be prevented. Best performance will be obtained with a dif-

ferential clock input drive, compared with a single-ended

drive.

As mentioned in Section 6.0, it is good practice to keep the

ADC clock line as short as possible and to keep it well away

from any other signals. Other signals can introduce jitter into

the clock signal, which can lead to reduced SNR perfor-

mance, and the clock can introduce noise into other lines.

Even lines with 90° crossings have capacitive coupling, so try

to avoid even these 90° crossings of the clock line.

20210717

FIGURE 5. Isolating the ADC Clock from other Circuitry

with a Clock Tree

23 www.national.com

ADC14155QML

Revision History

Date Released Revision Section Changes

11/12/08 A Initial Release Initial Release

05/22/09 B Electrical Dynamic Parameters Corrected Parameter SFDR limit moved to Min.

column. Revision A will be Archived.

10/01/09 C Electrical Section Dynamic Parameters, Logic and

power Supply, Timing and AC Characteristics, Note

Section

Added New Dynamic Parameters Section.

Changed from VOUT(1), VOUT(0) to VOH, VOL,

Added Notes 16 and 17. Revision B will be

Archived

11/12/09 D Pin Description Table and Section 7.0 Edits to Digital Power Pin #: 15, 35 description

and Section 7.0 third paragraph. Revision C will

be Archived.

01/07/2010 E Electrical DC Parameters Static Converter

Characteristics

Typical limits changed for Gain Error Tempco

from +8.0 to 4000 and Offset Error Tempco from

+0.5 to 900. Revision D will be Archived.

06/15/2010 F Electrical DC Parameters Static Converter

Characteristics

Typical limits changed for Gain Error Tempco

from 4000 to 0.007 and Offset Error Tempco

from 900 to 0.0001. Revision E will be Archived.

07/16/2010 G Modifications to data sheet removing the reference

to Single End Input test. General Description,

Heading Electrical section, Typical Performance

Characteristics DNL, INL and Dynamic

Performance, Para. 3.0 Analog Inputs

Change to General Description fourth

paragraph Pg 6-10: Under Headings in

Electrical section Added Differential Input Mode

Pg 14: Under Headings Added Differential Input

Mode Pg 18: Update to Figure 2 plot. Revision

F will be Archived.

www.national.com 24

ADC14155QML

Physical Dimensions inches (millimeters) unless otherwise noted

48-Lead Cer Quad Package

NS Package Number EL48A

25 www.national.com

ADC14155QML

Notes

ADC14155QML 14-Bit, 155 MSPS, 1.1 GHz Bandwidth A/D Converter

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