X9279 (R) Single Supply/Low Power/256-Tap/2-Wire Bus Data Sheet September 23, 2009 FN8175.4 Single Digitally-Controlled (XDCPTM) Potentiometer Features The X9279 integrates a single digitally controlled potentiometer (XDCP) on a monolithic CMOS integrated circuit. * 2-Wire Serial Interface for Write, Read, and Transfer Operations of the Potentiometer * 256 Resistor Taps The digital controlled potentiometer is implemented using 255 resistive elements in a series array. Between each element are tap points connected to the wiper terminal through switches. The position of the wiper on the array is controlled by the user through the 2-Wire bus interface. The potentiometer has associated with it a volatile Wiper Counter Register (WCR) and a four non-volatile Data Registers that can be directly written to and read by the user. The contents of the WCR controls the position of the wiper on the resistor array though the switches. Power-up recalls the contents of the default data register (DR0) to the WCR. The XDCP can be used as a three-terminal potentiometer or as a two terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing. * Wiper Resistance, 100 Typical @ 5V * 16 Non-volatile Data Registers for Each Potentiometer * Non-volatile Storage of Multiple Wiper Positions * Power-on Recall. Loads Saved Wiper Position on Power-up. * Standby Current < 5A Max * VCC: 2.7V to 5.5V Operation * 50k, 100k Versions of End-to-End Resistance * Endurance: 100,000 Data Changes per Bit per Register * 100 yr. Data Retention * 14 Ld TSSOP * Low Power CMOS * Pb-Free Available (RoHS Compliant) Functional Diagram VCC 2-WIRE BUS INTERFACE ADDRESS DATA STATUS BUS INTERFACE AND CONTROL RH WRITE READ TRANSFER INC/DEC 1 WIPER WIPER COUNTER REGISTER (WCR) CONTROL VSS 50k and 100k 256-TAPS POWER-ON RECALL POT DATA REGISTERS 16 BYTES RW RL CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005, 2009. All Rights Reserved All other trademarks mentioned are the property of their respective owners. X9279 Ordering Information PART NUMBER PART MARKING VCC LIMITS (V) POTENTIOMETER ORGANIZATION (k) TEMP RANGE (C) 5 10% 100 0 to +70 14 Ld TSSOP (4.4mm) M14.173 PACKAGE PKG. DWG. # X9279TV14* (Note 2) X9279 TV X9279TV14Z* (Note 1) X9279 TVZ 0 to +70 14 Ld TSSOP (4.4mm) (Pb-free) M14.173 X9279TV14I* (Note 2) X9279 TVI -40 to +85 14 Ld TSSOP (4.4mm) M14.173 X9279TV14IZ* (Note 1) X9279 TVZI -40 to +85 14 Ld TSSOP (4.4mm) (Pb-free) M14.173 X9279UV14* (Note 2) X9279 UV 0 to +70 14 Ld TSSOP (4.4mm) M14.173 X9279UV14Z* (Note 1) X9279 UVZ 0 to +70 14 Ld TSSOP (4.4mm) (Pb-free) M14.173 X9279UV14I* (Note 2) X9279 UVI -40 to +85 14 Ld TSSOP (4.4mm) M14.173 X9279UV14IZ* (Note 1) X9279 UVZI -40 to +85 14 Ld TSSOP (4.4mm) (Pb-free) M14.173 X9279TV14-2.7* (Note 2) X9279 TVF 0 to +70 14 Ld TSSOP (4.4mm) M14.173 X9279TV14Z-2.7* (Note 1) X9279 TVZF 0 to +70 14 Ld TSSOP (4.4mm) (Pb-free) M14.173 X9279TV14I-2.7* (Note 2) X9279 TVG -40 to +85 14 Ld TSSOP (4.4mm) M14.173 X9279TV14IZ-2.7* (Note 1) X9279 TVZG -40 to +85 14 Ld TSSOP (4.4mm) (Pb-free) M14.173 X9279UV14-2.7* (Note 2) X9279 UVF 0 to +70 14 Ld TSSOP (4.4mm) M14.173 X9279UV14Z-2.7* (Note 1) X9279 UVZF 0 to +70 14 Ld TSSOP (4.4mm) (Pb-free) M14.173 X9279UV14I-2.7* (Note 2) X9279 UVG -40 to +85 14 Ld TSSOP (4.4mm) M14.173 X9279UV14IZ-2.7* (Note 1) X9279 UVZG -40 to +85 14 Ld TSSOP (4.4mm) (Pb-free) M14.173 50 2.7 to 5.5 100 50 *Add "-T" suffix for tape and reel. Please refer to TB347 for details on reel specifications. NOTES: 1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 2. Not recommended for new designs. 2 FN8175.4 September 23, 2009 X9279 Detailed Functional Diagram VCC BANK 0 POWER-ON RECALL DR0 DR1 SCL DR2 DR3 INTERFACE AND CONTROL CIRCUITRY SDA A3 A2 A1 A0 RH WIPER 50k and 100k 256-TAPS COUNTER REGISTER (WCR) RL RW D ATA WP BANK 1 BANK 2 BANK 3 DR0 DR1 DR0 DR1 DR0 DR1 DR2 DR3 DR2 DR3 DR2 DR3 CONTROL 12 ADDITIONAL NON-VOLATILE REGISTERS 3 BANKS OF 4 REGISTERS x 8-BITS VSS Circuit Level Applications System Level Applications * Vary the gain of a voltage amplifier * Adjust the contrast in LCD displays * Provide programmable DC reference voltages for comparators and detectors * Control the power level of LED transmitters in communication systems * Control the volume in audio circuits * Set and regulate the DC biasing point in an RF power amplifier in wireless systems * Trim out the offset voltage error in a voltage amplifier circuit * Set the output voltage of a voltage regulator * Trim the resistance in Wheatstone bridge circuits * Control the gain, characteristic frequency and Q-factor in filter circuits * Set the scale factor and zero point in sensor signal conditioning circuits * Control the gain in audio and home entertainment systems * Provide the variable DC bias for tuners in RF wireless systems * Set the operating points in temperature control systems * Control the operating point for sensors in industrial systems * Trim offset and gain errors in artificial intelligent systems * Vary the frequency and duty cycle of timer ICs * Vary the DC biasing of a pin diode attenuator in RF circuits * Provide a control variable (I, V, or R) in feedback circuits 3 FN8175.4 September 23, 2009 X9279 Pinout connected to ground for proper operation. A match in the slave address serial data stream must be made with the Address input in order to initiate communication with the X9279. A maximum of 8 devices may occupy the 2-Wire serial bus. X9279 (14 LD TSSOP) TOP VIEW NC 1 14 VCC A0 2 13 RL NC 3 12 RH A2 4 11 RW SCL 5 10 A3 SDA VSS 6 9 A1 7 8 WP Potentiometer Pins RH, RL The RH and RL pins are equivalent to the terminal connections on a mechanical potentiometer. RW The wiper pin is equivalent to the wiper terminal of a mechanical potentiometer. Pin Functions Bias Supply Pins PIN TSSOP SYMBOL 1 NC No Connect 2 A0 Device Address for 2-Wire bus 3 NC No Connect FUNCTION Device Address for 2-Wire bus SYSTEM SUPPLY VOLTAGE (VCC) AND SUPPLY GROUND (VSS) The VCC pin is the system supply voltage. The VSS pin is the system ground. 4 A2 5 SCL Serial Clock for 2-Wire bus 6 SDA Serial Data Input/Output for 2-Wire bus NO CONNECT No connect pins should be left open. This pins are used for Intersil manufacturing and testing purposes. 7 VSS System Ground 8 WP Hardware Write Protect 9 A1 Device Address for 2-Wire bus 10 A3 Device Address for 2 wire-bus. Must be connected to Ground 11 RW Wiper Terminal of the Potentiometer 12 RH High Terminal of the Potentiometer 13 RL Low Terminal of the Potentiometer 14 VCC Other Pins HARDWARE WRITE PROTECT INPUT (WP) The WP pin when LOW prevents non-volatile writes to the Data Registers. Principles Of Operation Bus Interface Pins The X9279 is a integrated microcircuit incorporating a resistor array and associated registers and counter and the serial interface logic providing direct communication between the host and the digitally controlled potentiometers. This section provides detail description of the following: SERIAL DATA INPUT/OUTPUT (SDA) * Resistor Array Description The SDA is a bidirectional serial data input/output pin for a 2-Wire slave device and is used to transfer data into and out of the device. It receives device address, opcode, wiper register address and data sent from an 2-Wire master at the rising edge of the serial clock SCL, and it shifts out data after each falling edge of the serial clock SCL. * Serial Interface Description System Supply Voltage Pin Descriptions It is an open drain output and may be wire-ORed with any number of open drain or open collector outputs. An open drain output requires the use of a pull-up resistor. For selecting typical values, refer to the guidelines for calculating typical values on the bus pull-up resistors graph. SERIAL CLOCK (SCL) This input is used by 2-Wire master to supply 2-Wire serial clock to the X9279. * Instruction and Register Description Array Description The X9279 is comprised of a resistor array (see Figure 1). The array contains, in effect, 255 discrete resistive segments that are connected in series. The physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (RH and RL inputs). At both ends of each array and between each resistor segment is a CMOS switch connected to the wiper (RW) output. Within each individual array only one switch may be turned on at a time. DEVICE ADDRESS (A3 - A0) These switches are controlled by a Wiper Counter Register (WCR). The 8-bits of the WCR (WCR[7:0]) are decoded to select, and enable, one of 256 switches (see Table 1). The Address inputs A2 - A0 are used to set the least significant 3 bits of the 8-bit slave address, address pin A3 must be The WCR may be written directly. These Data Registers can the WCR can be read and written by the host system. 4 FN8175.4 September 23, 2009 X9279 SERIAL BUS INPUT SERIAL DATA PATH FROM INTERFACE CIRCUITRY REGISTER 0 (DR0) REGISTER 1 (DR1) 8 8 PARALLEL BUS INPUT BANK_0 Only REGISTER 2 (DR2) REGISTER 3 (DR3) WIPER COUNTER REGISTER (WCR) INC/DEC LOGIC IF WCR = 00[H] THEN RW = RL UP/DN IF WCR = FF[H] THEN RW = RH MODIFIED SCK RH C O U N T E R D E C O D E R UP/DN CLK RL RW FIGURE 1. DETAILED POTENTIOMETER BLOCK DIAGRAM Power-up and Down Recommendations. There are no restrictions on the power-up or power-down conditions of VCC and the voltages applied to the potentiometer pins provided that VCC is always more positive than or equal to VH, VL, and VW, i.e., VCC VH, VL, VW. The VCC ramp rate specification is always in effect. Serial Interface Description Serial Interface The X9279 supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master will always initiate data transfers and provide the clock for both transmit and receive operations. Therefore, the X9279 will be considered a slave device in all applications. Clock and Data Conventions Data states on the SDA line can change only during SCL LOW periods. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions (see Figure 2. 5 Start Condition All commands to the X9279 are preceded by the start condition, which is a HIGH to LOW transition of SDA while SCL is HIGH. The X9279 continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition is met (see Figure 2). Stop Condition All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA while SCL is HIGH (see Figure 2). Acknowledge Acknowledge is a software convention used to provide a positive handshake between the master and slave devices on the bus to indicate the successful receipt of data. The transmitting device, either the master or the slave, will release the SDA bus after transmitting eight bits. The master generates a ninth clock cycle and during this period the receiver pulls the SDA line LOW to acknowledge that it successfully received the eight bits of data. The X9279 will respond with an acknowledge after recognition of a start condition and its slave address and once again after successful receipt of the command byte. If the command is followed by a data byte the X9279 will respond with a final acknowledge (see Figure 2). FN8175.4 September 23, 2009 X9279 SCL FROM MASTER 1 8 9 DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER START ACKNOWLEDGE FIGURE 2. ACKNOWLEGE RESPONSE FROM RECEIVER Instruction and Register Description Acknowledge Polling The disabling of the inputs, during the internal non-volatile write operation, can be used to take advantage of the typical 5ms EEPROM write cycle time. Once the stop condition is issued to indicate the end of the non-volatile write command the X9279 initiates the internal write cycle. ACK Polling Sequence, Flow 1, can be initiated immediately. This involves issuing the start condition followed by the device slave address. If the X9279 is still busy with the write operation no ACK will be returned. If the X9279 has completed the write operation an ACK will be returned and the master can then proceed with the next operation. Flow 1: ACK Polling Sequence Non-volatile Write Command Completed EnterACK Polling Issue START Issue Slave Address ACK Returned? Issue STOP The first byte sent to the X9279 from the host, following a CS going HIGH to LOW, is called the Identification byte. The most significant four bits of the slave address are a device type identifier. The ID[3:0] bits is the device ID for the X9279; this is fixed as 0101[B] (refer to Table 3). The A[2:0] bits in the ID byte is the internal slave address. The physical device address is defined by the state of the A2 - A0 input pins. The slave address is externally specified by the user. The X9279 compares the serial data stream with the address input state; a successful compare of both address bits is required for the X9279 to successfully continue the command sequence. Only the device which slave address matches the incoming device address sent by the master executes the instruction. The A2 - A0 inputs can be actively driven by CMOS input signals or tied to VCC or VSS. Instruction Byte (I) The next byte sent to the X9279 contains the instruction and register pointer information. The three most significant bits are used provide the instruction opcode I [2:0]. The RB and RA bits point to one of the four Data Registers. P0 is the POT selection; since the X9279 is single POT, the P0 = 0. The format is shown in Table 4. No Yes Further Operation? Device Addressing: Identification Byte (ID and A) No Register Bank Selection (RB, RA, P1, P0) Yes Issue Instruction Issue STOP Proceed Proceed There are 16 registers organized into four banks. Bank 0 is the default bank of registers. Only Bank 0 registers can be used for Data Register to Wiper Counter Register operations. Banks 1, 2, and 3 are additional banks of registers (12 total) that can be used for 2-Wire write and read operations. The Data Registers in Banks 1, 2, and 3 cannot be used for direct read/write operations between the Wiper Counter Register. 6 FN8175.4 September 23, 2009 X9279 TABLE 1. REGISTER SELECTION (R0 TO R3) RB RA REGISTER SELECTION 0 0 0 0 1 1 1 TABLE 2. REGISTER BANK SELECTION (BANK 0 TO BANK 3) P1 P0 BANK SELECTION Data Register Read and Write; Wiper Counter Register Operations 0 0 0 Data Register Read and Write; Wiper Counter Register Operations 1 Data Register Read and Write; Wiper Counter Register Operations 0 1 1 Data Register Read and Write Only 1 0 2 Data Register Read and Write Only 0 2 Data Register Read and Write; Wiper Counter Register Operations 1 1 3 Data Register Read and Write Only 1 3 Data Register Read and Write; Wiper Counter Register Operations OPERATIONS OPERATIONS TABLE 3. IDENTIFICATION BYTE FORMAT Device Type Identifier Set to 0 for proper operation ID3 ID2 ID1 ID0 0 1 0 1 0 Internal Slave Address A2 A1 (MSB) A0 (LSB) TABLE 4. INSTRUCTION BYTE FORMAT P1 and P0 are used also for register Bank Selection for 2-Wire Register Write and Read operations Register Selection Instruction Opcode Register Selection Register Selected I3 I2 I1 I0 RB RA P1 (MSB) RB RA P0 DR0 0 0 (LSB) DR1 0 1 DR2 1 0 DR3 1 1 Pot Selection (Bank Selection) Set to P0 = 0 for potentiometer operations TABLE 5. INSTRUCTION SET INSTRUCTION Set I3 I2 I1 I0 RB RA P1 P0 Read Wiper Counter Register 1 0 0 1 0 0 0 0 Read the contents of the Wiper Counter Register Write Wiper Counter Register 1 0 1 0 0 0 0 0 Write new value to the Wiper Counter Register Read Data Register 1 0 1 1 1/0 1/0 1/0 1/0 Read the contents of the Data Register pointed to by P1 - P0 and RB - RA Write Data Register 1 1 0 0 1/0 1/0 1/0 1/0 Write new value to the Data Register pointed to by P1 - P0 and RB - RA XFR Data Register to Wiper Counter Register 1 1 0 1 1/0 1/0 0 0 Transfer the contents of the Data Register pointed to by RB-RA (Bank 0 only) to the Wiper Counter Register XFR Wiper Counter Register to Data Register 1 1 1 0 1/0 1/0 0 0 Transfer the contents of the Wiper Counter Register to the Register pointed to by RB-RA (Bank 0 only) Increment/Decrement Wiper Counter Register 0 0 1 0 0 0 0 0 Enable Increment/decrement of the Wiper Counter Register INSTRUCTION OPERATION NOTE: 3. 1/0 = data is one or zero 7 FN8175.4 September 23, 2009 X9279 TABLE 6. WIPER COUNTER REGISTER, WCR (8-bit), WCR[7:0]: (Used to store the current wiper position (Volatile, V) WCR7 WCR6 WCR5 WCR4 WCR3 WCR2 WCR1 WCR0 V V V V V V V V (MSB) (LSB) TABLE 7. DATA REGISTER, DR (8-BIT), BIT [7:0]: Used to store wiper positions or data (Non-volatile, NV) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 NV NV NV NV NV NV NV NV MSB LSB Device Description * Write Wiper Counter Register - change current wiper position of the potentiometer, Wiper Counter Register (WCR) The X9279 contains a Wiper Counter Register, for the DCP potentiometer. The Wiper Counter Register can be envisioned as a 8-bit parallel and serial load counter with its outputs decoded to select one of 256 switches along its resistor array. The contents of the WCR can be altered in four ways: it may be written directly by the host via the Write Wiper Counter Register instruction (serial load); it may be written indirectly by transferring the contents of one of four associated data registers via the XFR Data Register instruction (parallel load); it can be modified one step at a time by the Increment/Decrement instruction (see "Instruction Format" on page 10 for more details). Finally, it is loaded with the contents of its Data Register zero (DR0) upon power-up. The Wiper Counter Register is a volatile register; that is, its contents are lost when the X9279 is powered-down. Although the register is automatically loaded with the value in DR0 upon power-up, this may be different from the value present at power-down. Power-up guidelines are recommended to ensure proper loadings of the DR0 value into the WCR. The DR0 value of Bank 0 is the default value. Data Registers (DR) The potentiometer has four 8-bit non-volatile Data Registers (DR3-DR0). These can be read or written directly by the host. Data can also be transferred between any of the four Data Registers and the associated Wiper Counter Register. All operations changing data in one of the Data Registers is a non-volatile operation and will take a maximum of 10ms. If the application does not require storage of multiple settings for the potentiometer, the Data Registers can be used as regular memory locations for system parameters or user preference data. Bit [7:0] are used to store one of the 256 wiper positions (0~255). Instructions Four of the seven instructions are three bytes in length. These instructions are: * Read Data Register - read the contents of the selected Data Register; * Write Data Register - write a new value to the selected Data Register. The basic sequence of the three byte instructions is illustrated in Figure 4. These three-byte instructions exchange data between the WCR and one of the Data Registers. A transfer from a Data Register to a WCR is essentially a write to a static RAM, with the static RAM controlling the wiper position. The response of the wiper to this action will be delayed by tWRL. A transfer from the WCR (current wiper position), to a Data Register is a write to non-volatile memory and takes a minimum of tWR to complete. The transfer can occur between the potentiometer and one of its four associated registers (Bank 0). Two instructions require a two-byte sequence to complete. These instructions transfer data between the host and the X9279; either between the host and one of the data registers or directly between the host and the Wiper Counter Register. These instructions are: * XFR Data Register to Wiper Counter Register - This transfers the contents of one specified Data Register to the Wiper Counter Register. * XFR Wiper Counter Register to Data Register - This transfers the contents of the Wiper Counter Register to the specified Data Register. The final command is Increment/Decrement (Figures 5 and 6). The Increment/Decrement command is different from the other commands. Once the command is issued and the X9279 has responded with an acknowledge, the master can clock the selected wiper up and/or down in one segment steps; thereby, providing a fine tuning capability to the host. For each SCL clock pulse (tHIGH) while SDA is HIGH, the selected wiper will move one resistor segment towards the RH terminal. Similarly, for each SCL clock pulse while SDA is LOW, the selected wiper will move one resistor segment towards the RL terminal. See "Instruction Format" on page 10 for more details. * Read Wiper Counter Register - read the current wiper position of the potentiometer, 8 FN8175.4 September 23, 2009 X9279 SCL 0 SDA 1 0 1 0 S ID3 ID2 ID1 ID0 T A R Device ID T A1 0 A2 A0 A C K I3 Internal Address I2 I1 I0 Instruction Opcode 0 RB RA P1 P0 A C K Pot/Bank Address Register Address S T O P These commands only valid when P1 = P0 = 0 FIGURE 3. TWO-BYTE INSTRUCTION SEQUENCE SCL 0 1 0 ID3 ID2 ID1 ID0 0 SDA S T A R T 1 0 A2 A1 A C K A0 External Address Device ID I3 I2 I1 I0 RB RA P1 P0 A C K D7 D6 D5 D4 D3 D2 D1 D0 A C K S T O P D E C n S T O P WCR[7:0] valid only when P1 = P0 = 0; Register Pot/Bank Address or Address Data Register D[7:0] for all values of P1 and P0 Instruction Opcode FIGURE 4. THREE-BYTE INSTRUCTION SEQUENCE SCL SDA S T A R T 0 1 0 1 ID3 ID2 ID1 ID0 0 0 A2 A1 A0 External Address Device ID A C K I3 I2 I1 Instruction Opcode I0 RB RA Register Address P1 P0 A C Pot/Bank K Address I N C 1 I N C 2 I N C n D E C 1 FIGURE 5. INCREMENT/DECREMENT INSTRUCTION SEQUENCE INC/DEC CMD ISSUED tWRID SCL SD A VOLTAGE OUT VW/RW FIGURE 6. INCREMENT/DECREMENT TIMING LIMITS 9 FN8175.4 September 23, 2009 X9279 Instruction Format Read Wiper Counter Register (WCR) S T A R T Device Type Identifier 0 1 Device Addresses 0 1 0 A2 A1 A0 S A C K Instruction Opcode 1 0 0 Wiper Position (Sent by X9279 on SDA) M S A A C WC WC WC WC WC WC WC WC C R7 R6 R5 R4 R3 R2 R1 R0 K K S T O P Wiper Position (Sent by Master on SDA) S S A A WC WC WC WC WC WC WC WC C C K R7 R6 R5 R4 R3 R2 R1 R0 K S T O P Wiper Position (Sent by X9279 on SDA) M S A A WC WC WC WC WC WC WC WC C C R7 R6 R5 R4 R3 R2 R1 R0 K K S T O P DR/Bank Addresses 1 0 0 0 0 Write Wiper Counter Register (WCR) S T A R T Device Type Identifier 0 1 Device Addresses 0 1 0 A2 A1 Instruction Opcode S A C K A0 1 0 1 DR/Bank Addresses 0 0 0 0 0 Read Data Register (DR) S T A R T Device Type Identifier 0 1 0 Device Addresses 1 0 A2 A1 S A C K A0 Instruction Opcode 1 0 1 DR/Bank Addresses 1 RB RA P1 P0 S T A R T Device Type Identifier 0 1 0 Instruction Opcode Device Addresses 1 0 A2 S A0 A C K A1 1 1 0 Wiper Position (Sent by Master on SDA) DR/Bank Addresses 0 RB RA HIGH-VOLTAGE WRITE CYCLE Write Data Register (DR) P1 P0 S S S A WC WC WC WC WC WC WC WC A T C R7 R6 R5 R4 R3 R2 R1 R0 C O K P K Transfer Wiper Counter Register (WCR) to Data Register (DR) S T A R T Device Type Identifier 0 1 0 Device Addresses 1 0 A2 A1 Instruction Opcode S A C K A0 1 1 1 DR/Bank Addresses 0 RB RA 0 0 S A C K High-Voltage Write Cycle S T O P Transfer Data Register (DR) to Wiper Counter Register (WCR) Device Type Identifier S T A R T 0 1 0 Device Addresses 1 0 A2 A1 Instruction Opcode S A C K A0 1 1 0 DR/Bank Addresses 1 RB RA 0 0 S A C K S T O P Increment/Decrement Wiper Counter Register (WCR) S T A R T Device Type Identifier 0 1 0 Device Addresses 1 0 A2 A1 A0 S A C K Instruction Opcode 0 0 1 DR/Bank Addresses 0 0 0 0 0 S A C K Increment/Decrement (Sent by Master on SDA) I/D I/D . . . . I/D I/D S T O P NOTES: 4. "MACK"/"SACK": stands for the acknowledge sent by the master/slave. 5. "A3 ~ A0": stands for the device addresses sent by the master. 6. "X": indicates that it is a "0" for testing purpose but physically it is a "don't care" condition. 7. "I": stands for the increment operation, SDA held high during active SCL phase (high). 8. "D": stands for the decrement operation, SDA held low during active SCL phase (high). 10 FN8175.4 September 23, 2009 X9279 Absolute Maximum Ratings Thermal Information Voltage on SCL, SDA any Address Input with respect to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to +7V DV = | (VH - VL) | . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V IW (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6mA Thermal Resistance (Typical, Note 9) JA (C/W) 14 Lead TSSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Temperature Under Bias . . . . . . . . . . . . . . . . . . . . .-65C to +135C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Operating Conditions Temperature Range Commercial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to +70C Industrial. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40C to +85C Supply Voltage VCC Limits (Note 13) X9279 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V 10% X9279-2.7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V Wiper Max Current (IW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3mA Power Rating @ +25C, each pot . . . . . . . . . . . . . . . . . . . . . .50mW CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTE: 9. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. Analog Characteristics Operating Conditions over recommended industrial (2.7V) unless otherwise specified. SYMBOL PARAMETER TEST CONDITIONS MIN TYP RTOTAL End-to-End Resistance T version 100 RTOTAL End-to-End Resistance U version 50 End-to-End Resistance Tolerance MAX UNITS k k 20 % RW Wiper Resistance @ V = 3V IW = (VRH - VRL)/RTOTAL 300 RW Wiper Resistance @ V = 5V IW = (VRH - VRL)/RTOTAL 150 VTERM Voltage on any RH or RL Pin VSS = 0V VCC V Noise Ref: 1V Resolution Absolute Linearity (Note 10) Rw(n)(actual) - Rw(n)(expected) (Note 14) Relative Linearity (Note 11) Rw(n + 1) - [Rw(n) + MI] (Note 14) Temperature Coefficient of RTOTAL Ratiometric Temp. Coefficient CH/CL/CW Potentiometer Capacitances See Macro model VSS -120 dBV/Hz 0.4 % 1 MI (Note 12) 0.2 MI (Note 12) 300 ppm/C 20 ppm/C 10/10/25 pF NOTES: 10. Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a potentiometer. 11. Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. It is a measure of the error in step size. 12. MI = RTOT / 255 or (RH - RL)/255, single pot 13. During power-up VCC > VH, VL, and VW. 14. n = 0, 1, 2,....,255; m = 0, 1, 2,...., 254. 11 FN8175.4 September 23, 2009 X9279 DC Electrical Specifications SYMBOL Over the recommended Operating Conditions unless otherwise specified. PARAMETER TEST CONDITIONS MIN TYP MAX UNITS ICC1 VCC Supply Current (Active) fSCL = 400kHz; VCC = +6V; SDA = Open; (for 2-Wire, Active, Read and Volatile Write States only) 3 mA ICC2 VCC Supply Current (Non-volatile Write) fSCL = 400kHz; VCC = +6V; SDA = Open (for 2-Wire, Active, Non-volatile Write State only) 5 mA ISB VCC Current (Standby) VCC = +6V; VIN = VSS or VCC; SDA = VCC (for 2-Wire, Standby State only) 5 A ILI Input Leakage Current VIN = VSS to VCC 10 A ILO Output Leakage Current VOUT = VSS to VCC 10 A VIH Input HIGH Voltage VCC x 0.7 VCC + 1 V VIL Input LOW Voltage -1 VCC x 0.3 V VOL Output LOW Voltage 0.4 V IOL = 3mA Endurance and Data Retention PARAMETER Minimum Endurance MIN UNITS 100,000 Data changes per bit per register 100 years Data Retention Capacitance SYMBOL TEST TYP UNITS TEST CONDITIONS CIN/OUT Input /Output capacitance (SDA) 8 pF VOUT = 0V CIN Input capacitance (SCL, WP, A2, A1 and A0) 6 pF VIN = 0V Power-Up Timing SYMBOL PARAMETER MIN MAX UNITS 0.2 tr VCC (Note 15) VCC Power-up rate 50 V/ms tPUR (Note 16) Power-up to initiation of read operation 1 ms tPUW (Note 16) Power-up to initiation of write operation 50 ms NOTES: 15. This parameter is not 100% tested. 16. tPUR and tPUW are the delays required from the time the (last) power supply (VCC-) is stable until the specific instruction can be issued. These parameters are periodically sampled and not 100% tested. AC Test Conditions Input Pulse Levels VCC x 0.1 to VCC x 0.9 Input rise and fall times 10ns Input and output timing level VCC x 0.5 12 FN8175.4 September 23, 2009 X9279 Equivalent AC Load Circuit 5V SPICE MACROMODEL 3V 1533 RTOTAL 867 SDA PIN RH SDA PIN RL CW CL CL 10pF 100pF 100pF 25pF 10pF RW AC Timing SYMBOL PARAMETER MIN MAX UNITS 400 kHz fSCL Clock Frequency tCYC Clock Cycle Time 2500 ns tHIGH Clock High Time 600 ns tLOW Clock Low Time 1300 ns tSU:STA Start Setup Time 600 ns tHD:STA Start Hold Time 600 ns tSU:STO Stop Setup Time 600 ns tSU:DAT SDA Data Input Setup Time 100 ns tHD:DAT SDA Data Input Hold Time 30 ns tR SCL and SDA Rise Time 300 ns tF SCL and SDA Fall Time 300 ns tAA SCL Low to SDA Data Output Valid Time 0.9 s tDH SDA Data Output Hold Time 0 ns tI Noise Suppression Time Constant at SCL and SDA inputs 50 ns tBUF Bus Free Time (Prior to Any Transmission) 1200 ns tSU:WPA A0, A1 Setup Time 0 ns tHD:WPA A0, A1 Hold Time 0 ns High Voltage Write Cycle Timing SYMBOL PARAMETER tWR High-voltage write cycle time (store instructions) TYP MAX UNITS 5 10 ms XDCP Timing SYMBOL PARAMETER MIN MAX UNITS tWRPO Wiper response time after the third (last) power supply is stable 5 10 s tWRL Wiper response time after instruction issued (all load instructions) 5 10 s 13 FN8175.4 September 23, 2009 X9279 Symbol Table WAVEFORM INPUTS OUTPUTS Must be steady Will be steady May change from Low to High Will change from Low to High May change from High to Low Will change from High to Low Don't Care: Changes Allowed Changing: State Not Known N/A Center Line is High Impedance Timing Diagrams Start and Stop Timing (START) (STOP) tR tF SCL tSU:STA tHD:STA tSU:STO tR tF SDA Input Timing tCYC tHIGH SCL tLOW SDA tSU:DAT tHD:DAT tBUF Output Timing SCL SDA tAA 14 tDH FN8175.4 September 23, 2009 X9279 XDCP Timing (for All Load Instructions) (STOP) SCL LSB SDA tWRL VWx Write Protect and Device Address Pins Timing (START) (STOP) SCL ... (ANY INSTRUCTION) ... SDA ... tSU:WPA tHD:WPA WP A0, A1 Applications information Basic Configurations of Electronic Potentiometers +VR VR RW I Three terminal Potentiometer; Variable voltage divider 15 Two terminal Variable Resistor; Variable current FN8175.4 September 23, 2009 X9279 Application Circuits VS + VO - VIN VO (REG) 317 R1 R2 Iadj R1 R2 VO = (1+R2/R1)VS VO (REG) = 1.25V (1+R2/R1)+Iadj R2 VOLTAGE REGULATOR NON-INVERTING AMPLIFIER R1 R2 VS VS - VO + 100k - VO + R1 R2 VUL = {R1/(R1+R2)} VO(max) RLL = {R1/(R1+R2)} VO(min) 10k +12V } 10k } TL072 10k -12V COMPARATOR WITH HYSTERISIS OFFSET VOLTAGE ADJUSTMENT C VS + R2 R1 VS + VO R R3 R4 R1 = R2 = R3 = R4 = 10k VO = G VS -1/2 G +1/2 ATTENUATOR 16 VO - - R2 R1 GO = 1 + R2/R1 fc = 1/(2RC) FILTER FN8175.4 September 23, 2009 X9279 Application Circuits (Continued) R2 C1 VS R2 + - } } R1 VS R1 ZIN - VO + R3 ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq (R1 + R3) >> R2 VO = G VS G = - R2/R1 EQUIVALENT L-R CIRCUIT INVERTING AMPLIFIER C R2 - + R1 - } RA + } RB Frequency R1, R2, C Amplitude RA, RB FUNCTION GENERATOR 17 FN8175.4 September 23, 2009 X9279 Thin Shrink Small Outline Plastic Packages (TSSOP) M14.173 N INDEX AREA E 0.25(0.010) M E1 2 SYMBOL 3 0.05(0.002) -A- INCHES GAUGE PLANE -B1 14 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE B M 0.25 0.010 SEATING PLANE L A D -C- e A1 b A2 c 0.10(0.004) 0.10(0.004) M C A M B S MIN 1. These package dimensions are within allowable dimensions of JEDEC MO-153-AC, Issue E. MILLIMETERS MIN MAX NOTES A - 0.047 - 1.20 - A1 0.002 0.006 0.05 0.15 - A2 0.031 0.041 0.80 1.05 - b 0.0075 0.0118 0.19 0.30 9 c 0.0035 0.0079 0.09 0.20 - D 0.195 0.199 4.95 5.05 3 E1 0.169 0.177 4.30 4.50 4 e 0.026 BSC 0.65 BSC - E 0.246 0.256 6.25 6.50 - L 0.0177 0.0295 0.45 0.75 6 8o 0o N NOTES: MAX 14 0o 14 7 8o Rev. 2 4/06 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E1" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension "b" does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of "b" dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. (Angles in degrees) All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 18 FN8175.4 September 23, 2009