W83195CG-920
Winbond Clock Generator with
DDR I/II Buffer For VIA P4 Series
Chipset
Date: Apr/10/2006 Revision: 0.6
CLOCK GEN. with DDRI/II Buffer For VIA P4 SERIES CHIPSET
Publication Release Date: Apr. 2006
- I - Revision 0.6
W83195CG-920
W83195CG-920 Data Sheet Revision History
PAGES DATES VERSION WEB
VERSION MAIN CONTENTS
1
All of the versions before 0.50 are for internal
use.
2 n.a. 08/27/05 0.5 n.a. First published preliminary version.
3 n.a. 04/10/2006 0.6 n.a. Please see the blue text.
4
5
6
7
8
9
10
Please note that all data and specifications are subject to change without notice. All the trademarks of
products and companies mentioned in this data sheet belong to their respective owners.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where
malfunction of these products can reasonably be expected to result in personal injury. Winbond
customers using or selling these products for use in such applications do so at their own risk and
agree to fully indemnify Winbond for any damages resulting from such improper use or sales.
CLOCK GEN. with DDRI/II Buffer For VIA P4 SERIES CHIPSET
- II -
W83195CG-920
Table of Contents-
1. GENERAL DESCRIPTION......................................................................................................... 1
2. PRODUCT FEATURES.............................................................................................................. 1
3. PIN CONFIGURATION............................................................................................................... 2
4. BLOCK DIAGRAM...................................................................................................................... 2
5. PIN DESCRIPTION .................................................................................................................... 3
5.1 Crystal I/O ..................................................................................................................................3
5.2 CPU, AGP, PCI Clock Outputs .................................................................................................3
5.3 Fixed Frequency Outputs..........................................................................................................4
5.4 DRAM Buffer..............................................................................................................................4
5.5 I2C Control Interface .................................................................................................................5
5.6 Output Control Pins ...................................................................................................................5
5.7 Power an GND Pins ..................................................................................................................5
6. FREQUENCY SELECTION BY HARDWARE OR SOFTWARE................................................ 6
7. I2C CONTROL AND STATUS REGISTERS............................................................................... 7
7.1 Register 0: Frequency Select (Default =30h) ...........................................................................7
7.2 Register 1: SRC/CPU Clock (1 = Enable, 0 = Disable) (Default: XXh) ...................................7
7.3 Register 2: PCI Clock (1 = Enable, 0 = Disable) (Default: FEh) ..............................................8
7.4 Register 3: REF, 24_48,48,AGP Clock (1 = Enable, 0 = Disable) (Default: F7h)...................8
7.5 Register 4: Watchdog Control (Default: 86h)............................................................................8
7.6 Register 5: Watch dog timer (Default: 08h) ..............................................................................9
7.7 Register 6: M/N Program (Default: 90h) ...................................................................................9
7.8 Register 7: M/N Program (Default: 7Ah).................................................................................10
7.9 Register 8: Spread Spectrum Program (Default: 2Eh)...........................................................10
7.10 Register 9: Divider Ratio (Default: 84h) ..................................................................................10
7.11 Register 10: Control (Default: 0Fh) .........................................................................................11
7.12 Register 11: Control (Default: 90h) .........................................................................................12
7.13 Register 12: Control (Default: BCh) ........................................................................................12
7.14 Register 13: Control (Default: E4h).........................................................................................12
7.15 Register 14: Control (Default: 54h) .........................................................................................13
7.16 Register 15: Slew Rate Control (Default: 55h) .......................................................................13
7.17 Register 16: DRAM Buffer Control (1 = Enable, 0 = Disable) (Default: 7Fh) ........................14
7.18 Register 17: Slew Rate Control (Default: CFh) ......................................................................14
7.19 Register 18: M/N Time & Type Control (Default: 5Bh)...........................................................14
7.20 Register 19: Reserved (Default: 5Bh).....................................................................................15
7.21 Register 20: Winbond Chip ID – (Ready Only) (Default: 79h) ...............................................15
7.22 Register 21: Winbond Chip ID – (Ready Only) (Default: 50h) ...............................................15
CLOCK GEN. with DDRI/II Buffer For VIA P4 SERIES CHIPSET
Publication Release Date: Apr. 2006
- III - Revision 0.6
W83195CG-920
8. ACCESS INTERFACE.............................................................................................................. 17
8.1 Block Write protocol.................................................................................................................17
8.2 Block Read protocol ................................................................................................................17
8.3 Byte Write protocol ..................................................................................................................17
8.4 Byte Read protocol ..................................................................................................................17
9. SPECIFICATIONS.................................................................................................................... 18
9.1 ABSOLUTE MAXIMUM RATINGS.........................................................................................18
9.2 General Operating Characteristics..........................................................................................18
9.3 Skew Group timing clock.........................................................................................................18
9.4 CPU 0.7V Electrical Characteristics........................................................................................19
9.5 CPU 1.0V Electrical Characteristics........................................................................................19
9.6 AGP Electrical Characteristics ................................................................................................19
9.7 PCI Electrical Characteristics ..................................................................................................20
9.8 24M, 48M Electrical Characteristics........................................................................................20
9.9 REF Electrical Characteristics.................................................................................................20
10. ORDERING INFORMATION .................................................................................................... 21
11. HOW TO READ THE TOP MARKING ..................................................................................... 21
12. PACKAGE DRAWING AND DIMENSIONS ............................................................................. 22
CLOCK GEN. with DDRI/II Buffer For VIA P4 SERIES CHIPSET
Publication Release Date: Apr. 2006
- 1 - Revision 0.6
W83195CG-920
1. GENERAL DESCRIPTION
The W83195CG-920 is a Clock Synthesizer for VIA P4 series chipset.W83195CG-920 provides all
clocks required for high-speed microprocessor and provides step-less frequency programming and 32
different frequencies of CPU, AGP, and PCI clocks setting. All clocks are externally selectable with
smooth transitions.
The W83195CG-920 provides I2C serial bus interface to program the registers to enable or disable
each clock outputs and provides +/-0.25%, +/-0.5% center type and –0.5%, -1.0% down type spread
spectrum or programmable S.S.T. scale to reduce EMI.
The W83195CG-920 accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply.
2. PRODUCT FEATURES
• 1 pairs differential clock for CPU
• 1 pairs differential clock for Chipset
• 3 AGP clock outputs
• Support two DDRI/II DIMMS
• 7 PCI synchronous clocks, 1 free running
• 1 48MHz clock outputs for USB
• 1 24_48MHz for I/O chip, default 24MHz
• 2 REF 14.318MHz clock outputs
• AGP leads PCICLK from 1.5ns to 3.5ns
• I
2C 2-Wire serial interface supports block and byte mode read/write
• Step-less frequency programming
• Smooth frequency switch with selections from 66 to 400MHz
• Programmable clock outputs Slew rate control and Skew control
• +/- 0.25% center type spread spectrum in table mode
• Programmable S.S.T. scale to reduce EMI
• Programmable registers to enable/stop each output and select modes
• 56-pin SSOP package
CLOCK GEN. with DDRI/II Buffer For VIA P4 SERIES CHIPSET
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W83195CG-920
3. PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
FS0&/REF0
GND
XIN
XOUT
VDDAGP
AGP0
FS4&/AGP1
AGP2
GND
FS1*/PCI_F
PCI1
PCI2
GND
PCI3
PCI4
VDDPCI
PCI5
PCI6
GND
FS3&/48Mhz
FS2*/24_48MHz
VDD48
VDD
GND
IREF
PD#*/RESET#
SCLK*
SDATA*
VTT_PWRGD#/REF1
VDDR
GND
CPUT
CPUC
VDDC
VDDI
CPUCS_C
CPUCS_T
GND
FBOUT
BUF_IN
DDRT0
DDRC0
DDRT1
DDRC1
VDDD
GND
DDRT2
DDRC2
DDRT3
DDRC3
VDDD
GND
DDRT4
DDRC4
DDRT5
DDRC5
#: Active low
*: Internal pull up resistor 120KΩ to VDD
&: Internal Pull-down resistor 120KΩ to GND
4. BLOCK DIAGRAM
PLL2
XTAL
OSC
PLL1
Spread
Spectrum
M/N/Ratio
ROM
Latch
&POR
Control
Logic
&Config
Register
I2C
Interface
Divider
VCOCLK
48MHz
REF 0:1
CPUT
CPUC
AGP (0:2)
PCI_F
PCI 1:6
RESET#
Rref
XIN
XOUT
VTT_PWRGD#
FS(0:4)
PD#*
SDATA*
SCLK*
3
6
2
CPUCS_T
CPUCS_C
IREF
Divider 24_48MHz
BUF_IN
FBOUT
DDRT(0:5)
DDRC(0:5)
6
6
MULTSEL*
CLOCK GEN. with DDRI/II Buffer For VIA P4 SERIES CHIPSET
Publication Release Date: Apr. 2006
- 3 - Revision 0.6
W83195CG-920
5. PIN DESCRIPTION
BUFFER TYPE SYMBOL FUNCTION DESCRIPTION
IN Input
INtd120k Latch input pin and internal 120KΩ pull down
INtp120k Latch input pin and internal 120KΩ pull up
OUT Output
OD Open Drain
I/O Bi-directional Pin
I/OD Bi-directional Pin, Open Drain
# Active Low
* Internal 120kΩ pull-up
&Internal 120kΩ pull-down
5.1 Crystal I/O
PIN PIN NAME TYPE DESCRIPTION
3 XIN IN
Crystal input with internal loading capacitors (18pF) and feedback
resistors.
4 XOUT OUT
Crystal output at 14.318MHz nominally with internal loading
capacitors (18pF).
5.2 CPU, AGP, PCI Clock Outputs
PIN PIN NAME TYPE DESCRIPTION
53,52 CPUT
CPUC OUT Current Mode differential clock outputs for P4 CPU
49,48 CPUCS_C
CPUCS_T OUT 2.5V differential clock outputs for Chipset.
AGP1 OUT 3.3V 66MHz clock output
7 FS4&INtp120k
Latched input for FS4 at initial power up for H/W selecting the output
frequency clocks. This is internal 120KΩ pull up.
6 AGP0 OUT 3.3V 66MHz clock output.
8 AGP2 OUT 3.3V 66MHz clock output.
PCI_F OUT 3.3V 33MHz free running clock output.
10 FS1* INtp120k
Latched input for FS1 at initial power up for H/W selecting the output
frequency clocks. This is internal 120KΩ pull up.
CLOCK GEN. with DDRI/II Buffer For VIA P4 SERIES CHIPSET
- 4 -
W83195CG-920
CPU, AGP, PCI Clock Outputs, continued
PIN PIN NAME TYPE DESCRIPTION
11 PCI1 OUT 3.3V 33MHz clock output.
12 PCI2 OUT 3.3V 33MHz clock output.
14, 15
17, 18 PCI [3:6] OUT 3.3V 33MHz clock outputs.
5.3 Fixed Frequency Outputs
PIN PIN NAME TYPE DESCRIPTION
REF0 OUT 14.318MHz output.
1
FS0&INtd120k
Latched input for FS0 at initial power up for H/W selecting the output
frequency clocks. This is internal 120KΩ pull down.
REF1 OUT 14.318MHz output.
56 VTT-
_PWRGD# IN
Power good input signal comes from ACPI with low active. This 3.3V
input is level sensitive strobe used to determine FS [4:0] and
MULTSEL input are valid and is ready to sample. This pin is low
active.
48MHz OUT 48MHz clock output.
20
FS3&INtd120k
Latched input for FS3 at initial power up for H/W selecting the output
frequency clocks. This is internal 120KΩ pull down.
24_48MHz OUT 24MHz clock output
21
FS2* INtp120k
Latched input for FS2 at initial power up for H/W selecting the output
frequency clocks. This is internal 120KΩ pull up.
5.4 DRAM Buffer
PIN Pin Name Type Description
45 BUF_IN IN Reference input from chipset.
46 FBOUT OUT Feedback clock for chipset. Output voltage depends on VDDD
44,42,38
36,32,30 DDRT[0:5] OUT DDRI/II Clock outputs.
43,41,37
35,31,29 DDRC[0:5] OUT DDRI/II Clock outputs.
CLOCK GEN. with DDRI/II Buffer For VIA P4 SERIES CHIPSET
Publication Release Date: Apr. 2006
- 5 - Revision 0.6
W83195CG-920
5.5 I2C Control Interface
PIN PIN NAME TYPE DESCRIPTION
28 SDATA* I/OD
Serial data of I2C 2-wire control interface with internal pull-up resistor
120K.
27 SCLK* IN
Serial clock of I2C 2-wire control interface with internal pull-up resistor
120K.
5.6 Output Control Pins
PIN PIN NAME TYPE DESCRIPTION
25 IREF OUT
Deciding the reference current for the CPUT/C pairs. The pin was
connected to the precision resistor tied to ground to decide the
appropriate current.
RESET# OD
Select by register 1 bit 6 L_MODE if L_MODE=1 this pin is System
reset signal when the watchdog is time out. This pin will generate
250mS when the watchdog timer is timeout
26
PD#* IN Select by register 1 bit 6 L_MODE if L_MODE=0 this pin is Power
Down Function. This is internal 120KΩ pull up.
5.7 Power an GND Pins
PIN PIN NAME TYPE DESCRIPTION
5 VDDAGP PWR 3.3V power supply for AGP.
16 VDDPCI PWR 3.3V power supply for PCI.
22 VDD48 PWR 3.3V power supply for 48MHz.
23 VDD PWR 3.3V power supply analog core.
34,40 VDDD PWR 2.5V or 1.8V power for DDRI/II buffer part.
50 VDDI PWR 2.5V power supply for CPUCS_T/C.
51 VDDC PWR 3.3V power supply for CPUT/C.
55 VDDR PWR 3.3V power supply for REF
2,9,13,19,24,
33,39,47,54 GND PWR Ground pin for 3.3 V
CLOCK GEN. with DDRI/II Buffer For VIA P4 SERIES CHIPSET
- 6 -
W83195CG-920
6. FREQUENCY SELECTION BY HARDWARE OR SOFTWARE
This frequency table is used at power on latched FS [4:0] value or software programming at SSEL
[4:0] (Register 0 bit 7 ~ 3).
FS4 FS3 FS2 FS1 FS0 CPU (MHZ) AGP (MHZ) PCI (MHz)
0 0 0 0 0 103.0 68.6 34.3
0 0 0 0 1 140.0 70.0 35.0
0 0 0 1 0 206.0 68.6 34.3
0 0 0 1 1 171.0 68.4 34.2
0 0 1 0 0 266.6 66.6 33.3
0 0 1 0 1 133.3 66.6 33.3
0 0 1 1 0 200.0 66.6 33.3
0 0 1 1 1 166.6 66.6 33.3
0 1 0 0 0 100.0 66.6 33.3
0 1 0 0 1 133.3 66.6 33.3
0 1 0 1 0 200.0 66.6 33.3
0 1 0 1 1 166.6 66.6 33.3
0 1 1 0 0 333.3 66.6 33.3
0 1 1 0 1 100.0 66.6 33.3
0 1 1 1 0 400.0 66.6 33.3
0 1 1 1 1 200.0 66.6 33.3
1 0 0 0 0 202.0 67.3 33.6
1 0 0 0 1 200.0 66.6 33.3
1 0 0 1 0 204.0 68.0 34.0
1 0 0 1 1 206.0 68.6 34.3
1 0 1 0 0 208.0 69.3 34.6
1 0 1 0 1 166.6 66.6 33.3
1 0 1 1 0 210.0 70.0 35.0
1 0 1 1 1 212.0 70.6 35.3
1 1 0 0 0 168.0 67.2 33.6
1 1 0 0 1 100.0 66.6 33.3
1 1 0 1 0 170.0 68.0 34.0
1 1 0 1 1 172.0 68.8 34.4
1 1 1 0 0 100.0 66.6 33.3
1 1 1 0 1 133.3 66.6 33.3
1 1 1 1 0 200.0 66.6 33.3
1 1 1 1 1 166.6 66.6 33.3
CLOCK GEN. with DDRI/II Buffer For VIA P4 SERIES CHIPSET
Publication Release Date: Apr. 2006
- 7 - Revision 0.6
W83195CG-920
7. I2C CONTROL AND STATUS REGISTERS
(The register No. is increased by 1 if use byte data read/write protocol)
7.1 Register 0: Frequency Select (Default =30h)
BIT NAME PWD FUNCTION DESCRIPTION
7 SSEL [4] 0
6 SSEL [3] 0
5 SSEL [2] 1
4 SSEL [1] 1
3 SSEL [0] 0
Software frequency table selection through I2C
2 EN_SSEL 0
Enable software table selection FS [4:0].
0 = Hardware table setting (Jump mode).
1 = Software table setting through Bit7~3. (Jump less mode)
1 SPSPEN 0
Enable spread spectrum mode under clock output.
0 = Spread Spectrum mode disable
1 = Spread Spectrum mode enable
0 EN_SAFE_FREQ 0
Enable reload safe frequency when the watchdog is timeout.
0 = reload the FS [3:0] latched pins when watchdog time out.
1 = reload the safe frequency bit defined at Register 5 bit 4~0.
7.2 Register 1: SRC/CPU Clock (1 = Enable, 0 = Disable) (Default: XXh)
BIT NAME PWD FUNCTION DESCRIPTION
7 CPUCS_T
CPUCS_C 1 Pin 48,49 CPUCS_T/C output control
6 L_MODE 1
Selection for Pin 26. Power Down Input / System Reset Control
Output
1: System Reset feature (Default)
0: Power Down feature
5 CPUT/C 1
Pin 53,52 CPUT/C output control
4 FS4 X
Power on latched value of FS4 (7) pin. Default 0 (Read only)
3 FS3 X
Power on latched value of FS3 (20) pin. Default 1 (Read only)
2 FS2 X
Power on latched value of FS2 (21) pin. Default 0 (Read only)
1 FS1 X
Power on latched value of FS1 (10) pin. Default 1 (Read only)
0 FS0 X
Power on latched value of FS0 (1) pin. Default 0 (Read only)
CLOCK GEN. with DDRI/II Buffer For VIA P4 SERIES CHIPSET
- 8 -
W83195CG-920
7.3 Register 2: PCI Clock (1 = Enable, 0 = Disable) (Default: FEh)
BIT NAME PWD FUNCTION DESCRIPTION
7 PCI_F
1 Pin 10 PCI_F output control
6 PCI6 1 Pin 18 PCI6 output control
5 PCI5 1 Pin 17 PCI5 output control
4 PCI4 1 Pin 15 PCI4 output control
3 PCI3 1 Pin 14 PCI3 output control
2 PCI2 1 Pin 12 PCI2 output control
1 PCI1 1 Pin 11 PCI1 output control
0 INV_CPUCS 0 Invert the CPUCS phase, 0: Default, 1: Inverse
7.4 Register 3: REF, 24_48,48,AGP Clock (1 = Enable, 0 = Disable) (Default: F7h)
BIT NAME PWD FUNCTION DESCRIPTION
7 PREF1 1 Pin 56 REF1 output control
6 PREF0 1
Pin 1 REF0 output control
5 PUSB24 1
Pin 21, 24_48MHz output control
4 PUSB48 1
Pin 20, 48MHz output control
3 INV_USB48 0
Invert the 48MHz phase,
0: In phase with 24_48MHz, 1: 180 degrees out of phase
2 AGP2 1
Pin 8 AGP2 output control
1 AGP1 1
Pin 7 AGP1 output control
0 AGP0 1
Pin 6 AGP0 output control
7.5 Register 4: Watchdog Control (Default: 86h)
BIT NAME PWD DESCRIPTION TYPE
7 SEL24_48 1
24_ 48 MHz output selection,
1: 24 MHz (Default), 0: 48 MHz. R/W
6 EN_WD 0
Program this bit =>
1: Enable Watchdog Timer feature.
0: Disable Watchdog Timer feature.
Read-back this bit =>
During timer count down the bit read back to 1.
If count to zero, this bit read back to 0.
R/W
5 WD_TIMEOUT 0
Read Back only. Timeout Flag. This bit is Read Only.
1: Watchdog has ever started and counts to zero.
0: Watchdog is restarted and counting.
R
CLOCK GEN. with DDRI/II Buffer For VIA P4 SERIES CHIPSET
Publication Release Date: Apr. 2006
- 9 - Revision 0.6
W83195CG-920
Register 4: Watchdog Control (Default: 86h), continued
BIT NAME PWD DESCRIPTION TYPE
4 SAF_FREQ [4] 0 R/W
3 SAF_FREQ [3] 0
2 SAF_FREQ [2] 1
1 SAF_FREQ [1] 1
0 SAF_FREQ [0] 0
These bits will be reloaded in Reg-0 to select frequency
table. As the watchdog is timeout and
EN_SAFE_FREQ=1.
7.6 Register 5: Watch dog timer (Default: 08h)
BIT NAME PWD DESCRIPTION TYPE
7 WD_TIME [7] 0 R/W
6 WD_TIME [6] 0 R/W
5 WD_TIME [5] 0 R/W
4 WD_TIME [4] 0 R/W
3 WD_TIME [3] 1 R/W
2 WD_TIME [2] 0 R/W
1 WD_TIME [1] 0 R/W
0 WD_TIME [0] 0
Setting the down count depth (Failure decision). One bit
resolution represents 250ms. Default time depth is
8*250ms = 2.0 second. If the watchdog timer is counting,
this register will return present down count value.
R/W
7.7 Register 6: M/N Program (Default: 90h)
BIT NAME PWD FUNCTION DESCRIPTION
7 N_DIV [8] 1 Programmable N divisor value. Bit 7 ~0 are defined in the Register 7.
6 M_DIV [6] 0
5 M_DIV [5] 0
4 M_DIV [4] 1
3 M_DIV [3] 0
2 M_DIV [2] 0
1 M_DIV [1] 0
0 M_DIV [0] 0
Programmable M divisor value.
CLOCK GEN. with DDRI/II Buffer For VIA P4 SERIES CHIPSET
- 10 -
W83195CG-920
7.8 Register 7: M/N Program (Default: 7Ah)
BIT NAME PWD FUNCTION DESCRIPTION
7 N_DIV [7] 0
6 N_DIV [6] 1
5 N_DIV [5] 1
4 N_DIV [4] 1
3 N_DIV [3] 1
2 N_DIV [2] 0
1 N_DIV [1] 1
0 N_DIV [0] 0
Programmable N divisor value bit 7 ~0.
The bit 8 is defined in Register 6, Bit 7.
The bit 9 is defined in Register 9, Bit 7.
7.9 Register 8: Spread Spectrum Program (Default: 2Eh)
BIT NAME PWD FUNCTION DESCRIPTION
7 SP_UP [3] 0
6 SP_UP [2] 0
5 SP_UP [1] 1
4 SP_UP [0] 0
Spread Spectrum Up Counter bit 3 ~ bit 0.
3 SP_DOWN [3] 1
2 SP_DOWN [2] 1
1 SP_DOWN [1] 1
0 SP_DOWN [0] 0
Spread Spectrum Down Counter bit 3 ~ bit 0
2’s complement representation.
Ex: 1 -> 1111; 2 -> 1110; 7 -> 1001; 8 -> 1000
7.10 Register 9: Divider Ratio (Default: 84h)
BIT NAME PWD FUNCTION DESCRIPTION
7 N<9> 1 Programmable N divisor value bit 9
6 SEL_CLKSTOP 0 Refer to Table-2
5 IN to BOUT<2> 0
4 IN to BOUT<1> 0
3 IN to BOUT<0> 0
BUF_IN to FBOUT skew control.
300ps/per stage
2 DS2 1
1 DS1 0
0 DS0 0
Define the CPU/AGP/PCI divider ratio
Refer to Table-3
CLOCK GEN. with DDRI/II Buffer For VIA P4 SERIES CHIPSET
Publication Release Date: Apr. 2006
- 11 - Revision 0.6
W83195CG-920
Table-2
REGISTER 1 /BIT 6L_MODE PIN 26
0 PD#
1 RESET#
Table-3 CPU, AGP, PCI divider ratio selection Table
DS2~DS0 CPU AGP PCI
000 2 10 12
001 2 12 24
010 3 12 24
011 4 10 20
100 4 12 24
101 6 6 12
110 6 12 24
111 8 12 24
7.11 Register 10: Control (Default: 0Fh)
BIT NAME PWD FUNCTION DESCRIPTION
7 EN_MN_PROG 0
0: Output frequency depend on frequency table
1: Program all clock frequency by changing M/N value
The equation is VCO =14.318MHz*(N+4)/ M.
6 IN to OUT<2> 0
5 IN to OUT<1> 0
4 IN to OUT<0> 0
BUF_IN to OUT skew control.
300ps/per stage
3 IVAL<3> 1
2 IVAL<2> 1
1 IVAL<1> 1
0 IVAL<0> 1
Charge pump current selection
CLOCK GEN. with DDRI/II Buffer For VIA P4 SERIES CHIPSET
- 12 -
W83195CG-920
7.12 Register 11: Control (Default: 90h)
BIT NAME PWD FUNCTION DESCRIPTION
7 CPUT_DRI 1
CPUT output state in during POWER DOWN or Stop mode assertion.
0: Driven (2*Iref), 1: Tristate (Floating)
CPUC always tri-state (floating) in power down Assertion.
6 Reserve 0 Reserve
5 SPCNT [5] 0
4 SPCNT [4] 1
3 SPCNT [3] 0
2 SPCNT [2] 0
1 SPCNT [1] 0
0 SPCNT [0] 0
Spread Spectrum Programmable time, the resolution is 280ns.
Default period is 11.8us
7.13 Register 12: Control (Default: BCh)
Bit Name PWD Function Description
7 INV_CPU 1
Invert the CPU phase
0: Default, 1: Inverse
6 TRI_EN 0 Tri-state all output if set 1
5 SPSP_TYPE 1
Spread spectrum implementation method
1 : Pendulum type
0 : Original
4 Reserve 1
3 Reserve 1
Reserve
2 ASKEW [2] 1
1 ASKEW [1] 0
0 ASKEW [0] 0
CPU to AGP skew control, Skew resolution is 340ps
Expand the skew direction is same as
CPU_AGP_SKEW [2:0] setting
7.14 Register 13: Control (Default: E4h)
BIT NAME PWD FUNCTION DESCRIPTION
7 INV_AGP 1 Invert the AGP phase 0: Default, 1: Inverse
6 INV_PCI 1
Invert the PCI phase 0: Default, 1: Inverse
5 CSKEW [2] 1
4 CSKEW [1] 0
3 CSKEW [0] 0
CPU to CPUCS skew control, Skew resolution is 340ps
Expand the skew direction is same as
CPU_CPUCS_SKEW [2:0] setting
CLOCK GEN. with DDRI/II Buffer For VIA P4 SERIES CHIPSET
Publication Release Date: Apr. 2006
- 13 - Revision 0.6
W83195CG-920
Register 13: Control (Default: E4h), continued
BIT NAME PWD FUNCTION DESCRIPTION
2 PSKEW [2] 1
1 PSKEW [1] 0
0 PSKEW [0] 0
CPU to PCI skew control, Skew resolution is 340ps
Expand the skew direction is same as
CPU_PCI_SKEW [2:0] setting
7.15 Register 14: Control (Default: 54h)
BIT NAME PWD FUNCTION DESCRIPTION
7 Reserve 0
6 Reserve 1
Reserve
5 Reserve 0
4 Reserve 1
Reserve
3 Reserve 0
2 Reserve 1
Reserve
1 Reserve 0 Reserve
0 INV_DDR 0
Inverse feature
1: inverse DDROUT/FBOUT clock
0: Normal
(Default 0)
7.16 Register 15: Slew Rate Control (Default: 55h)
BIT NAME PWD FUNCTION DESCRIPTION
7 Reserve 0
6 Reserve 1
Reserve
5 Reserve 0
4 Reserve 1
Reserve
3 Reserve 0
2 Reserve 1
Reserve
1 Reserve 0
0 Reserve 1
Reserve
CLOCK GEN. with DDRI/II Buffer For VIA P4 SERIES CHIPSET
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W83195CG-920
7.17 Register 16: DRAM Buffer Control (1 = Enable, 0 = Disable) (Default: 7Fh)
BIT NAME PWD FUNCTION DESCRIPTION
7 Reserve 0 Reserve
6 FBOUT_EN 1 FBOUT output control
5 DDR5 1 DDRT5, DDRC5 output control
4 DDR4 1 DDRT4, DDRC4 output control
3 DDR3 1 DDRT3, DDRC3 output control
2 DDR2 1 DDRT2, DDRC2 output control
1 DDR1 1 DDRT1, DDRC1 output control
0 DDR0 1 DDRT0, DDRC0 output control
7.18 Register 17: Slew Rate Control (Default: CFh)
BIT NAME PWD FUNCTION DESCRIPTION
7 FBOUT_S2 1
6 FBOUT_S1 1
FBOUT slew rate control
11: Strong, 00: Weak, 10/01: Normal
5 Reserve 0
4 Reserve 0
Reserve
3 DDR3_S2 1
2 DDR3_S1 1
DDR3, 4,5 slew rate control
11: Strong, 00: Weak, 10/01: Normal
1 DDR0_S2 1
0 DDR0_S1 1
DDR0, 1,2 slew rate control
11: Strong, 00: Weak, 10/01: Normal
7.19 Register 18: M/N Time & Type Control (Default: 5Bh)
BIT NAME PWD FUNCTION DESCRIPTION
7 N_Time<2> 0
6 N_Time<1> 1
5 N_Time<0> 0
M/N mode N value change time control
4 M_Time<2> 1
3 M_Time<1> 1
2 M_Time<0> 0
M/N mode M value change time control
1 N_TYPE 1 Reserved for Winbond internal use, don’t modify it
0 M_TYPE 1 Reserved for Winbond internal use, don’t modify it
CLOCK GEN. with DDRI/II Buffer For VIA P4 SERIES CHIPSET
Publication Release Date: Apr. 2006
- 15 - Revision 0.6
W83195CG-920
M_TIME<2:0> OR N_TIME<2:0> M_DIVIDER OR N_DIVIDER TIMING COUNTER
000 6.152us
001 12.304us
010 24.608us
011 49.216us
100 98.432us
101 196.864us
110 393.728us
111 787.456us
7.20 Register 19: Reserved (Default: 5Bh)
7.21 Register 20: Winbond Chip ID – (Ready Only) (Default: 79h)
BIT NAME PWD FUNCTION DESCRIPTION
7 CHPI_ID [7] 0 Winbond Chip ID. W83195CG-920.
6 CHPI_ID [6] 1 Winbond Chip ID.
5 CHPI_ID [5] 1 Winbond Chip ID.
4 CHPI_ID [4] 1 Winbond Chip ID.
3 CHPI_ID [3] 1 Winbond Chip ID.
2 CHPI_ID [2] 0 Winbond Chip ID.
1 CHPI_ID [1] 0 Winbond Chip ID.
0 CHPI_ID [0] 1 Winbond Chip ID.
7.22 Register 21: Winbond Chip ID – (Ready Only) (Default: 50h)
BIT NAME PWD FUNCTION DESCRIPTION
7 MAS_ID [1] 0
6 MAS_ID [0] 1
MASK definition for master body
*A****: 01, *B****: 10,
*C****: 11, *D****: 00
5 SUB_ID [1] 0
4 SUB_ID [0] 1
MASK definition for code body
*A****001: 01, *A****002: 10,
*A****003: 11, *A****004: 00
3 MAS_VER_ID [1] 0
MASK version definition for master body
*A****001AA: 00, *A****001AB: 01,
*A****001AC: 10, *A****001AD: 11.
CLOCK GEN. with DDRI/II Buffer For VIA P4 SERIES CHIPSET
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W83195CG-920
Register 21: Winbond Chip ID – (Ready Only) (Default: 50h), continued
BIT NAME PWD FUNCTION DESCRIPTION
2 MAS_VER_ID [0] 0
1 SUB_VER_ID [1] 0
0 SUB_VER_ID [0] 0
MASK version definition for code body
*A****001A: 00, *A****001B: 01
*A****001C: 10, *A****001D: 11
CLOCK GEN. with DDRI/II Buffer For VIA P4 SERIES CHIPSET
Publication Release Date: Apr. 2006
- 17 - Revision 0.6
W83195CG-920
8. ACCESS INTERFACE
The W83195CG-920 provides I2C Serial Bus for microprocessor to read/write internal registers. In the
W83195CG-920 is provided Block Read/Block Write and Byte-Data Read/Write protocol. The I2C
address is defined at 0xD2.
Block Read and Block Write Protocol
8.1 Block Write protocol
8.2 Block Read protocol
## In block mode, the command code must filled 00H
8.3 Byte Write protocol
8.4 Byte Read protocol
CLOCK GEN. with DDRI/II Buffer For VIA P4 SERIES CHIPSET
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W83195CG-920
9. SPECIFICATIONS
9.1 ABSOLUTE MAXIMUM RATINGS
Stresses greater than those listed in this table may cause permanent damage to the device.
Precautions should be taken to avoid application of any voltage higher than the maximum rated
voltages to this circuit. Subjection to maximum conditions for extended periods may affect reliability.
Unused inputs must always be tied to an appropriate logic voltage level (Ground or VDD).
PARAMETER RATING
Absolute 3.3V Core Supply Voltage -0.5V to +4.6V
Absolute 3.3V I/O Supple Voltage - 0.5 V to + 4.6 V
Operating 3.3V Core Supply Voltage 3.135V to 3.465V
Operating 3.3V I/O Supple Voltage 3.135V to 3.465V
Storage Temperature - 65°C to + 150°C
Ambient Temperature - 55°C to + 125°C
Operating Temperature 0°C to + 70°C
Input ESD protection (Human body model) 2000V
9.2 General Operating Characteristics
VDD=VDDAGP=VDDC=VDDR=VDDPCI=VDD48= 3.3V
±
5 %, TA = 0
°
C to +70
°
C, Cl=10pF
PARAMETER SYMBOL MIN MAX UNITS TEST CONDITIONS
Input Low Voltage VIL 0.8 Vdc
Input High Voltage VIH 2.0 Vdc
Output Low Voltage VOL 0.4 Vdc All outputs using 3.3V power
Output High Voltage VOH 2.4 Vdc All outputs using 3.3V power
Operating Supply Current Idd 350 mA
CPU = 100 to 200 MHz
PCI = 33.3 Mhz with load
Input pin capacitance Cin 5 pF
Output pin capacitance Cout 6 pF
Input pin inductance Lin 7 nH
9.3 Skew Group timing clock
VDD=VDDAGP=VDDC=VDDR=VDDPCI=VDD48= 3.3V
±
5 %, TA = 0
°
C to +70
°
C, Cl=10pF
PARAMETER MIN TYP MAX UNITS TEST CONDITIONS
AGP to PCI Skew 1.5 2.6 3.5 ns Measured at 1.5V
CPU to CPU Skew 200 ps Crossing point
AGP to AGP Skew 250 ps Measured at 1.5V
PCI to PCI Skew 500 ps Measured at 1.5V
48MHz to 48MHz Skew 1000 ps Measured at 1.5V
REF to REF Skew 500 ps Measured at 1.5V
CLOCK GEN. with DDRI/II Buffer For VIA P4 SERIES CHIPSET
Publication Release Date: Apr. 2006
- 19 - Revision 0.6
W83195CG-920
9.4 CPU 0.7V Electrical Characteristics
VDDCPU= 3.3V
±
5 %, TA = 0
°
C to +70
°
C, Test load Rs=33, Rp=49.9 Cl=10pF, Vr=475,
IREF=2.32mA, Ioh=6*IREF
PARAMETER MIN MAX UNITS TEST CONDITIONS
Rise Time 175 700 ps 100 to 200 Mhz
Fall Time 175 700 ps 100 to 200Mhz
Absolute crossing point Voltages 250 550 mV 100 to 200Mhz
Cycle to Cycle jitter 150 ps 100 to 200Mhz
Duty Cycle 45 55 % 100 to 200Mhz
9.5 CPU 1.0V Electrical Characteristics
VDDCPU= 3.3V
±
5 %, TA = 0
°
C to +70
°
C, Test load Rs=33, Rp=49.9 Cl=10pF, Vr=221,
IREF=5mA, Ioh=4*IREF
Parameter Min Max Units Test Conditions
Rise Time 175 700 ps 100 to 200 Mhz
Fall Time 175 700 ps 100 to 200Mhz
Absolute crossing point Voltages 510 760 mV 100 to 200Mhz
Cycle to Cycle jitter 150 ps 100 to 200Mhz
Duty Cycle 45 55 % 100 to 200Mhz
9.6 AGP Electrical Characteristics
VDDAGP= 3.3V
±
5 %, TA = 0
°
C to +70
°
C, Test load, Cl=10pF,
PARAMETER MIN MAX UNITS TEST CONDITIONS
Rise Time 500 2000 ps Measure from 0.4V to 2.4V
Fall Time 500 2000 ps Measure from 2.4V to 0.4V
Cycle to Cycle jitter 250 ps Measure 1.5V point
Duty Cycle 45 55 %
Pull-Up Current Min -33 mA Vout=1.0V
Pull-Up Current Max -33 mA Vout=3.135V
Pull-Down Current Min 30 mA Vout=1.95V
Pull-Down Current Max 38 mA Vout=0.4V
CLOCK GEN. with DDRI/II Buffer For VIA P4 SERIES CHIPSET
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W83195CG-920
9.7 PCI Electrical Characteristics
VDDPCI= 3.3V
±
5 %, TA = 0
°
C to +70
°
C, Test load, Cl=10pF,
PARAMETER MIN MAX UNITS TEST CONDITIONS
Rise Time 500 2000 ps Measure from 0.4V to 2.4V
Fall Time 500 2000 ps Measure from 2.4V to 0.4V
Cycle to Cycle jitter 250 ps Measure 1.5V point
Duty Cycle 45 55 %
Pull-Up Current Min -33 mA Vout=1.0V
Pull-Up Current Max -33 mA Vout=3.135V
Pull-Down Current Min 30 mA Vout=1.95V
Pull-Down Current Max 38 mA Vout=0.4V
9.8 24M, 48M Electrical Characteristics
VDD48= 3.3V
±
5 %, TA = 0
°
C to +70
°
C, Test load, Cl=10pF,
PARAMETER MIN MAX UNITS TEST CONDITIONS
Rise Time 500 2000 ps Measure from 0.4V to 2.4V
Fall Time 500 2000 ps Measure from 2.4V to 0.4V
Long term jitter 500 ps Measure 1.5V point
Duty Cycle 45 55 %
Pull-Up Current Min -33 mA Vout=1.0V
Pull-Up Current Max -33 mA Vout=3.135V
Pull-Down Current Min 30 mA Vout=1.95V
Pull-Down Current Max 38 mA Vout=0.4V
9.9 REF Electrical Characteristics
VDDR= 3.3V
±
5 %, TA = 0
°
C to +70
°
C, Test load, Cl=10pF,
PARAMETER MIN MAX UNITS TEST CONDITIONS
Rise Time 1000 4000 ps Measure from 0.4V to 2.4V
Fall Time 1000 4000 ps Measure from 2.4V to 0.4V
Cycle to Cycle jitter 1000 ps Measure 1.5V point
Duty Cycle 45 55 %
Pull-Up Current Min -33 mA Vout=1.0V
Pull-Up Current Max -33 mA Vout=3.135V
Pull-Down Current Min 30 mA Vout=1.95V
Pull-Down Current Max 38 mA Vout=0.4V
CLOCK GEN. with DDRI/II Buffer For VIA P4 SERIES CHIPSET
Publication Release Date: Apr. 2006
- 21 - Revision 0.6
W83195CG-920
10. ORDERING INFORMATION
PART NUMBER PACKAGE TYPE PRODUCTION FLOW
W83195CG-920 56 PIN SSOP Commercial, 0°C to +70°C
11. HOW TO READ THE TOP MARKING
W83195CG-920
28051234
536GAABA
1st line: Winbond logo and the type number: W83195CG-920
2nd line: Tracking code 2 8051234
2: wafers manufactured in Winbond FAB 2
8051234: wafer production series lot number
3rd line: Tracking code 536 G A A BA
536: packages made in '2005, week 36
G: assembly house ID; O means OSE, G means GR
A: Internal use code
A: IC revision
BA: mask version
All the trade marks of products and companies mentioned in this data sheet belong to their
respective owners.
CLOCK GEN. with DDRI/II Buffer For VIA P4 SERIES CHIPSET
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W83195CG-920
12. PACKAGE DRAWING AND DIMENSIONS
E
e
b
Y
SEATING PLANE
c
L
c
L1
0
0.008
0.400
0.292
7.52
0
7.42
8
7.59
10.31
b
E
D
c
18.2
9
10.16
A1
A2
A
10.41
18.54
18.42
2.79
2.34
8
0.2990.296
0.092
0.110
0.410
0.720 0.7300.725
0.406
MIN.
DIMENSION IN INCH
SYMBOL
DIMENSION IN MM
MIN. NOM MAX. MAX.NOM
0.20
e
L
L1
Y
θ
0.008 0.0135
0.005 0.010
0.024 0.032
0.055
0.003
0.20 0.34
0.13 0.25
0.51 0.760.64 0.020 0.0300.025
0.61 0.81
1.40
0.08
HE
θ
θ
2.57 0.101
.045
.055
.035
.045
HE
0.40/0.50 DIA
TOP VIEW
END VIEW
SEE DETAIL "A"
PARTING LINE
SIDE VIEW
D
A1
A2 A
DETAIL"A"
0.095
0.012 0.016
0.088 0.090
0.010
0.040
2.41
0.30 0.41
2.24 2.29
0.25
1.02
CLOCK GEN. with DDRI/II Buffer For VIA P4 SERIES CHIPSET
Publication Release Date: Apr. 2006
- 23 - Revision 0.6
W83195CG-920
Please note that all data and specifications are subject to change without notice. All the trade marks
of products and companies mentioned in this data sheet belong to their respective owners.
Important Notice
Winbond products are not designed, intended, authorized or warranted for use as components
in systems or equipment intended for surgical implantation, atomic energy control
instruments, airplane or spaceship instruments, transportation instruments, traffic signal
instruments, combustion control instruments, or for other applications intended to support or
sustain life. Further more, Winbond products are not intended for applications wherein failure
of Winbond products could result or lead to a situation wherein personal injury, death or
severe property or environmental damage could occur.
Winbond customers using or selling these products for use in such applications do so at their
own risk and agree to fully indemnify Winbond for any damages resulting from such improper
use or sales.
