SiC781CD
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50 A, VRPower® Integrated Power Stage
DESCRIPTION
The SiC781 is an integrated power stage solution optimized
for synchronous buck applications to offer high current, high
efficiency and high power density performance. Packaged
in Vishay’s proprietary MLP 6 mm x 6 mm package, SiC781
enables voltage regulator designs to deliver currents up to
50 A per phase.
The internal power MOSFETs utilize Vishay’s
state-of-the-art trench MOSFET technology that delivers
industry benchmark performance to significantly reduce
switching and conduction losses.
The SiC781 incorporates an advanced MOSFET gate driver
IC that features high current driving capability, adaptive
dead-time control, an integrated bootstrap Schottky diode,
and a thermal warning (THWn) that alerts the system of
excessive junction temperature. This driver is compatible
with wide range of PWM controllers and supports tri-state
PWM logic (5 V) as well as zero current detection to improve
light load efficiency.
FEATURES
• Thermally enhanced PowerPAK® MLP66-40L package
• Industry benchmark MOSFET with integrated Schottky
diode
• Delivers up to 50 A continuous current
• Pin and functionally compatible with NCP5369N
• High frequency operation up to 1 MHz
• Optimized for 12 V input rail applications
• 5 V PWM logic with tri-state threshold
• Zero current detection and low side MOSFET turn off
during discontinuous mode
• Short PWM propagation delay (< 20 ns)
• Supports Intel PS2 requirement with ON Semiconductor’s
NCP5133 and NCP6133 controllers
• Thermal monitor flag
• Faster enable / disable
•V
CIN under voltage lock out (UVLO)
APPLICATIONS
• Synchronous buck converters
• Multi-phase VRDs for CPU, GPU and memory
• DC/DC POL modules
TYPICAL APPLICATION DIAGRAM
Fig. 1 - SiC781 Typical Application Diagram
PWM
controller
Gate
driver
5 V INPUT
OUTPUT
VCIN
DSBL#
PWM
THWn
V
DRV
GH
V
IN
BOOT
VSWH
P
GND
GL
C
GND
PHASE
ZCD_EN
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PINOUT CONFIGURATION
Fig. 2 - SiC781 Pin Configuration
PIN DESCRIPTION
PIN NUMBER NAME FUNCTION
1 ZCD_EN ZCD control. Active high
2V
CIN Supply voltage for internal logic circuitry
3V
DRV Supply voltage for internal gate driver
4 BOOT High-side driver bootstrap voltage
5, 37, P1 CGND Analog ground for the driver IC
6 GH High-side gate signal
7 PHASE Return path of high-side gate driver
8 to 14, P2 VIN Power stage input voltage. Drain of high-side MOSFET
15, 29 to 35, P3 VSWH Switch node of the power stage
16 to 28 PGND Power ground
36 GL Low-side gate signal
38 THWn Thermal warning open drain output
39 DSBL# Disable pin. Active low
40 PWM PWM control input
ORDERING INFORMATION
PART NUMBER PACKAGE MARKING CODE
SiC781CD-T1-GE3 PowerPAK MLP66-40L SiC781
SiC781DB Reference Board
ZCD_EN 1
VCIN 2
VDRV 3
BOOT 4
CGND 5
GH 6
PHASE 7
VIN 8
VIN 9
VIN 10
VIN 11
VIN 12
VIN 13
VIN 14
VSWH 15
PGND 16
PGND 17
PGND 18
PGND 19
PGND 20
28 PGND
27 PGND
26 PGND
25 PGND
24 PGND
23 PGND
22 PGND
21 PGND
30 VSWH
29 VSWH
31 VSWH
32 VSWH
33 VSWH
34 VSWH
35 VSWH
36 GL
37 CGND
38 THWn
39 DSBL#
40 PWM
P1
CGND
P2
VIN
P3
VSWH
Top view
1 ZCD_EN
2 VCIN
3 VDRV
4 BOOT
5 CGND
6 GH
7 PHASE
8 VIN
9 VIN
10 VIN
VIN 11
VIN 12
VIN 13
VIN 14
VSWH 15
PGND 16
PGND 17
PGND 18
PGND 19
PGND 20
PGND 28
PGND 27
PGND 26
PGND 25
PGND 24
PGND 23
PGND 22
PGND 21
VSWH 30
VSWH 29
31 VSWH
32 VSWH
33 VSWH
34 VSWH
35 VSWH
36 GL
37 CGND
38 THWn
39 DSBL#
40 PWM
Bottom view
P1
CGND
P2
VIN
P3
VSWH
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Notes
• Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
(1) The specification values indicate “AC voltage” is VSWH to PGND, -7 V (< 50 ns, 10 µJ), minimum and 27 V (< 50 ns), maximum.
(2) The specification value indicates “AC voltage” is VBOOT to PGND, 34 V (< 50 ns) maximum.
(3) The specification value indicates “AC voltage” is VBOOT to VPHASE, 8 V (< 20 ns) maximum.
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL PARAMETER SYMBOL LIMITS UNIT
Input Voltage VIN -0.3 to +20
V
Control Logic Supply Voltage VCIN -0.3 to +7
Drive Supply Voltage VDRV -0.3 to +7
Switch Node (DC voltage) VSWH
-0.3 to +20
Switch Node (AC voltage) (1) -7 to +27
BOOT Voltage (DC voltage) VBOOT
27
BOOT Voltage (AC voltage) (2) 34
BOOT to PHASE (DC voltage) VBOOT_PHASE
-0.3 to +7
BOOT to PHASE (AC voltage) (3) -0.3 to +8
All Logic Inputs and Outputs (PWM,
DSBL#, ZCD_EN and THWn) -0.3 to VCIN + 0.3
Max. Operating Junction Temperature TJ150
°CAmbient Temperature TA-40 to +125
Storage Temperature Tstg -65 to +150
Electrostatic Discharge Protection Human body model, JESD22-A114 4000 V
Charged device model, JESD22-C101 1000
RECOMMENDED OPERATING RANGE
ELECTRICAL MIN. TYP. MAX. UNIT
Input Voltage (VIN)4.5-16
V
Drive Supply Voltage (VDRV) 4.5 5 5.5
Control Logic Supply Voltage (VCIN) 4.5 5 5.5
Switch Node (VSWH, DC voltage) - - 20
BOOT to PHASE (VBOOT_PHASE, DC voltage) 4 4.5 5.5
Thermal Resistance
Thermal Resistance from Junction to Case - 2.5 - °C/W
Thermal Resistance from Junction to PAD - 1 -
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ELECTRICAL SPECIFICATIONS
PARAMETER SYMBOL
TEST CONDITIONS
UNLESS OTHERWISE SPECIFIED
(DSBL# = ZCD_EN = 5 V, VIN = 12 V,
VDRV = VCIN = 5 V, TA = 25 °C)
MIN. TYP. (1) MAX. UNIT
POWER SUPPLIES
Control Logic Supply Current IVCIN
VDSBL# = 0 V, no switching -85-
A
VDSBL# = 5 V, no switching - 275 -
VDSBL# = 5 V, fs = 300 kHz, D = 0.1 - 300 -
Drive Supply Current IVDRV
fs = 300 kHz, D = 0.1 -1524
mA
fs = 1 MHz, D = 0.1 -45-
VDSBL# = 0 V, no switching -35-µA
VDSBL# = 5 V, no switching -45-
BOOTSTRAP SUPPLY
Bootstrap Switch Forward Voltage VFIF = 2 mA --0.4V
PWM CONTROL INPUT
Rising Threshold VTH_PWM_R 3.4 3.7 4.2
V
Falling Threshold VTH_PWM_F 0.7 0.9 1.2
Tri-state Rising Threshold VTH_TRI_R 0.9 1.2 1.5
Tri-state Falling Threshold VTH_TRI_F 33.43.7
Tri-state Rising Threshold Hysteresis VHYS_TRI_R - 250 - mV
Tri-state Falling Threshold Hysteresis VHYS_TRI_F - 350 -
DRIVER TIMING
Tri-state to GH/GL Rising Propagation Delay tPD_TRI_R -30-
ns
Tri-state GH Hold-Off Time tTSHO_GH PWM high to tri-state - 35 -
Tri-state GL Hold-Off Time tTSHO_GL PWM low to tri-state - 120 -
GH - Turn Off Propagation Delay tPD_OFF_GH -20-
GH - Turn On Propagation Delay
(Dead time rising) tPD_ON_GH -8-
GL - Turn Off Propagation Delay tPD_OFF_GL -12-
GL - Turn On Propagation Delay
(Dead time falling) tPD_ON_GL -8-
DSBL# High to GH/GL Rising Propagation
Delay tPD_DSBL#_R Fig. 5 - 20 -
DSBL# Low to GH/GL Falling Propagation
Delay tPD_DSBL#_F -15-
DSBL#, ZCD_EN INPUT
DSBL# Logic Input Voltage VIH_DSBL# Input logic high 2 - -
V
VIL_DSBL# Input logic low - - 0.8
ZCD_EN Logic Input Voltage
VIH_ZCD_EN Input logic high 2 - -
VIL_ZCD_EN Input logic low - - 0.8
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Notes
(1) Typical limits are established by characterization and are not production tested.
(2) Guaranteed by design.
Note
(1) In this condition (PS2 mode), controller will deliver PWM signal switching between 5 V and 2 V. See the timing diagram in fig. 3.
Fig. 3 - Timing Diagram
PROTECTION
Under Voltage Lockout VUVLO
VCIN rising, on threshold -3.74.3V
VCIN falling, off threshold 2.7 3.2 -
Under Voltage Lockout Hysteresis VUVLO_HYST - 500 - mV
THWn Flag Set (2) TTHWn_SET - 160 -
°C
THWn Flag Clear (2) TTHWn_CLEAR - 135 -
THWn Flag Hysteresis (2) TTHWn_HYST -25-
THWn Output Low VOL_THWn ITHWn = 2 mA -0.02- V
DEVICE TRUTH TABLE
DSBL# ZCD_EN PWM GH GL
Open X X L L
LXXLL
HLHHL
HLTri-stateLL
HLLLL
HHHHL
H H H to tri-state (1) LH, IL > 0 A
L, IL < 0 A
HHL LH
H H L to tri-state L L
ELECTRICAL SPECIFICATIONS
PARAMETER SYMBOL
TEST CONDITIONS
UNLESS OTHERWISE SPECIFIED
(DSBL# = ZCD_EN = 5 V, VIN = 12 V,
VDRV = VCIN = 5 V, TA = 25 °C)
MIN. TYP. (1) MAX. UNIT
PWM
GH
GL
ZCD_EN
IL
High Low
0 A
IL= 0 A
GL is OFF when ZCD_EN
is LO
High
Zero current detect enable by
PWM to tri-state transition
Normal tri -state
operation
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DETAILED OPERATIONAL DESCRIPTION
PWM Input with Tri-state Function
The PWM input receives the PWM control signal from the VR
controller IC. The PWM input is designed to be compatible
with standard controllers using two state logic (H and L) and
advanced controllers that incorporate tri-state logic (H, L
and tri-state) on the PWM output. PWM input operates as
follows for two state logic. When PWM is driven above
VTH_PWM_R the low-side is turned off and the high-side is
turned on. When PWM input is driven below VTH_PWM_F the
high-side turns off and the low-side turns on. For tri-state
logic, the PWM input operates as above for driving the
MOSFETs. However, if the PWM input stays tri-state for the
tri-state hold-off period, tTSHO, both high-side and low-side
MOSFETs are turned off. This function allows the VR phase
to be disabled without negative output voltage swing
caused by inductor ringing and saves a Schottky diode
clamp. The PWM and tri-state regions are separated by
hysteresis to prevent false triggering.
The SiC781CD incorporates PWM voltage thresholds that
are compatible with 5 V logic.
Disable (DSBL#)
In the low-state, the DSBL# pin shuts down the driver IC and
disables both high-side and low-side MOSFETs. In this
state, the standby current is minimized. If DSBL# is left
unconnected an internal pull-down resistor will pull the pin
down to CGND and shut down the IC.
Diode Emulation Mode (ZCD_EN)
When ZCD_EN pin is high and PWM signal switches from
High to tri-state, GL is forced on (after normal BBM time) for
the duration of tri-state period. During this time, it is under
control of the ZCD (zero crossing detect) comparator. If,
after the internal blanking delay, the inductor current
becomes zero, GL is turned off. This improves light load
efficiency by avoiding discharge of output capacitors.
If PWM enters tri-state from Low, then device will go into
normal tri-state mode after tri-state delay. If ZCD_EN pin is
Low the GL output will be turned off regardless of Inductor
current, this is an alternative method of improving light load
efficiency by reducing switching losses.
This mode of operation is critical to meet improved
efficiencies required in Intel’s PS2 mode of operation for
memory and processor applications.
Thermal Warning (THWn)
The THWn pin is an open drain signal that flags the presence
of excessive junction temperature. Connect a maximum of
20 kΩ to pull this pin up to V
CIN. An internal temperature
sensor detects the junction temperature. The temperature
threshold is 160 °C. When this junction temperature is
exceeded the THWn flag is set. When the junction
temperature drops below 135 °C the device will clear the
THWn signal. The SiC781 does not stop operation when the
flag is set. The decision to shutdown must be made by an
external thermal control function.
Voltage Input (VIN)
This is the power input to the drain of the high-side
power MOSFET. This pin is connected to the high power
intermediate BUS rail.
Switch Node (VSWH and PHASE)
The switch node, VSWH, is the circuit power stage output.
This is the output applied to the power inductor and output
filter to deliver the output for the buck converter.
The PHASE pin is internally connected to the switch node
VSWH. This pin is to be used exclusively as the return pin for
the BOOT capacitor. A 20 kΩ resistor is connected between
GH and PHASE to provide a discharge path for the HS
MOSFET in the event that VCIN goes to zero while VIN is still
applied.
Ground Connections (CGND and PGND)
PGND (power ground) should be externally connected to
CGND (control signal ground). The layout of the printed circuit
board should be such that the inductance separating CGND
and PGND is minimized. Transient differences due to
inductance effects between these two pins should not
exceed 0.5 V.
Control and Drive Supply Voltage Input (VDRV, VCIN)
VCIN is the bias supply for the gate drive control IC. VDRV is
the bias supply for the gate drivers. It is recommended to
separate these pins through a resistor. This creates a low
pass filtering effect to avoid coupling of high frequency gate
driver noise into the IC.
Bootstrap Circuit (BOOT)
An integrated bootstrap diode is incorporated so that only
an external capacitor is necessary to complete the
bootstrap circuit. Connect a bootstrap capacitor with one
leg tied to BOOT pin and the other tied to PHASE pin.
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Shoot-Through Protection and Adaptive Dead Time
(AST)
The SiC781 has an internal adaptive logic to avoid shoot
through and optimize dead time. The shoot through
protection ensures that both high-side and low-side
MOSFETs are not turned on at the same time. The adaptive
dead time control operates as follows. The HS and LS gate
voltages are monitored to prevent the one turning on from
tuning on until the other’s gate voltage is sufficiently low
(< 1 V). Built in delays also ensure that one power MOS is
completely off, before the other can be turned on. This
feature helps to adjust dead time as gate transitions change
with respect to output current and temperature.
Under Voltage Lockout (UVLO)
During the start up cycle, the UVLO disables the gate drive
holding high-side and low-side MOSFET gate low until the
input voltage rail has reached a point at which the logic
circuitry can be safely activated. The SiC781 also
incorporates logic to clamp the gate drive signals to zero
when the UVLO falling edge triggers the shutdown of
the device. As an added precaution, a 20 kΩ resistor is
connected between GH and PHASE to provide a discharge
path for the HS MOSFET.
FUNCTIONAL BLOCK DIAGRAM
Fig. 4 - SiC781 Functional Block Diagram
PWM
CGND
20K
BOOT GH
V
SWH
GLPGND
+
-
V
ref
= 1 V
V
ref
= 1 V
GL
+
-
Anti-cross
conduction
control logic
V
DRV
PWM logic
control & state
machine
UVLO
Thermal monitor
& warning
THWn
ZCD_EN
VIN
PHASE
+
-
VSWH
V
SWH
VCIN
DSBL #
V
DRV
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OPERATION TIMING DIAGRAM: DSBL#
Fig. 5 - DSBL# Propagation Delay
PWM
DSBL #
GH
GL
t
PWM
DSBL #
GH
GL
t
DSBL# High to GH Rising Propagation Delay DSBL# High to GL R i sing Propagation Delay
Enable
PWM
DSBL #
GH
GL
DSBL# Low to GH Falling Propagation Delay
t
DSBL# Low to GL Falling Propagation Delay
PWM
DSBL #
GH
GL
t
Disable
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ELECTRICAL CHARACTERISTICS
(VIN = 12 V, FSW = 500 kHz, VDRV = VCIN = 5 V, unless noted otherwise), LO/P = 0.33 µH / DCR 0.83 mΩ (IHLP5050FD0R33-01)
Fig. 6 - Efficiency vs. IOUT
(Complete converter efficiency, PIN = [VIN x IIN + 5 V x (IDRV + ICIN )], POUT = VOUT x IOUT measured at output capacitor)
Fig. 7 - Power Losses vs. IOUT
(Includes losses dissipated in the SiC781 only)
78
80
82
84
86
88
90
92
94
0 4 8 1216202428323640
Efciency (%)
IOUT (A)
VOUT = 1.5 V; FCCM
VOUT = 1.35 V; FCCM
VOUT = 1.35 V; ZCD
0
1
2
3
4
5
6
7
8
9
10
0 4 8 12 16 20 24 28 32 36 40
Power Loss (W)
IOUT (A)
VOUT = 1.5 V; FCCM
VOUT = 1.35 V; FCCM
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Fig. 8 - PS2 Mode Operation (ZCD)
CH1 (green) = PWM (2V/div), CH2 (red) = GH (5V/div), CH3 (yellow) = GL (5V/div), CH4 (blue) = VSWH (5V/div)
RECOMMENDED LAND PATTERN PowerPAK MLP66-40L
CH1
CH2
CH3
CH4
1
1
0.025
0.100
0.100
0.100
0.100
0.025
40
0.100 0.100
0.100 0.100 0.100 0.100
0.600
2.600 1.700
0.320
0.310
40
2.200 2.200
0.276 0.276
0.200
4.600
All Dimensions are in milimeters
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PACKAGE OUTLINE DRAWING
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?62950.
40
1
2 x
2 x
Pin 1 dot
by marking
MLP66-40L
(6 mm x 6 mm)
10
1120
21
30
31
56
4
Top view
Bottom view
Side view
A
B
C
D
0.10 C B
E
0.10 C A A0.08 C
A1
A2 0.41 K2
K1
D2-1 Pin #1 dent
E2-1
e
D2-3 D2-2
E2-3 E2-2
(Nd-1)X
e
ref.
(Nd-1)X
e
ref.
0.10 M C A B
DIM.
MILLIMETERS INCHES
MIN. NOM. MAX. MIN. NOM. MAX.
A 0.70 0.75 0.80 0.027 0.029 0.031
A1 0.00 - 0.05 0.000 - 0.002
A2 0.20 ref. 0.008 ref.
b 0.20 0.25 0.30 0.078 0.098 0.011
D 6.00 BSC 0.236 BSC
e 0.50 BSC 0.019 BSC
E 6.00 BSC 0.236 BSC
L 0.35 0.40 0.45 0.013 0.015 0.017
N40 40
Nd 10 10
Ne 10 10
D2-1 1.45 1.50 1.55 0.057 0.059 0.061
D2-2 1.45 1.50 1.55 0.057 0.059 0.061
D2-3 2.35 2.40 2.45 0.095 0.094 0.096
E2-1 4.35 4.40 4.45 0.171 0.173 0.175
E2-2 1.95 2.00 2.05 0.076 0.078 0.080
E2-3 1.95 2.00 2.05 0.076 0.078 0.080
K1 0.73 BSC 0.028 BSC
K2 0.21 BSC 0.008 BSC
Package Information
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PowerPAK® MLP66-40 Case Outline
Notes
1. Use millimeters as the primary measurement
2. Dimensioning and tolerances conform to ASME Y14.5M. - 1994
3. N is the number of terminals. Nd is the number of terminals in X-direction and Ne is the number of terminals in Y-direction
4. Dimension b applies to plated terminal and is measured between 0.20 mm and 0.25 mm from terminal tip
5. The pin #1 identifier must be existed on the top surface of the package by using indentation mark or other feature of package body
6. Exact shape and size of this feature is optional
7. Package warpage max. 0.08 mm
8. Applied only for terminals
DIM.
MILLIMETERS INCHES
MIN. NOM. MAX. MIN. NOM. MAX.
A (8) 0.70 0.75 0.80 0.027 0.029 0.031
A1 0.00 - 0.05 0.000 - 0.002
A2 0.20 ref. 0.008 ref.
b (4) 0.20 0.25 0.30 0.078 0.098 0.011
D 6.00 BSC 0.236 BSC
e 0.50 BSC 0.019 BSC
E 6.00 BSC 0.236 BSC
L 0.35 0.40 0.45 0.013 0.015 0.017
N (3) 40 40
Nd (3) 10 10
Ne (3) 10 10
D2-1 1.45 1.50 1.55 0.057 0.059 0.061
D2-2 1.45 1.50 1.55 0.057 0.059 0.061
D2-3 2.35 2.40 2.45 0.095 0.094 0.096
E2-1 4.35 4.40 4.45 0.171 0.173 0.175
E2-2 1.95 2.00 2.05 0.076 0.078 0.080
E2-3 1.95 2.00 2.05 0.076 0.078 0.080
K1 0.73 BSC 0.028 BSC
K2 0.21 BSC 0.008 BSC
ECN: T14-0826-Rev. B, 12-Jan-15
DWG: 5986
40
1
2 x
2 x
Pin 1 dot
by marking
MLP66-40
(6 mm x 6 mm)
10
1120
21
30
31
56
4
Top View Bottom View
Side View
A
B
C
D
0.10 C B
E
0.10 C A A0.08 C
A1
A2 0.41
K2
K1
D2-1
E2-1
e
D2-3 D2-2
E2-3 E2-2
(Nd-1)X
e
ref.
(Nd-1)X
e
ref.
0.10
M
C A B
PAD Patter n
www.vishay.com Vishay Siliconix
Revision: 28-Feb-14 1Document Number: 67964
For technical questions, contact: analogswitchtechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Recommended Land Pattern PowerPAK® MLP66-40L
1
1
0.025
0.100
0.100
0.100
0.100
0.025
40
0.100 0.100
0.100 0.100 0.100 0.100
0.600
2.600 1.700
0.320
0.310
40
2.200 2.200
0.276 0.276
0.200
4.600
All Dimensions are in milimeters
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Revision: 08-Feb-17 1Document Number: 91000
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