Product
Technology
F r o m
SA306A
SA306U 1
SA306, SA306A
DESCRIPTION
The SA306 is a fully integrated switching amplier
designed primarily to drive three-phase Brushless
DC (BLDC) motors. Three independent half bridges
provide over 15 amperes peak output current under
microcontroller or DSC control. Thermal and short cir-
cuit monitoring is provided, which generates fault sig-
nals for the microcontroller to take appropriate action.
A block diagram is provided in Figure 1.
Additionally, cycle-by-cycle current limit offers user
programmable hardware protection independent of the
microcontroller. Output current is measured using an
innovative low loss technique. The SA306 is built using
a multi-technology process allowing CMOS logic con-
trol and complementary DMOS output power devices
on the same IC. Use of P-channel high side FETs en-
ables 60V operation without bootstrap or charge pump
circuitry.
The HSOP surface mount package balances excellent
thermal performance with the advantages of a low pro-
le surface mount package.
FEATURES
♦ Low cost 3 phase intelligent switching amplier
♦ Directly connects to most embedded Micro-
controllers and Digital Signal Controllers
♦ Integrated gate driver logic with dead-time
generation and shoot-through prevention
♦ Wide power supply range (8.5V to 60V)
♦ Over 15A peak output current per phase
♦ Independent current sensing for each output
♦ User programmable cycle-by-cycle current
limit protection
♦ Over-current and over-temperature warning
signals
APPLICATIONS
♦ 3 phase brushless DC motors
♦ Multiple DC brush motors
♦ 3 independent solenoid actuators
3 Phase Switching Amplifier
SA306A
Product Innovation From
FIGURE1.BLOCKDIAGRAM
SA306 Switching Amplifier
V
S
(phase A)
P G N D ( A & B )
Gate
Control
PWM
Signals
A
B
C
O ut A
O ut B
O ut C
P G N D (C )
T E M P
GND
V
S
(phase B& C )
V
S
+
I
LIM
/D IS 1
S C
D IS 2
S G N D
P hase A
P hase C
P hase B
Control
Logic
V
DD
Ia' Ib' Ic'
Ia'
Ib'
Ic'
Fault
Logic
Ia
Ic
Ib
A t
A b
B t
B b
C t
C b
V
DD
V
DD
V
DD
Copyright © Cirrus Logic, Inc. 2011
(All Rights Reserved)
www.cirrus.com
MAR2011
APEX-SA306UREVG
Product
Technology
F r o m
SA306A
2 SA306U
1.CHARACTERISTICSANDSPECIFICATIONS
ABSOLUTEMAXIMUMRATINGS
Parameter Symbol Min Max Units
SUPPLY VOLTAGE VS60 V
SUPPLY VOLTAGE VDD 5.5 V
LOGIC INPUT VOLTAGE (-0.5) (VDD+0.5) V
OUTPUT CURRENT, peak, 10ms (Note 2) IOUT 17 A
POWER DISSIPATION, avg, 25ºC (Note 2) PD100 W
TEMPERATURE, junction (Note 3) TJ150 °C
TEMPERATURE RANGE, storage TSTG −65 125 °C
OPERATING TEMPERATURE, case TA−40 125 °C
Parameter TestConditions2Min Typ Max Units
LOGIC
INPUT LOW 0.8 V
INPUT HIGH 2.0 V
OUTPUT LOW 0.3 V
OUTPUT HIGH 3.7 V
OUTPUT CURRENT
(SC, Temp, ILIM/DIS1) 50 mA
POWERSUPPLY
VSUVLO 50 60 V
VS UNDERVOLTAGE LOCKOUT,
(UVLO) 9 V
VDD 4.5 5.5 V
SUPPLY CURRENT, VS
20 kHz (One phase switching at
50% duty cycle) , VS=50V, VDD=5V 25 30 mA
SUPPLY CURRENT, VDD
20 kHz (One phase switching at
50% duty cycle) , VS=50V, VDD=5.5V 5 6.5 mA
CURRENTLIMIT
CURRENT LIMIT THRESHOLD (Vth) 3.95 V
Vth HYSTERESIS 100 mV
OUTPUT
CURRENT, CONTINUOUS 25ºC Case Temperature 8 A
RISING DELAY, TD(RISE) See Figure 10 270 ns
FALLING DELAY, TD(FALL) See Figure 10 270 ns
DISABLE DELAY, TD(DIS) See Figure 10 200 ns
ENABLE DELAY, TD(DIS) See Figure 10 200 ns
RISE TIME, T(RISE) See Figure 11 50 ns
FALL TIME, T(FALL) See Figure 11 50 ns
ON RESISTANCE
SOURCING (P-CHANNEL) 5A Load 300 600 mΩ
ON RESISTANCE
SINKING (N-CHANNEL) 5A Load 250 600 mΩ
SPECIFICATIONS
Product
Technology
F r o m
SA306A
SA306U 3
NOTES: 1. (All Min/Max characteristics and specications are guaranteed over the Specied Operating Condi-
tions. Typical performance characteristics and specications are derived from measurements taken
at typical supply voltages and TC = 25°C).
2. Long term operation at elevated temperature will result in reduced product life. De-rate internal power
dissipation to achieve high MTBF.
3. Output current rating may be limited by duty cycle, ambient temperature, and heat sinking. Under any
set of conditions, do not exceed the specied current rating or a junction temperature of 150°C.
Parameter TestConditions2Min Typ Max Units
THERMAL
THERMAL WARNING 135 ºC
THERMAL WARNING
HYSTERESIS 40 ºC
RESISTANCE, junction to case Full temperature range 1.25 1.5 ºC/W
TEMPERATURE RANGE, case Meets Specications -40 +125 ºC
Figure2A.
44-PinHSOPSlug-Up,PackageStyleHU
SPECIFICATIONS,continued
Figure2B.
44-PinHSOPSlug-Down,PackageStyleHR
Product
Technology
F r o m
SA306A
4 SA306U
DIODE FORWARD VOLTAGE - TOP FET
(P-Channel)
0
1
2
3
4
5
FORWARD VOLTAGE (V)
CURRENT (A)
0.5 1.51.31.10.90.7
DIODE FORWARD VOLTAGE - BOTTOM FET
(N-Channel)
0
1
2
3
4
5
FORWARD VOLTAGE (V)
CURRENT (A)
0.5 1.51.31.10.90.7
ON RESISTANCE - TOP FET
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
0.55
0.6
0.65
0.7
0.75
0.8
IOUT,(A)
RDS(on),(Ω)
VS=11
VS=13
VS=15
VS>17
100 987654321
(P-Channel)
ON RESISTANCE - BOTTOM FET
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
0.55
0.6
0.65
0.7
0.75
0.8
10
IOUT,(A)
RDS(on),(Ω)
VS=11
VS=13
VS=15
VS=17
VS>22
0 987654321
(N-Channel)
POWER DERATING
0
20
40
60
80
100
120
CASE TEMPERATURE, TC
POWER DISSIPATION, PD
-40 12080400
VDD SUPPLY CURRENT
4.5
4.6
4.7
4.8
4.9
5
0 50 100 150 200 250 300
FREQUENCY (kHz)
VDD SUPPLY CURRENT (mA)
ONE PHASE SWITCHING @
50% DUTY CYCLE; VS=50V
VDD SUPPLY CURRENT
4
4.5
5
5.5
6
6.5
7
7.5
8
10 20 30 40 50 60
VS SUPPLY VOLTAGE (V)
VDD SUPPLY CURRENT (mA)
ONE PHASE SWITCHING
FREQUENCY = 20kHz
50% DUTY CYCLE
25°C
125°C
CURRENT SENSE
0.1
1
10
0.01 0.1 1 10
SENSE CURRENT (mA)
LOAD CURRENT (A)
VS SUPPLY CURRENT
20
40
60
80
100
120
140
160
180
0 50 100 150 200 250 300
FREQUENCY (kHz)
V
S
SUPPLY CURRENT (mA)
ONE PHASE SWITCHING @
50% DUTY CYCLE; VS=50V
0
V
S
SUPPLY CURRENT
0
5
10
15
20
25
V
S
SUPPLY VOLTAGE (V)
V
S
SUPPLY CURRENT (mA)
125°C
25°C
ONE PHASE SWITCHING
FREQUENCY = 20kHz
50% DUTY CYCLE
10 20 30 40 50 60
Product
Technology
F r o m
SA306A
SA306U 5
Figure3A.ExternalConnections
44-pinHSOP,Slug-Up,HUPkg
Table1.PinDescriptions-44-pinHSOP,HR&HUPkg.
Pin# PinName SignalType SimpliedPinDescription
25,26,27 VS (phase A) Power High Voltage Supply (8.5-60V) supplies phase A only
38,39 OUT C Power Output Half Bridge C Power Output
40,41,42 PGND (phase C) Power High Current GND Return Path for Power Output C
8 SC Logic Output Indication of a short of an output to supply, GND or another phase
5 Cb Logic Input Logic high commands C phase lower FET to turn on
6 Ct Logic Input Logic high commands C phase upper FET to turn on
7 IC Analog Output Phase C current sense output
9 IB Analog Output Phase B current sense output
10 ILIM/DIS1 Logic Input/Output
As an output, logic high indicates cycle-by-cycle current limit, and
logic low indicates normal operation. As an input, logic high places
all outputs in a high impedance state and logic low disables the
cycle-by-cycle current limit function.
11 SGND Power Analog and digital GND – internally connected to PGND
12 Bt Logic Input Logic high commands B phase upper FET to turn on
13 Bb Logic Input Logic high commands B phase lower FET to turn on
14 Ab Logic Input Logic high commands A phase lower FET to turn on
15 At Logic Input Logic high commands A phase upper FET to turn on
16 VDD Power Logic Supply (5V)
17 IA Analog Output Phase A current sense output
18 DIS2 Logic Input Logic high places all outputs in a high impedance state
19 TEMP Logic Output Thermal indication of die temperature above 135ºC
33,34 OUT B Power Output Half Bridge B Power Output
35,36,37 VS (phase B&C) Power High Voltage Supply phase B & C
28,29 OUT A Power Output Half Bridge A Power Output
30,31,32 PGND (phase A&B) Power High Current GND Return Path for Power Outputs A & B
Figure3B.ExternalConnections
44-pinHSOP,Slug-Down,HRPkg.
NC
NC
NC
TEMP
DIS2
IA
Vdd
At
Ab
Bb
Bt
SGND
Ilim/DIS1
IB
SC
IC
Ct
Cb
NC
NC
NC
NC
SA306AHU-FH
XXXXXXXXXXXX COO
22 23
44
1
PIN #1 ID’s:
CHAMFER, ESD Triangle
TOP (SLUG) VIEW
HS
NC
VSA
VSA
VSA
OUTA
OUTA
PGNDA/B
PGNDA/B
PGNDA/B
OUTB
OUTB
VSB/C
VSB/C
VSB/C
OUTC
OUTC
PGNDC
PGNDC
PGNDC
NC
HS
NC
NC
NC
NC
Cb
Ct
IC
SC
IB
Ilim/DIS1
SGND
Bt
Bb
Ab
At
Vdd
IA
DIS2
TEMP
NC
NC
NC 22 23
44
1
PIN #1 ID’s:
CHAMFER, DIMPLE, ESD TRIANGLE
HS
NC
PGNDC
PGNDC
PGNDC
OUTC
OUTC
VSB/C
VSB/C
VSB/C
OUTB
OUTB
PGNDA/B
PGNDA/B
PGNDA/B
OUTA
OUTA
VSA
VSA
VSA
NC
HS
TOP VIEW
SA306AHR-FH
XXXXXXXXXXXX
COO
Product
Technology
F r o m
SA306A
6 SA306U
Table1.PinDescriptions-44-pinHSOP,HR&HUPkg.
Pin# PinName SignalType SimpliedPinDescription
23,44 HS Mechanical Pins connected to the package heat slug
1,2,3,4,20,
21,22,24,43 NC --- Do Not Connect
1.2PinDescriptions
VS:Supply voltage for the output transistors. These pins require decoupling (1μF capacitor with good high frequen-
cy characteristics is recommended) to the PGND pins. The decoupling capacitor should be located as close to
the VS and PGND pins as possible. Additional capacitance will be required at the VS pins to handle load current
peaks and potential motor regeneration. Refer to the applications section of this datasheet for additional discus-
sion regarding bypass capacitor selection. Note that VS (phase A) pins carry only the phase A supply current. VS
(phase B&C) carry supply current for phases B & C. Phase A may be operated at a different supply voltage from
phases B & C. Only the B & C supply pins are monitored for undervoltage conditions.
OUTA,OUTB,OUTC:These pins are the power output connections to the load. NOTE: When driving an induc-
tive load, it is recommended that two Schottky diodes with good switching characteristics (fast tRR specs) be
connected to each pin so that they are in parallel with the parasitic back-body diodes of the output FETs. (See
Section 2.6)
PGND:Power Ground. This is the ground return connection for the output FETs. Return current from the load ows
through these pins. PGND is internally connected to SGND through a resistance of a few ohms. See section 2.1
of this datasheet for more details.
SC:Short Circuit output. If a condition is detected on any output which is not in accordance with the input com-
mands, this indicates a short circuit condition and the SC pin goes high. The SC signal is blanked for approxi-
mately 200ns during switching transitions but in high current applications, short glitches may appear on the SC
pin. A high state on the SC output will not automatically disable the device. The SC pin includes an internal 12kΩ
series resistor.
Ab,Bb,Cb:These Schmitt triggered logic level inputs are responsible for turning the associated bottom, or lower
N-channel output FETs on and off. Logic high turns the bottom N-channel FET on, and a logic low turns the low
side N-channel FET off. If Ab, Bb, or Cb is high at the same time that a corresponding At, Bt, or Ct input is high,
protection circuitry will turn off both FETs in order to prevent shoot-through current on that output phase. Protec-
tion circuitry also includes a dead-time generator, which inserts dead time in the outputs in the case of simultane-
ous switching of the top and bottom input signals.
At,Bt,Ct:These Schmitt triggered logic level inputs are responsible for turning the associated top side, or upper
P-channel FET outputs on and off. Logic high turns the top P-channel FET on, and a logic low turns the top P-
channel FET off.
Ia,Ib,Ic:Current sense pins. The SA306 supplies a positive current to these pins which is proportional to the cur-
rent owing through the top side P-channel FET for that phase. Commutating currents owing through the back-
body diode of the P-channel FET or through external Schottky diodes are not registered on the current sense
pins. Nor do currents owing through the low side N-channel FET, in either direction, register at the current sense
pins. A resistor connected from a current sense pin to SGND creates a voltage signal representation of the phase
current that can be monitored with ADC inputs of a processor or external circuitry.
The current sense pins are also internally compared with the current limit threshold voltage reference, Vth. If
the voltage on any current sense pin exceeds Vth, the cycle by cycle current limit circuit engages. Details of this
functionality are described in the applications section of this datasheet.
ILIM/DIS1: This pin is directly connected to the disable circuitry of the SA306. Pulling this pin to logic high places OUT
A, OUT B, and OUT C in a high impedance state. This pin is also connected internally to the output of the current
limit latch through a 12kΩ resistor and can be monitored to observe the function of the cycle-by-cycle current limit
feature. Pulling this pin to a logic low effectively disables the cycle-by-cycle current limit feature.
SGND:This is the ground return connection for the VDD logic power supply pin. All internal analog and logic circuitry
is referenced to this pin. PGND is internally connected to GND through a resistance of a few ohms,. However, it
is highly recommended to connect the GND pin to the PGND pins externally as close to the device as possible.
Failure do to this may result in oscillations on the output pins during rising or falling edges.
Product
Technology
F r o m
SA306A
SA306U 7
VDD:This is the connection for the 5V power supply, and provides power for the logic and analog circuitry in the
SA306. This pin requires decoupling (at least 0.1µF capacitor with good high frequency characteristics is recom-
mended) to the SGND pin.
DIS2: The DIS2 pin is a Schmitt triggered logic level input that places OUT A, OUT B, and OUT C in a high imped-
ance state when pulled high. DIS2 has an internal 12kΩ pull-down resistor and may therefore be left uncon-
nected.
TEMP:This logic level output goes high when the die temperature of the SA306 reaches approximately 135ºC. This
pin WILL NOT automatically disable the device. The TEMP pin includes a 12kΩ series resistor.
HS:These pins are internally connected to the thermal slug on the reverse of the package. They should be con-
nected to GND. Neither the heat slug nor these pins should be used to carry high current.
NC:These “no-connect” pins should be left unconnected.
2.SA306OPERATION
The SA306 is designed primarily to drive three phase motors. However, it can be used for any application requir-
ing three high current outputs. The signal set of the SA306 is designed specically to interface with a DSP or
microcontroller. A typical system block diagram is shown in the gure below. Over-temperature, Short-Circuit and
Current Limit fault signals provide important feedback to the system controller which can safely disable the output
drivers in the presence of a fault condition. High side current monitors for all three phases provide performance
information which can be used to regulate or limit torque.
Figure4.SystemDiagram
The block diagram in Figure 5 illustrates the features of the input and output structures of the SA306. For simplicity,
a single phase is shown.
SA306 Switching Amplifier
BRUSHLESS
MOTOR
VS (phase A)
PGND (A&B)
Current
monitor
Signals
Sensor – Hall Sensors
or
Sensorless – Input from Stator leads
A
B
C
OUT A
OUT B
OUT C
PGND (C)
GND
VS (phase B&C)
VS +
Sensing
circuits
GND
SGND
Gate
Control
Control
Logic
Fault
Logic
T E M P
I
LIM
/D IS 1
S C
IA
IC
IB
V
DD
PWM
Signals
D IS 2
S G N D
A t
A b
B t
B b
C t
C b
M ic ro con troller
or DSC
Product
Technology
F r o m
SA306A
8 SA306U
Figure5.Inputandoutputstructuresforasinglephase
SGND
Gate
Control
VS
OUT A
PGND
At
Ab
SC
TEMP
SC
Logic
Temp
Sense
Ref
Ia
DIS2
ILIM/DIS1
UVLO
Ia'
+
_
Lim b
Lim c
+
_
VDD
Lim a
Current
Sense
12k
12k
12k
12k
Vth
Table2.TruthTable
At, Bt, Ct
Ab, Bb, Cb
Ia, Ib, Ic
ILIM/DIS1
DIS2
OUT A,
OUT B,
OUT C
Comments
0 0 X X X High-Z Top and Bottom output FETs for that phase are turned off.
0 1 <Vth 0 0 PGND Bottom output FET for that phase is turned on.
1 0 <Vth 0 0 VS Top output FET for that phase is turned on.
1 1 X X X High-Z Both output FETs for that phase are turned off.
X X >Vth 1 X High-Z Voltage on Ia, Ib, or Ic has exceeded Vth, which causes ILIM/DIS1 to go
high. This internally disables Top and Bottom output FETs for ALL phases.
X X X X 1 High-Z DIS2 pin pulled high, which disables all outputs.
X X X Pulled
High X High-Z Pulling the ILIM/DIS1 pin high externally acts as a second disable input,
which disables ALL output FETs.
X X X Pulled
Low 0
Determined
by PWM
inputs
Pulling the DIS2 pin low externally disables the cycle-by-cycle current limit
function. The state of the outputs is strictly a function of the PWM inputs.
X X X X X High-Z If VS is below the UVLO threshold all output FETs will be disabled.
Product
Technology
F r o m
SA306A
SA306U 9
2.1LayoutConsiderations
Output traces carry signals with very high dV/dt and dI/dt. Proper routing and adequate power supply bypassing
ensures normal operation. Poor routing and bypassing can cause erratic and low efciency operation as well as
ringing at the outputs.
The VS supply should be bypassed with a surface mount ceramic capacitor mounted as close as possible to the VS
pins. Total inductance of the routing from the capacitor to the VS and GND pins must be kept to a minimum to pre-
vent noise from contaminating the logic control signals. A low ESR capacitor of at least 25μF per ampere of output
current should be placed near the SA306 as well. Capacitor types rated for switching applications are the only types
that should be considered. Note that phases B & C share a VS connection and the bypass recommendation should
reect the sum of B & C phase current.
The bypassing requirements of the VDD supply are less stringent, but still necessary. A 0.1μF to 0.47μF surface
mount ceramic capacitor (X7R or NPO) connected directly to the VDD pin is sufcient.
SGND and PGND pins are connected internally. However, these pins must be connected externally in such a way
that there is no motor current owing in the logic and signal ground traces as parasitic resistances in the small
signal routing can develop sufcient voltage drops to erroneously trigger input transitions. Alternatively, a ground
plane may be separated into power and logic sections connected by a pair of back to back Schottky diodes. This
isolates noise between signal and power ground traces and prevents high currents from passing between the plane
sections.
Unused area on the top and bottom PCB planes should be lled with solid or hatched copper to minimize inductive
coupling between signals. The copper ll may be left unconnected, although a ground plane is recommended.
2.2FaultIndications
In the case of either an over-temperature
or short circuit fault, the SA306 will take
no action to disable the outputs. Instead,
the SC and TEMP signals are provided to
an external controller, where a determina-
tion can be made regarding the appropri-
ate course of action. In most cases, the SC
pin would be connected to a FAULT input
on the processor, which would immediately
disable its PWM outputs. The TEMP fault
does not require such an immediate re-
sponse, and would typically be connected
to a GPIO, or Keyboard Interrupt pin of
the processor. In this case, the processor
would recognize the condition as an exter-
nal interrupt, which could be processed in software via an Interrupt Service Routine. The processor could optionally
bring all inputs low, or assert a high level to either of the disable inputs on the SA306.
Figure 6 shows an external SR ip-op which provides a hard wired shutdown of all outputs in response to a fault
indication. An SC or TEMP fault sets the latch, pulling the disable pin high. The processor clears the latched condi-
tion with a GPIO. This circuit can be used in safety critical applications to remove software from the fault-shutdown
loop, or simply to reduce processor overhead.
In applications which may not have available GPIO, the TEMP pin may be externally connected to the adjacent
DIS1 pin. If the device temperature reaches ~135°C all outputs will be disabled, de-energizing the motor. The
SA306 will re-energize the motor when the device temperature falls below approximately 95°C. The TEMP pin
hysteresis is wide to reduce the likelihood of thermal oscillations which can greatly reduce the life of the device.
Figure6.ExternalFaultLatchCircuit
SA306
PROCESSOR
INTERRUPT
GPIO
PWM
SC
DIS2 TEMP
LATCHED FAULT
FAULT RESET
Product
Technology
F r o m
SA306A
10 SA306U
2.3Under-VoltageLockout
The undervoltage lockout condition results in the SA306 unilaterally disabling all output FETs until VS is above the
UVLO threshold indicated in the spec table. There is no external signal indicating that an undervoltage lockout
condition is in progress. The SA306 has two VS connections: one for phase A, and another for phases B & C. The
supply voltages on these pins need not be the same, but the UVLO will engage if either is below the threshold.
Hysteresis on the UVLO circuit prevents oscillations with typical power supply variations.
2.4CurrentSense
External power shunt resistors are not required with the SA306. Forward current in each top, P-channel output FET
is measured and mirrored to the respective current sense output pin, Ia, Ib and Ic. By connecting a resistor between
each current sense pin and a reference, such as ground, a voltage develops across the resistor that is proportional
to the output current for that phase. An ADC can monitor the voltages on these resistors for protection or for closed
loop torque control in some application congurations. The current sense pins source current from the VDD supply.
Headroom required for the current sense circuit is approximately 0.5V. The nominal scale factor for each propor-
tional output current is shown in the typical performance plot on page 4 of this datasheet.
2.5Cycle-By-CycleCurrentLimit
In applications where the current in the
motor is not directly controlled, both the
average current rating of the motor and
the inrush current must be considered
when selecting a proper amplier. For
example, a 1A continuous motor might
require a drive amplier that can deliver
well over 10A peak in order to survive the
inrush condition at start-up.
Because the output current of each up-
per output FET is measured, the SA306
is able to provide a very robust current
limit scheme. This enables the SA306
to safely and easily drive virtually any
brushless motor through a start-up in-
rush condition. With limited current, the
starting torque and acceleration are also
limited. The plot in Figure 7 shows start-
ing current and back EMF with and with-
out current limit enabled.
If the voltage of any of the three cur-
rent sense pins exceeds the current limit
threshold voltage (Vth), all outputs are
disabled. After all current sense pins fall below the Vth threshold voltage AND the offending phase’s top side input
goes low, the output stage will return to an active state on the rising edge of ANY top side input command signal (At,
Bt, or Ct). With most commutation schemes, the current limit will reset each PWM cycle. This scheme regulates the
peak current in each phase during each PWM cycle as illustrated in the timing diagram below. The ratio of average
to peak current depends on the inductance of the motor winding, the back EMF developed in the motor, and the
width of the pulse.
Figure 8 illustrates the current limit trigger and reset sequence. Current limit engages and ILIM/DIS1 goes high when
any current sense pin exceeds Vth. Notice that the moment at which the current sense signal exceeds the Vth
threshold is asynchronous with respect to the input PWM signal. The difference between the PWM period and the
motor winding L/R time constant will often result in an audible beat frequency sometimes called a sub-cycle oscilla-
tion. This oscillation can be seen on the ILIM/DIS1 pin waveform in Figure 8.
TIME
NON-LIMITED BACK EMF
LIMITED BACK EMF
LIMITED MOTOR CURRENT
NON-LIMITED MOTOR CURRENT
Figure7.Start-upVoltageandCurrent
Product
Technology
F r o m
SA306A
SA306U 11
Input signals commanding 0% or 100% duty
cycle may be incompatible with the current
limit feature due to the absence of rising edg-
es of At, Bt, and Ct except when commutating
phases. At high RPM, this may result in poor
performance. At low RPM, the motor may stall
if the current limit trips and the motor current
reaches zero without a commutation edge
which will typically reset the current limit latch.
The current limit feature may be disabled by
tying the ILIM/DIS1 pin to GND. The current
sense pins will continue to provide top FET
output current information.
Typically, the current sense pins source cur-
rent into grounded resistors which provide
voltages to the current limit comparators. If in-
stead the current limit resistors are connected
to a voltage output DAC, the current limit can
be controlled dynamically from the system
controller. This technique essentially reduces
the current limit threshold voltage to (Vth-
VDAC). During expected conditions of high
torque demand, such as start-up or reversal,
the DAC can adjust the current limit dynami-
cally to allow periods of high current. In normal operation when low current is expected, the DAC output voltage can
increase, reducing the current limit setting to provide more conservative fault protection.
2.6ExternalFlybackDiodes
External y-back diodes will offer superior reverse recovery char-
acteristics and lower forward voltage drop than the internal back-
body diodes. In high current applications, external yback diodes
can reduce power dissipation and heating during commutation of
the motor current. Reverse recovery time and capacitance are
the most important parameters to consider when selecting these
diodes. Ultra-fast rectiers offer better reverse recovery time and
Schottky diodes typically have low capacitance. Individual appli-
cation requirements will be the guide when determining the need
for these diodes and for selecting the component which is most
suitable.
3.PowerDissipation
The thermally enhanced package of the SA306 allows several options for managing the power dissipated in the
three output stages. Power dissipation in traditional PWM applications is a combination of output power dissipation
and switching losses. Output power dissipation depends on the quadrant of operation and whether external yback
diodes are used to carry the reverse or commutating currents. Switching losses are dependent on the frequency of
the PWM cycle as described in the typical performance graphs.
Figure9.SchottkyDiodes
OUTA
OUTC
OUTB
VSVSVS
SA306
At INPUT
OUTA
IA
Vth
I
LIM
/DIS1
Figure8.CurrentLimitWaveforms
Product
Technology
F r o m
SA306A
12 SA306U
TOP INPUT
BOTTOM INPUT
DELAY TIMING
OUTPUT
DISABLE
td(fall) td(dis)td(rise) td(dis)
td(dis)
td(dis)
Figure10.TimingDiagrams
TOP INPUT
BOTTOM INPUT
OUTPUT
t(fall)
t(rise)
20%
80%
Figure11.OutputResponse
4.OrderingAndProductStatusInformation
MODEL TEMPERATURE PACKAGE PRODUCTION STATUS
SA306AHU-FH -40 to +125ºC 44 pin Power SOP-Slug Up
(HU package drawing)
Samples Available
SA306AHR-FH -40 to +125ºC 44 pin Power SOP-Slug Down
(HR package drawing)
Samples Available
Product
Technology
F r o m
SA306A
SA306U 13
CONTACTINGCIRRUSLOGICSUPPORT
For all Apex Precision Power product questions and inquiries, call toll free 800-546-2739 in North America.
For inquiries via email, please contact apex.support@cirrus.com.
International customers can also request support by contacting their local Cirrus Logic Sales Representative.
To nd the one nearest to you, go to www.cirrus.com
IMPORTANT NOTICE
Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject
to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant
information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale
supplied at the time of order acknowledgment, including those pertaining to warranty, indemnication, and limitation of liability. No responsibility is assumed by Cirrus
for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third
parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights,
copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives con-
sent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent
does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROP-
ERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED TO BE
SUITABLE FOR USE IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PROD-
UCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUS-
TOMER’S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE
CUSTOMER OR CUSTOMER’S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES,
BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL
LIABILITY, INCLUDING ATTORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES.
Cirrus Logic, Cirrus, and the Cirrus Logic logo designs, Apex Precision Power, Apex and the Apex Precision Power logo designs are trademarks of Cirrus Logic, Inc.
All other brand and product names in this document may be trademarks or service marks of their respective owners.