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June 2003
STSI-144 Scalable Time-Slot Interchanger
Hardware Design Guide
Introduction
This document describes the hardware interfaces to
Agere Systems Inc. scalable time-slot interchanger
(STSI-144) device. Information relevant to the use of
the device in a board design is covered. Ball descrip-
tions, dc electrical characteristics, timing diagrams,
ac timing parameters, packaging, and operating con-
ditions are included.
Relat ed Documents
More information on the STSI-144 is contained in the
following documents:
■STSI-144 Product Description
■STSI-144 Register Description
■STSI-144 Systems Design Guide
Description
Block Diagram and High-Level Interface Definition
Figure 1. Block Diagram and High-Level Interface Definition
TEST ACCESS
PORT
CLOCK
GENERATOR
READ ADDRESS
COUNTER
CONNECTION
STORE
WRITE ADDRESS
COUNTER
DATA
STORE
MICROPROCESSOR
INTERFACE
TRANSMIT
CHI
TRANSLATION
TABLE LOOKUP
TEST PA TTERN
GENERATOR
TEST PATTERN
MONITOR
SWITCH
FABRIC
RECEIVE
HSL
TRANSMIT
HSL
RECEIVE
CHI
16
64 64
16
Table of Contents
Contents Page Contents Page
2Agere Systems Inc.
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Hardware Design Guide
STSI-144 Scalable Time-Slot Interchanger
Introduction ....................................................................1
Relat ed Do cuments................ ....... ...... ....... ....... ...... ....1
Description.....................................................................1
Block Diagram and High-Level Interface Definition.....1
Ball Information..............................................................3
Ball Diagram................................................................3
Package B all A ssignments................ ....... ...... ....... ......4
Ball Types..................................................................10
Ball De finitions...........................................................10
Absolute Maximum Ratings .........................................14
Handli n g Pre cautions.............. ...... ....... ....... ...... ...........14
ESD Tole r a n ce............ ...... ....... ....... ....... ...... .............14
Packag e Th e rma l Ch a r a cteristi cs............... ....... ...... ..14
Recommended Operating Conditions..........................14
dc Electrical Characteristics.........................................15
Timing Diagrams and ac Characteristics .....................17
Outlin e Di a g r a ms ........ ....................... .. ........... ....... ......29
Ordering Informati on....................................................30
Figure Page
Figure 1. Block Diagram and High-Level Interface
Definition........................................................ 1
Figure 2. Package Diagram (Top View)........................ 3
Figure 3. CHICLK Timing Specifications..................... 17
Figure 4. MPUCLK Timing Specifications................... 17
Figure 5. ac Timing Measurement Specification......... 18
Figure 6. CHI Interface Timing.................................... 19
Figure 7. Typical Receive CHI Timing with
16.384 Mbits/s Data and
16.384 MHz CHICLK....... ......... .. ......... ........ 20
Figure 8. Transmit CHI Timing with
16.384 Mbits/s Data and
16.384 MHz CHICLK....... ......... .. ......... ........ 20
Figure 9. Typical Receive CHI Timing with
8.192 Mbits/s Data and
16.384 MHz CHICLK....... ......... .. ......... ........ 21
Figure 10. Transmit CHI Timing with
8.192 Mbits/s Data and
16.384 MHz CHICLK................................. 21
Figure 11. Typical Receive CHI Timing with
4.096 Mbits/s Data and
16.384 MHz CHICLK................................. 22
Figure 12. Transmit CHI Timing with
4.096 Mbits/s Data and
16.384 MHz CHICLK................................. 22
Figure 13. Typical Receive CHI Timing with
2.048 Mbits/s Data and
16.384 MHz CHICLK................................. 23
Figure 14. Transmit CHI Timing with
2.048 Mbits/s Data and
16.384 MHz CHICLK................................. 23
Figure 15. Typical Receive CHI Timing with
8.192 Mbits/s Data and
8.192 MHz CHICLK.............. ......... ......... .. . 24
Figure 16. Transmit CHI Timing with 8.192 Mbits/s
Data and 8.192 MHz CHICLK................ ... 24
Figure 17. CHI 3-State Output Control ....................... 25
Figure 18. Microprocessor Port Timing—
Read Cy cl e..... ........... ... ........... ....... ...... ..... 26
Figure 19. Microprocessor Port Timing—
Write Cycle................................................ 27
Figure 20. LVDS Output Timing Specifications .......... 28
Table Page
Table 1. Package Ball Assignments in
Signal Name Order........................... ......... ..... 4
Table 2. Package Ball Assignments in
Ball Number Order ......................................... 6
Table 3. Package Ball Assignments in
Ball Number Order (Top View)....................... 8
Table 4. Package Ball Assignments In
Ball Number Order (Bottom View).................. 9
Table 5 . Bal l Types...... ...................... ....... ....... ...... ..... 10
Table 6 . Ti mi n g Por t...... ...................... ....... ....... ....... .. 10
Table 7. Transmit and Receive Concentration
Highways...................................................... 11
Table 8. Control Port................................................... 11
Table 9. High-Speed Serial Link Signals.................... 12
Table 10. Initialization and Test Access ..................... 12
Table 1 1. Power Ball s........ ....... ....... ....... ...... ....... ....... 13
Table 12. Absolute Maximum Ratings........................ 14
Table 13. ESD Tolerance ........................................... 14
Table 1 4. Power Cons um p ti o n ............................ ....... 14
Table 15. Operating Conditions.................................. 14
Table 16. CMOS Inputs................ .. ....... ......... ......... ... 15
Table 17. CMOS Outputs ........................................... 15
Table 18. CMOS Bidirectionals
(Excluding TXD[63:00]).............................. 15
Table 19. CMOS Bidirectionals (TXD[63:00])............. 15
Table 20. LVDS Receiver dc Parameters....... ......... ... 16
Table 21. LVDS Transmitter dc Parameters............... 16
Table 22. CHICLK Timing Specifications.................... 17
Table 2 3. MP UCLK Timi ng S p ec i fi cation s.................. 17
Table 24. ac Timing Measurement Specification........ 18
Table 25. CHI Interface Timing................................... 19
Table 26. CHI 3-State Output Control..................... . ... 25
Table 27. Microprocessor Port Timing—
Read Cycle.......... ......... .. ....... ......... ............ 26
Table 28. Microprocessor Port Timing—
Write Cy cl e.. ........... ....... ...... ....... ....... ....... .. 27
Table 2 9. LVDS ac Chara cteristics............... ... ........... 28
Agere Systems Inc. 3
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June 2003 Hardware Design Guide
STSI-144 Scalable Time-Slot Interchanger
Ball Information
Ball Diagram
The STSI-144 is housed in a 388-ball plastic ball grid array. Figure 2 shows the ball arrangement viewed from the
top of the package. The balls are spaced on a 1.0 mm pitch.
Figure 2. Package Diagram (Top View)
B
C
A
E
F
D
H
J
G
L
M
K
P
R
N
U
V
T
W
Y
AB
AA
2
3
15
6
48710
11
913
14
12 16
15
17
19
20
18 2221
AC
AD
AE
AF
23 24 25 26
4Agere Systems Inc.
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June 2003
Hardware Design Guide
STSI-144 Scalable Time-Slot Interchanger
Ball Information (continued)
Package Ball Assignments
Table 1. Package Ball Assignments in Signal Name Order
Symbol Ball Symbol Ball Symbol Ball Symbol Ball Symbol Ball
ADDR00 L24 DATA09 Y25 HSLINP12 A12 MPUCLK U23 RXD18 AF16
ADDR01 M26 DATA10 Y24 HSLINP13 C12 PAR0 AC26 RXD19 AE16
ADDR02 M25 DATA11 AA26 HSLINP14 B13 PAR1 AB24 RXD20 AF17
ADDR03 M24 DATA12 AA25 HSLINP15 C13 R/W L26 RXD21 AF18
ADDR04 N26 DATA13 AA24 HSLOUTN00 A14 REF10 D18 RXD22 AE18
ADDR05 N25 DATA14 AB26 HSLOUTN01 D14 REF14 C18 RXD23 AF19
ADDR06 N24 DATA15 AB25 HSLOUTN02 A15 REFCLK AD26 RXD24 AF20
ADDR07 P26 DT J24 HSLOUTN03 C15 REFSYNC AF25 RXD25 AE20
ADDR08 P25 FSYNC AC20 HSLOUTN04 A16 RESET K25 RXD26 AF21
ADDR09 P24 HIZ AC25 HSLOUTN05 C16 RESHI C19 RXD27 AF22
ADDR10 R26 HSLINN00 B3 HSLOUTN06 A17 RESLO D19 RXD28 AE22
ADDR11 R25 HSLINN01 C4 HSLOUTN07 A18 RSV1 G25 RXD29 AF23
ADDR12 R24 HSLINN02 B4 HSLOUTN08 A19 RSV2 G26 RXD30 AF24
ADDR13 T26 HSLINN03 B5 HSLOUTN09 A20 RSV3 F24 RXD31 AE24
ADDR14 T25 HSLINN04 B6 HSLOUTN10 C21 RSV4 F25 RXD32 AD4
ADDR15 T24 HSLINN05 C6 HSLOUTN11 B21 RSV5 F26 RXD33 AE4
AS L25 HSLINN06 A7 HSLOUTN12 B22 RSV6 E26 RXD34 AD5
CHICLK AC24 HSLINN07 A8 HSLOUTN13 C22 RSV7 D26 RXD35 AD6
CK155MHZN D11 HSLINN08 D8 HSLOUTN14 B23 RSV8 D25 RXD36 AE6
CK155MHZP C11 HSLINN09 B9 HSLOUTN15 B24 RSV9 D24 RXD37 AD7
CK78MHZ AC18 HSLINN10 A9 HSLOUTP00 B14 RXD00 AE3 RXD38 AD8
CKSPD0 E24 HSLINN11 C10 HSLOUTP01 C14 RXD01 AF3 RXD39 AE8
CKSPD1 E25 HSLINN12 A11 HSLOUTP02 B15 RXD02 AF4 RXD40 AD9
CS K24 HSLINN13 B12 HSLOUTP03 D15 RXD03 AE5 RXD41 AD10
CTAPIN0 D5 HSLINN14 A13 HSLOUTP04 B16 RXD04 AF5 RXD42 AE10
CTAPIN1 D7 HSLINN15 D13 HSLOUTP05 D16 RXD05 AF6 RXD43 AD11
CTAPIN2 D10 HSLINP00 A3 HSLOUTP06 B17 RXD06 AE7 RXD44 AD12
CTAPIN3 D12 HSLINP01 C5 HSLOUTP07 B18 RXD07 AF7 RXD45 AE12
CTAPIN4 B11 HSLINP02 A4 HSLOUTP08 B19 RXD08 AF8 RXD46 AD13
DATA00 U26 HSLINP03 A5 HSLOUTP09 B20 RXD09 AE9 RXD47 AE13
DATA01 U25 HSLINP04 A6 HSLOUTP10 D21 RXD10 AF9 RXD48 AE14
DATA02 V26 HSLINP05 C7 HSLOUTP11 A21 RXD11 AF10 RXD49 AD14
DATA03 V25 HSLINP06 B7 HSLOUTP12 A22 RXD12 AE11 RXD50 AE15
DATA04 V24 HSLINP07 B8 HSLOUTP13 C23 RXD13 AF11 RXD51 AD15
DATA05 W26 HSLINP08 C8 HSLOUTP14 A23 RXD14 AF12 RXD52 AD16
DATA06 W25 HSLINP09 C9 HSLOUTP15 A24 RXD15 AF13 RXD53 AE17
DATA07 W24 HSLINP10 A10 HSLRFSEL AE26 RXD16 AF14 RXD54 AD17
DATA08 Y26 HSLINP11 B10 INT K26 RXD17 AF15 RXD55 AD18
Agere Systems Inc. 5
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June 2003 Hardware Design Guide
STSI-144 Scalable Time-Slot Interchanger
Ball Information (continued)
Package Ball Assignments (continued)
Table 1. Package Ball Assignments in Signal Name Order (continued)
Symbol Ball Symbol Ball Symbol Ball Symbol Ball Symbol Ball
TXD27 AB1 VDD15 N11 VDDPLL AC22 VSS L11
RXD56 AE19 TXD28 AB2 VDD15 N12 VIO P4 VSS L12
RXD57 AD19 TXD29 AC1 VDD15 N15 VPRE AF2 VSS L15
RXD58 AD20 TXD30 AD1 VDD15 N16 VSS A1 VSS L16
RXD59 AE21 TXD31 AD2 VDD15 P11 VSS A2 VSS L23
RXD60 AD21 TXD32 D3 VDD15 P12 VSS A26 VSS M11
RXD61 AD22 TXD33 D2 VDD15 P15 VSS AA4 VSS M12
RXD62 AE23 TXD34 E3 VDD15 P16 VSS AA23 VSS M15
RXD63 AD23 TXD35 F3 VDD15 R13 VSS AC4 VSS M16
TCK H25 TXD36 F2 VDD15 R14 VSS AC6 VSS M23
TDI H24 TXD37 G3 VDD15 T13 VSS AC8 VSS N4
TDO H26 TXD38 H3 VDD15 T14 VSS AC10 VSS N13
TMS J26 TXD39 H2 VDD33 A25 VSS AC11 VSS N14
TRSTN J25 TXD40 J3 VDD33 AB4 VSS AC13 VSS P13
TXD00 C2 TXD41 K3 VDD33 AB23 VSS AC15 VSS P14
TXD01 C1 TXD42 K2 VDD33 AC5 VSS AC16 VSS P23
TXD02 D1 TXD43 L3 VDD33 AC7 VSS AC19 VSS R4
TXD03 E2 TXD44 M3 VDD33 AC9 VSS AC23 VSS R11
TXD04 E1 TXD45 M2 VDD33 AC12 VSS AD3 VSS R12
TXD05 F1 TXD46 N3 VDD33 AC14 VSS AD24 VSS R15
TXD06 G2 TXD47 N2 VDD33 AC17 VSS AD25 VSS R16
TXD07 G1 TXD48 P2 VDD33 C25 VSS AE1 VSS T4
TXD08 H1 TXD49 P3 VDD33 C26 VSS AE2 VSS T11
TXD09 J2 TXD50 R2 VDD33 D6 VSS AE25 VSS T12
TXD10 J1 TXD51 R3 VDD33 D9 VSS AF1 VSS T15
TXD11 K1 TXD52 T3 VDD33 D22 VSS AF26 VSS T16
TXD12 L2 TXD53 U2 VDD33 E4 VSS B1 VSS T23
TXD13 L1 TXD54 U3 VDD33 E23 VSS B2 VSS U24
TXD14 M1 TXD55 V3 VDD33 G4 VSS B25 VSS V4
TXD15 N1 TXD56 W2 VDD33 H23 VSS B26 VSS W23
TXD16 P1 TXD57 W3 VDD33 J4 VSS C3 VSS Y4
TXD17 R1 TXD58 Y3 VDD33 K23 VSS C24 VSSCDR0 D17
TXD18 T1 TXD59 AA2 VDD33 M4 VSS D4 VSSCDR1 C20
TXD19 T2 TXD60 AA3 VDD33 N23 VSS D23 VSSPLL AC21
TXD20 U1 TXD61 AB3 VDD33 R23 VSS F4
TXD21 V1 TXD62 AC2 VDD33 U4 VSS F23
TXD22 V2 TXD63 AC3 VDD33 V23 VSS G23
TXD23 W1 VDD15 L13 VDD33 W4 VSS G24
TXD24 Y1 VDD15 L14 VDD33 Y23 VSS H4
TXD25 Y2 VDD15 M13 VDDCDR0 C17 VSS J23
TXD26 AA1 VDD15 M14 VDDCDR1 D20 VSS K4
6Agere Systems Inc.
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Hardware Design Guide
STSI-144 Scalable Time-Slot Interchanger
Ball Information (continued)
Package Ball Assignments (continued)
Table 2. Package Ball Assignments in Ball Number Order
Ball Symbol Ball Symbol Ball Symbol Ball Symbol Ball Symbol
A1 VSS B19 HSLOUTP08 D11 CK155MHZN H23 VDD33 M23 VSS
A2 VSS B20 HSLOUTP09 D12 CTAPIN3 H24 TDI M24 ADDR03
A3 HSLINP00 B21 HSLOUTN11 D13 HSLINN15 H25 TCK M25 ADDR02
A4 HSLINP02 B22 HSLOUTN12 D14 HSLOUTN01 H26 TDO M26 ADDR01
A5 HSLINP03 B23 HSLOUTN14 D15 HSLOUTP03 J1 TXD10 N1 TXD15
A6 HSLINP04 B24 HSLOUTN15 D16 HSLOUTP05 J2 TXD09 N2 TXD47
A7 HSLINN06 B25 VSS D17 VSSCDR0 J3 TXD40 N3 TXD46
A8 HSLINN07 B26 VSS D18 REF10 J4 VDD33 N4 VSS
A9 HSLINN10 C1 TXD01 D19 RESLO J23 VSS N11 VDD15
A10 HSLINP10 C2 TXD00 D20 VDDCDR1 J24 DT N12 VDD15
A11 HSLINN12 C3 VSS D21 HSLOUTP10 J25 TRSTN N13 VSS
A12 HSLINP12 C4 HSLINN01 D22 VDD33 J26 TMS N14 VSS
A13 HSLINN14 C5 HSLINP01 D23 VSS K1 TXD11 N15 VDD15
A14 HSLOUTN00 C6 HSLINN05 D24 RSV9 K2 TXD42 N16 VDD15
A15 HSLOUTN02 C7 HSLINP05 D25 RSV8 K3 TXD41 N23 VDD33
A16 HSLOUTN04 C8 HSLINP08 D26 RSV7 K4 VSS N24 ADDR06
A17 HSLOUTN06 C9 HSLINP09 E1 TXD04 K23 VDD33 N25 ADDR05
A18 HSLOUTN07 C10 HSLINN11 E2 TXD03 K24 CS N26 ADDR04
A19 HSLOUTN08 C11 CK155MHZP E3 TXD34 K25 RESET P1 TXD16
A20 HSLOUTN09 C12 HSLINP13 E4 VDD33 K26 INT P2 TXD48
A21 HSLOUTP11 C13 HSLINP15 E23 VDD33 L1 TXD13 P3 TXD49
A22 HSLOUTP12 C14 HSLOUTP01 E24 CKSPD0 L2 TXD12 P4 VIO
A23 HSLOUTP14 C15 HSLOUTN03 E25 CKSPD1 L3 TXD43 P11 VDD15
A24 HSLOUTP15 C16 HSLOUTN05 E26 RSV6 L4 VSS P12 VDD15
A25 VDD33 C17 VDDCDR0 F1 TXD05 L11 VSS P13 VSS
A26 VSS C18 REF14 F2 TXD36 L12 VSS P14 VSS
B1 VSS C19 RESHI F3 TXD35 L13 VDD15 P15 VDD15
B2 VSS C20 VSSCDR1 F4 VSS L14 VDD15 P16 VDD15
B3 HSLINN00 C21 HSLOUTN10 F23 VSS L15 VSS P23 VSS
B4 HSLINN02 C22 HSLOUTN13 F24 RSV3 L16 VSS P24 ADDR09
B5 HSLINN03 C23 HSLOUTP13 F25 RSV4 L23 VSS P25 ADDR08
B6 HSLINN04 C24 VSS F26 RSV5 L24 ADDR00 P26 ADDR07
B7 HSLINP06 C25 VDD33 G1 TXD07 L25 AS R1 TXD17
B8 HSLINP07 C26 VDD33 G2 TXD06 L26 R/W R2 TXD50
B9 HSLINN09 D1 TXD02 G3 TXD37 M1 TXD14 R3 TXD51
B10 HSLINP11 D2 TXD33 G4 VDD33 M2 TXD45 R4 VSS
B11 CTAPIN4 D3 TXD32 G23 VSS M3 TXD44 R11 VSS
B12 HSLINN13 D4 VSS G24 VSS M4 VDD33 R12 VSS
B13 HSLINP14 D5 CTAPIN0 G25 RSV1 M11 VSS R13 VDD15
B14 HSLOUTP00 D6 VDD33 G26 RSV2 M12 VSS R14 VDD15
B15 HSLOUTP02 D7 CTAPIN1 H1 TXD08 M13 VDD15 R15 VSS
B16 HSLOUTP04 D8 HSLINN08 H2 TXD39 M14 VDD15 R16 VSS
B17 HSLOUTP06 D9 VDD33 H3 TXD38 M15 VSS R23 VDD33
B18 HSLOUTP07 D10 CTAPIN2 H4 VSS M16 VSS R24 ADDR12
Agere Systems Inc. 7
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STSI-144 Scalable Time-Slot Interchanger
Ball Information (continued)
Package Ball Assignments (continued)
Table 2. Package Ball Assignments in Ball Number Order (continued)
Ball Symbol Ball Symbol Ball Symbol Ball Symbol
R25 ADDR11 Y23 VDD33 AC25 HIZ AE17 RXD53
R26 ADDR10 Y24 DATA10 AC26 PAR0 AE18 RXD22
T1 TXD18 Y25 DATA09 AD1 TXD30 AE19 RXD56
T2 TXD19 Y26 DATA08 AD2 TXD31 AE20 RXD25
T3 TXD52 AA1 TXD26 AD3 VSS AE21 RXD59
T4 VSS AA2 TXD59 AD4 RXD32 AE22 RXD28
T11 VSS AA3 TXD60 AD5 RXD34 AE23 RXD62
T12 VSS AA4 VSS AD6 RXD35 AE24 RXD31
T13 VDD15 AA23 VSS AD7 RXD37 AE25 VSS
T14 VDD15 AA24 DATA13 AD8 RXD38 AE26 HSLRFSEL
T15 VSS AA25 DATA12 AD9 RXD40 AF1 VSS
T16 VSS AA26 DATA11 AD10 RXD41 AF2 VPRE
T23 VSS AB1 TXD27 AD11 RXD43 AF3 RXD01
T24 ADDR15 AB2 TXD28 AD12 RXD44 AF4 RXD02
T25 ADDR14 AB3 TXD61 AD13 RXD46 AF5 RXD04
T26 ADDR13 AB4 VDD33 AD14 RXD49 AF6 RXD05
U1 TXD20 AB23 VDD33 AD15 RXD51 AF7 RXD07
U2 TXD53 AB24 PAR1 AD16 RXD52 AF8 RXD08
U3 TXD54 AB25 DATA15 AD17 RXD54 AF9 RXD10
U4 VDD33 AB26 DATA14 AD18 RXD55 AF10 RXD11
U23 MPUCLK AC1 TXD29 AD19 RXD57 AF11 RXD13
U24 VSS AC2 TXD62 AD20 RXD58 AF12 RXD14
U25 DATA01 AC3 TXD63 AD21 RXD60 AF13 RXD15
U26 DATA00 AC4 VSS AD22 RXD61 AF14 RXD16
V1 TXD21 AC5 VDD33 AD23 RXD63 AF15 RXD17
V2 TXD22 AC6 VSS AD24 VSS AF16 RXD18
V3 TXD55 AC7 VDD33 AD25 VSS AF17 RXD20
V4 VSS AC8 VSS AD26 REFCLK AF18 RXD21
V23 VDD33 AC9 VDD33 AE1 VSS AF19 RXD23
V24 DATA04 AC10 VSS AE2 VSS AF20 RXD24
V25 DATA03 AC11 VSS AE3 RXD00 AF21 RXD26
V26 DATA02 AC12 VDD33 AE4 RXD33 AF22 RXD27
W1 TXD23 AC13 VSS AE5 RXD03 AF23 RXD29
W2 TXD56 AC14 VDD33 AE6 RXD36 AF24 RXD30
W3 TXD57 AC15 VSS AE7 RXD06 AF25 REFSYNC
W4 VDD33 AC16 VSS AE8 RXD39 AF26 VSS
W23 VSS AC17 VDD33 AE9 RXD09
W24 DATA07 AC18 CK78MHZ AE10 RXD42
W25 DATA06 AC19 VSS AE11 RXD12
W26 DATA05 AC20 FSYNC AE12 RXD45
Y1 TXD24 AC21 VSSPLL AE13 RXD47
Y2 TXD25 AC22 VDDPLL AE14 RXD48
Y3 TXD58 AC23 VSS AE15 RXD50
Y4 VSS AC24 CHICLK AE16 RXD19
8Agere Systems Inc.
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Hardware Design Guide
STSI-144 Scalable Time-Slot Interchanger
Ball Information (continued)
Package Ball Assignments (contin ued)
Table 3. Package Ball Assignments in Ball Number Order (Top View)
1234567891011121314151617181920212223242526
AVSS VSS HSLINP
00 HSLINP
02 HSLINP
03 HSLINP
04 HSLINN
06 HSLINN
07 HSLINN
10 HSLINP
10 HSLINN
12 HSLINP
12 HSLINN
14 HSLOUTN
00 HSLOUTN
02 HSLOUTN
04 HSLOUTN
06 HSLOUTN
07 HSLOUTN
08 HSLOUTN
09 HSLOUTP
11 HSLOUTP
12 HSLOUTP
14 HSLOUTP
15 VDD33A VSS
BVSS VSS HSLINN
00 HSLINN
02 HSLINN
03 HSLINN
04 HSLINP
06 HSLINP
07 HSLINN
09 HSLINP
11 CTAPIN4 HSLINN
13 HSLINP
14 HSLOUTP
00 HSLOUTP
02 HSLOUTP
04 HSLOUTP
06 HSLOUTP
07 HSLOUTP
08 HSLOUTP
09 HSLOUTN
11 HSLOUTN
12 HSLOUTN
14 HSLOUTN
15 VSS VSS
CTXD01 TXD00 VSS HSLINN
01 HSLINP
01 HSLINN
05 HSLINP
05 HSLINP
08 HSLINP
09 HSLINN
11 CK155
MHZP HSLINP
13 HSLINP
15 HSLOUTP
01 HSLOUTN
03 HSLOUTN
05 VDDCDR0 REF14 RESHI VSSCDR1 HSLOUTN
10 HSLOUTN
13 HSLOUTP
13 VSS VDD33 VDD33
DTXD02 TXD33 TXD32 VSS CTAPIN0 VDD33 CTAPIN1 HSLINN
08 VDD33 CTAPIN2 CK155
MHZN CTAPIN3 HSLINN
15 HSLOUTN
01 HSLOUTP
03 HSLOUTP
05 VSSCDR0 REF10 RESLO VDDCDR1 HSLOUTP
10 VDD33 VSS RSV9 RSV8 RSV7
ETXD04 TXD03 TXD34 VDD33 ————————— —————————VDD3 CKSPD0 CKSPD1 RSV6
FTXD05 TXD36 TXD35 VSS ————————— —————————VSS RSV3 RSV4 RSV5
GTXD07 TXD06 TXD37 VDD33 ————————— —————————VSS VSS RSV1 RSV2
HTXD08 TXD39 TXD38 VSS ————————— —————————VDD33 TDI TCK TDO
JTXD10 TXD09 TXD40 VDD33 ————————— —————————VSS DT TRSTN TMS
KTXD11 TXD42 TXD41 VSS ————————— —————————
VDD33 CS RESET INT
LTXD13 TXD12 TXD43 VSS ——————VSS VSS VDD15 VDD15 VSS VSS ——————VSS ADDR00 AS R/W
MTXD14 TXD45 TXD44 VDD33 ——————VSS VSS VDD15 VDD15 VSS VSS ——————VSS ADDR03 ADDR02 ADDR01
NTXD15 TXD47 TXD46 VSS ——————VDD15 VDD15 VSS VSS VDD15 VDD15 ——————VDD33 ADDR06 ADDR05 ADDR04
PTXD16 TXD48 TXD49 VIO ——————VDD15 VDD15 VSS VSS VDD15 VDD15 ——————VSS ADDR09 ADDR08 ADDR07
RTXD17 TXD50 TXD51 VSS ——————VSS VSS VDD15 VDD15 VSS VSS ——————VDD33 ADDR12 ADDR11 ADDR10
TTXD18 TXD19 TXD52 VSS ——————VSS VSS VDD15 VDD15 VSS VSS ——————VSS ADDR15 ADDR14 ADDR13
UTXD20 TXD53 TXD54 VDD33 ————————— —————————MPUCLKVSS DATA01 DATA00
VTXD21 TXD22 TXD55 VSS ————————— —————————VDD33 DATA04 DATA03 DATA02
WTXD23 TXD56 TXD57 VDD33 ————————— —————————VSS DATA07 DATA06 DATA05
YTXD24 TXD25 TXD58 VSS ————————— —————————V
DD33 DATA10 DATA09 DATA08
AA TXD26 TXD59 TXD60 VSS ————————— —————————VSS DATA13 DATA12 DATA11
AB TXD27 TXD28 TXD61 VDD33 ————————— —————————VDD33 PAR1 DATA15 DATA14
AC TXD29 TXD62 TXD63 VSS VDD33 VSS VDD33 VSS VDD33 VSS VSS VDD33 VSS VDD33 VSS VSS VDD33 CK78MHZ VSS FSYNC VSSPLL VDDPLL VSS CHICLK HIZ PAR0
AD TXD30 TXD31 VSS RXD32 RXD34 RXD35 RXD37 RXD38 RXD40 RXD41 RXD43 RXD44 RXD46 RXD49 RXD51 RXD52 RXD54 RXD55 RXD57 RXD58 RXD60 RXD61 RXD63 VSS VSS REFCLK
AE VSS VSS RXD00 RXD33 RXD03 RXD36 RXD06 RXD39 RXD09 RXD42 RXD12 RXD45 RXD47 RXD48 RXD50 RXD19 RXD53 RXD22 RXD56 RXD25 RXD59 RXD28 RXD62 RXD31 VSS HSLRFSEL
AF VSS VPRE RXD01 RXD02 RXD04 RXD05 RXD07 RXD08 RXD10 RXD11 RXD13 RXD14 RXD15 RXD16 RXD17 RXD18 RXD20 RXD21 RXD23 RXD24 RXD26 RXD27 RXD29 RXD30 REFSYNC VSS
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June 2003
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STSI-144 Scalable Time-Slot Interchanger
Agere Systems Inc. 9
Ball Information (continued)
Package Ball Assignments (continued)
Table 4. Package Ball Assignments in Ball Number Order (Bottom View)
1234567891011121314151617181920212223242526
AF VSS VPRE RXD01 RXD02 RXD04 RXD05 RXD07 RXD08 RXD10 RXD11 RXD13 RXD14 RXD15 RXD16 RXD17 RXD18 RXD20 RXD21 RXD23 RXD24 RXD26 RXD27 RXD29 RXD30 REFSYNC VSS
AE VSS VSS RXD00 RXD33 RXD03 RXD36 RXD06 RXD39 RXD09 RXD42 RXD12 RXD45 RXD47 RXD48 RXD50 RXD19 RXD53 RXD22 RXD56 RXD25 RXD59 RXD28 RXD62 RXD31 VSS HSLRFSEL
AD TXD30 TXD31 VSS RXD32 RXD34 RXD35 RXD37 RXD38 RXD40 RXD41 RXD43 RXD44 RXD46 RXD49 RXD51 RXD52 RXD54 RXD55 RXD57 RXD58 RXD60 RXD61 RXD63 VSS VSS REFCLK
AC TXD29 TXD62 TXD63 VSS VDD33 VSS VDD33 VSS VDD33 VSS VSS VDD33 VSS VDD33 VSS VSS VDD33 CK78MHZ VSS FSYNC VSSPLL VDDPLL VSS CHICLK HIZ PAR0
AB TXD27 TXD28 TXD61 VDD33 ————————— —————————VDD33 PAR1 DATA15 DATA14
AA TXD26 TXD59 TXD60 VSS ————————— —————————VSS DATA13 DATA12 DATA11
YTXD24 TXD25 TXD58 VSS ————————— —————————V
DD33 DATA10 DATA09 DATA08
WTXD23 TXD56 TXD57 VDD33 ————————— —————————VSS DATA07 DATA06 DATA05
VTXD21 TXD22 TXD55 VSS ————————— —————————VDD33 DATA04 DATA03 DATA02
UTXD20 TXD53 TXD54 VDD33 ————————— —————————MPUCLKVSS DATA01 DATA00
TTXD18 TXD19 TXD52 VSS ——————VSS VSS VDD15 VDD15 VSS VSS ——————VSS ADDR15 ADDR14 ADDR13
RTXD17 TXD50 TXD51 VSS ——————VSS VSS VDD15 VDD15 VSS VSS ——————VDD33 ADDR12 ADDR11 ADDR10
PTXD16 TXD48 TXD49 VIO ——————VDD15 VDD15 VSS VSS VDD15 VDD15 ——————VSS ADDR09 ADDR08 ADDR07
NTXD15 TXD47 TXD46 VSS ——————VDD15 VDD15 VSS VSS VDD15 VDD15 ——————VDD33 ADDR06 ADDR05 ADDR04
MTXD14 TXD45 TXD44 VDD33 ——————VSS VSS VDD15 VDD15 VSS VSS ——————VSS ADDR03 ADDR02 ADDR01
LTXD13 TXD12 TXD43 VSS ——————VSS VSS VDD15 VDD15 VSS VSS ——————VSS ADDR00 AS R/W
KTXD11 TXD42 TXD41 VSS ————————— —————————
VDD33 CS RESET INT
JTXD10 TXD09 TXD40 VDD33 ————————— —————————VSS DT TRSTN TMS
HTXD08 TXD39 TXD38 VSS ————————— —————————VDD33 TDI TCK TDO
GTXD07 TXD06 TXD37 VDD33 ————————— —————————VSS VSS RSV1 RSV2
FTXD05 TXD36 TXD35 VSS ————————— —————————VSS RSV3 RSV4 RSV5
ETXD04 TXD03 TXD34 VDD33 ————————— —————————VDD3 CKSPD0 CKSPD1 RSV6
DTXD02 TXD33 TXD32 VSS CTAPIN0 VDD33 CTAPIN1 HSLINN
08 VDD33 CTAPIN2 CK155
MHZN CTAPIN3 HSLINN
15 HSLOUTN
01 HSLOUTP
03 HSLOUTP
05 VSSCDR0 REF10 RESLO VDDCDR1 HSLOUTP
10 VDD33 VSS RSV9 RSV8 RSV7
CTXD01 TXD00 VSS HSLINN
01 HSLINP
01 HSLINN
05 HSLINP
05 HSLINP
08 HSLINP
09 HSLINN
11 CK155
MHZP HSLINP
13 HSLINP
15 HSLOUTP
01 HSLOUTN
03 HSLOUTN
05 VDDCDR0 REF14 RESHI VSSCDR1 HSLOUTN
10 HSLOUTN
13 HSLOUTP
13 VSS VDD33 VDD33
BVSS VSS HSLINN
00 HSLINN
02 HSLINN
03 HSLINN
04 HSLINP
06 HSLINP
07 HSLINN
09 HSLINP
11 CTAPIN4 HSLINN
13 HSLINP
14 HSLOUTP
00 HSLOUTP
02 HSLOUTP
04 HSLOUTP
06 HSLOUTP
07 HSLOUTP
08 HSLOUTP
09 HSLOUTN
11 HSLOUTN
12 HSLOUTN
14 HSLOUTN
15 VSS VSS
AVSS VSS HSLINP
00 HSLINP
02 HSLINP
03 HSLINP
04 HSLINN
06 HSLINN
07 HSLINN
10 HSLINP
10 HSLINN
12 HSLINP
12 HSLINN
14 HSLOUTN
00 HSLOUTN
02 HSLOUTN
04 HSLOUTN
06 HSLOUTN
07 HSLOUTN
08 HSLOUTN
09 HSLOUTP
11 HSLOUTP
12 HSLOUTP
14 HSLOUTP
15 VDD33A VSS
10 Agere Systems Inc.
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Hardware Design Guide
STSI-144 Scalable Time-Slot Interchanger
Ball Information (continued)
Ball Types
This table describes each type of input, output, and I/O ball used on the STSI-144.
Table 5. Ball Types
The dc switching and other electrical characteristics are specified later in this document.
Ball Definitions
This section describes the function of each of the device balls. The balls are listed by ball name. Package ball num-
bers are listed in Table 1 of this document. The static parameters (drive currents, switching thresholds, etc.) for
each ball type (input, output, etc.) are described in Table 16 through Table 21.
Table 6. Timing Port
Type Label Description
I CMOS input, TTL switching thresholds.
I pd CMOS input, TTL switching thresholds with internal pull-down resistor.
I pu CMOS input, TTL switching thresholds with internal pull-up resistor.
OCMOS output.
O od Open drain output.
LIN LVDS inputs.
LOUT LVDS outputs.
I/O Bidirectional ball; CMOS input with TTL switching thresholds and CMOS output.
None Analog inputs for external resistors, capacitors, voltage references, etc.
P Power and ground.
Ball Name Type Name/Descri ption
FSYNC I Frame Synchronization. This signal indicates the beginning of a 125 µs frame event (8 kHz).
The FSYNC ball can be programmed as active-low or active-high, but its polarity is the same
for all concentration highway interfaces (CHI). FSYNC can be sampled on either the positive
or negative edge of CHICLK. Time-slot numbers and bit offsets for each CHI are assigned
relative to the detection of FSYNC.
CHICLK I Clock. This is the master synchronous clock for the transmit and receive concentration
highways. The frequency can be 8.192 MHz or 16.384 MHz. It must be at least as fast as the
highest CHI data rate.
CKSPD0 I Clock Speed. Static control input that should be tied according to the frequency of CHICLK. If
CHICLK is connected to an 8.192 MHz source, CKSPD0 should be tied to VSS. If CHICLK is
connected to a 16.384 MHz source, CKSPD0 should be tied to VDD33.
CKSPD1 I pd Clock Speed. Reserved, leave disconnected. 20 kΩ pull-down resistor.
Agere Systems Inc. 11
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STSI-144 Scalable Time-Slot Interchanger
Ball Information (continued)
Ball Definitions (continued)
Table 7. Transmit and Receive Concentration Highways
Table 8. Control Port
Ball Name Type Name/Description
RXD[63:00] I pd Receive Data [6 3:0]. Receive concentration highways. These are serial, synchronous data
streams which may be individually programmed to operate at 2.048 Mbits/s, 4.096 Mbits/s,
8.192 Mbits/s, or 16.384 Mbits/s. They carry 32, 64, 128, or 256 time slots (respectively) each
occupying eight contiguous bits. 20 kΩ pull-down resistor.
TXD[63:32] I/O Transmit Data [63:32]. Normally these are output concentration highway data streams with
data rate options identical to the RXD inputs. These balls can be configured to operate as
bidirectional multiplex ports. Further information can be found in the system design guide.
20 kΩ pull-down resistor.
TXD[31:00] I/O Transmit Data [31:00]. Normally these are output concentration highway data streams with
data rate options identical to the RXD inputs. These balls can be configured to operate as
bidirectional multiplex ports such as H.110. Further information can be found in the system
design guide. 20 kΩ resistor connected to VPRE.
Ball
Name Type Name/Description
MPUCLK I Processor Clock. This clock is used to sample address, data, and control signals from the
microprocessor. This clock must be within the range of 0 MHz—66 MHz. Required for operation.
CS IChip Select. Active-low chip select. This input is held low for the duration of any read or write
access to the STSI-144. Required for operation.
AS IAddress Strobe . Active-low address strobe that is one MPUCLK cycle wide at the start of a
microprocessor access cycle to the STSI-144. This is used to initiate a microprocessor access.
Required for operation.
R/W IRead/Write. Cycle se lection. R/W is set high during a read cycle, or set low for a write cycle.
Required for operation.
ADDR
[15:00] I pu Address [15:00]. ADDR[15] is the most significant bit and ADDR[00] is the least significant bit
for addressing all the internal registers during microprocessor access cycles. All addresses are
16-bit word addresses; hence, in a typical application ADDR[00] of the STSI-144 device would
be connected to address bit 1 of a byte addressable system address bus. Required for
operation. 200 kΩ pull-up resistor.
Note: The STSI-144 is little-endian; the least significant byte is stored in the lowest address and
the most significant byte is stored in the highest address. Care must be exercised in
connection to microprocessors that use big-endian byte ordering.
DATA
[15:00] I/O Data [15:00]. Data bus for all transfers between the microprocessor and the internal registers.
The balls are inputs during write cycles and outputs during read cycles. DATA15 is the most
significant bit, and DATA00 is the least significant bit. Required for operation.
PAR[1:0] I/O Control Port Parity [1:0]. Byte-wide parity bits for data. P A R[1] is the parity for DATA [15:8], and
PAR[0] is the parity for DATA [7:0]. The parity sense (even or odd) is application programmable
via a register bit in the STSI-144. Not required for operation.
DT OData Transfer Acknowledge. Active-low for one MPUCLK cycle. Indicates that data has been
written during write cycles or that data is valid during read cycles. High impedance when CS is a
1 and driven when CS is 0. Required for operation.
INT O od Interrupt. This output is asserted low to indicate that an interrupt condition has occurred. This
signal remains active-low until the interrupt status register has been cleared or masked.
12 Agere Systems Inc.
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STSI-144 Scalable Time-Slot Interchanger
Ball Information (continued)
Ball Definitions (continued)
Table 9. High-Speed Serial Link Signals
* One of either CK78MHZ or CK155MHZ[P,N] is required, the other may be left unconnected.
Table 10. Initialization and Test Access
Ball Name Type Name/Description
HSLIN[P,N]
[15:00] LIN High-speed Serial Link Input. 622.08 Mbits/s LVDS data input. Unused inputs may be
left disconnec ted.
HSLOUT[P,N]
[15:00] LOUT High-speed Serial Link Output. 622.08 Mbits/s LVDS data output.
CK155MHZ[P,N] LIN 155.52 MHz LVDS reference clock input.*
CK78MHZ I pu 77.76 MHz CMOS reference clock input. 200 kΩ pull-up resistor.*
HSLRFSEL I pd High-speed Serial Link Reference Select. HSL clock reference select. 50 kΩ pul l-
down resistor.
0 = 78 MHz. The CK78MHZ input is used as the reference.
1 = 155 MHz. The CK155MHZ[P,N] input is used as the reference.
REFCLK O Reference Clock Output. 8 kHz, 16.384 MHz, or 38.88 MHz derived from an HSL input
stream. (See Reference_Clock_Select in the Global_Control register in the STSI-144
Register Description.)
REFSYNC O Reference Synchronization Output. Active-high 8 kHz sync pulse, one REFCLK
period wide, derived from an HSL input stream.
RESHI None External 100 Ω Resistor Pin 1. A 100 Ω ± 1% resistor is required as a reference for
LVDS buffers.
RESLO None External 100 Ω Resistor Pin 2.
REF10 None External 1.0 V Reference. (Optional) Selected by Power_Control register bit 2.
REF14 None External 1.4 V Reference. (Optional) Selected by Power_Control register bit 2.
CTAP[4:0] None LVDS Termination Center Taps. (Optional) Bypass to ground with 0.01 µF capacitor.
Ball Name Type Name/Description
RESET I pu Reset. Global reset, active-low. Initializes all internal registers to their default state. The reset
occurs asynchronously, but RESET should be held low for at least 1 µs. 20 kΩ pull-up resistor.
TCK I pu Test Clock. This signal provides timing for the boundary scan and test access port (TAP)
controller. Should be static except during boundary-scan testing. 20 kΩ pull-up resistor.
TDI I pu Test Data In. Dat a input for the boundary scan. Sampled on the rising edge of TCK. 20 kΩ pull-
up resistor.
TMS I pu Test Mode Select (Active-Low). Controls boundary-scan test operations. TMS is sampled on
the rising edge of TCK. 20 kΩ pul l- up re sistor.
TRSTN I pd Test Reset (Active-Low). This signal is an asynchronous reset for the TAP controller. 20 kΩ
pull-down resistor.
TDO O Test Data Out. Updated on the falling edge of TCK. The TDO output is high impedance except
when scanning out test data.
HIZ I pu Output Enable. All output and bidrectional buffers will be high impedance when this input is
low unless boundary scan is enabled (TRSTN = 1). 20 kΩ pull-up resistor.
RSV[9:1] — Reserved [9:1]. These balls are used by Agere Systems during the manufacturing process.
They must be left unconnected.
Agere Systems Inc. 13
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STSI-144 Scalable Time-Slot Interchanger
Ball Information (continued)
Ball Definitions (continued)
Table 11. Power Balls
Symbol Type Name/Description
VDD33 PI/O Power. Power supply balls for the I/O pads (3.3 V ± 5%).
VDD15 PCore Power. Power supply balls for the core (1.5 V ± 5%).
VSS PGround. Common ground balls for 3.3 V and 1.5 V supplies.
VPRE PPrecharge. Precharge voltage to support H.110 hot insertion on TXD[31:00]. If the device is
used in an H.1 10 hot insertion applications, the signal should be connected to backplane early
voltage; otherwise connect this signal to ground.
VIO PPCI Buffer Voltage Select. For an H.110 application using TXD[31:00] in a 5 V signaling
environment, connect this signal to 5 V. For an H.110 application using TXD[31:00] in a 3 V
signaling environment, connect this signal to VDD33. For all other applications, connect this
signal to VDD33.
VDDPLL PPLL Power . 1.5 V power supply for the internal phase-locked loop. Must include local 0.01 µF
capacitor to VSSPLL.
VSSPLL PPLL Ground. Isolated ground for the internal phase-locked loop.
VDDCDR[1,0] PIsolated Clock/Data Recovery 1.5 V ± 5% Power. These pins require a dedicated inductor/
capacitor (L/C) pi filter with local bypass capacitors.
VSSCDR[1,0] PIsolated Clock/Data Recovery Ground.
14 Agere Systems Inc.
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STSI-144 Scalable Time-Slot Interchanger
Absolute Maximum Ratings
Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are absolute
stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those
given in the operational sections of the data sheet. Exposure to absolute maximum ratings for extended periods can
adversely affect device reliability.
Table 12. Abso lute Maximum Ratings
Handling Precautions
Although electrostatic discharge (ESD) protection circuitry has been designed into this device, proper precautions
must be taken to avoid exposure to ESD and electrical overstress (EOS) during all handling, assembly, and test
operations. Agere employs both a human-body model (HBM) and a charged-device model (CDM) qualification
requirement in order to determine ESD-susceptibility limits and protection design evaluation. ESD voltage
thresholds are dependent on the circuit parameters used in each of the models, as defined by JEDEC’s
JESD22-A114 (HBM) and JESD22-C101 (CDM) standards.
ESD Tolerance
Table 13. ESD Tolerance
Package Thermal Characteristic s
Table 14. Power Consumption
■ΘJA = 20 °C/W.
* MPUCLK = 66 MHz, CHICLK = 16.384 MHz, TA = 25 °C, all CHIs active, all outputs loaded with 50 pF. All HSLs active.
Recommended Operating Conditions
Table 15. Operating Conditions
Parameter Min Max Unit
Supply Voltage (VDD33) –0.5 4.2 V
Supply Voltage (VDD15) –0.5 1.8 V
Input Voltage:
TXD[63:00]
All Other Inputs –0.5
–0.3 5.5
VDD33 + 0.3 V
Storage Temperature –40 125 °C
Junction Temperature — 125 °C
Device Voltage Type
STSI-144 2,000 V HBM (human-body model)
500 V CDM (charged-device model)
Supply Voltage Typ*Max
VDD33 750 mW at 3.3 V 900 mW at 3.47 V
VDD15 750 mW at 1.5 V 900 mW at 1.6 V
Parameter Min Typ Max Unit
Supply Voltage (VDD33) 3.14 3.3 3.47 V
Supply Voltage (VDD15) 1.4 1.5 1.6 V
Ambient Temperature –40 — 85 °C
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STSI-144 Scalable Time-Slot Interchanger
dc Electrical Characteristics
This section describes all the static parameters associated with all the ball types used in the STSI-144 device.
Table 16. CMOS Inputs
* Excludes current due to pull-up or pull-down resistors.
Table 17. CMOS Outputs
Table 18. CMOS Bidirectio nals (Excl u ding TXD[ 63:00 ] )
Table 19. CMOS Bidirectio nals (TX D[ 63:00 ])
Parameter Symbol Conditions Min Typ Max Unit
Input Leakage Current IIL VSS < VIN < VDD33 —— 1* µA
High-input Voltage VIH —2.0—VDD33 + 0.3 V
Low-input Voltage VIL —–0.3—0.8V
Input Capacitance CI——2.5—pF
Parameter Symbol Conditions Min Typ Max Unit
Output Voltage Low VOL IOL = –10 mA — — 0.4 V
Output Voltage High VOH IOL = 10 mA 2.4 — — V
Output Curr ent Low IOL ———10mA
Output Curr ent High I OH ———10mA
Output Capaci tance CO——3—pF
HIZ Output Leakage
Current IOZ ———10µA
Parameter Symbol Conditions Min Typ Max Unit
Leakage Current ILVSS < VIN < VDD33 ——11µA
High-input Voltage VIH —2.0—VDD33 + 0.3 V
Low-input Voltage VIL — –0.3 — 0.8 V
Biput Capacitance CIB ——5.0—pF
Output Voltage Low VOL IOL = –10 mA — — 0.4 V
Output Voltage High VOH IOL = 10 mA 2.4 — — V
Parameter Symbol Conditions Min Max Unit
Leakage Current ILVSS < VIN < VDD33 —10µA
High-input Voltage VIH VIO = 5.0 V
VIO = 3.3V 2.0
0.5 VDD33 5.5
VDD33 + 0.5 V
Low-input Voltage VIL VIO = 5.0 V
VIO = 3.3V –0.5
–0.5 0.8
0.3 VDD33 V
Biput Capacitance CIB — — 10 pF
Output Voltage Low VOL IOL = 1.5 mA, VIO = 3.3 V
IOL = 6.0 mA, VIO = 5.0 V —
—0.1 VDD33
0.55 V
Output Voltage High VOH IOL = –0.5 mA, VIO = 3.3 V
IOL = –2.0 mA, VIO = 5.0 V 0.9 VDD33
2.4 —
—V
Pos itive-going Threshold Vt+ —1.22.0V
Negative-going Threshold Vt– —0.61.6V
Hysteresis (Vt+ – Vt–)VHYS —0.4—V
16 Agere Systems Inc.
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STSI-144 Scalable Time-Slot Interchanger
dc Electrical Characteristics (continued)
Table 20. LVDS Receiver dc Parameters
Table 21. LVDS Transmitter dc Parameters
Parameter Symbol Conditions Min Typ Max Unit
Common-mode Input Range VCM |VGPD| < 925 mV,
dc – 1 MHz 0.0 1.2 2.4 V
Input Differential Threshold VIDTH |VGPD| < 925 mV,
450 MHz –100 — 100 mV
Input Differential Hysteresis VHYST (+VIDTHH) – (–VIDTHL)25——mV
Receiver Differential Input
Impedance RIN Built-in center-tapped
termination 80 100 120 Ω
Parameter Symbol Conditions Min Typ Max Unit
Output Voltage High, P or N VOH RLOAD = 100 Ω ± 1% — — 1.475*
* External references selected (LVDS_Voltage_Reference_Select = 1), REF10 = 1.0 V ± 3%, REF14 = 1.4 V ± 3%.
V
Output Voltage Low, P or N VOL RLOAD = 100 Ω ± 1% 0.925*——V
Output Differen tia l Vo ltage |VOD|RLOAD = 100 Ω ± 1% 0.25 — 0.45*V
Output Offset Voltage VOS RLOAD = 100 Ω ± 1% 1.125*— 1.275*Ω
Output Impe dan ce ,
Differential ROVCM = 1.0 V and 1.4 V 80 100 120 Ω
Change in Differential Voltage
Between Complementary States |∆VOD|RLOAD = 100 Ω ± 1% — — 25 mV
Change in Output Offset Voltage
Between Complementary States |∆VOS|RLOAD = 100 Ω ± 1% — — 25 mV
Output Curr ent ISA, ISB Driver shorted to GND — — 24 mA
Output Curr ent ISAB Driver shorted together — — 12 mA
Power-off Output Leakage |IXA|,
|IXB|HSL disabled,
VPAD, VPADN = 0 V—2.5 V ——10mA
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STSI-144 Scalable Time-Slot Interchanger
Timing Diagrams and ac Characteristics
Figure 3 and Figure 4 describe the timing specifications for the input clocks on the STSI-144.
Figure 3. CHICLK Timing Specifications
Table 22. CHICLK Timing Specifications
* VIH to VIH or VIL to VIL.
Figure 4. MPUCLK Timing Specifications
Table 23. MPUCLK Timing Specifications
* VIH to VIH or VIL to VIL.
Parameter Description Min Typ Max Unit
t1CHICLK Rise Time — 2 7 ns
t2CHICLK Width (8.192 MHz)* 48.84 — 73.24 ns
t2CHICLK Width (16.384 MHz)* 24.42 — 36.62 ns
t3CHICLK Fall Time — 2 7 ns
t4CHICLK Period (8.192 MHz) — 122.07 — ns
t4CHICLK Period (16.384 MHz) — 61.03 — ns
Parameter Description Min Typ Max Unit
t5MPUCLK Rise Time — 2 7 ns
t6MPUCLK Width* 6.06 — — ns
t7MPUC LK Fall Ti me — 2 7 ns
t8MPUCLK Period 15.2 — — ns
t1VDD33
VIL
VIH VIH
VIL
t3
t4
50%
t2
t5VDD33
VIL
VIH VIH
VIL
t7
t8
50%
t6
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Timing Diagrams and ac Characteristics (continued)
Figure 5 shows the ac timing specifications for the STSI-144. All timing parameters are referenced to VIHmin and
VILmax. The reference signal polarity may be inverted for some timing parameters.
Figure 5. ac T iming Measurement Specification
Table 24. ac Timing Measurement Specification
Parameter Description
t9Setup Time
t10 Hold Ti me
t11 Output Delay
t12 Output 3-State Time
t9
VIL
VIH
VIL
t11
t10
t12
REFERENCE SIGNAL
INPUT SIGNAL
OUTPUT SIGNAL
VIH
VIL
HIZ
VOH
VOL
HIZ
HIZ
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STSI-144 Scalable Time-Slot Interchanger
Timing Diagrams and ac Characteristics (continued)
Note: This figure assumes STSI-144 is programmed to sample FSYNC on rising edge of CHICLK.
Figure 6. CHI Interface Timing
Table 25. CHI Interface Timing
* Applies if Driver_Enable_Control = 01; see Figure 17, CHI 3-State Output Control, if Driver_Enable_Control = 11.
All timing specifications are with respect to VIHmin and VILmax as shown in Figure 5. All timing specifications also
apply under the following conditions:
■If FS is active-low.
■If the falling edge of CHICLK is specified as the active edge.
■At all RXD and TXD rates (16.384 Mbits/s, 8.192 Mbits/s, 4.096 Mbits/s, or 2.048 Mbits/s) with a CHICLK
frequency of 16.384 MHz or 8.192 MHz.
Parameter Description Min Max Unit
t13 FSYNC Setup T ime to Active CHICLK Edge 10 — ns
t14 FSYNC Hold Time from Active CHICLK Edge 5 — ns
t15 RXD Setup to Active CHICLK Edge 10 — ns
t16 RXD Hold Ti me from Active CHICLK Edge 5 — ns
t17 TXD High Z to Data Valid — 15 ns
t18 TXD Propagation Delay from Active CHICLK Edge 2 12 ns
t19 Transmit Data High Impedance* — 15 ns
t
18
t
19
TXD
CHICLK
t
13
t
14
t
17
RXD
FSYNC
t
15
t
16
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STSI-144 Scalable Time-Slot Interchanger
Timing Diagrams and ac Characteristics (continued)
Note: For this timing diagram, it is assumed that FSYNC has been programmed to be active-high, and to be sampled by the rising edge of the
CHICLK.
Figure 7. Typical Receive CHI Timing with 16.384 Mbits/s Data and 16.384 MHz CHICLK
Notes:
1/4 bit off set not valid with 16 Mbits/s data.
For this timing diagram, it is assumed that FSYNC has been programmed to be active-high, and to be sampled by the rising edge of the
CHICLK.
Figure 8. Transmit CHI Timing with 16.384 Mbits/s Data and 16.384 MHz CHICLK
FSYNC
CHICLK
w/ 0 offset da ta s a m p le d
w/ ¼ bit offset d ata s a m p le d
w/ ½ bit offset data sampled
w/ ¾ bit offset da ta s a m p le d
w/ bit offset = 1 da ta s a m p le d
w/ 2¾ bit offset da ta s a m p le d
w/ bit offset = 7 da ta s a m p le d
da ta s a m p le d
d ata s a m p le d
da ta s a m p le d
w/ TS offset = 1,
bit offset = 0 TS254 B6 TS254 B7 TS255 B0
TS0 B 1
TS0 B 0TS255 B1
T
S255 B2
T
S255 B3
T
S255 B 4
TS0 B 4 TS 0 B 5
TS254 B7 TS255 B0 TS255 B1 TS255 B2
T
S255 B3
T
S255 B4
T
S255 B 5
T
S255 B6
TS 0 B 0 TS0 B1 TS0 B 2 TS 0 B 3
TS 255 B 6 TS 255 B 7 TS0 B0 TS0 B1 TS0 B 2 TS 0 B 3 TS0 B4 TS0 B 5
TS255 B6
T
S255 B7 TS0 B0 TS0 B1 TS0 B2 TS0 B3 TS0 B4 TS0 B5
TS255 B5
TS255 B3 TS255 B4 TS255 B5
TS255 B5 TS255 B6 TS255 B7
TS255 B6 TS255 B7
TS255 B6
T
S255 B7 TS0 B0 TS0 B1 TS0 B2 TS0 B3
T
S255 B6 TS255 B7
T
S255 B5
T
S255 B7 TS0 B 0
w/ TS offset = 13,
bit offset = 3¼ TS242 B3 TS242 B4 TS242 B5 TS243 B4
T
S243 B5TS242 B6
T
S242 B7
T
S243 B 0
T
S243 B1
TS255 B7 TS0 B0
T
S243 B2 TS243 B3
TS0 B 5 TS 0 B 6TS0 B3 TS0 B 4
TS0 B1 TS0 B 2 TS 0 B3
TS 0 B 7 TS1 B0TS 0 B 1 TS0 B2
w/ TS offset = 255,
bit offset = 7¾ TS255 B6
TS0 B 4TS0 B 0
TS255 B6 TS255 B7 TS0 B0 TS0 B1 TS0 B2 TS 0 B3 TS0 B4 TS0 B5
FSYNC
CHICLK
w/ 0 offset
w/ ½ bit offset
w/ bit offset = 1
w/ TS offset = 255,
bit offs et = 7½ TS255 B6 TS255 B7 TS0 B0
w/ TS offset = 1,
bit offset = 0
TS0 B2 TS0 B 3 TS0 B4
TS254 B5 TS254 B6 TS 254 B7
T
S255 B0
TS255 B4 TS255 B5
TS0 B3 TS0 B4
T
S255 B1
T
S255 B2 TS255 B3
TS0 B0 TS0 B1
TS255 B4 TS255 B5
TS255 B5 TS255 B6 TS 255 B7 TS0 B0
TS0 B3 TS0 B4 TS0 B5
TS0 B5
TS0 B1 TS0 B2
TS0 B1 TS0 B2
TS255 B6
T
S255 B7
TS255 B5 TS2 55 B6 TS255 B7 TS 0 B0 TS0 B1 TS0 B2 TS0 B3 TS0 B4
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June 2003 Hardware Design Guide
STSI-144 Scalable Time-Slot Interchanger
Timing Diagrams and ac Characteristics (continued)
Note: For this timing diagram, it is assumed that FSYNC has been programmed to be active-high, and to be sampled by the rising edge of the
CHICLK.
Figure 9. Typical Receive CHI Timing with 8.192 Mbits/s Data and 16.384 MHz CHICLK
Note: For this timing diagram, it is assumed that FSYNC has been programmed to be active-high, and to be sampled by the rising edge of the
CHICLK.
Figure 10. Tr ansmit CHI Timing with 8.192 Mbits/s Data and 16.384 MHz CHICLK
FSYNC
CHICLK
w/ 0 offset data sampled
w/ ¼ bit offs et data sampled
w/ ½ bit offs et data sampled
w/ ¾ bit offs et data sampled
w/ bit off set = 1 data sampled
w/ 2¾ bit offs et data sampled
w/ bit off set = 7 data sampled
data sampled
data sampled
data sampled TS0 B2 TS0 B3 TS0 B4
w/ TS of fset = 127,
bit offset = 7¾ TS 127 B7 TS0 B0 T S0 B 1
TS127 B2 TS127 B3 TS127 B4
w/ TS offset = 13,
bit offset = 3¼ TS114 B 4 TS114 B5 TS114 B6 TS114 B7 TS115 B0 TS115 B1
w/ TS offset = 1,
bit off set = 0 T S126 B7 TS127 B0 TS127 B1
TS127 B4 TS127 B5
TS 127 B4 T S127 B5
TS127 B0 TS127 B1 TS127 B2 TS127 B3
TS127 B6 TS127 B7
TS0 B2 TS0 B 3
TS0 B2 TS0 B3
TS0 B0 TS0 B 1
TS127 B6 TS127 B7 TS0 B0 TS 0 B1
TS 127 B6 T S127 B7 TS0 B0 TS0 B1
TS0 B3 TS0 B4
TS127 B7 T S0 B0 TS0 B1 TS0 B2 TS0 B3
TS127 B 7 TS0 B0 TS0 B1 TS 0 B2
TS127 B7 TS0 B0 TS0 B1 TS0 B2 TS0 B3 TS0 B4
FSYNC
CHICLK
w/ 0 offset
w/ ¼ bit offset
w/ ½ bit offset
w/ bit offset = 1
TS 127 B6 TS127 B7 TS0 B0 T S0 B1 TS0 B2 TS0 B3
TS0 B2 TS0 B3
TS127 B6 T S 127 B7 TS0 B0 T S0 B1 TS0 B2
TS127 B6 TS127 B7 TS0 B0 TS0 B1
TS 127 B5 TS127 B6 TS127 B7 TS0 B0
w/ TS offset = 1,
bit offset = 0
TS127 B7 TS0 B0 TS0 B1
w/ TS offset = 127,
bit offset = 7¾
TS 126 B6 TS126 B7 TS127 B0 TS127 B1
TS0 B2 TS0 B3
TS0 B1 TS0 B2
TS127 B2 TS127 B3
TS0 B3
22 Agere Systems Inc.
Advance Information
June 2003
Hardware Design Guide
STSI-144 Scalable Time-Slot Interchanger
Timing Diagrams and ac Characteristics (continued)
Note: For this timing diagram, it is assumed that FSYNC has been programmed to be active-high, and to be sampled by the rising edge of the
CHICLK.
Figure 11. Typical Receive CHI Timing with 4.096 Mbits/s Data and 16.384 MHz CHICLK
Note: For this timing diagram, it is assumed that FSYNC has been programmed to be active-high, and to be sampled by the rising edge of the
CHICLK.
Figure 12. Transmit CHI Timing with 4.096 Mbits/s Data and 16.384 MHz CHICLK
FSYNC
CHICLK
w/ 0 offset data sampled
w/ ¼ bit offset data sam p led
w/ ½ bit offset data sam p led
w/ ¾ bit offset data sampl e d
w/ bit offset = 1 data sampled
w/ 2¾ bit offset data sample d
w/ bit offset = 7 data sampled
data sampled
data sampl e d
data sampl e d
TS50 B7
w/ TS offset = 63,
bit offset = 7¾ TS0 B0 TS0 B1 TS0 B2
w/ TS offset = 13,
bit offset = 3¼ TS50 B 4 TS50 B 5 TS50 B6
w/ T S offset = 1,
bit offset = 0 TS63 B 0 TS63 B1 TS63 B2
TS63 B5 TS63 B6 TS63 B7
TS63 B 1 TS63 B2 TS63 B3
TS63 B 7 TS0 B0 TS0 B1
TS63 B 7 TS0 B0 TS0 B1
TS63 B7 TS0 B0 TS0 B1 TS0 B2
TS0 B0 TS0 B1 TS0 B2
TS63 B 7 TS0 B0 TS0 B1 TS0 B2
FSYNC
CHICLK
w/ 0 offset
w/ ¼ bit offs et
w/ ½ bit offs et
w/ bit offset = 1
w/ TS offset = 63,
bit offset = 7¾
TS62 B7 TS63 B0 TS63 B1
w/ TS off set = 1,
bit offset = 0
TS63 B6 TS63 B7 TS0 B0
TS63 B7 TS0 B0 TS0 B1 TS0 B2
TS63 B6 TS63 B7 TS0 B0 TS0 B1
TS63 B7 TS0 B0 TS0 B1
TS63 B7 TS0 B0 TS0 B1
Agere Systems Inc. 23
Advance Information
June 2003 Hardware Design Guide
STSI-144 Scalable Time-Slot Interchanger
Timing Diagrams and ac Characteristics (continued)
Note: For this timing diagram, it is assumed that FSYNC has been programmed to be active-high, and to be sampled by the rising edge of the
CHICLK.
Figure 13. Typical Receive CHI Timing with 2.048 Mbits/s Data and 16.384 MHz CHICLK
Note: For this timing diagram, it is assumed that FSYNC has been programmed to be active-high, and to be sampled by the rising edge of the
CHICLK.
Figure 14. Tr ansmit CHI Timing with 2.048 Mbits/s Data and 16.384 MHz CHICLK
FSYNC
CHICLK
w/ 0 offset data sampled
w/ ¼ bit offset data sampled
w/ ½ bit offset data sampled
w/ ¾ bit offset data sampled
w/ bit offset = 1 data sampled
w/ 2¾ bit offset data sampled
w/ bit offset = 7 data sampled
data sampled
data sampled
data sampled
w/ TS offset = 31,
bit offset = 7¾ TS0 B0 TS0 B1 TS0
w/ TS offset = 1,
bit offset = 0 TS31 B0 TS31 B1
w/ TS offset = 13,
bit offset = 3¼ TS18 B5 TS18 B6
TS31 B5 TS31 B6 TS31
TS31 B1 TS31 B2
TS31 B7 TS0 B0 TS0
TS31 B7 TS0 B0
TS0 B0 TS0 B1
TS0 B0 TS0 B1
TS31 B7 TS0 B0 TS0 B1
FSYNC
CHICLK
w/ 0 offset
w/ ¼ bit offset
w/ ½ bit offset
w/ bit offset = 1
TS30 B7 TS31 B0
T
S31 B01
w/ TS offset = 1,
bit offset = 0
TS31 B7 TS0 B0 TS0 B1
w/ TS offset = 31,
bit offset = 7¾
TS31 B7 TS0 B0
TS31 B6 TS31 B7 TS0 B0
TS31 B7 TS0 B0 TS0 B 1
TS31 B 7 TS0 B0
24 Agere Systems Inc.
Advance Information
June 2003
Hardware Design Guide
STSI-144 Scalable Time-Slot Interchanger
Timing Diagrams and ac Characteristics (continued)
Note: For this timing diagram, it is assumed that FSYNC has been programmed to be active-high, and to be sampled by the rising edge of the
CHICLK.
Figure 15. Typical Receive CHI Timing with 8.192 Mbits/s Data and 8.192 MHz CHICLK
Notes:
1/4 bit off set not valid with 8 MHz data and 8 MHz clock.
For this timing diagram, it is assumed that FSYNC has been programmed to be active-high, and to be sampled by the rising edge of the
CHICLK.
Figure 16. Transmit CHI Timing with 8.192 Mbits/s Data and 8.192 MHz CHICLK
FSYNC
CHICLK
w/ 0 offset data sampled
w/ ¼ bit offset data sampled
w/ ½ bit offset data sampled
w/ ¾ bit offset data sampled
w/ bit offset = 1 data sampled
w/ 2¾ bit offset data sampled
w/ bit offset = 7 data sampled
data sampled
data sampled
data sampled TS0 B5 TS0 B6 TS0 B7 TS1 B0TS0 B1 TS0 B2 TS0 B3 TS0 B 4
w/ TS offset = 127,
bit offset = 7¾ TS127 B6 TS127 B7 TS0 B0
T
S115 B2 TS115 B3 TS115 B4
T
S115 B5TS114 B6
T
S114 B7
T
S115 B0
T
S115 B1
w/ TS offset = 13,
bit offset = 3¼ TS114 B3 TS114 B4 TS114 B5
T
S127 B5
T
S127 B6 TS127 B7 TS0 B0
TS0 B 0 TS0 B1
w/ TS offset = 1,
bit offset = 0 TS126 B6 TS126 B7 TS127 B0 TS127 B1
T
S127 B2
T
S127 B3
T
S127 B4
TS0 B3
TS126 B7 TS127 B0 TS127 B1 TS127 B2
T
S127 B3
T
S127 B4
T
S127 B5
T
S127 B6
T
S127 B7
T
S127 B7 TS0 B0 TS0 B1 TS0 B2TS127 B3 TS127 B4
T
S127 B5 TS127 B6
TS0 B5
TS127 B5 TS127 B6 TS127 B7 TS0 B0 TS0 B1 TS0 B2 TS0 B3 TS0 B4
TS0 B1 TS0 B2 TS0 B3 TS0 B4TS127 B5 TS127 B6
T
S127 B7 TS0 B0
TS0 B2 TS0 B3 TS0 B4 TS0 B5TS127 B6
T
S127 B7 TS0 B0 TS0 B1
TS0 B2 TS0 B3 TS0 B4 TS0 B5TS127 B6 TS127 B7 TS0 B0 TS0 B1
TS127 B6 TS127 B7 TS0 B0 TS0 B1 TS0 B2 TS0 B3 TS0 B4 TS0 B5
FSYNC
CHICLK
w/ 0 offset
w/ ½ bit offset
w/ bit offset = 1
S127 B5
w/ TS offset = 127,
bit offset = 7½ TS127 B6 TS1 2 7 B7 TS0 B 0 TS0 B 1 TS0 B2 TS0 B 3 TS0 B 4 TS0 B 5
TS0 B4
w/ TS offset = 1,
bit offset = 0 T S 126 B5 TS126 B6
S126 B7 TS127 B0
S127 B1
S127 B2
S127 B3
S127 B4
TS0 B0 TS0 B1 TS0 B2 TS0 B3TS127 B4 TS127 B5
S127 B6 TS127 B7
TS0 B1 TS0 B2 TS0 B3 TS0 B4TS127 B5 TS127 B6 TS127 B7 TS0 B0
TS127 B5 TS127 B6
S127 B7 TS0 B0 TS0 B1 TS0 B2 TS0 B3 TS0 B4 TS0 B5
Agere Systems Inc. 25
Advance Information
June 2003 Hardware Design Guide
STSI-144 Scalable Time-Slot Interchanger
Timing Diagrams and ac Characteristics (continued)
Figure 17. CHI 3-State Output Control
Table 26. CHI 3-State Output Control
Control in the table below refers to bits [6:4] in Transmit_CHI_Global_Configuration register (0x0C84). This only
applies if bits 13 and 12 of the corresponding T ransmit_CHI_Control register (0x0C00—0x0C7E) are set to 11. See
STSI-144 Register Description.
Parame ter Contr ol Refer en ce Po int *
* Like edge is the reference edge (rising or falling) as defined by the Transmit_Clock_Edge bit in the
Transmit_CHI_Global_Configuration (0x0C84) registe r. See STSI-144 Register Description document for further details.
Min†
† All timing specifications are with respect to the parameters shown in Figure 5.
Max†Unit
t20 000 After Previous Like Edge in 16 MHz 50 59 ns
001 After Previous Like Edge in 16 MHz 44 53 ns
010 After Previous Like Edge in 16 MHz 38 47 ns
011 After Previous Like Edge in 16 MHz 32 41 ns
t21 000 After Previous Opposite Edge in 8 MHz 50 59 ns
001 After Previous Opposite Edge in 8 MHz 44 53 ns
010 After Previous Opposite Edge in 8 MHz 38 47 ns
011 After Previous Opposite Edge in 8 MHz 32 41 ns
t22 100 After Previous Like Edge (8 MHz mode only) 111 120 ns
101 After Previous Like Edge (8 MHz mode only) 105 114 ns
110 After Previous Like Edge (8 MHz mode only) 99 108 ns
111 After Previous Like Edge (8 MHz mode only) 93 102 ns
CHICLK
16.384 MHz
t
20
TXD
16.384 Mbits/s
CHICLK
8.192 MHz
TXD
8.192 Mbits/s
CHICLK
8.192 MHz
TXD
8.192 Mbits/s
t
21
t
22
26 Agere Systems Inc.
Advance Information
June 2003
Hardware Design Guide
STSI-144 Scalable Time-Slot Interchanger
Timing Diagrams and ac Characteristics (continued)
Figure 18. Microprocessor Port Timing—Read Cycle
Table 27. Microprocessor Port Timing—Read Cycle
* All timing specifications are with respect to the parameters shown in Figure 5.
Parameter Description Min*Max*Unit
t23 Address Setup 5 — ns
t24 Address Hold 1 — ns
t25 Chip Sel ect Setup 5 — ns
t26 Chip Select Hold 1 — ns
t27 Address Strobe Setup 5 — ns
t28 Address Strobe Hold 1 — ns
t29 R/W Setup 5 — ns
t30 R/W Hold 1 — ns
t31 Data Output Enable — 15 ns
t32 Data Clock to Valid 1 7 ns
t33 Data High Impedance — 8 ns
t34 DT High Impedance to Valid 1 15 ns
t35 DT Clock to Out 1 7 ns
t36 DT Valid to High Impedance 1 8 ns
MPUCLK
DATA[15:00]
PAR[1:0]
t
24
t
23
ADDR[15:00]
CS
AS
R/W
DT
t
25
t
27
t
28
t
29
t
31
t
35
t
34
t
26
t
30
t
32
t
35
t
36
t
33
Agere Systems Inc. 27
Advance Information
June 2003 Hardware Design Guide
STSI-144 Scalable Time-Slot Interchanger
Timing Diagrams and ac Characteristics (continued)
Figure 19. Microprocessor Port Timing—Write Cycle
Table 28. Microprocessor Port Timing—Write Cycle
* All timing specifications are with respect to the parameters shown in Figure 5.
Note: Posted writes follow the same timing shown in Figure 19 and Table 28. A posted write may return a DT prior
to the device completing the write cycle. This allows the microprocessor to continue operation while the
STSI-144 completes the write.
Parameter Description Min*Max*Unit
t37 Addres s Set up 5 — ns
t38 Addres s Hol d 1 — ns
t39 Chip Select Setup 5 — ns
t40 Chip Select H old 1 — ns
t41 Addres s Strobe Setup 5 — ns
t42 Addres s Strobe Hold 1 — ns
t43 R/W Setup 5 — ns
t44 R/W Hold 1 — ns
t45 Data Setup 5 — ns
t46 Data Hold 1 — ns
t47 DT High Impedance to Valid 1 15 ns
t48 DT Clock to Out 1 7 ns
t49 DT Valid to High Impedance 1 8 ns
MPUCLK
DATA[15:00]
PAR[1:0]
t
38
t
37
ADDR[15:00]
CS
AS
R/W
DT
t
39
t
41
t
42
t
43
t
45
t
48
t
47
t
40
t
44
t
46
t
48
t
49
28 Agere Systems Inc.
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June 2003
Hardware Design Guide
STSI-144 Scalable Time-Slot Interchanger
Timing Diagrams and ac Characteristics (continued)
Figure 20. LVDS Output Timing Specifications
Table 29. LVDS ac Characteristics
Parameter Symbol Description Conditions Min Typ Max Unit
t49 tRVOD Rise Time,
20% to 80% ZL = 100 Ω ± 1%,
CP = 3.0 pF, CN = 3.0 pF 100 — 210 ps
t50 tFVOD Fall Ti me,
80% to 20% ZL = 100 Ω ± 1%,
CP = 3.0 pF, CN = 3.0 pF 100 — 210 ps
t49
20%
80% t50
20%
80%
Agere Systems Inc. 29
Advance Information
June 2003 Hardware Design Guide
STSI-144 Scalable Time-Slot Interchanger
Outline Diagrams
Dimensions are in millimeters.
0.61 ± 0.08 1.17 ± 0.05 2.51 MAX
SEATI N G PLA N E
SOLDER BALL
0.60 ± 0.10 0.20
AF
AE
AD
AC
AB
AA
Y
W
V
U
T
R
G
25 SPACES @ 1.00 = 25.00
P
N
M
L
K
J
H
1 2 3 4 5 6 7 8 9 10 12 14 16 18 22 24 2620
11 13 15 17 2119 23 25
F
E
D
C
B
A
CENTER ARRAY
25 SPACES
A1 BAL L
0.63 ± 0.10
@ 1.00 = 25.00
FOR TH ERMAL
ENHANCEMENT
CORNER
1.50 TYP.
1.20 x 45° APPROX
A1 INDICATOR
(GOLD PLATED) 24.50 ± 0.10
SQUARE
27.00
SQUARE
TYP 3 PLACES
3.00 x 45° APPROX
TYP 4 CORNERS
USE OF EJECTOR
PINS IS OPTIONAL
TOP VIEW
Advance Information
June 2003
Hardware Design Guide
STSI-144 Scalable Time-Slot Interchanger
Agere Systems Inc. r eserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. Agere,
Agere Systems, and the Agere logo are trademarks of Agere Systems Inc.
Copyright © 2003 Agere Syste ms Inc.
All Rights R eserved
June 2003
DS03-126SWCH (Replaces DS02-096S W CH)
For additional information, contact your Agere Systems Account Manager or the following:
INTERNET: http://www.agere.com
E-MAIL: docmaster@agere.com
N. AMERICA: Agere Systems Inc., Lehigh Valley Central Campus, Room 10A-301C, 1110 American Parkway NE, Allentown, PA 18109-9138
1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610 - 712-4106)
ASIA: Agere Systems Hong Kong Ltd., Suites 3201 & 3210-12, 32/F, Tower 2, The Gateway, Harbour City, Kowloon
Tel. (852) 3129-2000, FAX (852) 3129-2020
CHINA: (86) 21-5047-1212 (Shanghai), (86) 755-25881122 (Shenzhen)
JAPAN: (81) 3-5421-1600 (Tokyo ), KORE A: (82) 2-767-1850 (Seoul), SINGAPORE: (65) 6778-8833, TAIWA N: (886) 2-2725-5858 (Taipei)
EUROPE: Tel. (44 ) 134 4 296 400
Ordering Information
Device Part Number Ball Count Package Comcode
STSI-144 TTSI144641BL-1 388 PBGAM1T 109101899