Advance Information June 2003 STSI-144 Scalable Time-Slot Interchanger Hardware Design Guide Introduction Related Documents This document describes the hardware interfaces to Agere Systems Inc. scalable time-slot interchanger (STSI-144) device. Information relevant to the use of the device in a board design is covered. Ball descriptions, dc electrical characteristics, timing diagrams, ac timing parameters, packaging, and operating conditions are included. More information on the STSI-144 is contained in the following documents: STSI-144 Product Description STSI-144 Register Description STSI-144 Systems Design Guide Description Block Diagram and High-Level Interface Definition 16 TRANSMIT HSL TEST ACCESS PORT TEST PATTERN MONITOR TEST PATTERN GENERATOR TRANSLATION TABLE LOOKUP 16 RECEIVE HSL DATA STORE 64 RECEIVE CHI TRANSMIT CHI SWITCH FABRIC WRITE ADDRESS COUNTER CONNECTION STORE READ ADDRESS COUNTER MICROPROCESSOR INTERFACE CLOCK GENERATOR Figure 1. Block Diagram and High-Level Interface Definition 64 STSI-144 Scalable Time-Slot Interchanger Hardware Design Guide Advance Information June 2003 Table of Contents Contents Page Introduction ....................................................................1 Related Documents .....................................................1 Description .....................................................................1 Block Diagram and High-Level Interface Definition .....1 Ball Information ..............................................................3 Ball Diagram ................................................................3 Package Ball Assignments ..........................................4 Ball Types..................................................................10 Ball Definitions...........................................................10 Absolute Maximum Ratings .........................................14 Handling Precautions ...................................................14 ESD Tolerance ..........................................................14 Package Thermal Characteristics..............................14 Recommended Operating Conditions ..........................14 dc Electrical Characteristics .........................................15 Timing Diagrams and ac Characteristics .....................17 Outline Diagrams .........................................................29 Ordering Information ....................................................30 Figure Page Figure 1. Block Diagram and High-Level Interface Definition........................................................ 1 Figure 2. Package Diagram (Top View) ........................ 3 Figure 3. CHICLK Timing Specifications ..................... 17 Figure 4. MPUCLK Timing Specifications ................... 17 Figure 5. ac Timing Measurement Specification ......... 18 Figure 6. CHI Interface Timing .................................... 19 Figure 7. Typical Receive CHI Timing with 16.384 Mbits/s Data and 16.384 MHz CHICLK ................................... 20 Figure 8. Transmit CHI Timing with 16.384 Mbits/s Data and 16.384 MHz CHICLK ................................... 20 Figure 9. Typical Receive CHI Timing with 8.192 Mbits/s Data and 16.384 MHz CHICLK ................................... 21 Figure 10. Transmit CHI Timing with 8.192 Mbits/s Data and 16.384 MHz CHICLK ................................. 21 Figure 11. Typical Receive CHI Timing with 4.096 Mbits/s Data and 16.384 MHz CHICLK ................................. 22 Figure 12. Transmit CHI Timing with 4.096 Mbits/s Data and 16.384 MHz CHICLK ................................. 22 Figure 13. Typical Receive CHI Timing with 2.048 Mbits/s Data and 16.384 MHz CHICLK ................................. 23 Figure 14. Transmit CHI Timing with 2.048 Mbits/s Data and 16.384 MHz CHICLK ................................. 23 2 Contents Page Figure 15. Typical Receive CHI Timing with 8.192 Mbits/s Data and 8.192 MHz CHICLK................................... Figure 16. Transmit CHI Timing with 8.192 Mbits/s Data and 8.192 MHz CHICLK ................... Figure 17. CHI 3-State Output Control ....................... Figure 18. Microprocessor Port Timing-- Read Cycle................................................ Figure 19. Microprocessor Port Timing-- Write Cycle................................................ Figure 20. LVDS Output Timing Specifications .......... Table 24 24 25 26 27 28 Page Table 1. Package Ball Assignments in Signal Name Order......................................... 4 Table 2. Package Ball Assignments in Ball Number Order ......................................... 6 Table 3. Package Ball Assignments in Ball Number Order (Top View) ....................... 8 Table 4. Package Ball Assignments In Ball Number Order (Bottom View).................. 9 Table 5. Ball Types ..................................................... 10 Table 6. Timing Port ................................................... 10 Table 7. Transmit and Receive Concentration Highways...................................................... 11 Table 8. Control Port................................................... 11 Table 9. High-Speed Serial Link Signals .................... 12 Table 10. Initialization and Test Access ..................... 12 Table 11. Power Balls................................................. 13 Table 12. Absolute Maximum Ratings ........................ 14 Table 13. ESD Tolerance ........................................... 14 Table 14. Power Consumption ................................... 14 Table 15. Operating Conditions .................................. 14 Table 16. CMOS Inputs .............................................. 15 Table 17. CMOS Outputs ........................................... 15 Table 18. CMOS Bidirectionals (Excluding TXD[63:00]) .............................. 15 Table 19. CMOS Bidirectionals (TXD[63:00]) ............. 15 Table 20. LVDS Receiver dc Parameters................... 16 Table 21. LVDS Transmitter dc Parameters............... 16 Table 22. CHICLK Timing Specifications.................... 17 Table 23. MPUCLK Timing Specifications.................. 17 Table 24. ac Timing Measurement Specification........ 18 Table 25. CHI Interface Timing................................... 19 Table 26. CHI 3-State Output Control......................... 25 Table 27. Microprocessor Port Timing-- Read Cycle................................................. 26 Table 28. Microprocessor Port Timing-- Write Cycle ................................................. 27 Table 29. LVDS ac Characteristics............................. 28 Agere Systems Inc. STSI-144 Scalable Time-Slot Interchanger Hardware Design Guide Advance Information June 2003 Ball Information Ball Diagram The STSI-144 is housed in a 388-ball plastic ball grid array. Figure 2 shows the ball arrangement viewed from the top of the package. The balls are spaced on a 1.0 mm pitch. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF Figure 2. Package Diagram (Top View) Agere Systems Inc. 3 STSI-144 Scalable Time-Slot Interchanger Hardware Design Guide Advance Information June 2003 Ball Information (continued) Package Ball Assignments Table 1. Package Ball Assignments in Signal Name Order 4 Symbol Ball Symbol Ball Symbol Ball Symbol Ball Symbol Ball ADDR00 L24 DATA09 Y25 HSLINP12 A12 MPUCLK U23 RXD18 AF16 ADDR01 M26 DATA10 Y24 HSLINP13 C12 PAR0 AC26 RXD19 AE16 ADDR02 M25 DATA11 AA26 HSLINP14 B13 PAR1 AB24 RXD20 AF17 ADDR03 M24 DATA12 AA25 HSLINP15 C13 R/W L26 RXD21 AF18 ADDR04 N26 DATA13 AA24 HSLOUTN00 A14 REF10 D18 RXD22 AE18 ADDR05 N25 DATA14 AB26 HSLOUTN01 D14 REF14 C18 RXD23 AF19 ADDR06 N24 DATA15 AB25 HSLOUTN02 A15 REFCLK AD26 RXD24 AF20 ADDR07 P26 DT J24 HSLOUTN03 C15 REFSYNC AF25 RXD25 AE20 ADDR08 P25 FSYNC AC20 HSLOUTN04 A16 RESET K25 RXD26 AF21 ADDR09 P24 HIZ AC25 HSLOUTN05 C16 RESHI C19 RXD27 AF22 ADDR10 R26 HSLINN00 B3 HSLOUTN06 A17 RESLO D19 RXD28 AE22 ADDR11 R25 HSLINN01 C4 HSLOUTN07 A18 RSV1 G25 RXD29 AF23 ADDR12 R24 HSLINN02 B4 HSLOUTN08 A19 RSV2 G26 RXD30 AF24 ADDR13 T26 HSLINN03 B5 HSLOUTN09 A20 RSV3 F24 RXD31 AE24 ADDR14 T25 HSLINN04 B6 HSLOUTN10 C21 RSV4 F25 RXD32 AD4 ADDR15 T24 HSLINN05 C6 HSLOUTN11 B21 RSV5 F26 RXD33 AE4 AS L25 HSLINN06 A7 HSLOUTN12 B22 RSV6 E26 RXD34 AD5 CHICLK AC24 HSLINN07 A8 HSLOUTN13 C22 RSV7 D26 RXD35 AD6 CK155MHZN D11 HSLINN08 D8 HSLOUTN14 B23 RSV8 D25 RXD36 AE6 CK155MHZP C11 HSLINN09 B9 HSLOUTN15 B24 RSV9 D24 RXD37 AD7 CK78MHZ AC18 HSLINN10 A9 HSLOUTP00 B14 RXD00 AE3 RXD38 AD8 CKSPD0 E24 HSLINN11 C10 HSLOUTP01 C14 RXD01 AF3 RXD39 AE8 CKSPD1 E25 HSLINN12 A11 HSLOUTP02 B15 RXD02 AF4 RXD40 AD9 CS K24 HSLINN13 B12 HSLOUTP03 D15 RXD03 AE5 RXD41 AD10 CTAPIN0 D5 HSLINN14 A13 HSLOUTP04 B16 RXD04 AF5 RXD42 AE10 CTAPIN1 D7 HSLINN15 D13 HSLOUTP05 D16 RXD05 AF6 RXD43 AD11 CTAPIN2 D10 HSLINP00 A3 HSLOUTP06 B17 RXD06 AE7 RXD44 AD12 CTAPIN3 D12 HSLINP01 C5 HSLOUTP07 B18 RXD07 AF7 RXD45 AE12 CTAPIN4 B11 HSLINP02 A4 HSLOUTP08 B19 RXD08 AF8 RXD46 AD13 DATA00 U26 HSLINP03 A5 HSLOUTP09 B20 RXD09 AE9 RXD47 AE13 DATA01 U25 HSLINP04 A6 HSLOUTP10 D21 RXD10 AF9 RXD48 AE14 DATA02 V26 HSLINP05 C7 HSLOUTP11 A21 RXD11 AF10 RXD49 AD14 DATA03 V25 HSLINP06 B7 HSLOUTP12 A22 RXD12 AE11 RXD50 AE15 DATA04 V24 HSLINP07 B8 HSLOUTP13 C23 RXD13 AF11 RXD51 AD15 DATA05 W26 HSLINP08 C8 HSLOUTP14 A23 RXD14 AF12 RXD52 AD16 DATA06 W25 HSLINP09 C9 HSLOUTP15 A24 RXD15 AF13 RXD53 AE17 DATA07 W24 HSLINP10 A10 HSLRFSEL AE26 RXD16 AF14 RXD54 AD17 DATA08 Y26 HSLINP11 B10 INT K26 RXD17 AF15 RXD55 AD18 Agere Systems Inc. STSI-144 Scalable Time-Slot Interchanger Hardware Design Guide Advance Information June 2003 Ball Information (continued) Package Ball Assignments (continued) Table 1. Package Ball Assignments in Signal Name Order (continued) Symbol RXD56 RXD57 RXD58 RXD59 RXD60 RXD61 RXD62 RXD63 TCK TDI TDO TMS TRSTN TXD00 TXD01 TXD02 TXD03 TXD04 TXD05 TXD06 TXD07 TXD08 TXD09 TXD10 TXD11 TXD12 TXD13 TXD14 TXD15 TXD16 TXD17 TXD18 TXD19 TXD20 TXD21 TXD22 TXD23 TXD24 TXD25 TXD26 Ball Symbol Ball Symbol Ball Symbol Ball Symbol Ball AE19 AD19 AD20 AE21 AD21 AD22 AE23 AD23 H25 H24 H26 J26 J25 C2 C1 D1 E2 E1 F1 G2 G1 H1 J2 J1 K1 L2 L1 M1 N1 P1 R1 T1 T2 U1 V1 V2 W1 Y1 Y2 AA1 TXD27 TXD28 TXD29 TXD30 TXD31 TXD32 TXD33 TXD34 TXD35 TXD36 TXD37 TXD38 TXD39 TXD40 TXD41 TXD42 TXD43 TXD44 TXD45 TXD46 TXD47 TXD48 TXD49 TXD50 TXD51 TXD52 TXD53 TXD54 TXD55 TXD56 TXD57 TXD58 TXD59 TXD60 TXD61 TXD62 TXD63 VDD15 VDD15 VDD15 VDD15 AB1 AB2 AC1 AD1 AD2 D3 D2 E3 F3 F2 G3 H3 H2 J3 K3 K2 L3 M3 M2 N3 N2 P2 P3 R2 R3 T3 U2 U3 V3 W2 W3 Y3 AA2 AA3 AB3 AC2 AC3 L13 L14 M13 M14 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDDCDR0 VDDCDR1 N11 N12 N15 N16 P11 P12 P15 P16 R13 R14 T13 T14 A25 AB4 AB23 AC5 AC7 AC9 AC12 AC14 AC17 C25 C26 D6 D9 D22 E4 E23 G4 H23 J4 K23 M4 N23 R23 U4 V23 W4 Y23 C17 D20 VDDPLL VIO VPRE VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS AC22 P4 AF2 A1 A2 A26 AA4 AA23 AC4 AC6 AC8 AC10 AC11 AC13 AC15 AC16 AC19 AC23 AD3 AD24 AD25 AE1 AE2 AE25 AF1 AF26 B1 B2 B25 B26 C3 C24 D4 D23 F4 F23 G23 G24 H4 J23 K4 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS L11 L12 L15 L16 L23 M11 M12 M15 M16 M23 N4 N13 N14 P13 P14 P23 R4 R11 R12 R15 R16 T4 T11 T12 T15 T16 T23 U24 V4 W23 Y4 D17 C20 AC21 Agere Systems Inc. VSSCDR0 VSSCDR1 VSSPLL 5 STSI-144 Scalable Time-Slot Interchanger Hardware Design Guide Advance Information June 2003 Ball Information (continued) Package Ball Assignments (continued) Table 2. Package Ball Assignments in Ball Number Order 6 Ball Symbol Ball Symbol Ball Symbol Ball Symbol Ball Symbol A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 VSS VSS HSLINP00 HSLINP02 HSLINP03 HSLINP04 HSLINN06 HSLINN07 HSLINN10 HSLINP10 HSLINN12 HSLINP12 HSLINN14 HSLOUTN00 HSLOUTN02 HSLOUTN04 HSLOUTN06 HSLOUTN07 HSLOUTN08 HSLOUTN09 HSLOUTP11 HSLOUTP12 HSLOUTP14 HSLOUTP15 VDD33 VSS VSS VSS HSLINN00 HSLINN02 HSLINN03 HSLINN04 HSLINP06 HSLINP07 HSLINN09 HSLINP11 CTAPIN4 HSLINN13 HSLINP14 HSLOUTP00 HSLOUTP02 HSLOUTP04 HSLOUTP06 HSLOUTP07 B19 B20 B21 B22 B23 B24 B25 B26 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 HSLOUTP08 HSLOUTP09 HSLOUTN11 HSLOUTN12 HSLOUTN14 HSLOUTN15 VSS VSS TXD01 TXD00 VSS HSLINN01 HSLINP01 HSLINN05 HSLINP05 HSLINP08 HSLINP09 HSLINN11 CK155MHZP HSLINP13 HSLINP15 HSLOUTP01 HSLOUTN03 HSLOUTN05 VDDCDR0 REF14 RESHI VSSCDR1 HSLOUTN10 HSLOUTN13 HSLOUTP13 VSS VDD33 VDD33 TXD02 TXD33 TXD32 VSS CTAPIN0 VDD33 CTAPIN1 HSLINN08 VDD33 CTAPIN2 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 E1 E2 E3 E4 E23 E24 E25 E26 F1 F2 F3 F4 F23 F24 F25 F26 G1 G2 G3 G4 G23 G24 G25 G26 H1 H2 H3 H4 CK155MHZN CTAPIN3 HSLINN15 HSLOUTN01 HSLOUTP03 HSLOUTP05 VSSCDR0 REF10 RESLO VDDCDR1 HSLOUTP10 VDD33 VSS RSV9 RSV8 RSV7 TXD04 TXD03 TXD34 VDD33 VDD33 CKSPD0 CKSPD1 RSV6 TXD05 TXD36 TXD35 VSS VSS RSV3 RSV4 RSV5 TXD07 TXD06 TXD37 VDD33 VSS VSS RSV1 RSV2 TXD08 TXD39 TXD38 VSS H23 H24 H25 H26 J1 J2 J3 J4 J23 J24 J25 J26 K1 K2 K3 K4 K23 K24 K25 K26 L1 L2 L3 L4 L11 L12 L13 L14 L15 L16 L23 L24 L25 L26 M1 M2 M3 M4 M11 M12 M13 M14 M15 M16 VDD33 TDI TCK TDO TXD10 TXD09 TXD40 VDD33 VSS M23 M24 M25 M26 N1 N2 N3 N4 N11 N12 N13 N14 N15 N16 N23 N24 N25 N26 P1 P2 P3 P4 P11 P12 P13 P14 P15 P16 P23 P24 P25 P26 R1 R2 R3 R4 R11 R12 R13 R14 R15 R16 R23 R24 VSS ADDR03 ADDR02 ADDR01 TXD15 TXD47 TXD46 VSS VDD15 VDD15 VSS VSS VDD15 VDD15 VDD33 ADDR06 ADDR05 ADDR04 TXD16 TXD48 TXD49 VIO VDD15 VDD15 VSS VSS VDD15 VDD15 VSS ADDR09 ADDR08 ADDR07 TXD17 TXD50 TXD51 VSS VSS VSS VDD15 VDD15 VSS VSS VDD33 ADDR12 DT TRSTN TMS TXD11 TXD42 TXD41 VSS VDD33 CS RESET INT TXD13 TXD12 TXD43 VSS VSS VSS VDD15 VDD15 VSS VSS VSS ADDR00 AS R/W TXD14 TXD45 TXD44 VDD33 VSS VSS VDD15 VDD15 VSS VSS Agere Systems Inc. STSI-144 Scalable Time-Slot Interchanger Hardware Design Guide Advance Information June 2003 Ball Information (continued) Package Ball Assignments (continued) Table 2. Package Ball Assignments in Ball Number Order (continued) Ball Symbol Ball Symbol Ball Symbol Ball Symbol R25 R26 T1 T2 T3 T4 T11 T12 T13 T14 T15 T16 T23 T24 T25 T26 U1 U2 U3 U4 U23 U24 U25 U26 V1 V2 V3 V4 V23 V24 V25 V26 W1 W2 W3 W4 W23 W24 W25 W26 Y1 Y2 Y3 Y4 ADDR11 ADDR10 TXD18 TXD19 TXD52 VSS VSS VSS VDD15 VDD15 VSS VSS VSS ADDR15 ADDR14 ADDR13 TXD20 TXD53 TXD54 VDD33 MPUCLK VSS DATA01 DATA00 TXD21 TXD22 TXD55 VSS VDD33 DATA04 DATA03 DATA02 TXD23 TXD56 TXD57 VDD33 VSS DATA07 DATA06 DATA05 TXD24 TXD25 TXD58 VSS Y23 Y24 Y25 Y26 AA1 AA2 AA3 AA4 AA23 AA24 AA25 AA26 AB1 AB2 AB3 AB4 AB23 AB24 AB25 AB26 AC1 AC2 AC3 AC4 AC5 AC6 AC7 AC8 AC9 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24 VDD33 DATA10 DATA09 DATA08 TXD26 TXD59 TXD60 VSS VSS DATA13 DATA12 DATA11 TXD27 TXD28 TXD61 VDD33 VDD33 PAR1 DATA15 DATA14 TXD29 TXD62 TXD63 VSS VDD33 VSS VDD33 VSS VDD33 VSS VSS VDD33 VSS VDD33 VSS VSS VDD33 CK78MHZ VSS FSYNC VSSPLL VDDPLL VSS CHICLK AC25 AC26 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AE1 AE2 AE3 AE4 AE5 AE6 AE7 AE8 AE9 AE10 AE11 AE12 AE13 AE14 AE15 AE16 HIZ PAR0 TXD30 TXD31 VSS RXD32 RXD34 RXD35 RXD37 RXD38 RXD40 RXD41 RXD43 RXD44 RXD46 RXD49 RXD51 RXD52 RXD54 RXD55 RXD57 RXD58 RXD60 RXD61 RXD63 VSS VSS REFCLK VSS VSS RXD00 RXD33 RXD03 RXD36 RXD06 RXD39 RXD09 RXD42 RXD12 RXD45 RXD47 RXD48 RXD50 RXD19 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25 AE26 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 AF25 AF26 RXD53 RXD22 RXD56 RXD25 RXD59 RXD28 RXD62 RXD31 VSS HSLRFSEL VSS VPRE RXD01 RXD02 RXD04 RXD05 RXD07 RXD08 RXD10 RXD11 RXD13 RXD14 RXD15 RXD16 RXD17 RXD18 RXD20 RXD21 RXD23 RXD24 RXD26 RXD27 RXD29 RXD30 REFSYNC VSS Agere Systems Inc. 7 Advance Information June 2003 STSI-144 Scalable Time-Slot Interchanger Hardware Design Guide Ball Information (continued) Package Ball Assignments (continued) Table 3. Package Ball Assignments in Ball Number Order (Top View) A 1 2 3 4 5 6 7 8 9 10 11 12 VSS VSS HSLINP 00 HSLINP 02 HSLINP 03 HSLINP 04 HSLINN 06 HSLINN 07 HSLINN 10 HSLINP 10 HSLINN 12 HSLINP 12 HSLINN HSLOUTN HSLOUTN HSLOUTN HSLOUTN HSLOUTN HSLOUTN HSLOUTN HSLOUTP HSLOUTP HSLOUTP HSLOUTP 14 00 02 04 06 07 08 09 11 12 14 15 13 14 15 16 17 18 19 20 21 22 23 24 VSS VSS 25 26 VDD33A VSS HSLINN 00 HSLINN 02 HSLINN 03 HSLINN 04 HSLINP 06 HSLINP 07 HSLINN 09 HSLINP CTAPIN4 HSLINN 11 13 HSLINP HSLOUTP HSLOUTP HSLOUTP HSLOUTP HSLOUTP HSLOUTP HSLOUTP HSLOUTN HSLOUTN HSLOUTN HSLOUTN 14 00 02 04 06 07 08 09 11 12 14 15 C TXD01 TXD00 VSS HSLINN 01 HSLINP 01 HSLINN 05 HSLINP 05 HSLINP 08 HSLINP 09 HSLINN 11 CK155 MHZP HSLINP 13 HSLINP HSLOUTP HSLOUTN HSLOUTN VDDCDR0 15 01 03 05 REF14 RESHI VSSCDR1 HSLOUTN HSLOUTN HSLOUTP 10 13 13 D TXD02 TXD33 TXD32 VSS CTAPIN0 VDD33 VDD33 CTAPIN2 CK155 MHZN CTAPIN3 HSLINN HSLOUTN HSLOUTP HSLOUTP VSSCDR0 15 01 03 05 REF10 RESLO VDDCDR1 HSLOUTP 10 VDD33 VSS RSV9 RSV8 RSV7 E TXD04 TXD03 TXD34 VDD33 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- VDD3 CKSPD0 CKSPD1 RSV6 F TXD05 TXD36 TXD35 VSS -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- VSS RSV3 RSV4 RSV5 G TXD07 TXD06 TXD37 VDD33 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- VSS VSS RSV1 RSV2 H TXD08 TXD39 TXD38 VSS -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- VDD33 TDI TCK TDO J TXD10 TXD09 TXD40 VDD33 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- VSS DT TRSTN TMS K TXD11 TXD42 TXD41 VSS -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- VDD33 CS RESET INT L TXD13 TXD12 TXD43 VSS -- -- -- -- -- -- VSS VSS VDD15 VDD15 VSS VSS -- -- -- -- -- -- VSS ADDR00 AS R/W M TXD14 TXD45 TXD44 VDD33 -- -- -- -- -- -- VSS VSS VDD15 VDD15 VSS VSS -- -- -- -- -- -- VSS ADDR03 ADDR02 ADDR01 N TXD15 TXD47 TXD46 VSS -- -- -- -- -- -- VDD15 VDD15 VSS VSS VDD15 VDD15 -- -- -- -- -- -- VDD33 ADDR06 ADDR05 ADDR04 P TXD16 TXD48 TXD49 VIO -- -- -- -- -- -- VDD15 VDD15 VSS VSS VDD15 VDD15 -- -- -- -- -- -- VSS ADDR09 ADDR08 ADDR07 R TXD17 TXD50 TXD51 VSS -- -- -- -- -- -- VSS VSS VDD15 VDD15 VSS VSS -- -- -- -- -- -- VDD33 ADDR12 ADDR11 ADDR10 B CTAPIN1 HSLINN 08 VSS VSS VSS VDD33 VDD33 T TXD18 TXD19 TXD52 VSS -- -- -- -- -- -- VSS VSS VDD15 VDD15 VSS VSS -- -- -- -- -- -- VSS ADDR15 ADDR14 ADDR13 U TXD20 TXD53 TXD54 VDD33 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- MPUCLK VSS DATA01 DATA00 V TXD21 TXD22 TXD55 VSS -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- VDD33 DATA04 DATA03 DATA02 W TXD23 TXD56 TXD57 VDD33 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- VSS DATA07 DATA06 DATA05 TXD24 TXD25 TXD58 VSS -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- VDD33 DATA10 DATA09 DATA08 AA TXD26 TXD59 TXD60 VSS -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- VSS DATA13 DATA12 DATA11 AB TXD27 TXD28 TXD61 VDD33 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- VDD33 PAR1 DATA15 DATA14 AC TXD29 TXD62 TXD63 VSS VDD33 VSS VDD33 VSS VDD33 VSS VSS VDD33 VSS VDD33 VSS VSS VDD33 CK78MHZ VSS FSYNC VSSPLL VDDPLL VSS CHICLK HIZ PAR0 AD TXD30 TXD31 VSS RXD32 RXD34 RXD35 RXD37 RXD38 RXD40 RXD41 RXD43 RXD44 RXD46 RXD49 RXD51 RXD52 RXD54 RXD55 RXD57 RXD58 RXD60 RXD61 RXD63 VSS VSS REFCLK Y AE VSS VSS RXD00 RXD33 RXD03 RXD36 RXD06 RXD39 RXD09 RXD42 RXD12 RXD45 RXD47 RXD48 RXD50 RXD19 RXD53 RXD22 RXD56 RXD25 RXD59 RXD28 RXD62 RXD31 VSS HSLRFSEL AF VSS VPRE RXD01 RXD02 RXD04 RXD05 RXD07 RXD08 RXD10 RXD11 RXD13 RXD14 RXD15 RXD16 RXD17 RXD18 RXD20 RXD21 RXD23 RXD24 RXD26 RXD27 RXD29 RXD30 REFSYNC VSS 8 Agere Systems Inc. Advance Information June 2003 STSI-144 Scalable Time-Slot Interchanger Hardware Design Guide Ball Information (continued) Package Ball Assignments (continued) Table 4. Package Ball Assignments in Ball Number Order (Bottom View) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 AF VSS VPRE RXD01 RXD02 RXD04 RXD05 RXD07 RXD08 RXD10 RXD11 RXD13 RXD14 RXD15 RXD16 RXD17 RXD18 RXD20 RXD21 RXD23 RXD24 RXD26 RXD27 RXD29 RXD30 REFSYNC VSS AE VSS VSS RXD00 RXD33 RXD03 RXD36 RXD06 RXD39 RXD09 RXD42 RXD12 RXD45 RXD47 RXD48 RXD50 RXD19 RXD53 RXD22 RXD56 RXD25 RXD59 RXD28 RXD62 RXD31 VSS HSLRFSEL AD TXD30 TXD31 VSS RXD32 RXD34 RXD35 RXD37 RXD38 RXD40 RXD41 RXD43 RXD44 RXD46 RXD49 RXD51 RXD52 RXD54 RXD55 RXD57 RXD58 RXD60 RXD61 RXD63 VSS VSS REFCLK AC TXD29 TXD62 TXD63 VSS VDD33 VSS VDD33 VSS VDD33 VSS VSS VDD33 VSS VDD33 VSS VSS VDD33 CK78MHZ VSS FSYNC VSSPLL VDDPLL VSS CHICLK HIZ PAR0 AB TXD27 TXD28 TXD61 VDD33 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- VDD33 PAR1 DATA15 DATA14 AA TXD26 TXD59 TXD60 VSS -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- VSS DATA13 DATA12 DATA11 TXD24 TXD25 TXD58 VSS -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- VDD33 DATA10 DATA09 DATA08 W TXD23 TXD56 TXD57 VDD33 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- VSS DATA07 DATA06 DATA05 V TXD21 TXD22 TXD55 VSS -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- VDD33 DATA04 DATA03 DATA02 U TXD20 TXD53 TXD54 VDD33 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- MPUCLK VSS DATA01 DATA00 T TXD18 TXD19 TXD52 VSS -- -- -- -- -- -- VSS VSS VDD15 VDD15 VSS VSS -- -- -- -- -- -- VSS ADDR15 ADDR14 ADDR13 R TXD17 TXD50 TXD51 VSS -- -- -- -- -- -- VSS VSS VDD15 VDD15 VSS VSS -- -- -- -- -- -- VDD33 ADDR12 ADDR11 ADDR10 P TXD16 TXD48 TXD49 VIO -- -- -- -- -- -- VDD15 VDD15 VSS VSS VDD15 VDD15 -- -- -- -- -- -- VSS ADDR09 ADDR08 ADDR07 N TXD15 TXD47 TXD46 VSS -- -- -- -- -- -- VDD15 VDD15 VSS VSS VDD15 VDD15 -- -- -- -- -- -- VDD33 ADDR06 ADDR05 ADDR04 M TXD14 TXD45 TXD44 VDD33 -- -- -- -- -- -- VSS VSS VDD15 VDD15 VSS VSS -- -- -- -- -- -- VSS ADDR03 ADDR02 ADDR01 L TXD13 TXD12 TXD43 VSS -- -- -- -- -- -- VSS VSS VDD15 VDD15 VSS VSS -- -- -- -- -- -- VSS ADDR00 AS R/W K TXD11 TXD42 TXD41 VSS -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- VDD33 CS RESET INT J TXD10 TXD09 TXD40 VDD33 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- VSS DT TRSTN TMS H Y TXD08 TXD39 TXD38 VSS -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- VDD33 TDI TCK TDO G TXD07 TXD06 TXD37 VDD33 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- VSS VSS RSV1 RSV2 F TXD05 TXD36 TXD35 VSS -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- VSS RSV3 RSV4 RSV5 E TXD04 TXD03 TXD34 VDD33 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- VDD3 CKSPD0 CKSPD1 RSV6 D TXD02 TXD33 TXD32 VSS CTAPIN0 VDD33 VDD33 CTAPIN2 CK155 MHZN CTAPIN3 HSLINN HSLOUTN HSLOUTP HSLOUTP VSSCDR0 15 01 03 05 REF10 RESLO VDDCDR1 HSLOUTP 10 VDD33 VSS RSV9 RSV8 RSV7 C TXD01 TXD00 VSS HSLINN 01 HSLINP 01 HSLINN 05 HSLINP 09 HSLINN 11 CK155 MHZP HSLINP 13 REF14 RESHI VSSCDR1 HSLOUTN HSLOUTN HSLOUTP 10 13 13 VSS VDD33 VDD33 CTAPIN1 HSLINN 08 HSLINP 05 HSLINP 08 HSLINP HSLOUTP HSLOUTN HSLOUTN VDDCDR0 15 01 03 05 B VSS VSS HSLINN 00 HSLINN 02 HSLINN 03 HSLINN 04 HSLINP 06 HSLINP 07 HSLINN 09 HSLINP CTAPIN4 HSLINN 11 13 HSLINP HSLOUTP HSLOUTP HSLOUTP HSLOUTP HSLOUTP HSLOUTP HSLOUTP HSLOUTN HSLOUTN HSLOUTN HSLOUTN 14 00 02 04 06 07 08 09 11 12 14 15 VSS VSS A VSS VSS HSLINP 00 HSLINP 02 HSLINP 03 HSLINP 04 HSLINN 06 HSLINN 07 HSLINN 10 HSLINP 10 HSLINN HSLOUTN HSLOUTN HSLOUTN HSLOUTN HSLOUTN HSLOUTN HSLOUTN HSLOUTP HSLOUTP HSLOUTP HSLOUTP 14 00 02 04 06 07 08 09 11 12 14 15 VDD33A VSS Agere Systems Inc. HSLINN 12 HSLINP 12 9 STSI-144 Scalable Time-Slot Interchanger Hardware Design Guide Advance Information June 2003 Ball Information (continued) Ball Types This table describes each type of input, output, and I/O ball used on the STSI-144. Table 5. Ball Types Type Label Description I CMOS input, TTL switching thresholds. I pd CMOS input, TTL switching thresholds with internal pull-down resistor. I pu CMOS input, TTL switching thresholds with internal pull-up resistor. O CMOS output. O od Open drain output. LIN LVDS inputs. LOUT LVDS outputs. I/O Bidirectional ball; CMOS input with TTL switching thresholds and CMOS output. None Analog inputs for external resistors, capacitors, voltage references, etc. P Power and ground. The dc switching and other electrical characteristics are specified later in this document. Ball Definitions This section describes the function of each of the device balls. The balls are listed by ball name. Package ball numbers are listed in Table 1 of this document. The static parameters (drive currents, switching thresholds, etc.) for each ball type (input, output, etc.) are described in Table 16 through Table 21. Table 6. Timing Port Ball Name Type FSYNC CHICLK CKSPD0 CKSPD1 10 Name/Description I Frame Synchronization. This signal indicates the beginning of a 125 s frame event (8 kHz). The FSYNC ball can be programmed as active-low or active-high, but its polarity is the same for all concentration highway interfaces (CHI). FSYNC can be sampled on either the positive or negative edge of CHICLK. Time-slot numbers and bit offsets for each CHI are assigned relative to the detection of FSYNC. I Clock. This is the master synchronous clock for the transmit and receive concentration highways. The frequency can be 8.192 MHz or 16.384 MHz. It must be at least as fast as the highest CHI data rate. I Clock Speed. Static control input that should be tied according to the frequency of CHICLK. If CHICLK is connected to an 8.192 MHz source, CKSPD0 should be tied to VSS. If CHICLK is connected to a 16.384 MHz source, CKSPD0 should be tied to VDD33. I pd Clock Speed. Reserved, leave disconnected. 20 k pull-down resistor. Agere Systems Inc. STSI-144 Scalable Time-Slot Interchanger Hardware Design Guide Advance Information June 2003 Ball Information (continued) Ball Definitions (continued) Table 7. Transmit and Receive Concentration Highways Ball Name Type Name/Description RXD[63:00] I pd Receive Data [63:0]. Receive concentration highways. These are serial, synchronous data streams which may be individually programmed to operate at 2.048 Mbits/s, 4.096 Mbits/s, 8.192 Mbits/s, or 16.384 Mbits/s. They carry 32, 64, 128, or 256 time slots (respectively) each occupying eight contiguous bits. 20 k pull-down resistor. TXD[63:32] I/O Transmit Data [63:32]. Normally these are output concentration highway data streams with data rate options identical to the RXD inputs. These balls can be configured to operate as bidirectional multiplex ports. Further information can be found in the system design guide. 20 k pull-down resistor. TXD[31:00] I/O Transmit Data [31:00]. Normally these are output concentration highway data streams with data rate options identical to the RXD inputs. These balls can be configured to operate as bidirectional multiplex ports such as H.110. Further information can be found in the system design guide. 20 k resistor connected to VPRE. Table 8. Control Port Ball Name Type Name/Description MPUCLK I Processor Clock. This clock is used to sample address, data, and control signals from the microprocessor. This clock must be within the range of 0 MHz--66 MHz. Required for operation. CS I Chip Select. Active-low chip select. This input is held low for the duration of any read or write access to the STSI-144. Required for operation. AS I Address Strobe. Active-low address strobe that is one MPUCLK cycle wide at the start of a microprocessor access cycle to the STSI-144. This is used to initiate a microprocessor access. Required for operation. R/W I ADDR [15:00] DATA [15:00] PAR[1:0] DT INT Read/Write. Cycle selection. R/W is set high during a read cycle, or set low for a write cycle. Required for operation. I pu Address [15:00]. ADDR[15] is the most significant bit and ADDR[00] is the least significant bit for addressing all the internal registers during microprocessor access cycles. All addresses are 16-bit word addresses; hence, in a typical application ADDR[00] of the STSI-144 device would be connected to address bit 1 of a byte addressable system address bus. Required for operation. 200 k pull-up resistor. Note: The STSI-144 is little-endian; the least significant byte is stored in the lowest address and the most significant byte is stored in the highest address. Care must be exercised in connection to microprocessors that use big-endian byte ordering. I/O Data [15:00]. Data bus for all transfers between the microprocessor and the internal registers. The balls are inputs during write cycles and outputs during read cycles. DATA15 is the most significant bit, and DATA00 is the least significant bit. Required for operation. I/O Control Port Parity [1:0]. Byte-wide parity bits for data. PAR[1] is the parity for DATA [15:8], and PAR[0] is the parity for DATA [7:0]. The parity sense (even or odd) is application programmable via a register bit in the STSI-144. Not required for operation. O Data Transfer Acknowledge. Active-low for one MPUCLK cycle. Indicates that data has been written during write cycles or that data is valid during read cycles. High impedance when CS is a 1 and driven when CS is 0. Required for operation. O od Interrupt. This output is asserted low to indicate that an interrupt condition has occurred. This signal remains active-low until the interrupt status register has been cleared or masked. Agere Systems Inc. 11 STSI-144 Scalable Time-Slot Interchanger Hardware Design Guide Advance Information June 2003 Ball Information (continued) Ball Definitions (continued) Table 9. High-Speed Serial Link Signals Ball Name Type Name/Description HSLIN[P,N] [15:00] LIN High-speed Serial Link Input. 622.08 Mbits/s LVDS data input. Unused inputs may be left disconnected. HSLOUT[P,N] [15:00] LOUT High-speed Serial Link Output. 622.08 Mbits/s LVDS data output. CK155MHZ[P,N] LIN 155.52 MHz LVDS reference clock input.* CK78MHZ I pu 77.76 MHz CMOS reference clock input. 200 k pull-up resistor.* HSLRFSEL I pd High-speed Serial Link Reference Select. HSL clock reference select. 50 k pulldown resistor. 0 = 78 MHz. The CK78MHZ input is used as the reference. 1 = 155 MHz. The CK155MHZ[P,N] input is used as the reference. REFCLK O Reference Clock Output. 8 kHz, 16.384 MHz, or 38.88 MHz derived from an HSL input stream. (See Reference_Clock_Select in the Global_Control register in the STSI-144 Register Description.) REFSYNC O Reference Synchronization Output. Active-high 8 kHz sync pulse, one REFCLK period wide, derived from an HSL input stream. RESHI None External 100 Resistor Pin 1. A 100 1% resistor is required as a reference for LVDS buffers. RESLO None External 100 Resistor Pin 2. REF10 None External 1.0 V Reference. (Optional) Selected by Power_Control register bit 2. REF14 None External 1.4 V Reference. (Optional) Selected by Power_Control register bit 2. CTAP[4:0] None LVDS Termination Center Taps. (Optional) Bypass to ground with 0.01 F capacitor. * One of either CK78MHZ or CK155MHZ[P,N] is required, the other may be left unconnected. Table 10. Initialization and Test Access Ball Name Type RESET I pu Reset. Global reset, active-low. Initializes all internal registers to their default state. The reset occurs asynchronously, but RESET should be held low for at least 1 s. 20 k pull-up resistor. TCK I pu Test Clock. This signal provides timing for the boundary scan and test access port (TAP) controller. Should be static except during boundary-scan testing. 20 k pull-up resistor. TDI I pu Test Data In. Data input for the boundary scan. Sampled on the rising edge of TCK. 20 k pullup resistor. TMS I pu Test Mode Select (Active-Low). Controls boundary-scan test operations. TMS is sampled on the rising edge of TCK. 20 k pull-up resistor. TRSTN TDO HIZ RSV[9:1] 12 Name/Description I pd Test Reset (Active-Low). This signal is an asynchronous reset for the TAP controller. 20 k pull-down resistor. O Test Data Out. Updated on the falling edge of TCK. The TDO output is high impedance except when scanning out test data. I pu Output Enable. All output and bidrectional buffers will be high impedance when this input is low unless boundary scan is enabled (TRSTN = 1). 20 k pull-up resistor. -- Reserved [9:1]. These balls are used by Agere Systems during the manufacturing process. They must be left unconnected. Agere Systems Inc. Advance Information June 2003 STSI-144 Scalable Time-Slot Interchanger Hardware Design Guide Ball Information (continued) Ball Definitions (continued) Table 11. Power Balls Symbol Type VDD33 P I/O Power. Power supply balls for the I/O pads (3.3 V 5%). VDD15 P Core Power. Power supply balls for the core (1.5 V 5%). VSS P Ground. Common ground balls for 3.3 V and 1.5 V supplies. VPRE P Precharge. Precharge voltage to support H.110 hot insertion on TXD[31:00]. If the device is used in an H.110 hot insertion applications, the signal should be connected to backplane early voltage; otherwise connect this signal to ground. VIO P PCI Buffer Voltage Select. For an H.110 application using TXD[31:00] in a 5 V signaling environment, connect this signal to 5 V. For an H.110 application using TXD[31:00] in a 3 V signaling environment, connect this signal to VDD33. For all other applications, connect this signal to VDD33. VDDPLL P PLL Power. 1.5 V power supply for the internal phase-locked loop. Must include local 0.01 F capacitor to VSSPLL. VSSPLL P PLL Ground. Isolated ground for the internal phase-locked loop. VDDCDR[1,0] P Isolated Clock/Data Recovery 1.5 V 5% Power. These pins require a dedicated inductor/ capacitor (L/C) pi filter with local bypass capacitors. VSSCDR[1,0] P Isolated Clock/Data Recovery Ground. Agere Systems Inc. Name/Description 13 STSI-144 Scalable Time-Slot Interchanger Hardware Design Guide Advance Information June 2003 Absolute Maximum Ratings Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for extended periods can adversely affect device reliability. Table 12. Absolute Maximum Ratings Parameter Supply Voltage (VDD33) Supply Voltage (VDD15) Input Voltage: TXD[63:00] All Other Inputs Storage Temperature Junction Temperature Min Max Unit -0.5 -0.5 4.2 1.8 V V -0.5 -0.3 -40 -- 5.5 VDD33 + 0.3 125 125 V C C Handling Precautions Although electrostatic discharge (ESD) protection circuitry has been designed into this device, proper precautions must be taken to avoid exposure to ESD and electrical overstress (EOS) during all handling, assembly, and test operations. Agere employs both a human-body model (HBM) and a charged-device model (CDM) qualification requirement in order to determine ESD-susceptibility limits and protection design evaluation. ESD voltage thresholds are dependent on the circuit parameters used in each of the models, as defined by JEDEC's JESD22-A114 (HBM) and JESD22-C101 (CDM) standards. ESD Tolerance Table 13. ESD Tolerance Device Voltage Type STSI-144 2,000 V 500 V HBM (human-body model) CDM (charged-device model) Supply Voltage Typ* Max VDD33 VDD15 750 mW at 3.3 V 750 mW at 1.5 V 900 mW at 3.47 V 900 mW at 1.6 V Package Thermal Characteristics Table 14. Power Consumption JA = 20 C/W. * MPUCLK = 66 MHz, CHICLK = 16.384 MHz, TA = 25 C, all CHIs active, all outputs loaded with 50 pF. All HSLs active. Recommended Operating Conditions Table 15. Operating Conditions Parameter Supply Voltage (VDD33) Supply Voltage (VDD15) Ambient Temperature 14 Min Typ Max Unit 3.14 1.4 -40 3.3 1.5 -- 3.47 1.6 85 V V C Agere Systems Inc. STSI-144 Scalable Time-Slot Interchanger Hardware Design Guide Advance Information June 2003 dc Electrical Characteristics This section describes all the static parameters associated with all the ball types used in the STSI-144 device. Table 16. CMOS Inputs Parameter Input Leakage Current High-input Voltage Low-input Voltage Input Capacitance Symbol Conditions Min Typ Max Unit IIL VIH VIL CI VSS < VIN < VDD33 -- -- -- -- 2.0 -0.3 -- -- -- -- 2.5 1* VDD33 + 0.3 0.8 -- A V V pF * Excludes current due to pull-up or pull-down resistors. Table 17. CMOS Outputs Parameter Output Voltage Low Output Voltage High Output Current Low Output Current High Output Capacitance HIZ Output Leakage Current Symbol Conditions Min Typ Max Unit VOL VOH IOL IOH CO IOZ IOL = -10 mA IOL = 10 mA -- -- -- -- -- 2.4 -- -- -- -- -- -- -- -- 3 -- 0.4 -- 10 10 -- 10 V V mA mA pF A Table 18. CMOS Bidirectionals (Excluding TXD[63:00]) Parameter Symbol Conditions Min Typ Max Unit IL VIH VIL CIB VOL VOH VSS < VIN < VDD33 -- -- -- IOL = -10 mA IOL = 10 mA -- 2.0 -0.3 -- -- 2.4 -- -- -- 5.0 -- -- 11 VDD33 + 0.3 0.8 -- 0.4 -- A V V pF V V Leakage Current High-input Voltage Low-input Voltage Biput Capacitance Output Voltage Low Output Voltage High Table 19. CMOS Bidirectionals (TXD[63:00]) Parameter Symbol Conditions Min Max Unit Leakage Current High-input Voltage IL VIH VIL Biput Capacitance Output Voltage Low CIB VOL Output Voltage High VOH Positive-going Threshold Negative-going Threshold Hysteresis (Vt+ - Vt-) Vt+ Vt- VHYS -- 2.0 0.5 VDD33 -0.5 -0.5 -- -- -- 0.9 VDD33 2.4 1.2 0.6 0.4 10 5.5 VDD33 + 0.5 0.8 0.3 VDD33 10 0.1 VDD33 0.55 -- -- 2.0 1.6 -- A V Low-input Voltage VSS < VIN < VDD33 VIO = 5.0 V VIO = 3.3V VIO = 5.0 V VIO = 3.3V -- IOL = 1.5 mA, VIO = 3.3 V IOL = 6.0 mA, VIO = 5.0 V IOL = -0.5 mA, VIO = 3.3 V IOL = -2.0 mA, VIO = 5.0 V -- -- -- Agere Systems Inc. V pF V V V V V 15 STSI-144 Scalable Time-Slot Interchanger Hardware Design Guide Advance Information June 2003 dc Electrical Characteristics (continued) Table 20. LVDS Receiver dc Parameters Parameter Symbol Conditions Min Typ Max Unit VCM |VGPD| < 925 mV, dc - 1 MHz 0.0 1.2 2.4 V Input Differential Threshold VIDTH |VGPD| < 925 mV, 450 MHz -100 -- 100 mV Input Differential Hysteresis VHYST (+VIDTHH) - (-VIDTHL) 25 -- -- mV RIN Built-in center-tapped termination 80 100 120 Symbol Conditions Min Typ Max VOH RLOAD = 100 1% Output Voltage Low, P or N VOL RLOAD = 100 1% 0.925 -- -- Output Differential Voltage |VOD| RLOAD = 100 1% 0.25 -- 0.45* Output Offset Voltage VOS RLOAD = 100 1% 1.125 -- 1.275 Output Impedance, Differential RO VCM = 1.0 V and 1.4 V 80 100 120 Change in Differential Voltage |VOD| Between Complementary States RLOAD = 100 1% -- -- 25 mV Change in Output Offset Voltage |VOS| Between Complementary States RLOAD = 100 1% -- -- 25 mV Common-mode Input Range Receiver Differential Input Impedance Table 21. LVDS Transmitter dc Parameters Parameter Output Voltage High, P or N -- -- * * 1.475 Unit * V V * V Output Current ISA, ISB Driver shorted to GND -- -- 24 mA Output Current ISAB Driver shorted together -- -- 12 mA Power-off Output Leakage |IXA|, |IXB| HSL disabled, VPAD, VPADN = 0 V--2.5 V -- -- 10 mA * External references selected (LVDS_Voltage_Reference_Select = 1), REF10 = 1.0 V 3%, REF14 = 1.4 V 3%. 16 Agere Systems Inc. STSI-144 Scalable Time-Slot Interchanger Hardware Design Guide Advance Information June 2003 Timing Diagrams and ac Characteristics Figure 3 and Figure 4 describe the timing specifications for the input clocks on the STSI-144. t2 t1 t3 VDD33 VIH VIH 50% VIL VIL t4 Figure 3. CHICLK Timing Specifications Table 22. CHICLK Timing Specifications Parameter Description Min Typ Max Unit -- 2 7 ns t1 CHICLK Rise Time t2 CHICLK Width (8.192 MHz)* 48.84 -- 73.24 ns t2 CHICLK Width (16.384 MHz)* 24.42 -- 36.62 ns t3 CHICLK Fall Time -- 2 7 ns t4 CHICLK Period (8.192 MHz) -- 122.07 -- ns t4 CHICLK Period (16.384 MHz) -- 61.03 -- ns * VIH to VIH or VIL to VIL. t6 t5 t7 VDD33 VIH VIH 50% VIL VIL t8 Figure 4. MPUCLK Timing Specifications Table 23. MPUCLK Timing Specifications Parameter Description t5 MPUCLK Rise Time t6 MPUCLK Width* t7 MPUCLK Fall Time t8 MPUCLK Period Min Typ Max Unit -- 2 7 ns 6.06 -- -- ns -- 2 7 ns 15.2 -- -- ns * VIH to VIH or VIL to VIL. Agere Systems Inc. 17 STSI-144 Scalable Time-Slot Interchanger Hardware Design Guide Advance Information June 2003 Timing Diagrams and ac Characteristics (continued) Figure 5 shows the ac timing specifications for the STSI-144. All timing parameters are referenced to VIHmin and VILmax. The reference signal polarity may be inverted for some timing parameters. VIH REFERENCE SIGNAL VIL VIL t9 INPUT SIGNAL t10 VIH HIZ VIL t11 OUTPUT SIGNAL HIZ t12 VOH HIZ VOL Figure 5. ac Timing Measurement Specification Table 24. ac Timing Measurement Specification Parameter t9 t10 t11 t12 18 Description Setup Time Hold Time Output Delay Output 3-State Time Agere Systems Inc. STSI-144 Scalable Time-Slot Interchanger Hardware Design Guide Advance Information June 2003 Timing Diagrams and ac Characteristics (continued) FSYNC t13 t14 t15 t16 CHICLK RXD t17 t18 t19 TXD Note: This figure assumes STSI-144 is programmed to sample FSYNC on rising edge of CHICLK. Figure 6. CHI Interface Timing Table 25. CHI Interface Timing Parameter Description Min Max Unit t13 FSYNC Setup Time to Active CHICLK Edge 10 -- ns t14 FSYNC Hold Time from Active CHICLK Edge 5 -- ns t15 RXD Setup to Active CHICLK Edge 10 -- ns t16 RXD Hold Time from Active CHICLK Edge 5 -- ns t17 TXD High Z to Data Valid -- 15 ns t18 TXD Propagation Delay from Active CHICLK Edge 2 12 ns t19 Transmit Data High Impedance* -- 15 ns * Applies if Driver_Enable_Control = 01; see Figure 17, CHI 3-State Output Control, if Driver_Enable_Control = 11. All timing specifications are with respect to VIHmin and VILmax as shown in Figure 5. All timing specifications also apply under the following conditions: If FS is active-low. If the falling edge of CHICLK is specified as the active edge. At all RXD and TXD rates (16.384 Mbits/s, 8.192 Mbits/s, 4.096 Mbits/s, or 2.048 Mbits/s) with a CHICLK frequency of 16.384 MHz or 8.192 MHz. Agere Systems Inc. 19 STSI-144 Scalable Time-Slot Interchanger Hardware Design Guide Advance Information June 2003 Timing Diagrams and ac Characteristics (continued) FSYNC CHICLK w/ 0 offset w/ 1/4 bit offset w/ 1/2 bit offset w/ 3/4 bit offset w/ bit offset = 1 w/ 23/4 bit offset TS255 B6 TS255 B7 TS255 B6 TS255 B7 TS255 B6 TS255 B5 TS255 B3 TS255 B4 TS0 B1 TS0 B2 TS0 B5 TS0 B4 TS0 B3 TS0 B0 TS0 B5 TS0 B4 TS0 B3 TS0 B2 TS255 B6 TS255 B7 data sampled TS0 B4 TS0 B3 TS0 B2 TS0 B0 TS0 B1 data sampled TS0 B0 TS255 B7 data sampled TS255 B5 TS0 B3 TS0 B2 TS0 B0 TS0 B1 data sampled TS255 B7 TS255 B6 TS0 B2 TS0 B0 TS0 B1 data sampled TS255 B7 TS255 B6 TS255 B5 TS0 B0 TS0 B1 data sampled TS0 B4 TS0 B3 TS0 B1 TS0 B5 TS0 B5 TS0 B4 TS0 B2 TS0 B3 w/ bit offset = 7 TS254 B7 TS255 B0 TS255 B1 TS255 B2 data sampled TS255 B3 TS255 B4 TS255 B5 TS255 B6 TS255 B7 TS0 B 0 TS0 B1 w/ TS offset = 1, bit offset = 0 TS254 B6 TS254 B7 TS255 B0 TS255 B1 data sampled TS255 B2 TS255 B3 TS255 B4 TS255 B5 TS255 B6 TS255 B7 TS0 B0 w/ TS offset = 13, bit offset = 31/4 w/ TS offset = 255, bit offset = 73/4 TS242 B3 TS255 B6 TS242 B4 TS255 B7 TS242 B5 TS242 B6 data sampled TS0 B0 TS242 B7 TS0 B1 TS0 B2 data sampled TS243 B0 TS0 B3 TS243 B1 TS0 B4 TS243 B2 TS0 B5 TS243 B4 TS243 B3 TS0 B6 TS0 B7 TS243 B5 TS1 B0 Note: For this timing diagram, it is assumed that FSYNC has been programmed to be active-high, and to be sampled by the rising edge of the CHICLK. Figure 7. Typical Receive CHI Timing with 16.384 Mbits/s Data and 16.384 MHz CHICLK FSYNC CHICLK w/ 0 offset w/ 1/2 bit offset TS255 B5 TS255 B6 TS255 B5 TS255 B7 TS255 B6 TS0 B0 TS255 B7 TS0 B1 TS0 B0 TS0 B2 TS0 B1 TS0 B3 TS0 B2 TS0 B4 TS0 B3 TS0 B5 TS0 B4 w/ bit offset = 1 TS255 B4 TS255 B5 TS255 B6 TS255 B7 TS0 B0 TS0 B1 TS0 B2 TS0 B3 TS0 B4 w/ TS offset = 1, bit offset = 0 TS254 B5 TS254 B6 TS254 B7 TS255 B0 TS255 B1 TS255 B2 TS255 B3 TS255 B4 TS255 B5 w/ TS offset = 255, bit offset = 71/2 TS255 B6 TS255 B7 TS0 B0 TS0 B1 TS0 B2 TS0 B3 TS0 B4 TS0 B5 Notes: 1/4 bit offset not valid with 16 Mbits/s data. For this timing diagram, it is assumed that FSYNC has been programmed to be active-high, and to be sampled by the rising edge of the CHICLK. Figure 8. Transmit CHI Timing with 16.384 Mbits/s Data and 16.384 MHz CHICLK 20 Agere Systems Inc. STSI-144 Scalable Time-Slot Interchanger Hardware Design Guide Advance Information June 2003 Timing Diagrams and ac Characteristics (continued) FSYNC CHICLK w/ 0 offset TS127 B7 TS0 B0 TS0 B1 TS0 B2 TS0 B3 TS0 B4 data sampled w/ 1/4 bit offset TS127 B7 TS0 B0 TS0 B1 TS0 B2 TS0 B3 TS0 B4 data sampled w/ 1/2 bit offset TS127 B7 TS0 B0 TS0 B1 TS0 B2 TS0 B3 data sampled w/ 3/4 bit offset TS 127 B6 TS127 B7 TS0 B0 TS0 B2 TS0 B1 TS0 B3 data sampled w/ bit offset = 1 TS127 B6 TS127 B7 TS0 B0 TS0 B1 TS0 B2 TS0 B3 data sampled w/ 23/4 bit offset TS 127 B4 TS127 B5 TS127 B6 TS0 B0 TS127 B7 TS0 B1 data sampled w/ bit offset = 7 TS127 B0 TS127 B1 TS127 B2 TS127 B3 TS127 B4 TS127 B5 TS127 B1 TS127 B2 TS127 B3 TS127 B4 data sampled w/ TS offset = 1, bit offset = 0 TS126 B7 data sampled w/ TS offset = 13, bit offset = 31/4 w/ TS offset = 127, bit offset = 73/4 TS127 B0 TS114 B4 TS114 B5 TS114 B6 TS114 B7 TS115 B0 TS115 B1 data sampled TS 127 B7 TS0 B0 TS0 B1 TS0 B2 TS0 B3 TS0 B4 data sampled Note: For this timing diagram, it is assumed that FSYNC has been programmed to be active-high, and to be sampled by the rising edge of the CHICLK. Figure 9. Typical Receive CHI Timing with 8.192 Mbits/s Data and 16.384 MHz CHICLK FSYNC CHICLK w/ 0 offset w/ 1/4 bit offset TS 127 B6 TS127 B7 TS127 B6 w/ 1/2 bit offset TS0 B0 TS127 B7 TS127 B6 TS0 B1 TS0 B0 TS127 B7 TS0 B2 TS0 B1 TS0 B0 TS0 B3 TS0 B2 TS0 B1 TS0 B3 TS0 B2 TS0 B3 w/ bit offset = 1 TS 127 B5 TS127 B6 TS127 B7 TS0 B0 TS0 B1 TS0 B2 w/ TS offset = 1, bit offset = 0 TS 126 B6 TS126 B7 TS127 B0 TS127 B1 TS127 B2 TS127 B3 w/ TS offset = 127, bit offset = 73/4 TS127 B7 TS0 B0 TS0 B1 TS0 B2 TS0 B3 Note: For this timing diagram, it is assumed that FSYNC has been programmed to be active-high, and to be sampled by the rising edge of the CHICLK. Figure 10. Transmit CHI Timing with 8.192 Mbits/s Data and 16.384 MHz CHICLK Agere Systems Inc. 21 STSI-144 Scalable Time-Slot Interchanger Hardware Design Guide Advance Information June 2003 Timing Diagrams and ac Characteristics (continued) FSYNC CHICLK w/ 0 offset TS0 B0 TS0 B1 TS0 B2 data sampled w/ 1/4 bit offset TS63 B7 TS0 B0 TS0 B1 TS0 B2 data sampled w/ 1/2 bit offset TS63 B7 TS0 B0 TS0 B1 TS0 B2 data sampled w/ 3/4 bit offset TS63 B7 TS0 B0 TS0 B1 data sampled w/ bit offset = 1 TS63 B7 TS0 B0 TS0 B1 data sampled w/ 23/4 bit offset TS63 B5 TS63 B6 TS63 B7 data sampled w/ bit offset = 7 TS63 B1 TS63 B2 TS63 B3 TS63 B1 TS63 B2 data sampled w/ TS offset = 1, bit offset = 0 w/ TS offset = 13, bit offset = 31/4 TS63 B0 data sampled TS50 B4 TS50 B5 TS50 B6 TS50 B7 data sampled w/ TS offset = 63, bit offset = 73/4 TS0 B0 TS0 B1 TS0 B2 data sampled Note: For this timing diagram, it is assumed that FSYNC has been programmed to be active-high, and to be sampled by the rising edge of the CHICLK. Figure 11. Typical Receive CHI Timing with 4.096 Mbits/s Data and 16.384 MHz CHICLK FSYNC CHICLK w/ 0 offset TS63 B7 w/ 1/4 bit offset w/ 1/2 bit offset TS0 B0 TS63 B7 TS63 B6 TS0 B1 TS0 B0 TS63 B7 TS0 B1 TS0 B0 TS0 B1 w/ bit offset = 1 TS63 B6 TS63 B7 TS0 B0 w/ TS offset = 1, bit offset = 0 TS62 B7 TS63 B0 TS63 B1 w/ TS offset = 63, bit offset = 73/4 TS63 B7 TS0 B0 TS0 B1 TS0 B2 Note: For this timing diagram, it is assumed that FSYNC has been programmed to be active-high, and to be sampled by the rising edge of the CHICLK. Figure 12. Transmit CHI Timing with 4.096 Mbits/s Data and 16.384 MHz CHICLK 22 Agere Systems Inc. STSI-144 Scalable Time-Slot Interchanger Hardware Design Guide Advance Information June 2003 Timing Diagrams and ac Characteristics (continued) FSYNC CHICLK TS0 B0 w/ 0 offset TS0 B1 data sampled TS0 B0 w/ 1/4 bit offset TS0 B1 data sampled w/ 1/2 bit offset TS31 B7 TS0 B0 TS0 B1 data sampled TS31 B7 w/ 3/4 bit offset TS0 B0 TS0 data sampled TS31 B7 w/ bit offset = 1 TS0 B0 data sampled TS31 B5 w/ 23/4 bit offset TS31 B6 TS31 data sampled TS31 B1 w/ bit offset = 7 TS31 B2 data sampled w/ TS offset = 1, bit offset = 0 TS31 B0 TS31 B1 data sampled w/ TS offset = 13, bit offset = 31/4 TS18 B5 TS18 B6 data sampled w/ TS offset = 31, bit offset = 73/4 TS0 B0 TS0 B1 TS0 data sampled Note: For this timing diagram, it is assumed that FSYNC has been programmed to be active-high, and to be sampled by the rising edge of the CHICLK. Figure 13. Typical Receive CHI Timing with 2.048 Mbits/s Data and 16.384 MHz CHICLK FSYNC CHICLK w/ 0 offset TS31 B7 w/ 1/4 bit offset TS0 B0 TS31 B7 TS0 B0 TS31 B7 w/ 1/2 bit offset TS0 B1 TS0 B0 w/ bit offset = 1 TS31 B6 TS31 B7 TS0 B0 w/ TS offset = 1, bit offset = 0 TS30 B7 TS31 B0 TS31 B01 w/ TS offset = 31, bit offset = 73/4 TS31 B7 TS0 B0 TS0 B1 Note: For this timing diagram, it is assumed that FSYNC has been programmed to be active-high, and to be sampled by the rising edge of the CHICLK. Figure 14. Transmit CHI Timing with 2.048 Mbits/s Data and 16.384 MHz CHICLK Agere Systems Inc. 23 STSI-144 Scalable Time-Slot Interchanger Hardware Design Guide Advance Information June 2003 Timing Diagrams and ac Characteristics (continued) FSYNC CHICLK w/ 0 offset w/ 1/4 bit offset TS127 B6 TS127 B6 w/ 1/2 bit offset w/ 3/4 bit offset w/ bit offset = 1 w/ 23/4 bit offset TS127 B7 TS127 B7 TS127 B6 TS127 B5 TS127 B3 TS127 B4 TS127 B6 TS127 B7 data sampled TS0 B0 TS0 B5 TS0 B4 TS0 B3 TS0 B2 TS0 B5 TS0 B4 TS0 B3 TS0 B2 TS0 B1 TS0 B4 TS0 B3 TS0 B2 TS0 B1 TS0 B0 data sampled TS127 B7 TS0 B0 data sampled TS127 B5 TS0 B3 TS0 B2 TS0 B0 TS0 B1 data sampled TS127 B7 TS127 B6 TS0 B2 TS0 B0 TS0 B1 data sampled TS127 B7 TS127 B6 TS127 B5 TS0 B0 TS0 B1 data sampled TS0 B5 TS0 B4 TS0 B3 TS0 B1 TS0 B5 TS0 B4 TS0 B2 TS0 B3 w/ bit offset = 7 TS126 B7 TS127 B0 TS127 B1 TS127 B2 data sampled TS127 B3 TS127 B4 TS127 B5 TS127 B6 TS127 B7 TS0 B 0 TS0 B1 w/ TS offset = 1, bit offset = 0 TS126 B6 TS126 B7 TS127 B0 TS127 B1 data sampled TS127 B2 TS127 B3 TS127 B4 TS127 B5 TS127 B6 TS127 B7 TS0 B0 w/ TS offset = 13, bit offset = 31/4 w/ TS offset = 127, bit offset = 73/4 TS114 B3 TS127 B6 TS114 B4 TS127 B7 TS114 B5 TS114 B6 data sampled TS0 B0 TS114 B7 TS0 B1 TS0 B2 data sampled TS115 B0 TS0 B3 TS115 B1 TS0 B4 TS115 B2 TS0 B5 TS115 B3 TS0 B6 TS115 B4 TS0 B7 TS115 B5 TS1 B0 Note: For this timing diagram, it is assumed that FSYNC has been programmed to be active-high, and to be sampled by the rising edge of the CHICLK. Figure 15. Typical Receive CHI Timing with 8.192 Mbits/s Data and 8.192 MHz CHICLK FSYNC CHICLK w/ 0 offset w/ 1/2 bit offset TS127 B5 TS127 B6 TS127 B5 TS127 B7 TS127 B6 TS0 B0 TS127 B7 TS0 B1 TS0 B0 TS0 B2 TS0 B1 TS0 B3 TS0 B2 TS0 B4 TS0 B3 TS0 B5 TS0 B4 w/ bit offset = 1 TS127 B4 TS127 B5 TS127 B6 TS127 B7 TS0 B0 TS0 B1 TS0 B2 TS0 B3 TS0 B4 w/ TS offset = 1, bit offset = 0 TS126 B5 TS126 B6 TS126 B7 TS127 B0 TS127 B1 TS127 B2 TS127 B3 TS127 B4 TS127 B5 w/ TS offset = 127, bit offset = 71/2 TS127 B6 TS127 B7 TS0 B0 TS0 B1 TS0 B2 TS0 B3 TS0 B4 TS0 B5 Notes: 1/4 bit offset not valid with 8 MHz data and 8 MHz clock. For this timing diagram, it is assumed that FSYNC has been programmed to be active-high, and to be sampled by the rising edge of the CHICLK. Figure 16. Transmit CHI Timing with 8.192 Mbits/s Data and 8.192 MHz CHICLK 24 Agere Systems Inc. STSI-144 Scalable Time-Slot Interchanger Hardware Design Guide Advance Information June 2003 Timing Diagrams and ac Characteristics (continued) CHICLK 16.384 MHz t20 TXD 16.384 Mbits/s CHICLK 8.192 MHz t21 TXD 8.192 Mbits/s CHICLK 8.192 MHz t22 TXD 8.192 Mbits/s Figure 17. CHI 3-State Output Control Table 26. CHI 3-State Output Control Control in the table below refers to bits [6:4] in Transmit_CHI_Global_Configuration register (0x0C84). This only applies if bits 13 and 12 of the corresponding Transmit_CHI_Control register (0x0C00--0x0C7E) are set to 11. See STSI-144 Register Description. Parameter Control t20 t21 t22 Reference Point* Min Max Unit 000 After Previous Like Edge in 16 MHz 50 59 ns 001 After Previous Like Edge in 16 MHz 44 53 ns 010 After Previous Like Edge in 16 MHz 38 47 ns 011 After Previous Like Edge in 16 MHz 32 41 ns 000 After Previous Opposite Edge in 8 MHz 50 59 ns 001 After Previous Opposite Edge in 8 MHz 44 53 ns 010 After Previous Opposite Edge in 8 MHz 38 47 ns 011 After Previous Opposite Edge in 8 MHz 32 41 ns 100 After Previous Like Edge (8 MHz mode only) 111 120 ns 101 After Previous Like Edge (8 MHz mode only) 105 114 ns 110 After Previous Like Edge (8 MHz mode only) 99 108 ns 111 After Previous Like Edge (8 MHz mode only) 93 102 ns * Like edge is the reference edge (rising or falling) as defined by the Transmit_Clock_Edge bit in the Transmit_CHI_Global_Configuration (0x0C84) register. See STSI-144 Register Description document for further details. All timing specifications are with respect to the parameters shown in Figure 5. Agere Systems Inc. 25 STSI-144 Scalable Time-Slot Interchanger Hardware Design Guide Advance Information June 2003 Timing Diagrams and ac Characteristics (continued) MPUCLK t23 t24 ADDR[15:00] t26 t25 CS t27 t28 AS t30 t29 R/W t32 t31 t33 DATA[15:00] PAR[1:0] t35 t35 t36 t34 DT Figure 18. Microprocessor Port Timing--Read Cycle Table 27. Microprocessor Port Timing--Read Cycle Parameter Description Min* Max* Unit t23 Address Setup 5 -- ns t24 Address Hold 1 -- ns t25 Chip Select Setup 5 -- ns t26 Chip Select Hold 1 -- ns t27 Address Strobe Setup 5 -- ns t28 Address Strobe Hold 1 -- ns t29 R/W Setup 5 -- ns t30 R/W Hold 1 -- ns t31 Data Output Enable -- 15 ns t32 Data Clock to Valid 1 7 ns t33 Data High Impedance -- 8 ns t34 DT High Impedance to Valid 1 15 ns t35 DT Clock to Out 1 7 ns t36 DT Valid to High Impedance 1 8 ns * All timing specifications are with respect to the parameters shown in Figure 5. 26 Agere Systems Inc. STSI-144 Scalable Time-Slot Interchanger Hardware Design Guide Advance Information June 2003 Timing Diagrams and ac Characteristics (continued) MPUCLK t37 t38 ADDR[15:00] t40 t39 CS t41 AS t42 t44 t43 R/W t46 t45 DATA[15:00] PAR[1:0] DT t48 t48 t47 t49 Figure 19. Microprocessor Port Timing--Write Cycle Table 28. Microprocessor Port Timing--Write Cycle Parameter Description Min* Max* Unit t37 Address Setup 5 -- ns t38 Address Hold 1 -- ns t39 Chip Select Setup 5 -- ns t40 Chip Select Hold 1 -- ns t41 Address Strobe Setup 5 -- ns t42 Address Strobe Hold 1 -- ns t43 R/W Setup 5 -- ns t44 R/W Hold 1 -- ns t45 Data Setup 5 -- ns t46 Data Hold 1 -- ns t47 DT High Impedance to Valid 1 15 ns t48 DT Clock to Out 1 7 ns t49 DT Valid to High Impedance 1 8 ns * All timing specifications are with respect to the parameters shown in Figure 5. Note: Posted writes follow the same timing shown in Figure 19 and Table 28. A posted write may return a DT prior to the device completing the write cycle. This allows the microprocessor to continue operation while the STSI-144 completes the write. Agere Systems Inc. 27 STSI-144 Scalable Time-Slot Interchanger Hardware Design Guide Advance Information June 2003 Timing Diagrams and ac Characteristics (continued) t49 t50 80% 20% 80% 20% Figure 20. LVDS Output Timing Specifications Table 29. LVDS ac Characteristics Parameter Symbol 28 Description Conditions Min Typ Max Unit t49 tR VOD Rise Time, 20% to 80% ZL = 100 1%, CP = 3.0 pF, CN = 3.0 pF 100 -- 210 ps t50 tF VOD Fall Time, 80% to 20% ZL = 100 1%, CP = 3.0 pF, CN = 3.0 pF 100 -- 210 ps Agere Systems Inc. STSI-144 Scalable Time-Slot Interchanger Hardware Design Guide Advance Information June 2003 Outline Diagrams Dimensions are in millimeters. TOP VIEW 27.00 SQUARE 24.50 0.10 SQUARE A1 INDICATOR (GOLD PLATED) 1.50 TYP. USE OF EJECTOR PINS IS OPTIONAL 3.00 x 45 APPROX TYP 4 CORNERS 1.20 x 45 APPROX TYP 3 PLACES 1.17 0.05 0.61 0.08 2.51 MAX SEATING PLANE 0.20 0.60 0.10 SOLDER BALL 25 SPACES @ 1.00 = 25.00 CENTER ARRAY FOR THERMAL ENHANCEMENT A1 BALL CORNER Agere Systems Inc. AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A 0.63 0.10 25 SPACES @ 1.00 = 25.00 1 2 3 4 5 6 7 8 9 10 12 14 16 18 20 22 24 26 11 13 15 17 19 21 23 25 29 STSI-144 Scalable Time-Slot Interchanger Hardware Design Guide Advance Information June 2003 Ordering Information Device Part Number Ball Count Package Comcode STSI-144 TTSI144641BL-1 388 PBGAM1T 109101899 For additional information, contact your Agere Systems Account Manager or the following: INTERNET: http://www.agere.com E-MAIL: docmaster@agere.com N. AMERICA: Agere Systems Inc., Lehigh Valley Central Campus, Room 10A-301C, 1110 American Parkway NE, Allentown, PA 18109-9138 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA: Agere Systems Hong Kong Ltd., Suites 3201 & 3210-12, 32/F, Tower 2, The Gateway, Harbour City, Kowloon Tel. (852) 3129-2000, FAX (852) 3129-2020 CHINA: (86) 21-5047-1212 (Shanghai), (86) 755-25881122 (Shenzhen) JAPAN: (81) 3-5421-1600 (Tokyo), KOREA: (82) 2-767-1850 (Seoul), SINGAPORE: (65) 6778-8833, TAIWAN: (886) 2-2725-5858 (Taipei) EUROPE: Tel. (44) 1344 296 400 Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. Agere, Agere Systems, and the Agere logo are trademarks of Agere Systems Inc. Copyright (c) 2003 Agere Systems Inc. All Rights Reserved June 2003 DS03-126SWCH (Replaces DS02-096SWCH)