Small, 3.75 kV RMS Quad Digital Isolators
Data Sheet
ADuM3480/ADuM3481/ADuM3482
Rev. A Document Feedback
Informa
tion furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2012–2014 Analog Devices, Inc. All rights reserved.
Technical Support www.analog.com
FEATURES
Up to 25 Mbps data rate (NRZ)
Low propagation delay: 25 ns typical
Low dynamic power consumption
1.8 V to 5 V level translation
High temperature operation: 125°C
High common-mode transient immunity: >25 kV/µs
Output default select
20-lead, RoHS-compliant, SSOP package
Safety and regulatory approvals:
UL recognition: 3750 V rms for 1 minute per UL 1577
CSA Component Acceptance Notice #5A
VDE certificate of conformity
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
VIORM = 560 V peak
APPLICATIONS
General-purpose multichannel isolation
SPI interface/data converter isolation
Industrial field bus isolation
GENERAL DESCRIPTION
The ADuM3480/ADuM3481/ADuM34821 are quad-channel
digital isolators based on the Analog Devices, Inc., iCoupler®
technology. Combining high speed CMOS and monolithic air
core transformer technology, these isolation components provide
outstanding performance characteristics superior to alternatives
such as optocoupler devices and other integrated couplers. With
typical propagation delay reduced to 25 ns, pulse width
distortion is also halved.
The four channels of the ADuM3480/ADuM3481/ADuM3482
are available in a variety of channel configurations with two data
rate grades up to 25 Mbps (see the Ordering Guide section). All
models use separate core and I/O power supplies. The core
operates between 3.0 V and 5.5 V, whereas the I/O supply can
range from 1.8 V to 5.5 V. If I/O operation is required within
the range of the core supply, the two supplies can be tied together
to allow single-supply operation. When the I/O must interface
with logic levels that are different from the core supply voltage,
the I/O supply operates independently of the core supply over
its wider range. The minimum I/O supply voltage is 1.8 V, which
allows compatibility with low voltage logic. Both core and I/O
supplies are required for proper operation.
FUNCTIONAL BLOCK DIAGRAMS
REG REG
V
DDL1
V
DDL2
120
GND
1
GND
2
219
V
IA
V
OA
318
ENCODE DECODE
V
IB
V
OB
417
ENCODE DECODE
V
IC
V
OC
516
ENCODE DECODE
V
ID
V
OD
615
ENCODE DECODE
NC CTRL
2
714
V
DD1
V
DD2
813
V
DDC1
V
DDC2
912
GND
1
GND
2
10 11
ADuM3480
10459-001
Figure 1. ADuM3480
REG REG
VDDL1 VDDL2
120
GND1GND2
219
VIA VOA
318
ENCODE DECODE
VIB VOB
417
ENCODE DECODE
VIC VOC
516
ENCODE DECODE
VOD VID
615
DECODE ENCODE
CTRL
1
CTRL
2
714
V
DD1
V
DD2
813
V
DDC1
V
DDC2
912
GND
1
GND
2
10 11
ADuM3481
10459-002
Figure 2. ADuM3481
REG REG
VDDL1 VDDL2
120
GND1GND2
219
VIA VOA
318
ENCODE DECODE
VIB VOB
417
ENCODE DECODE
VOC VIC
516
DECODE ENCODE
VOD VID
615
DECODE ENCODE
CTRL
1
CTRL
2
714
V
DD1
V
DD2
813
V
DDC1
V
DDC2
912
GND
1
GND
2
10 11
ADuM3482
10459-003
Figure 3. ADuM3482
1 Protected by U.S. Patents 5,952,849; 6,873,065; 6,903,578; and 7,075,329. Other patents are pending.
ADuM3480/ADuM3481/ADuM3482 Data Sheet
Rev. A | Page 2 of 20
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagrams ............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Electrical Characteristics—5 V Operation................................ 3
Electrical Characteristics—3 V Operation................................ 5
Electrical Characteristics—1.8 V Operation ............................ 7
Package Characteristics ............................................................... 9
Regulatory Information ............................................................... 9
Regulatory Approvals ................................................................... 9
Insulation and Safety Related Specifications ............................ 9
DIN V VDE V 0884-10 (VDE V 0884-10) Insulation
Characteristics ............................................................................ 10
Recommended Operating Conditions .................................... 10
Absolute Maximum Ratings ......................................................... 11
ESD Caution................................................................................ 11
Pin Configurations and Function Descriptions ......................... 12
Typical Performance Characteristics ........................................... 15
Applications Information .............................................................. 17
Supply Voltages ........................................................................... 17
Printed Circuit Board Layout ................................................... 17
Propagation Delay Related Parameters ................................... 17
DC Correctness and Magnetic Field Immunity ..................... 17
Power Consumption .................................................................. 18
Insulation Lifetime ..................................................................... 19
Outline Dimensions ....................................................................... 20
Ordering Guide .......................................................................... 20
REVISION HISTORY
6/14—Rev. 0 to Rev. A
Changed Safety Certification Status from Pending to Approved
(Throughout) .................................................................................... 1
Changes to Table 12 .......................................................................... 9
Changed Highest Allowable Overvoltage from 5300 VPEAK to
4000 VPEAK ........................................................................................ 10
Changes to DC Correctness and Magnetic Field Immunity
Section .............................................................................................. 17
Changes to Ordering Guide .......................................................... 20
7/12—Revision 0: Initial Version
Data Sheet ADuM3480/ADuM3481/ADuM3482
Rev. A | Page 3 of 20
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—5 V OPERATION
All typical specifications are at TA = 25°C, VDDL1 = VDD1 = VDDL2 = VDD2 = 5 V. Minimum/maximum specifications apply over the entire
recommended operation range: 4.5 V ≤ VDDL1, VDD1 ≤ 5.5 V, 4.5 V ≤ VDDL2, VDD2 ≤ 5.5 V, −40°C ≤ TA ≤ +125°C, unless otherwise noted.
Switching specifications are tested with CL = 15 pF, and CMOS signal levels, unless otherwise noted.
Table 1.
Parameter Symbol
A Grade
B Grade
Unit Test Conditions/Comments Min Typ Max Min Typ Max
SWITCHING SPECIFICATIONS
Pulse Width PW 1000 40 ns Within PWD limit
Data Rate 1 25 Mbps Within PWD limit
Propagation Delay tPHL, tPLH 65 90 25 33 ns 50% input to 50% output
Pulse Width Distortion PWD 6 3 ns |tPLH − tPHL|
Change vs. Temperature 7 3 ps/°C
Propagation Delay Skew tPSK 50 17 ns Between any two units
Channel Matching
Codirectional tPSKCD 19 5 ns
Opposing Direction tPSKOD 25 7 ns
Jitter 2 2 ns
Table 2.
Parameter Symbol
1 Mbps—A, B Grades 25 Mbps—B Grade
Unit Test Conditions/Comments Min Typ Max Min Typ Max
SUPPLY CURRENT
ADuM3480 IDD1 2.0 2.9 8.6 12 mA
IDDL1 0.11 0.4 0.2 0.6 mA
IDD2 5.1 6.9 6.0 7.5 mA
IDDL2 0.2 0.7 2.1 4.8 mA CL = 0 pF
ADuM3481 IDD1 2.8 3.0 7.9 10 mA
IDDL1 0.14 0.5 0.7 1.4 mA CL = 0 pF
IDD2 4.3 5.7 6.7 7.8 mA
IDDL2 0.18 0.6 1.6 3.2 mA CL = 0 pF
ADuM3482 IDD1 3.5 4.1 7.3 8.8 mA
IDDL1 0.16 0.5 1.2 2.4 mA CL = 0 pF
IDD2 3.5 4.7 7.3 8.8 mA
IDDL2 0.16 0.65 1.2 2.4 mA CL = 0 pF
ADuM3480/ADuM3481/ADuM3482 Data Sheet
Rev. A | Page 4 of 20
Table 3.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
DC SPECIFICATIONS
Input Voltage Threshold
Logic High VIH 0.7 VDDLx V
Logic Low VIL 0.3 VDDLx V
Output Voltages
Logic High VOH VDDLx − 0.1 5.0 V IOx = −20 µA, VIx = VIxH
VDDLx − 0.4 4.8 V IOx = −4 mA, VIx = VIxH
Logic Low VOL 0.0 0.1 V IOx = 20 µA, VIx = VIxL
0.2 0.4 V IOx = 4 mA, VIx = VIxL
I
I
−10
+0.01
+10
µA
0 V ≤ V
Ix
≤ V
DDLx
, 0 V ≤ V
CTRLx
≤ V
DDLx
Supply Current per Channel
Quiescent Supply Current
Regulator Input Side IDDI (Q) 0.50 0.60 mA
I/O Input IDDIL (Q) 0.027 0.05 mA
Regulator Output Side IDDO (Q) 1.26 1.7 mA
I/O Output IDDOL (Q) 0.031 0.10 mA
Dynamic Supply Current
Regulator Input Side IDDI (D) 0.070 mA/Mbps
I/O Input IDDIL (D) 0.90 µA/Mbps
Regulator Output Side IDDO (D) 0.010 mA/Mbps
I
DDOL (D)
0.020
mA/Mbps
AC SPECIFICATIONS
Output Rise/Fall Time tR/tF 2.5 ns 10% to 90%
1
|CM|
25
35
kV/µs
V
Ix
= V
DDLx
, V
CM
= 1000 V, transient
magnitude = 800 V
Refresh Period tr 1.66 µs
1 |CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining VOL < 0.8 × VDDLx or VOH > 0.7 × VDDIx. The common-mode voltage slew
rates apply to both rising and falling common-mode voltage edges.
Data Sheet ADuM3480/ADuM3481/ADuM3482
Rev. A | Page 5 of 20
ELECTRICAL CHARACTERISTICS—3 V OPERATION
All typical specifications are at TA = 25°C, VDDL1 = VDD1 = VDDL2 = VDD2 = 3.0 V. Minimum/maximum specifications apply over the entire
recommended operation range: 3.0 V ≤ VDDL1,VDD1 ≤ 3.6 V, 3.0 V ≤ VDDL2, VDD2 ≤ 3.6 V, −40°C ≤ TA ≤ +125°C, unless otherwise noted.
Switching specifications are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted.
Table 4.
Parameter Symbol
A Grade B Grade
Unit Test Conditions/Comments Min Typ Max Min Typ Max
SWITCHING SPECIFICATIONS
Pulse Width PW 1000 40 ns Within PWD limit
Data Rate 1 25 Mbps Within PWD limit
Propagation Delay tPHL, tPLH 71 99 28 38 ns 50% input to 50% output
Pulse Width Distortion PWD 2 12 3 5 ns |tPLH − tPHL|
Change vs. Temperature 7 3 ps/°C
Propagation Delay Skew tPSK 58 20 ns Between any two units
Channel Matching
Codirectional tPSKCD 20 6 ns
Opposing Direction tPSKOD 26 9 ns
Jitter 4 3 ns
Table 5.
Parameter Symbol
1 Mbps—A, B Grades 25 Mbps—B Grade
Unit Test Conditions/Comments Min Typ Max Min Typ Max
SUPPLY CURRENT
ADuM3480 IDD1 1.4 2.9 8.1 11 mA
IDDL1 0.08 0.4 0.13 0.5 mA
IDD2 4.9 6.7 5.8 7.2 mA
IDDL2 0.14 0.40 1.4 2.5 mA CL = 0 pF
ADuM3481 IDD1 2.3 3.0 7.5 9.8 mA
IDDL1 0.09 0.4 0.46 1.4 mA CL = 0 pF
IDD2 4.0 5.7 6.4 7.5 mA
IDDL2 0.12 0.5 1.1 2.7 mA CL = 0 pF
ADuM3482 IDD1 3.2 4.2 7.0 8.8 mA
IDDL1 0.11 0.5 0.78 1.7 mA CL = 0 pF
I
DD2
3.2
4.2
7.0
8.8
mA
IDDL2 0.11 0. 5 0.78 1.7 mA CL = 0 pF
ADuM3480/ADuM3481/ADuM3482 Data Sheet
Rev. A | Page 6 of 20
Table 6.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
DC SPECIFICATIONS
Input Voltage Threshold
Logic High VIH 0.7 VDDLx V
Logic Low VIL 0.3 VDDLx V
Output Voltages
Logic High VOH VDDLx − 0.1 3.0 V IOx = −20 µA, VIx = VIxH
VDDLx − 0.4 2.8 V IOx = −4 mA, VIx = VIxH
Logic Low VOL 0.0 0.1 V IOx = 20 µA, VIx = VIxL
0.2 0.4 V IOx = 4 mA, VIx = VIxL
Input Current per Channel
I
I
−10
+0.01
+10
µA
0 V ≤ V
Ix
≤ V
DDLx
, 0 V ≤ V
CTRLx
≤ V
DDLx
Supply Current per Channel
Quiescent Supply Current
Regulator Input Side IDDI (Q) 0.36 0.5 mA
I/O Input IDDIL (Q) 0.019 0.050 mA
Regulator Output Side IDDO (Q) 1.21 1.7 mA
I/O Output IDDOL (Q) 0.021 0.050 mA
Dynamic Supply Current
Regulator Input Side IDDI (D) 0.070 mA/Mbps
I/O Input IDDIL (D) 0.53 µA/Mbps
Regulator Output Side IDDO (D) 0.010 mA/Mbps
I/O Output
I
DDOL (D)
0.013
mA/Mbps
AC SPECIFICATIONS
Output Rise/Fall Time tR/tF 3 ns 10% to 90%
Common-Mode Transient Immunity
1
|CM|
25
35
kV/µs
V
Ix
= V
DDLx
, V
CM
= 1000 V,
transient magnitude = 800 V
Refresh Period tr 1.66 µs
1 |CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining VOL < 0.8 × VDDLx or VOH > 0.7 × VDDIx. The common-mode voltage slew
rates apply to both rising and falling common-mode voltage edges.
Data Sheet ADuM3480/ADuM3481/ADuM3482
Rev. A | Page 7 of 20
ELECTRICAL CHARACTERISTICS—1.8 V OPERATION
All typical specifications are at TA = 25°C, VDDL1 = 1.8 V, VDD1 = 3.0 V, VDDL2 = 1.8 V, VDD2 = 3.0 V. Minimum/maximum specifications
apply over the entire recommended operation range: VDDL1 = 1.8 V, 3.0 V ≤ VDD1 ≤ 3.6 V, VDDL2 = 1.8 V, 3.0 V ≤ VDD2 ≤ 3.6 V,−40°C ≤ TA ≤
+125°C; unless otherwise noted. Switching specifications are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted.
Table 7.
Parameter Symbol
A Grade B Grade
Unit Test Conditions/Comments Min Typ Max Min Typ Max
SWITCHING SPECIFICATIONS
Pulse Width PW 1000 40 ns Within PWD limit
Data Rate 1 25 Mbps Within PWD limit
Propagation Delay tPHL, tPLH 86 145 43 85 ns 50% input to 50% output
Pulse Width Distortion PWD 6 32 6 30 ns |tPLH − tPHL|
Change vs. Temperature 7 3 ps/°C
Propagation Delay Skew tPSK 93 60 ns Between any two units
Channel Matching
Codirectional tPSKCD 40 34 ns
Opposing Direction tPSKOD 55 37 ns
Jitter 4 3 ns
Table 8.
Parameter Symbol
1 Mbps—A, B Grades 25 Mbps—B Grade
Unit Test Conditions/Comments Min Typ Max Min Typ Max
SUPPLY CURRENT
ADuM3480 IDD1 1.4 1.9 8.1 11 mA
IDDL1 0.04 0.3 0.07 0.4 mA
IDD2 4.7 6.5 5.7 7.3 mA
I
DDL2
0.08
0.5
0.82
1.5
mA
C
L
= 0 pF
ADuM3481 IDD1 2.3 2.8 7.5 10 mA
IDDL1 0.05 0.35 0.25 0.7 mA CL = 0 pF
IDD2 3.9 5.7 6.3 8.0 mA
IDDL2 0.07 0.4 0.63 1.3 mA CL = 0 pF
ADuM3482 IDD1 3.1 3.8 6.9 8.7 mA
IDDL1 0.06 0.4 0.44 1.1 mA CL = 0 pF
IDD2 3.1 4.5 6.9 8.8 mA
IDDL2 0.06 0.40 0.44 1.1 mA CL = 0 pF
ADuM3480/ADuM3481/ADuM3482 Data Sheet
Rev. A | Page 8 of 20
Table 9.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
DC SPECIFICATIONS
Input Voltage Threshold
Logic High VIH 0.7 VDDLx V
Logic Low VIL 0.3 VDDLx V
Output Voltages
Logic High VOH VDDLx − 0.1 1.8 V IOx = −20 µA, VIx = VIxH
VDDLx − 0.4 1.6 V IOx = −2 mA, VIx = VIxH
Logic Low VOL 0.0 0.1 V IOx = 20 µA, VIx = VIxL
0.2 0.4 V IOx = 2 mA, VIx = VIxL
Input Current per Channel
I
I
−10
+0.01
+10
µA
0 V ≤ V
Ix
≤ V
DDLx
, 0 V ≤ V
CTRLx
≤ V
DDLx
Supply Current per Channel
Quiescent Supply Current
Regulator Input Side IDDI (Q) 0.39 0.45 mA
I/O Input IDDIL (Q) 0.010 0.025 mA
Regulator Output Side IDDO (Q) 1.17 1.5 mA
I/O Output IDDOL (Q) 0.012 0.038 mA
Dynamic Supply Current
Regulator Input Side IDDI (D) 0.071 mA/Mbps
I/O Input IDDIL (D) 0.25 µA/Mbps
Regulator Output Side IDDO (D) 0.010 mA/Mbps
I/O Output
I
DDOL (D)
0.0077
mA/Mbps
AC SPECIFICATIONS
Output Rise/Fall Time tR/tF 3 ns 10% to 90%
Common-Mode Transient Immunity
1
|CM|
25
35
kV/µs
V
Ix
= V
DDLx
, V
CM
= 1000 V,
transient magnitude = 800 V
Refresh Period tr 1.66 µs
1 |CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining VOL < 0.8 × VDDLx or VOH > 0.7 × VDDIx. The common-mode voltage slew
rates apply to both rising and falling common-mode voltage edges.
Data Sheet ADuM3480/ADuM3481/ADuM3482
Rev. A | Page 9 of 20
PACKAGE CHARACTERISTICS
Table 10.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
Resistance (Input-to-Output)1 RI-O 1012 Ω
Capacitance (Input-to-Output)1 CI-O 2.2 pF f = 1 MHz
Input Capacitance2 CI 4.0 pF
IC Junction-to-Case Thermal Resistance
θ
JC
50.5
°C/W
Thermocouple located at center of package underside,
test conducted on 4-layer board with thin traces
1 The device is considered a 2-terminal device: Pin 1 to Pin 10 are shorted together; Pin 11 to Pin 20 are shorted together.
2 Input capacitance is from any input data pin to ground.
REGULATORY INFORMATION
The ADuM3480/ADuM3481/ADuM3482 are approved by the organizations listed in Table 11. See Table 16 and the Insulation Lifetime
section for the recommended maximum working voltages for specific cross-isolation waveforms and insulation levels.
REGULATORY APPROVALS
Table 11.
UL CSA VDE
Recognized under the UL 1577
component recognition program1
Approved under CSA Component
Acceptance Notice #5A
Certified according to DIN V VDE V 0884-10
(VDE V 0884-10):2006-122
Single protection, 3750 V rms
isolation voltage
Basic insulation per CSA 60950-1-03 and
IEC 60950-1, 400 V rms (565 V peak)
maximum working voltage
Reinforced insulation, 560 V peak
File E214100 File 205078 File 2471900-4880-0001
1 In accordance with UL 1577, each ADuM3480/ADuM3481/ADuM3482 is proof tested by applying an insulation test voltage of ≥4500 V rms for 1 second (current
leakage detection limit = 10 µA).
2 In accordance with DIN V VDE V 0884-10, each of the ADuM348x is proof tested by applying an insulation test voltage of ≥1050 V peak for 1 second (partial discharge
detection limit = 5 pC). The asterisk (*) marking branded on the component designates DIN V VDE V 0884-10 approval.
INSULATION AND SAFETY RELATED SPECIFICATIONS
Table 12.
Parameter Symbol Value Unit Test Conditions/Comments
Rated Dielectric Insulation Voltage 3750 V rms 1-minute duration
Minimum External Air Gap (Clearance) L(I01) >5.1 mm Measured from input terminals to output terminals,
shortest distance through air, in the plane of the PCB
Minimum External Tracking (Creepage)
L(I02)
>5.1
mm
Measured from input terminals to output terminals,
shortest distance path along body
Minimum Internal Gap (Internal Clearance) 0.017 min mm Distance through insulation
Tracking Resistance (Comparative Tracking Index) CTI >400 V DIN IEC 112/VDE 0303 Part 1
Isolation Group II Material Group (DIN VDE 0110, 1/89, Table 1)
ADuM3480/ADuM3481/ADuM3482 Data Sheet
Rev. A | Page 10 of 20
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 INSULATION CHARACTERISTICS
These isolators are suitable for reinforced electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by
protective circuits. The asterisk (*) marking on packages denotes DIN V VDE V 0884-10 approval.
Table 13.
Description Test Conditions/Comments Symbol Characteristic Unit
Installation Classification per DIN VDE 0110
For Rated Mains Voltage ≤ 150 V rms I to IV
For Rated Mains Voltage ≤ 300 V rms I to III
For Rated Mains Voltage ≤ 400 V rms I to II
Climatic Classification 40/105/21
Pollution Degree per DIN VDE 0110, Table 1 2
Maximum Working Insulation Voltage VIORM 560 VPEAK
Input-to-Output Test Voltage, Method B1 VIORM × 1.875 = Vpd(m), 100% production test, tini = tm =
1 sec, partial discharge < 5 pC
Vpd(m) 1050 VPEAK
Input-to-Output Test Voltage, Method A
After Environmental Tests Subgroup 1 VIORM × 1.5 = Vpd(m), tini = 60 sec, tm = 10 sec, partial
discharge < 5 pC
Vpd(m) 840 VPEAK
After Input and/or Safety Test Subgroup 2
and Subgroup 3
VIORM × 1.2 = Vpd(m), tini = 60 sec, tm = 10 sec, partial
discharge < 5 pC
Vpd(m) 672 VPEAK
Highest Allowable Overvoltage VIOTM 4000 VPEAK
Withstand Isolation Voltage
1 minute withstand rating
V
ISO
3750
V
RMS
Surge Isolation Voltage VPEAK = 10 kV, 1.2 µs rise time, 50 µs, 50% fall time VIOSM 6000 VPEAK
Safety Limiting Values
Maximum value allowed in the event of a failure
(see Figure 4)
Case Temperature TS 150 °C
Total Power Dissipation IS1 2.47 W
Insulation Resistance at TS VIO = 500 V RS >109 Ω
AMBI E NT TE M P E RATURE ( °C)
SAFETY-LIMITING POWER (W)
0
0
3.0
2.5
2.0
1.5
1.0
0.5
50 100 150 200
10459-004
Figure 4. Thermal Derating Curve, Dependence of Safety Limiting Values
with Ambient Temperature per DIN V VDE V 0884-10
RECOMMENDED OPERATING CONDITIONS
Table 14.
Parameter Symbol Min Max Unit
Operating Temperature TA −40 +125 °C
Supply Voltages1 VDDL1, VDDL2 1.8 5.5 V
VDD1, VDD2 3.0 5.5 V
Input Signal Rise and Fall
Times
1.0 ms
1 See the DC Correctness and Magnetic Field Immunity section for information
on immunity to external magnetic fields.
Data Sheet ADuM3480/ADuM3481/ADuM3482
Rev. A | Page 11 of 20
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 15.
Parameter Rating
Supply Voltages (VDD1, VDD2, VDDL1,
VDDL2, VDDC1, VDDC2)
−0.5 V to +7.0 V
Input Voltages (VIA, VIB, VIC, VID, VCTRL1,
VCTRL2)
−0.5 V to VDDI + 0.5 V
Output Voltages (VOA, VOB, VOC, VOD) −0.5 V to VDDO + 0.5 V
Average Output Current per Pin1 −10 mA to +10 mA
Common-Mode Transients2 −100 kV/μs to +100 kV/μs
Storage Temperature (TST) Range −65°C to +150°C
Ambient Operating Temperature
(TA) Range
−40°C to +125°C
1 See Figure 4 for maximum rated current values for various temperatures.
2 Refers to common-mode transients across the insulation barrier. Common-
mode transients exceeding the absolute maximum ratings may cause
latch-up or permanent damage.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 16. Maximum Continuous Working Voltage
Supporting 50-Year Minimum Lifetime1
Parameter Max Unit
Applicable
Certification
AC Voltage, Bipolar
Waveform
565 V peak All certifications
AC Voltage, Unipolar
Waveform
848 V peak
DC Voltage 848 V peak
1 Refers to the continuous voltage magnitude imposed across the isolation
barrier. See the Insulation Lifetime section for more information.
ESD CAUTION
ADuM3480/ADuM3481/ADuM3482 Data Sheet
Rev. A | Page 12 of 20
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
*PI N 2 AND P IN 10 ARE I NTERNALL Y CONNECTED.
CONNE CTING BO TH T O PCB S IDE 1 GRO UND IS
RECO M M E NDE D. PI N 11 AND P IN 19 ARE
INTERNAL LY CONNECTED. CO NNE CTI NG BO TH
TO PCB SIDE 2 GRO UND IS RE COMM E NDE D.
NOTES
1. NC = NO CO NNE CTI ON. THI S P IN I S NOT
CONNE CTED I NTERNALL Y AND CAN BE LEFT
FLOATING OR CONNECTED TO VDD1 OR G ND1.
1
2
3
4
20
19
18
17
516
615
714
912
10 11
813
ADuM3480
TOP VI EW
(No t t o Scal e)
VDDL1
GND1*
VIA
VIB
VIC
VID
NC
VDD1
VDDC1
GND1*
VDDL2
GND2*
VOA
VOB
VOC
VOD
CTRL2
VDD2
VDDC2
GND2*
10459-005
Figure 5. ADuM3480 Pin Configuration
Table 17. ADuM3480 Pin Function Descriptions
Pin No. Mnemonic Description
1 VDDL1 1.8 V to 5.5 V Supply Voltage for Isolator Side 1 Input/Output Circuits. Bypass VDDL1 to GND1 with a 0.01 µF to 0.1 µF
ceramic capacitor. For 3.0 V to 5.5 V input/output operation, VDDL1 can be connected directly to VDD1.
2 GND1 Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 10 are internally connected, and connecting both to
the PCB ground plane as close to the part as possible is recommended.
3 VIA Logic Input A.
4 VIB Logic Input B.
5 VIC Logic Input C.
6 VID Logic Input D.
7 NC No Connection. This pin is not connected internally and can be left floating or connected to VDD1 or GND1.
8 VDD1 3.0 V to 5.5 V Supply Voltage for Isolator Side 1.
9
V
DDC1
Output Pin of an Internal Regulator for Side 1. Bypass V
DDC1
to GND
1
with a 0.01 µF to 0.1 µF ceramic capacitor. Do
not use this pin to power external circuits.
10 GND1 Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 10 are internally connected, and connecting both to
the PCB ground plane as close to the part as possible is recommended.
11 GND2 Ground 2. Ground reference for Isolator Side 2. Pin 11 and Pin 19 are internally connected, and connecting both to
the PCB ground plane as close to the part as possible is recommended.
12 VDDC2 Output Pin of an Internal Regulator for Side 2. Bypass VDDC2 to GND2 with a 0.01 µF to 0.1 µF ceramic capacitor. Do
not use this pin to power external circuits.
13 VDD2 3.0 V to 5.5 V Supply Voltage for Isolator Side 2.
14 CTRL2 Select Side 2 Output Default Level. Low = default output low. High = default output high.
15 VOD Logic Output D.
16
V
OC
Logic Output C.
17 VOB Logic Output B.
18 VOA Logic Output A.
19 GND2 Ground 2. Ground reference for Isolator Side 2. Pin 11 and Pin 19 are internally connected, and connecting both to
the PCB ground plane as close to the part as possible is recommended.
20 VDDL2 1.8 V to 5.5 V Supply Voltage for Isolator Side 2 Input/Output Circuits. Bypass VDDL2 to GND2 with a 0.01 µF to 0.1 µF
ceramic capacitor. For 3.0 V to 5.5 V input/output operation, VDDL2 can be connected directly to VDD2.
Data Sheet ADuM3480/ADuM3481/ADuM3482
Rev. A | Page 13 of 20
*PI N 2 AND P IN 10 ARE I NTERNALL Y CONNECTED.
CONNE CTING BO TH T O PCB S IDE 1 GRO UND IS
RECO M M E NDE D. PI N 11 AND P IN 19 ARE
INTERNAL LY CONNECTED. CO NNE CTI NG BO TH
TO PCB SIDE 2 GRO UND IS RE COMM E NDE D.
1
2
3
4
20
19
18
17
516
615
714
912
10 11
813
ADuM3481
TOP VI EW
(No t t o Scal e)
VDDL1
GND1*
VIA
VIB
VIC
VOD
CTRL1
VDD1
VDDC1
GND1*
VDDL2
GND2*
VOA
VOB
VOC
VID
CTRL2
VDD2
VDDC2
GND2*
10459-006
Figure 6. ADuM3481 Pin Configuration
Table 18. ADuM3481 Pin Function Descriptions
Pin No. Mnemonic Description
1 VDDL1 1.8 V to 5.5 V Supply Voltage for Isolator Side 1 Input/Output Circuits. Bypass VDDL1 to GND1 with a 0.01 µF to 0.1 µF
ceramic capacitor. For 3.0 V to 5.5 V input/output operation, VDDL1 can be connected directly to VDD1.
2 GND1 Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 10 are internally connected, and connecting both to
the PCB ground plane as close to the part as possible is recommended.
3 VIA Logic Input A.
4 VIB Logic Input B.
5 VIC Logic Input C.
6 VOD Logic Output D.
7 CTRL1 Select Side 1 Output Default Level. Low = default output low. High = default output high.
8 VDD1 3.0 V to 5.5 V Supply Voltage for Isolator Side 1.
9 VDDC1 Output Pin of an Internal Regulator for Side 1. Bypass VDDC1 to GND1 with a 0.01 µF to 0.1 µF ceramic capacitor. Do
not use this pin to power external circuits.
10 GND1 Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 10 are internally connected, and connecting both to
the PCB ground plane as close to the part as possible is recommended.
11 GND2
Ground 2. Ground reference for Isolator Side 2. Pin 11 and Pin 19 are internally connected, and connecting both to
the PCB ground plane as close to the part as possible is recommended.
12 VDDC2 Output Pin of an Internal Regulator for Side 2. Bypass VDDC2 to GND2 with a 0.01 µF to 0.1 µF ceramic capacitor. Do
not use this pin to power external circuits.
13 VDD2 3.0 V to 5.5 V Supply Voltage for Isolator Side 2.
14 CTRL2 Select Side 2 Output Default Level. Low = default output low. High = default output high.
15 VID Logic Input D.
16 VOC Logic Output C.
17 VOB Logic Output B.
18 VOA Logic Output A.
19 GND2 Ground 2. Ground reference for Isolator Side 2. Pin 11 and Pin 19 are internally connected, and connecting both to
the PCB ground plane as close to the part as possible is recommended.
20 VDDL2 1.8 V to 5.5 V Supply Voltage for Isolator Side 2 Input/Output Circuits. Bypass VDDL2 to GND2 with a 0.01 µF to 0.1 µF
ceramic capacitor. For 3.0 V to 5.5 V input/output operation, VDDL2 can be connected directly to VDD2.
ADuM3480/ADuM3481/ADuM3482 Data Sheet
Rev. A | Page 14 of 20
*PI N 2 AND P IN 10 ARE I NTERNALL Y CONNECTED.
CONNE CTING BO TH T O PCB S IDE 1 GRO UND IS
RECO M M E NDE D. PI N 11 AND P IN 19 ARE
INTERNAL LY CONNECTED. CO NNE CTI NG BO TH
TO PCB SIDE 2 GRO UND IS RE COMM E NDE D.
1
2
3
4
20
19
18
17
516
615
714
912
10 11
813
ADuM3482
TOP VI EW
(No t t o Scal e)
VDDL1
GND1*
VIA
VIB
VOC
VOD
CTRL1
VDD1
VDDC1
GND1*
VDDL2
GND2*
VOA
VOB
VIC
VID
CTRL2
VDD2
VDDC2
GND2*
10459-007
Figure 7. ADuM3482 Pin Configuration
Table 19. ADuM3482 Pin Function Descriptions
Pin No. Mnemonic Description
1 VDDL1 1.8 V to 5.5 V Supply Voltage for Isolator Side 1 Input/Output Circuits. Bypass VDDL1 to GND1 with a 0.01 µF to 0.1 µF
ceramic capacitor. For 3.0 V to 5.5 V input/output operation, VDDL1 can be connected directly to VDD1.
2 GND1 Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 10 are internally connected, and connecting both to
the PCB ground plane as close to the part as possible is recommended.
3 VIA Logic Input A.
4 VIB Logic Input B.
5 VOC Logic Output C.
6 VOD Logic Output D.
7 CTRL1 Select Side 1 Output Default Level. Low = default output low. High = default output high.
8 VDD1 3.0 V to 5.5 V Supply Voltage for Isolator Side 1.
9 VDDC1 Output Pin of Internal Regulator for Side 1. Bypass VDDC1 to GND1 with a 0.01 µF to 0.1 µF ceramic capacitor. Do not
use this pin to power external circuits.
10 GND1 Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 10 are internally connected, and connecting both to
the PCB ground plane as close to the part as possible is recommended.
11 GND2 Ground 2. Ground reference for Isolator Side 2. Pin 11 and Pin 19 are internally connected, and connecting both to
the PCB ground plane as close to the part as possible is recommended.
12 VDDC2 Output Pin of Internal Regulator for Side 2. Bypass VDDC2 to GND2 with a 0.01 µF to 0.1 µF ceramic capacitor. Do not
use this pin to power external circuits.
13 VDD2 3.0 V to 5.5 V Supply Voltage for Isolator Side 2.
14 CTRL2 Select Side 2 Output Default Level. Low = default output low. High = default output high.
15 VID Logic Input D.
16 VIC Logic Input C.
17 VOB Logic Output B.
18
V
OA
Logic Output A.
19 GND2
Ground 2. Ground reference for Isolator Side 2. Pin 11 and Pin 19 are internally connected, and connecting both to
the PCB ground plane as close to the part as possible is recommended.
20 VDDL2 1.8 V to 5.5 V Supply Voltage for Isolator Side 2 Input/Output Circuits. Bypass VDDL2 to GND2 with a 0.01 µF to 0.1 µF
ceramic capacitor. For 3.0 V to 5.5 V input/output operation, VDDL2 can be connected directly to VDD2.
Data Sheet ADuM3480/ADuM3481/ADuM3482
Rev. A | Page 15 of 20
TYPICAL PERFORMANCE CHARACTERISTICS
DATA RATE (M bp s)
I
DDI
CURRENT /CHANNEL ( mA)
0
0
2.5
2.0
1.5
1.0
0.5
51015 2520
10459-008
V
DD
= 5V/V
DDL
= 5V
V
DD
= 5V/V
DDL
= 1.8V
Figure 8. Typical VDDI = 5 V Supply Current per Input Channel vs. Data Rate
for 5 V and 1.8 V I/O Operation
DATA RATE (M bp s)
I
DDI
CURRENT /CHANNE L (mA)
0
0
2.5
2.0
1.5
1.0
0.5
51015 2520
10459-009
V
DD
= 3.3V/V
DDL
= 3.3V
V
DD
= 3.3V/V
DDL
= 1.8V
Figure 9. Typical VDDI = 3.3 V Supply Current per Input Channel vs. Data Rate
for 3.3 V, and 1.8 V I/O Operation
DATA RATE (M bp s)
I
DDO
CURRENT / CHANNE L ( mA)
0
0
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
51015 2520
10459-010
V
DD
= 5V/V
DDL
= 1.8V
V
DD
= 5V/V
DDL
= 5V
Figure 10. Typical VDDO = 5 V Supply Current per Output Channel vs. Data
Rate for 5 V and 1.8 V I/O Operation
DATA RATE (M bp s)
I
DDO
CURRENT / CHANNE L ( mA)
0
0
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
51015 2520
10459-011
V
DD
= 3.3V/V
DDL
= 1.8V
V
DD
= 3.3V/V
DDL
= 3.3V
Figure 11. Typical VDDO = 3.3 V Supply Current per Output Channel vs. Data
Rate for 3.3 V and 1.8 V I/O Operation
DATA RATE (M bp s)
V
DDIL
CURRENT /CHANNE L (mA)
0
0
0.06
0.05
0.04
0.03
0.02
0.01
51015 2520
10459-012
V
DDL
= 5V
V
DDL
= 3.3V
V
DDL
= 1.8V
Figure 12. Typical VDDIL Input Supply Current vs. Data Rate for 5 V, 3.3 V, and
1.8 V Operation
DATA RATE (M bp s)
I
DDOL
CURRENT /CHANNE L (mA)
0
0
0.6
0.5
0.4
0.3
0.2
0.1
51015 2520
10459-013
V
DDL
= 5V
V
DDL
= 1.8V
V
DDL
= 3.3V
Figure 13. Typical VDDOL Output Supply Current vs. Data Rate
for 5 V, 3.3 V, and 1.8 V, CL = 0 pF Operation
ADuM3480/ADuM3481/ADuM3482 Data Sheet
Rev. A | Page 16 of 20
DATA RATE (M bp s)
I
DDOL
CURRENT /CHANNE L (mA)
0
0
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
51015 2520
10459-014
V
DDL
= 5V
V
DDL
= 1.8V
V
DDL
= 3.3V
Figure 14. Typical VDDOL Output Supply Current vs. Data Rate
for 5 V, 3.3 V, and 1.8 V, CL = 15 pF Operation
Data Sheet ADuM3480/ADuM3481/ADuM3482
Rev. A | Page 17 of 20
APPLICATIONS INFORMATION
SUPPLY VOLTAGES
The ADuM3480/ADuM3481/ADuM3482 devices are built
around a fixed voltage internal data transfer core. The core
voltage is 2.7 V, which is generated by regulating the VDD1 and
VDD2 voltages with an internal LDO. To ensure proper headroom
for the LDO, the VDD1 and VDD2 inputs must be in the 3.0 V to 5.5 V
range. Additional pins, VDDC1 and VDDC2, are provided for direct
bypass of the LDO output, ensuring clean stable core operation.
Bypass capacitors to ground of between 0.01 μF and 0.1 μF are
required for each of these supply or dedicated bypass pins.
The ADuM3480/ADuM3481/ADuM3482 provide independent
supplies for the I/O buffers, VDDL1 and VDDL2, which have wider
operating ranges than that required for the core. This allows the
I/O supply voltage to range between 1.8 V and 5.5 V. The VDDLx
supplies must also be bypassed with between 0.01 μF and 0.1 μF
capacitors.
Having independent power supplies for the I/O and core allows
several power configurations depending on the I/O voltage
required and the available power supply rails. If one power
supply is available, the VDDx and VDDLx pins can be connected
together and operate between 3.0 V and 5.5 V. If lower I/O
supply voltage is required, to interface with low voltage logic,
two supply rails are required. For example, if the I/O is 1.8 V
logic, the VDDLx pin can be connected to a 1.8 V supply rail. The
core supply voltage for VDDx requires an input of between 3.0 V and
5.5 V, so an available 3.3 V or 5 V supply rail can be used. The I/O
and core supply voltage on each side are independent and different
configurations can be used on each side of the device.
PRINTED CIRCUIT BOARD LAYOUT
The ADuM3480/ADuM3481/ADuM3482 digital isolator requires
no external interface circuitry for the logic interfaces. Power supply
bypassing to the local ground is required at all four power supply
pins, VDD1, VDDL1, VDD2, and VDDL2, as well as at the two internal
regulator bypass pins: VDDC1 and VDDC2 (see Figure 15). Placement
of the recommended bypass capacitors is shown in Figure 15. The
capacitor value should be between 0.01 μF and 0.1 μF. The total lead
length between both ends of the capacitor and the input power
supply pin should not exceed 20 mm.
V
DDL1
GND
1
V
IA
V
IB
V
IC
/V
OC
V
ID
/V
OD
CTRL
1
V
DD1
V
DDC1
GND
1
V
DDL2
GND
2
V
OA
V
OB
V
OC
/V
IC
V
OD
/V
ID
CTRL
2
V
DD2
V
DDC2
GND
2
10459-016
Figure 15. Recommended Printed Circuit Board (PCB) Layout
In applications involving high common-mode transients, it is
important to minimize board coupling across the isolation barrier.
Furthermore, design the board layout so that any coupling that
does occur equally affects all pins on a given component side.
Failure to follow this design guideline can allow voltage differentials
between pins that exceed the absolute maximum ratings of the
device during high voltage transients, which can lead to latch-up or
permanent damage.
PROPAGATION DELAY RELATED PARAMETERS
Propagation delay is a parameter that describes the time it takes
a logic signal to propagate through a component. The input-to-
output propagation delay time for a high to low transition may
differ from the propagation delay time of a low to high transition.
INPUT (V
Ix
)
OUTPUT (V
Ox
)
t
PLH
t
PHL
50%
50%
10459-017
Figure 16. Propagation Delay Parameters
Pulse width distortion is the maximum difference between
these two propagation delay values and an indication of how
accurately the timing of the input signal is preserved.
Channel to channel matching refers to the maximum amount of
time that the propagation delay differs between channels within
a single ADuM3480/ADuM3481/ADuM3482 component.
Propagation delay skew refers to the maximum amount of time
that the propagation delay differs between multiple ADuM3480/
ADuM3481/ADuM3482 components operating under the same
conditions.
DC CORRECTNESS AND MAGNETIC FIELD
IMMUNITY
Positive and negative logic transitions at the isolator input cause
narrow (~1 ns) pulses to be sent via the transformer to the decoder.
The decoder is bistable and is, therefore, either set or reset by
the pulses indicating input logic transitions. In the absence of
logic transitions at the input for more than ~1.7 μs, the current
dc state is sent to the output to ensure dc correctness at the output.
If the decoder receives no pulses for more than about 5 μs, the
input side is assumed to be unpowered or nonfunctional, in which
case the isolator output is forced to a default state (see Table 17,
Table 18, or Table 19) by the watchdog timer circuit.
ADuM3480/ADuM3481/ADuM3482 Data Sheet
Rev. A | Page 18 of 20
The limitation on the magnetic field immunity of the device is set
by the condition in which induced voltage in the receiving coil
of the transformer is sufficiently large to either falsely set or
reset the decoder. The following analysis defines such conditions.
The ADuM3480/ADuM3481/ADuM3482 are examined in a
3 V operating condition because it represents the most
susceptible mode of operation of these products.
The pulses at the transformer output have an amplitude of
greater than 1.5 V. The decoder has a sensing threshold of
approximately = 1.0 V, thereby establishing a 0.5 V margin
within which induced voltages can be tolerated. The voltage
induced across the receiving coil is given by
V = (−dβ / dt)∑πrn2; n = 1, 2, …, N
where:
β is the magnetic flux density.
rn is the radius of the nth turn in the receiving coil.
N is the number of turns in the receiving coil.
Given the geometry of the receiving coil in the ADuM3480/
ADuM3481/ADuM3482 and an imposed requirement that the
induced voltage be, at most, 50% of the 0.5 V margin at the
decoder, a maximum allowable magnetic field is calculated as
shown in Figure 17.
100
10
1
0.1
0.01
0.0011k 100M10k
MAXIMUM ALLOWABLE MAGNETIC FLUX
DENSI TY ( kgau ss)
100k 1M 10M
MAGNE TI C FI E LD F RE QUENCY ( Hz )
10459-018
Figure 17. Maximum Allowable External Magnetic Flux Density
For example, at a magnetic field frequency of 1 MHz, the
maximum allowable magnetic field of 0.5 kgauss induces a voltage
of 0.25 V at the receiving coil. This is about 50% of the sensing
threshold and does not cause a faulty output transition. If such
an event occurs, with the worst-case polarity, during a transmitted
pulse, it reduces the received pulse from >1.0 V to 0.75 V. This is
still well above the 0.5 V sensing threshold of the decoder.
The preceding magnetic flux density values correspond to
specific current magnitudes at given distances away from the
ADuM3480/ADuM3481/ADuM3482 transformers. Figure 18
expresses these allowable current magnitudes as a function of
frequency for selected distances. The ADuM3480/ADuM3481/
ADuM3482 are very insensitive to external fields. Only extremely
large, high frequency currents that are very close to the component
are a concern. For the 1 MHz example noted, a 1.2 kA current would
need to be placed 5 mm away from the ADuM3480/ADuM3481/
ADuM3482 to affect component operation.
1000
100
10
1
0.1
0.011k 100M10k
MAXI M UM ALL OW ABLE CURRE NT (kA)
100k 1M 10M
MAGNE TI C FI E LD F RE QUENCY ( Hz )
DISTANCE = 5mm
DISTANCE = 1m
DISTANCE = 100mm
10459-019
Figure 18. Maximum Allowable Current for Various Current to ADuM3480
Spacings
Note that at combinations of strong magnetic field and high
frequency, or any loops formed by PCB traces, can induce
sufficiently large error voltages to trigger the thresholds of
succeeding circuitry. Take care to avoid PCB structures that
form loops.
POWER CONSUMPTION
The supply current at a given channel of the ADuM3480/
ADuM3481/ADuM3482 isolator is a function of the supply
voltage, the data rate of the channel, and the output load of the
channel.
Calculating IDD1 or IDD2
For each input channel, assuming worst case I/O voltage, the
supply current is given by
IDDI = IDDI (Q) RD ≤ 2.5 × RR
IDDI = IDDI (D) × (RD−RR) + IDDI (Q) RD > 2.5 × RR
For each output channel, the supply current is given by
IDDO = IDDO (D) × RD + IDDO (Q)
Data Sheet ADuM3480/ADuM3481/ADuM3482
Rev. A | Page 19 of 20
Calculating IDDL1 or IDDL2
For each input channel, the supply current is given by
IDDIL = IDDIL (D) × RD + IDDIL (Q)
For each output channel, the supply current is given by
)(
3
)(
2
10
QDDOLD
DDOLL
DDDOLDDOL
IR
VC
II +
××
+=
−
where:
CL is the output load capacitance (pF).
VDDOL is the output supply voltage (V).
RD is the input logic signal data rate (Mbps); it is twice the input
frequency, expressed in units of MHz.
RR is the input stage refresh rate (Mbps) = 1/tr (µs)
IDDI (Q), IDDIL (Q), IDDO (Q), IDDOL (Q) are the specified input and output
quiescent supply currents (mA).
IDDI (D), IDDIL (D), IDDO (D), and IDDOL(D) are the input and output
dynamic supply currents per channel (mA/Mbps).
As inputs and outputs can be present on each side of the device,
the calculations refer to the current drawn from the local supply.
For example, if an output is on Side 2 of a part, the IDDOL current
is drawn from the VDDL2 pin of the part. The IDDL1 and IDDL2 currents
are dependent on VDDL1 and VDDL2, the data rate, and the capacitive
load. It is nearly independent of the value of the core supplies.
To calculate the total IDD1, IDDL1, IDD2, and IDDL2 supply current, the
supply currents for each input and output channel corresponding to
VDD1, VDDL1, VDD2, and VDDL2 are calculated and totaled, or read from
Figure 8 through Figure 14.
The input current for the regulated core power supplies is
nearly independent of the I/O voltage, and scales with data rate.
The IDDI current is not linear down to dc, but goes to a minimum
value between about 2.5 × RR and dc. This is due to the refresh
circuit establishing a minimum data rate; the values in Figure 8 and
Figure 9 and the quiescent currents in Table 3, Table 6, and Table 9
approximate the current in this region. VDDI, VDDO, VDDIL, and
VDDOL represent the voltages on the core and I/O power supply
pins for the input and output of a given channel. I represents an
input, O is an output, and L denotes an I/O supply.
INSULATION LIFETIME
All insulation structures eventually break down when subjected to
voltage stress over a sufficiently long period. The rate of insulation
degradation depends on the characteristics of the voltage waveform
applied across the insulation. In addition to the testing performed
by the regulatory agencies, Analog Devices carries out an extensive
set of evaluations to determine the lifetime of the insulation
structure within the ADuM3480/ADuM3481/ADuM3482.
Analog Devices performs accelerated life testing using voltage
levels that are higher than the rated continuous working voltage.
Acceleration factors for several operating conditions are determined.
These factors allow calculation of the time to failure at the actual
working voltage. The values shown in Table 16 summarize the
peak voltage for 50 years of service life for a bipolar ac operating
condition and the maximum CSA/VDE approved working voltages.
In many cases, the approved working voltage is higher than the
50-year service life voltage. Operation at these high working
voltages can lead to shortened insulation life in some cases.
The insulation lifetime of the
ADuM3480/ADuM3481/ADuM3482 depends on the voltage
waveform type imposed across the isolation barrier. The iCoupler
insulation structure degrades at different rates depending on
whether the waveform is bipolar ac, unipolar ac, or dc. Figure 19,
Figure 20,and Figure 21 illustrate these different isolation
voltage waveforms.
Bipolar ac voltage is the most stringent environment. The goal
of a 50-year operating lifetime under the ac bipolar condition
determines the maximum working voltage recommended by
Analog Devices.
In the case of unipolar ac or dc voltage, the stress on the insulation
is significantly lower. This allows operation at higher working
voltages while still achieving a 50-year service life. The working
voltages listed in Table 16 can be applied while maintaining the
50-year minimum lifetime, provided that the voltage conforms to
either the unipolar ac or dc voltage case. Treat any cross-insulation
voltage waveform that does not conform to Figure 19, Figure 20,
or Figure 21 as a bipolar ac waveform, and limit its peak voltage
to the 50-year lifetime voltage value listed in Table 16.
Note that the voltage presented in Figure 20 is shown as sinusoidal
for illustration purposes only. It is meant to represent any voltage
waveform varying between 0 V and some limiting value. The limiting
value can be positive or negative, but the voltage cannot cross 0 V.
0V
RATED P E AK V OL TAG E
10459-020
Figure 19. Bipolar AC Waveform
0V
RATED P E AK V OL TAG E
10459-021
Figure 20. Unipolar AC Waveform
0V
RATED P E AK V OL TAG E
10459-023
Figure 21. DC Waveform
ADuM3480/ADuM3481/ADuM3482 Data Sheet
Rev. A | Page 20 of 20
OUTLINE DIMENSIONS
COM PLI ANT TO JEDE C S TANDARDS MO-1 50- AE
060106-A
20 11
10
1
7.50
7.20
6.90
8.20
7.80
7.40
5.60
5.30
5.00
SEATING
PLANE
0.05 MIN
0.65 BS C
2.00 MAX
0.38
0.22
COPLANARITY
0.10
1.85
1.75
1.65
0.25
0.09
0.95
0.75
0.55
8°
4°
0°
Figure 22. 20-Lead Standard Small Outline Package [SSOP]
(RS-20)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
No. of Inputs,
VDD1 Side
No. of Inputs,
VDD2 Side
Maximum
Data Rate
Max Prop
Delay, 5 V
Temperature
Range Package Description
Package
Option
ADuM3480ARSZ 4 0 1 Mbps 90 ns −40°C to +125°C 20-Lead SSOP RS-20
ADuM3480ARSZ-RL7 4 0 1 Mbps 90 ns −40°C to +125°C 20-Lead SSOP, 7” Reel RS-20
ADuM3480BRSZ 4 0 25 Mbps 33 ns −40°C to +125°C 20-Lead SSOP RS-20
ADuM3480BRSZ-RL7 4 0 25 Mbps 33 ns −40°C to +125°C 20-Lead SSOP, 7” Reel RS-20
ADuM3481ARSZ 3 1 1 Mbps 90 ns −40°C to +125°C 20-Lead SSOP RS-20
ADuM3481ARSZ-RL7 3 1 1 Mbps 90 ns −40°C to +125°C 20-Lead SSOP, 7” Reel RS-20
ADuM3481BRSZ 3 1 25 Mbps 33 ns −40°C to +125°C 20-Lead SSOP RS-20
ADuM3481BRSZ-RL7 3 1 25 Mbps 33 ns −40°C to +125°C 20-Lead SSOP, 7” Reel RS-20
EVAL-ADuM3481EBZ Evaluation Board
ADuM3482ARSZ 2 2 1 Mbps 90 ns −40°C to +125°C 20-Lead SSOP RS-20
ADuM3482ARSZ-RL7 2 2 1 Mbps 90 ns −40°C to +125°C 20-Lead SSOP, 7” Reel RS-20
ADuM3482BRSZ 2 2 25 Mbps 33 ns −40°C to +125°C 20-Lead SSOP RS-20
ADuM3482BRSZ-RL7 2 2 25 Mbps 33 ns −40°C to +125°C 20-Lead SSOP, 7” Reel RS-20
1 Z = RoHS Compliant Part.
©2012–2014 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D10459-0-6/14(A)