TBD
MAPBGA–225
15 mm x 15 mm QFN12
##_mm_x_##mm
SOT-343R
##_mm_x_##mm PKG-TBD
## mm x ## mm
257 MAPBGA
(14 x 14 x 0.8 mm)
(20 x 20 x 1.4 mm)
144 LQFP
Freescale Semiconductor
Data Sheet: Advance Information Document Number: MPC5643L
Rev. 9, 6/2013
© Freescale Semiconductor, Inc., 200 9–2013. All rights reserved.
This document contains information on a product under development. Freescale reserves
the right to change or discontinue this product without notice.
MPC5643L
• High-performance e200z4d dual core
— 32-bit Power Architecture® technology CPU
— Core frequency as high as 120 MHz
— Dual issue five-stage pipeline core
— Variable Length Encoding (VLE)
— Memory Management Unit (MMU)
— 4 KB instruction cache with error detection code
— Signal processing engine (SPE)
• Memory available
— 1 MB flash memory with ECC
— 128 KB on-chip SRAM with ECC
— Built-in RWW capabilities for EEPROM emulation
• SIL3/ASILD innovative safety concept: LockStep mode and
Fail-safe protection
— Sphere of replication (SoR) for key components (such as
CPU core, eDMA, crossbar switch)
— Fault collection and control unit (FCCU)
— Redundancy control and checker unit (RCCU) on outputs
of the SoR connected to FCCU
— Boot-time Built-In Self-Test for Memory (MBIST) and
Logic (LBIST) triggered by hardware
— Boot-time Built-In Self-Test for ADC and flash memory
triggered by software
— Replicated safety enhanced watchdog
— Replicated ju nction temperature sensor
— Non-maskable interrupt (NMI)
— 16-region memory protection unit (MPU)
— Clock monitoring units (CMU)
— Power management unit (PMU)
Qorivva MPC5643L
Microcontroller Data Sheet
— Cyclic redundancy check (CRC) unit
• Decoupled Parallel mode for high-perfo rmance use of
replicated cores
• Nexus Class 3+ interface
• Interrupts
— Replicated 16-priority controller
— Replicated 16-channel eDMA controller
• GPIOs individually programmable as input, output or
special function
• Three 6-channel general-purpose eTimer units
• 2 FlexPWM units
— Four 16-bit channels per module
• Communications interfaces
— 2 LINFlexD channels
— 3 DSPI channels with automatic chip selec t
generation
— 2 FlexCAN interfaces (2.0B Active) with 32
message objects
— FlexRay module (V2.1 Rev. A) with 2 channels,
64 message buffers and d ata rates up to 10 Mbit/s
• Two 12-bit analog-to-digital co nverters (ADCs)
— 16 input channels
— Programmable cross triggering unit (CTU) to
synchronize ADCs conversion with timer and
PWM
• Sine wave generator (D/A with low pass filter)
• On-chip CAN/UART bootstrap loader
•Single 3.0 V to 3.6 V voltage supply
• Ambient temperature range –40 °C to 125 °C
• Junction temperature range –40 °C to 150 °C
MPC5643L Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor2
Table of Contents
1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.1 Document overview . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.3 Device comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
1.5 Feature details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
1.5.1 High-performance e200z4d core. . . . . . . . . . . . .7
1.5.2 Crossbar switch (XBAR) . . . . . . . . . . . . . . . . . . .8
1.5.3 Memory Protection Unit (MPU) . . . . . . . . . . . . . .8
1.5.4 Enhanced Direct Memory Access (eDMA) . . . . .8
1.5.5 On-chip flash memory with ECC . . . . . . . . . . . . .9
1.5.6 On-chip SRAM with ECC. . . . . . . . . . . . . . . . . . .9
1.5.7 Platform flash memory controller. . . . . . . . . . . . .9
1.5.8 Platform Static RAM Controller (SRAMC) . . . . .10
1.5.9 Memory subsystem access time . . . . . . . . . . . .10
1.5.10 Error Correction Status Module (ECSM) . . . . . .11
1.5.11 Peripheral bridge (PBRIDGE) . . . . . . . . . . . . . .11
1.5.12 Interrupt Controller (INTC). . . . . . . . . . . . . . . . .11
1.5.13 System clocks and clock generation . . . . . . . . .12
1.5.14 Frequency-Modulated Phase-Locked Loop
(FMPLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
1.5.15 Main oscillator . . . . . . . . . . . . . . . . . . . . . . . . . .13
1.5.16 Internal Reference Clock (RC) oscillator . . . . . .13
1.5.17 Clock, reset, power, mode and test control
modules (MC_CGM, MC_RGM, MC_PCU, and MC_ME)
13
1.5.18 Periodic Interrupt Timer Module (PIT) . . . . . . . .13
1.5.19 System Timer Module (STM). . . . . . . . . . . . . . .13
1.5.20 Software Watchdog Timer (SWT) . . . . . . . . . . .14
1.5.21 Fault Collection and Control Unit (FCCU) . . . . .14
1.5.22 System Integration Unit Lite (SIUL). . . . . . . . . .14
1.5.23 Non-Maskable Interrupt (NMI). . . . . . . . . . . . . .14
1.5.24 Boot Assist Module (BAM). . . . . . . . . . . . . . . . .14
1.5.25 System Status and Configuration Module
(SSCM). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
1.5.26 FlexCAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
1.5.27 FlexRay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
1.5.28 Serial communication interface module
(LINFlexD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
1.5.29 Deserial Serial Peripheral Interface (DSPI). . . .17
1.5.30 FlexPWM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
1.5.31 eTimer module. . . . . . . . . . . . . . . . . . . . . . . . . .18
1.5.32 Sine Wave Generator (SWG) . . . . . . . . . . . . . .19
1.5.33 Analog-to-Digital Converter module (ADC) . . . .19
1.5.34 Cross Triggering Unit (CTU) . . . . . . . . . . . . . . .19
1.5.35 Cyclic Redundancy Checker (CRC) Unit. . . . . .20
1.5.36 Redundancy Control and Checker Unit (RCCU)20
1.5.37 Junction temperature sensor. . . . . . . . . . . . . . .20
1.5.38 Nexus Port Controller (NPC) . . . . . . . . . . . . . . .20
1.5.39 IEEE 1149.1 JTAG Controller (JTAGC) . . . . . . .21
1.5.40 Voltage regulator / Power Management Unit
(PMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
1.5.41 Built-In Self-Test (BIST) capability . . . . . . . . . . 22
2 Package pinouts and signal descriptions . . . . . . . . . . . . . . . 23
2.1 Package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.2 Supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
2.3 System pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
2.4 Pin muxing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
3.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . 76
3.3 Recommended operating conditions. . . . . . . . . . . . . . 77
3.4 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . 78
3.4.1 General notes for specifications at maximum
junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 80
3.5 Electromagnetic Interference (EMI) characteristics. . . 81
3.6 Electrostatic discharge (ESD) characteristics . . . . . . . 82
3.7 Static latch-up (LU) . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
3.8 Voltage regulator electrical characteristics . . . . . . . . . 83
3.9 DC electrical characteristics . . . . . . . . . . . . . . . . . . . . 86
3.10 Supply current characteristics . . . . . . . . . . . . . . . . . . . 87
3.11 Temperature sensor electrical characteristics . . . . . . . 90
3.12 Main oscillator electrical characteristics . . . . . . . . . . . 90
3.13 FMPLL electrical characteristics . . . . . . . . . . . . . . . . . 92
3.14 16 MHz RC oscillator electrical characteristics . . . . . . 94
3.15 ADC electrical characteristics . . . . . . . . . . . . . . . . . . . 94
3.15.1 Input Impedance and ADC Accuracy. . . . . . . . 94
3.16 Flash memory electrical characteristics. . . . . . . . . . . . 99
3.17 SWG electrical characteristics. . . . . . . . . . . . . . . . . . 100
3.18 AC specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
3.18.1 Pad AC specifications . . . . . . . . . . . . . . . . . . 101
3.19 Reset sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
3.19.1 Reset sequence duration . . . . . . . . . . . . . . . . 102
3.19.2 Reset sequence description. . . . . . . . . . . . . . 102
3.19.3 Reset sequence trigger mapping . . . . . . . . . . 105
3.19.4 Reset sequence — start condition . . . . . . . . . 106
3.19.5 External watchdog window. . . . . . . . . . . . . . . 107
3.20 AC timing characteristics. . . . . . . . . . . . . . . . . . . . . . 107
3.20.1 RESET pin characteristics . . . . . . . . . . . . . . . 108
3.20.2 WKUP/NMI timing . . . . . . . . . . . . . . . . . . . . . 109
3.20.3 IEEE 1149.1 JTAG interface timing . . . . . . . . 109
3.20.4 Nexus timing . . . . . . . . . . . . . . . . . . . . . . . . . .111
3.20.5 External interrupt timing (IRQ pin) . . . . . . . . . 114
3.20.6 DSPI timing . . . . . . . . . . . . . . . . . . . . . . . . . . 115
4 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
4.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . 120
5 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
6 Document revision history. . . . . . . . . . . . . . . . . . . . . . . . . . 126
Introduction
MPC5643L Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor 3
1 Introduction
1.1 Document overview
This document describes the features of the family and options available within the family members, and highlights important
electrical and physical characteristics of the devices.
This document provides electrical specifications, pin assignments, and package diagrams for the MPC5643L series of
microcontroller units (MCUs). For functional characteristics, see the MPC5 643L Microcontroller Reference Manual. For use
of the MPC5643Lin a fail-safe system according to safety standard ISO26262, see the Safety Application Guide for MPC5643L.
1.2 Description
The MPC5643L series microcontrollers are system-on-chip devices that are built on Power Architecture technology and contain
enhancements that improve the architecture’s fit in embedded applicati ons, inclu de addit ion al instruction support for digital
signal processing (DSP) and integrate technologies such as an enhanced time processor unit, enhanced queued analog-to-digital
converter, Controller Area Network, and an enhanced modular input-output system.
The MPC5643L family of 32-bit microcontrollers is the latest achievement in integrated automotive application controllers. It
belongs to an expanding range of automotive-focused products designed to address electrical hydraulic power steering (EHPS),
electric power steering (EPS) and airbag applications . The advanced and cost-efficient host processor core of the MPC5643L
automotive controller family complies with the Power Architecture embedded category. It operates at speeds as high as
120 MHz and offers high-performance processing optim ized for low power consumption. It capitalizes on the available
development infrastructure of current Power Architecture devices and is supported with software drivers, operating systems and
configuration code to assist with users’ implementations.
1.3 Device comparison
Table 1. MPC5643L device summary
Feature MPC5643L
CPU Type 2 × e200z4
(in lock-step or decoupled operation)
Architecture Harvard
Execution speed 0–120 MHz (+2% FM)
DMIPS intrinsic performance >240 MIPS
SIMD (DSP + FPU) Yes
MMU 16 entry
Instruction set PPC Yes
Instruction set VLE Yes
Instruction cache 4 KB, EDC
MPU-16 regions Yes, replicated module
Semaphore unit (SEMA4) Yes
Buses Core bus AHB, 32-bit address, 64-bit data
Internal periphery bus 32-bit address, 32-bit data
Crossbar Master × slave ports Lock Step Mode: 4 × 3
Decoupled Parallel Mode: 6 × 3
MPC5643L Microcontroller Data Sheet, Rev. 9
Introduction
Freescale Semiconductor4
Memory Flash 1 MB, ECC, RWW
Static RAM (SRAM) 128 KB, ECC
Modules Interrupt Controller (INTC) 16 interrupt levels, replicated module
Periodic Interrupt Timer (PIT) 1 × 4 channels
System Timer Module (STM) 1 × 4 channels, replicated module
Software Watchdog Timer (SWT) Yes, replicated module
eDMA 16 channels, replicated mo dule
FlexRay 1 × 64 message buffers, dual channel
FlexCAN 2 × 32 message buffers
LINFlexD (UART and LIN with DMA suppo rt) 2
Clock out Yes
Fault Collection and Control Unit (FCCU) Yes
Cross Triggering Unit (CTU) Yes
eTimer 3 × 6 channels1
FlexPWM 2 Module 4 × (2 + 1) channels2
Analog-to-Digital Converter (ADC) 2 × 12-bit ADC, 16 channels per ADC
(3 internal, 4 shared and 9 external)
Sine Wave Generator (SWG) 32 point
Modules
(cont.) Deserial Serial Peripheral Interface (DSPI) 3 × DSPI
as many as 8 chip selects
Cyclic Redundancy Checker (CRC) unit Yes
Junction temperature sensor (TSENS) Yes, replicated module
Digital I/Os 16
Supply Device power supply
3.3 V with integrated bypassable ballast transistor
External ballast transistor not needed for bare die
Analog reference voltage 3.0 V – 3.6 V and 4.5 V – 5.5 V
Clocking Frequency-modulated phase-locked loop (FMPLL) 2
Internal RC oscillator 16 MHz
External crystal oscillator 4 – 40 MHz
Debug Nexus Level 3+
Table 1. MPC5643L dev ice summary (continued)
Feature MPC5643L
Introduction
MPC5643L Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor 5
1.4 Block diagram
Figure 1 shows a top-level block diagram of the MPC5643L device.
Packages LQFP 144 pins
MAPBGA 257 MAPBGA
Temperature Temperature range (junction) –40 to 150 °C
Ambient temperature range using external ball ast
transistor (LQFP) –40 to 125 °C
Ambient temperature range using external ball ast
transistor (BGA) –40 to 125 °C
1The third eT imer (eTimer_2) is available with external I/O access only in the BGA package, on the LQFP p ackage
eTimer_2 is available internally only without any external I/O access.
2The second FlexPWM module is available only in the BGA package.
Table 1. MPC5643L dev ice summary (continued)
Feature MPC5643L
MPC5643L Microcontroller Data Sheet, Rev. 9
Introduction
Freescale Semiconductor6
Figure 1. MPC5643L block diagram
ADC – Analog-to-Digital Converter
BAM – Boot Assist Module
CMU – Clock Monitoring Unit
CRC – Cyclic Redundancy Check unit
CTU – Cross Triggering Unit
DSPI – Serial Peripherals Interface
ECC – Error Correction Code
ECSM – Error Correction Status Module
eDMA – Enhanced Direct Memory Access controller
FCCU – Fault Collection and Control Unit
FlexCAN – Controller Area Network controller
FMPLL – Frequency Modulated Phase Locked Loop
INTC – Interrupt Controller
IRCOSC – Internal RC Oscillator
JTAG – Joint Test Action Group interface
LINFlexD – LIN controller with DMA support
MC – Mode Entry, Clock, Reset, & Power
PBRIDGE – Peripheral bridge
PIT – Periodic Interrupt Timer
PMU – Power Management Unit
RC – Redundancy Checker
RTC – Real Time Clock
SEMA4 – Semaphor e Unit
SIUL – System Integration Unit Lite
SSCM – System Status and Configuration Module
STM – System Timer Module
SWG – Sine Wave Generator
SWT – Software Watchdog Timer
TSENS – Temperature Sensor
XOSC – Crystal Oscillator
SRAM
PMU
SWT
ECSM
STM
INTC
eDMA
Crossbar Switch
VLE
MMU
I-CACHE
SPE
e200z4
VLE
MMU
I-CACHE
SPE
e200z4
Memory Protection Unit Crossbar Switch
Memory Protection Unit
PBRIDGE
JTAG
Nexus
JTAG
Nexus
RC
RC
RC
RC
FlexRay
PBRIDGE
TSENS TSENS
ECC bits
Flash memory
ECC bits + logic
SIUL
MC
WakeUp
ADC
ADC
XOSC
BAM
SSCM
Secondary FMPLL
FMPLL
IRCOSC
CMU
CMU
CTU
PIT
FCCU
FlexPWM
FlexPWM
eTimer
eTimer
eTimer
FlexCAN
FlexCAN
LINFlexD
LINFlexD
DSPI
DSPI
DSPI CRC
CMU
SEMA4
SWT
ECSM
STM
INTC
eDMA
SEMA4
SWG
ECC logic for SRAM ECC logic for SRAM
Introduction
MPC5643L Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor 7
1.5 Feature details
1.5.1 High-performance e200z4d core
The e200z4d Power Architecture® core provides the following features:
• 2 independent execution units, both supporting fixed-point and floating-point operations
• Dual issue 32-bit Power Architecture technology compliant
— 5-stage pipeline (IF, DEC, EX1, EX2, WB)
— In-order execution and instruction retireme nt
• Full supp ort for Power Architecture instruction set and Variable Length Encoding (VLE)
— Mix of classic 32-bit and 16 -bit instruction allowed
— Optimization of code size possib le
• Thirty-two 64-bit general purpose registers (GPRs)
• Harvard bus (32-bit address, 64-bit data)
— I-Bus interface capable of one outstanding transaction plus one piped with no wait-on-data return
— D-Bus interface capable of two transactions outstanding to fill AHB pipe
• I-cache and I-cache controller
— 4 KB, 256-bit cache line (programmable for 2- or 4-way)
• No data cache
• 16-entry MMU
• 8-entry branch table buffer
• Branch look-ahead instruction buffer to accelerate branching
• Dedicated branch address calculator
• 3 cycles worst case for missed branch
• Load/store unit
— Fully pipelined
— Single-cycle load latency
— Big- and little-endian modes supported
— Misaligned access support
— Single stall cycle on load to use
• Single-cycle throughput (2-cycl e latency) integer 32 × 32 multiplication
• 4 – 14 cycles int e ger 32 × 32 division (average division on various benchmark of nine cycles)
• Single precision float ing-point unit
— 1 cycle throughput (2-cycle latency) floating-point 32 × 32 mult iplication
— Target 9 cycles (worst case acceptable is 12 cycles) throughput floating-point 32 × 32 division
— Special square root and min/max function imp lemented
• Signal processing support: APU-SPE 1.1
— Support for vectorized mode: as many as two floating-point instructio ns per clock
• Vectored interrupt support
• Reservat ion instruction to support read-modify -write constructs
• Extensive system development and tracing su pport via Nexus debug port
MPC5643L Microcontroller Data Sheet, Rev. 9
Introduction
Freescale Semiconductor8
1.5.2 Crossbar switch (XBAR)
The XBAR multi-port crossbar switch supports simultaneous connections between four master ports and three slave ports. The
crossbar supports a 32-bit address bus wi dth and a 64-bi t data bus wid th.
The crossbar allows four concurrent transactions to occur from any master port to any slave port, although one of those transfers
must be an instruction fetch from internal flash memory. If a slave port is simultaneously requested by more than one master
port, arbitration logic selects the higher priority master and grants it ownership of the slave port. All other masters requesting
that slave port are stalled until the higher priority master completes its transactio ns.
The crossbar provides the following features:
• 4 masters and 3 slaves supported per each replicated crossbar
— Masters allocation for each crossbar: e200z4d core with two independent bus interface units (BIU) for I and D
access (2 masters), one eDMA, one FlexRay
— Slaves allocation for each crossbar: a redundant flash-memory controller with 2 slave ports to guarantee maximum
flexibility to handle Instruction and Data array, one redundant SRAM controller with 1 slave port each and 1
redundant peripheral bus bridge
• 32-bit address bus and 64-bi t data bus
• Programmable arbitration priority
— Requesting masters can be treated with equal priority and are granted access to a slave port in round-robin method,
based upon the ID of the last master to be granted access or a priority order can be assigned by software at
application run time
• Temporary dy namic priority elevation of masters
The XBAR is replicated for each processing channel.
1.5.3 Memory Protection Unit (MPU)
The Memory Protection Unit splits the physical memory into 16 different regions. Each master (eDMA, FlexRay , CPU) can be
assigned different access rights to each region.
• 16-region MPU with concurrent checks against each master access
• 32-byte granu larity for protected address region
The memory protection unit is replicated for each processing channel.
1.5.4 Enhanced Direct Memory Access (eDMA)
The enhanced direct memory access (eDMA) controller is a second-generation module capable of performing complex data
movements via 16 programmable channels, with minimal intervention from the host processor . The hardware microarchitecture
includes a DMA engine which performs source and destination address calculations, and the actual data movement operations,
along with an SRAM-based memory containing the transfer control descriptors (TCD) for the channels. This implementation
is used to minimize the overall block size.
The eDMA module provides the following features:
• 16 chan nels supporting 8-, 16-, and 32-bit value single or block transfers
• Support variable sized queues and circular buffered queue
• Source and destinati on address registers independently configured to post-increment or stay constan t
• Support major and minor loop offset
• Support minor and major loop done signals
• DMA task in iti ated either by hardware requestor or by software
• Each DMA task can opti onally generate an interrupt at completion and retirement of the task
• Signal to indicate closure of last minor loop
Introduction
MPC5643L Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor 9
• Transfer control descriptors mapped inside the SRAM
The eDMA controller is replicated for each processing channel.
1.5.5 On-chip flash memory with ECC
This device includes programmable, non-volatile flash memory. The non-volatile me mory (NVM) can be used for instruction
storage or data storage, or both. The flash memory module interfaces with the system bus through a dedicated flash memory
array controller. It supports a 64-bit data bus width at the system bus port, and a 128-bit read data interface to flash memory.
The module contains four 128-bit prefetch buffers. Prefetch buffer hits allow no-wait responses. Buffer misses incur a 3 wait
state response at 120 MHz.
The flash memory module provides the following features
• 1 MB of fl ash memory in unique multi-partitioned hard macro
• Sectori zation: 16 KB + 2 × 48 KB + 16 KB + 2 × 64 KB + 2 × 128 KB + 2 × 256 KB
• EEPROM em ulation (in software) within same module but on different partition
• 16 KB test sector and 16 KB shadow block for test, censorship device and user opt ion bits
• Wait states:
— 3 wait states for frequencies =< 120 MHz
— 2 wait states for frequencies =< 80 MHz
— 1 wait state for frequencies =< 60 MHz
• Fla sh mem ory line 128-bit wide with 8-bit ECC on 64-b it word (total 144 bits)
• Accessed via a 64-bit wide bus for write and a 128-bit wide array for read operations
• 1-bit error correction, 2-bit error detection
1.5.6 On-chip SRAM with ECC
The MPC5643L SRAM provides a general-purpose single port memory.
ECC handling is done on a 32-bit boundary for data and it is extended to the address to have th e highest po ssi ble diagnostic
coverage including the array internal address decoder.
The SRAM module provides the following features:
• System SRAM: 128 KB
• ECC on 32-bit word (syndrome of 7 bits)
— ECC covers SRAM bus address
• 1-bit error correction, 2-bit error detection
• Wait states:
— 1 wait state for frequencies =< 120 MHz
— 0 wait states for frequencies =< 80 MHz
1.5.7 Platform flash memory controller
The following list summarizes the key features of the flash memory controller:
• Single AHB port interface supports a 64-bit data bus. All AHB aligned and unaligned reads within the 32-bit container
are supported. Only aligned wo rd writes are supported.
• Array interfaces support a 128-bit read data bus and a 64-bit write data bus for each bank.
• Code flash (bank0) interface provides configurable read buffering and page prefetch support.
— Four page-read buffers (each 128 bits wide) and a prefetch controller support speculative reading and optimized
flash access.
MPC5643L Microcontroller Data Sheet, Rev. 9
Introduction
Freescale Semiconductor10
• Single-cycle read responses (0 AHB data-phase wait states) for hits in the buffers. The buffers implement a
least-recently-used replacement algorithm to maximize performance.
• Programmable response for read-while-write sequences inclu ding support for stall-while-writ e, optional stall
notification interrupt, optional flash operation abort , and optional abort notification interrupt.
• Separate and independent configurable access timing (on a per bank basis) to support use across a wide range of
platforms and frequencies.
• Support of address-based read access timing for emulation of other memory types.
• Su pport for reporting of single- and multi-bit err or events.
• Typical operatin g configuration loaded into programming model by system reset.
The platform flash controller is replicated for each processor.
1.5.8 Platform Static RAM Controller (SRAMC)
The SRAMC module is the platform SRAM array controller, with integrated error detection and correction.
The main features of the SRAMC provide connectivity for the following interfaces:
• XBAR Slave Port (64-bit data path)
• ECSM (ECC Error Reporting, error injection and configuration)
• SRAM array
The following functions are implemented :
• ECC encodi ng (32-bit boundary for data and complete address bus)
• ECC decodi ng (32-bit boundary and entire address)
• Address translation from the AHB protocol on the XBAR to the SRAM array
The platform SRAM controller is replicated for each processor.
1.5.9 Memory subsystem access time
Every memory access the CPU performs requires at least one system clock cycle for the data phase of the access. Slower
memories or peripherals may require additional data phase wait states. Additional data phase wait states may also occur if the
slave being accessed is not parked on the requesting master in the crossbar.
Table 2 shows the number of additional data phase wait states required for a range of memory accesses.
Table 2. Platform memory access time summary
AHB transfer Data phase
wait states Description
e200z4d instruction fetch 0 Flash memory prefetch buffer hit (page hit)
e200z4d instruction fetch 3 Flash memory prefetch buffer miss
(based on 4-cycle random flash array access time)
e200z4d data read 0–1 SRAM read
e200z4d data write 0 SRAM 32-bit write
Introduction
MPC5643L Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor 11
1.5.10 Error Correction Status Module (ECSM)
The ECSM on this device manages the ECC configuration and reporting for the platform memories (flash memory and SRAM).
It does not implement the actual ECC calculation. A detected error (double error for flash memory or SRAM) is also reported
to the FCCU. The following errors and indications are reported into the ECSM dedicated registers:
• ECC error status and configuration for flash memory and SRAM
• ECC error reporting for flash memory
• ECC error reporting for SRAM
• ECC error injection for SRAM
1.5.11 Peripheral bridge (PBRIDGE)
The PBRIDGE implements the following features:
• Duplicated periphery
• Master access privilege level per peripheral (per master: read access enable; write access enable)
• Checker ap plied on PBRIDGE outpu t toward peri phery
• Byte endianess swap capability
1.5.12 Interrupt Controller (INTC)
The INTC provides priority-based preemptive scheduling of interrupt requests, suitable for statically scheduled hard re al-tim e
systems.
For high-priority interrupt requests, the time from the assertion of the interrupt request from the peripheral to when the processor
is executing the interrupt service routine (ISR) has been minimized. The INTC provides a unique vector for each interrupt
request source for quick determination of which ISR needs to be executed. It also provides an ample number of priorities so that
lower priority ISRs do not delay the execution of higher priority ISRs. To allow the appropriate priorities for each source of
interrupt request, the priority of each interrupt request is software configurable.
The INTC supports the priority ceiling protocol for coherent accesses. By providing a modifiable priority mask, the priority can
be raised temporarily so that all tasks which share the resource can not preempt each other.
The INTC provides the following features:
• Duplicated periphery
• Unique 9-bit vector per interrupt source
• 16 priority levels with fixed hardware arbitration within priority levels for each interrupt source
• Priority elevation for shared resource
The INTC is replicated for each processor.
e200z4d data write 0 SRAM 64-bit write (executed as 2 x 32-bit writes)
e200z4d data write 0–2 SRAM 8-,16-bit write
(Read-modify-Write for ECC)
e200z4d flash memory read 0 Flash memory prefetch buffer hit (page hit)
e200z4d flash memory read 3 Flash memory prefetch buffer miss (at 120 MHz; includes 1 cycle
of program flash memory controller arbitration)
Table 2. Platform memory access time summary (continued)
AHB transfer Data phase
wait states Description
MPC5643L Microcontroller Data Sheet, Rev. 9
Introduction
Freescale Semiconductor12
1.5.13 System clocks and clock generation
The following list summarizes the system clock and clock generation on this device:
• Lock status cont inuously monitored by lock detect circuitry
• Loss-of-clo ck (LOC) de tecti on fo r reference and feedback clocks
• On-chip loop filter (for improved electromagnetic interference performance and fewer external components required)
• Programmabl e outpu t clock divider of system clock (1, 2, 4, 8)
• FlexPWM module and as many as three eTimer modules running on an auxiliary clock independent from system clock
(with max frequency 120 MHz)
• On-chip crystal oscillator with automatic level control
• Dedicated internal 16 MHz internal RC oscillator for rapid start-up
— Supports automated frequency trimming by hardware during device startup and by user application
• Auxiliary clock domain for motor control periphery (FlexPWM, eTimer, CTU, ADC, and SWG)
1.5.14 Frequency-Modulated Phase-Locked Loop (FMPLL)
Each device has two FMPLLs.
Each FMPLL allows the user to generate high speed system clocks starting from a minimum reference of 4 MHz input clock.
Further, the FMPLL supports programmable frequency modulation of the system clock. The FMPLL multiplication factor,
output clock divider ratio are all software configurable. The FMPLLs have the following maj or features:
• Input frequency: 4–40 MHz continuous range (limit ed by the cry sta l oscill ator)
• Voltage controlled oscillator (VCO) range: 256–512 MHz
• Frequency modulation via software control to reduce and control emission peaks
— Modulation depth ±2% if centered or 0% to –4% if downshifted via software control register
— Modulation frequency: triangular modulation with 25 kHz nominal rate
• Option to switch modulation on and off via software interface
• Out put divider (ODF) for reduced frequency operation without re-lock
• 3 modes of operation
— Bypass mode
— Normal FMPLL mode with crystal reference (default)
— Normal FMPLL mode with external reference
• Lock monitor circuitry with lock status
• Loss-of-l ock detection for reference and feedback clocks
• Self-clocked mode (SCM) operation
• On-chip loop filter
• Aux ili ary FMPLL
— Used for FlexRay due to precise symbol rate requirem e nt by th e prot ocol
— Used for motor control periphery and connected IP (A/D digital interface CTU) to allow independent frequencies
of operation for PWM and timers and jitter-free control
— Option to enable/disable modulati on to avoid protocol violation on jitter and/or potential unadjusted error in
electric motor control loop
— Allows to run motor control periphery at different (precisely lower, equal or higher as required) frequency than
the system to ensure higher resolution
Introduction
MPC5643L Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor 13
1.5.15 Main oscillator
The main oscillator provides these features:
• Input frequ e ncy rang e 4–40 MHz
• Crystal input mode
• External reference clock (3.3 V) input mode
• FMPLL reference
1.5.16 Internal Reference Clock (RC) oscillator
The architecture uses constant current charging of a capacitor. The voltage at the capacitor is compared to the stable bandgap
reference voltage. The RC oscillator is the device safe clock.
The RC oscillator provides these features:
• Nominal frequency 16 MHz
• ±5% variati on over volt age and temperature after process trim
• Clock output of the RC oscillator serves as system clock source in case loss of lock or loss of clock is detected by the
FMPLL
• RC oscillator is used as the default system clock during startup and can be used as back-up input source of FMPLL(s)
in case XOSC fails
1.5.17 Clock, reset, power, mode and test control modules (MC_CGM,
MC_RGM, MC_PCU, and MC_ME)
These modules provide the following:
• Clock gating and clock distribution contro l
• Halt , stop mode control
• Flexible configurable system and auxiliary clock dividers
• Various execution modes
— HALT and STOP mode as reduced activity low power mode
— Reset, Idle, Test, Safe
— Various RUN modes with software selectable powered modules
— No stand-by mode implemented (no internal switchable power domains)
1.5.18 Periodic Interrupt Timer Module (PIT)
The PIT module implements the following features:
• 4 general purpose interrupt ti mers
• 32-bit counter resolution
• Can be used for so ftware tick or DMA trigger operation
1.5.19 System Timer Module (STM)
The STM implements the following features:
• Up-coun ter wi th 4 output compare registers
• OS task prot ectio n and hardware tick implementation per AUTOSAR1 requirement
1.Automotive Open System Architecture
MPC5643L Microcontroller Data Sheet, Rev. 9
Introduction
Freescale Semiconductor14
The STM is replicated for each processor.
1.5.20 Soft ware Watchdog Timer (SWT)
This module implement s the following features:
• Fault tolerant output
• Safe internal RC oscillator as reference clock
• Windowed watchdog
• Program flow control monitor with 16-bit pseudorandom key generation
• All ows a high level of safety (SIL3 monitor)
The SWT module is replicated for each processor.
1.5.21 Fault Collection and Control Unit (FCCU)
The FCCU module has the following features:
• Redundant collection of hardware checker results
• Redun dant collection of error information and la tch of faults from critical modules on the device
• Col lection of self-test results
• Con figurable and graded fault control
— Internal reactions (no internal reaction, IRQ, Functional Reset, Destructive Reset, or Safe mode entered)
— External reaction (failure is reported to the external/surrounding system via configurable output pins)
1.5.22 System Integration Unit Lite (SIUL)
The SIUL controls MCU reset configuration, pad configuration, external interrupt , general purpose I/O (GPIO), internal
peripheral multiplexing, and system reset operation. The reset configuration block contains the external pin boot configuration
logic. The pad configuration block contro ls the static electrical characteristics of I/O pins. The GPIO block provides uniform
and discrete input/output cont rol of the I/O pins of the MCU.
The SIU provides the following features:
• Centralized pad control on a per-pin basis
— Pin function selection
— Configurable weak pull-up/down
— Configurable slew rate cont rol (slow/medium/fast)
— Hysteresis on GPIO pins
— Configurable automatic safe mode pad control
• Input filtering for external interrupts
1.5.23 Non-Maskable Interrupt (NMI)
The non-maskable interrupt with de-glit chin g filter supports high-priority core exceptions.
1.5.24 Boot Assist Module (BAM)
The BAM is a block of read-only memory with hard-coded content. The BAM program is executed only if serial booting mode
is selected via boot configuration pins.
Introduction
MPC5643L Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor 15
The BAM provides the following features:
• Enables boo ting via serial mode (FlexCAN or LINFlex-UART)
• Supports programmable 64-bit password protection for serial boot mode
• Supports serial bootloading of either Power Architecture code (default) or Freescale VLE code
• Aut om atic switch to serial boot mode if internal flash me mory is blank or invalid
1.5.25 System Status and Configuration Module (SSCM)
The SSCM on this device features the following:
• System configuration and status
• Debu g port st atus and debug port enable
• Multiple boot code starting locations out of reset through implementation of search for valid Reset Configuration Half
Word
• Sets up the MMU to allow user boot code to execute as either Power Architecture code (default) or as Freescale VLE
code out of flash memory
• Triggering of device self-tests during reset phase of device boot
1.5.26 FlexCAN
The FlexCAN module is a communication controller implementing the CAN protocol according to Bosch Specification version
2.0B. The CAN protocol was designed to be used primarily as a vehicle serial data bus, meeting the specific requirements of
this field: real-time processing, reliable operation in the EMI environment of a vehicle, cost-effectiveness and required
bandwidth.
The FlexCAN module provides the following features:
• Full im plementation of the CAN protocol specification, version 2.0B
— Standard data and remote frames
— Extended data and remote frames
— 0 to 8 bytes data length
— Programmable bit rate as fast as 1Mbit/s
• 32 me ssage buffers of 0 to 8 bytes data length
• Each message buffer configurable as receive or transmit buffer, all supporting standard and extended messages
• Programmable loop-back mode supporting self-test operation
• 3 programmable mask registers
• Programmable transmit-first scheme: lowest ID or lowest buffer number
• Time stamp based on 16-bit free-running timer
• Glo bal network time, synchronized by a specific message
• Maskable interrupts
• Independent of the transmission medium (an external transceiver is assumed)
• High immunity to EMI
• Short latency time due to an arbitration schem e for high-priority messages
• Transmit features
— Supports configuration of mul tiple mailboxes to form message queu es of scalable depth
— Arbitration scheme according to message ID or message buffer number
— Internal arbitration to guarantee no inner or outer priority inversion
— Transmit abort procedure and notification
• Receive features
MPC5643L Microcontroller Data Sheet, Rev. 9
Introduction
Freescale Semiconductor16
— Individ ual programmable filters for each mailbox
— 8 mailboxes configurable as a 6-entry receive FIFO
— 8 programmable acceptance filters for receive FIFO
• Programmable clock source
— System clock
— Direct oscillator clock to avoid FMPLL jitter
1.5.27 FlexRay
The FlexRay module provides the following features:
• Full im plementation of FlexRay Protocol Specification 2.1 Rev. A
• 64 config urable message buffers can be handled
• Dual channel or single channel mode of operation, each as fast as 10 Mbit/s data rate
• Message buffers configurable as transmit or receive
• Message buffer size configurable
• Messag e filterin g for all message buffers based on Frame ID, cycle count, and message ID
• Programmable acceptance filters for receive FIFO
• Message buffer header, status, and payload data stored in system memory (SRAM)
• Internal FlexRay memories have error detection and correction
1.5.28 Serial communication interface module (LINFlexD)
The LINFlexD module (LINFlex with DMA support) on this device features the following:
• Suppo rts LIN Master mode, LIN Slave mode and UART mode
• LIN state machine compliant to LIN1.3, 2.0, and 2.1 specifications
• Manages LIN frame transmission and reception without CPU intervention
• LIN features
— Autonomous LIN frame handling
— Message buffer to store as many as 8 data bytes
— Supports messages as long as 64 bytes
— Detection and flagging of LIN errors (Sync field, delimiter , ID parity, bit framing, checksum and T ime-out errors)
— Classic or extended checksum calculation
— Configurable break durati on of up to 50-bit times
— Programmable baud rate prescalers (13-bit mantissa, 4-bit fractional)
— Diagnostic features (Loop back, LIN bus stuck dominant detection)
— Interrupt driven operation with 16 interrupt sources
• LIN slave mode features
— Autonomous LIN header handling
— Autonomous LIN response handling
• UART mode
— Full-duplex operation
— Standard non return-to-zero (NRZ) mark/space format
— Data buffers with 4-byte receive, 4-byte transmit
— Configurable word lengt h (8-bit , 9-bit, 16-bit, or 17-bit words)
— Configurable parity scheme: none, odd, even, always 0
— Speed as fast as 2 Mbit/s
Introduction
MPC5643L Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor 17
— Error detection and flagging (Parity, Noise and Framing errors)
— Interrupt driven operation with four interrupt sources
— Separate transmitter and receiver CPU interrupt sources
— 16-bit programmable baud-rate modulus counter and 16-bit fractional
— Two receiver wake-up methods
• Su pport for DMA enabled transfers
1.5.29 Deserial Serial Peripheral Interface (DSPI)
The DSPI modules provide a synchronous serial interface for communication between the MPC564 3L and external devices.
A DSPI module provides these features:
• Full du plex, synchronous transfers
• Master or slave operation
• Programmabl e master bi t rates
• Programmabl e clock pol arit y and phase
• End-of-transmi ssion interrupt flag
• Programmable transfer baud rate
• Programmable data frames from 4 to 16 bits
• As many as 8 chip select lines available, depending on package and pin multiplex ing
• 4 clock and transfer attributes registers
• Chip select strobe available as alternate function on one of the chip select pins for de-glitching
• FIFOs for buffering as many as 5 transfers on the transmit and receive side
• Queu eing operation possible through use of the eDMA
• General purpose I/O function alit y on pin s wh en not used for SPI
1.5.30 FlexPWM
The pulse width modulator module (FlexPWM) contains four PWM channels, each of which is configured to control a single
half-bridge power stage. T wo modules are included on 257 MAPBGA devices; on the 144 LQFP package, only one module is
present. Additionally, four fault input channels are provided per FlexPWM module.
This PWM is capable of controlling most motor types, including:
• AC inducti on motors (ACIM)
• Permanent Magn et AC motors (PMAC)
• Brushless (BLDC) and brush DC motors (BDC)
• Switched (SRM) and variable reluctance motors (VRM)
• Stepper motors
A FlexPWM module implements the following features:
• 16 bi ts of resol ution for center, edge aligned, and asymmetrical PWMs
• Maximum operating frequency as high as 120 MHz
— Clock source not modulated and independent from system clock (generated via secondary FMPLL)
• Fine gran ularity control for enhanced resolution of the PWM period
• PWM outp uts can operat e as compleme ntary pairs or independent channels
• Ability to accept signed numbers for PWM generation
• Independent control of both edges of each PWM output
• Synchronization to external hardware or other PWM supported
MPC5643L Microcontroller Data Sheet, Rev. 9
Introduction
Freescale Semiconductor18
• Double buffered PWM registers
— Integral reload rates from 1 to 16
— Half cycle reload capability
• Mul tipl e ADC trigger events can be generated per PWM cycle via hardware
• Fault inputs can be assigned to control multiple PW M outputs
• Programmable filters for fault inputs
• Independently pr og rammable PWM outp ut polarity
• Independent top and bottom deadtime insertion
• Each complementary pair can operate with its own PWM frequency and deadtime values
• Individual software control for each PWM output
• All outputs can be forced to a value simultaneously
• PWMX pin can optionally output a third signal from each channel
• Chann els not used fo r PWM generation can be used for buffered output compare functions
• Chann els not used fo r PWM ge nerat ion can be used for input capture functions
• Enhanced dual edge capture functionality
• Option to supply the source for each complementary PWM signal pair from any of the following:
— External digital pin
— Internal timer channel
— External ADC input, taking in to account values set in ADC high- and low-limit registers
• DMA support
1.5.31 eTimer module
The MPC5643L provides three eTimer modules (on the LQFP package eTimer_2 is available internally only without any
external I/O access). Six 16-bit general purpose up/down timer/counters per module are implemented with the following
features:
• Maxim um clock frequency of 120 MHz
• Individual channel capability
— Input capture trigger
— Output compare
— Double buffer (to capture rising edge and falling edge)
— Separate prescaler for each counter
— Selectable clock source
— 0–100% pulse measurement
— Rotation direction flag (Quad decoder mode)
• Maxim um count rate
— Equals peripheral clock divided by 2 for external event count ing
— Equals peripheral clock for internal clock counting
• Cascadeable counters
• Programmable count modulo
• Quadrature decode capabilities
• Counters can share available input pi ns
• Cou nt once or repeatedly
• Preloadable coun ters
• Pins availab le as GPIO when tim er functionality not in use
• DMA support
Introduction
MPC5643L Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor 19
1.5.32 Sine Wave Generator (SWG)
A digital-to-analog converter is available to generate a sine wave based on 32 stored values for external devices (ex: resolver).
1.5.33 Analog-to-Digital Converter module (ADC)
The ADC module features include:
Analog part:
• 2 on-chip ADCs
— 12-bit resolution SAR architecture
— Same digital interface as in the MPC5604P family
— A/D Channels: 9 external , 3 internal and 4 shared with other A/ D (total 16 channels)
— One channel dedicated to each T-sensor to enable temperature reading during application
— Separated reference for each ADC
— Shared analog supply voltage fo r both ADCs
— One sample and hold unit per ADC
— Adjustable sampling and conversion tim e
Digital part:
• 4 analog watchdogs comparing ADC results against predefined levels (low, high, range) before results are stored in
the appropriate ADC result location
• 2 modes of operation: CPU Mode or CTU Mode
• CPU mode features
— Register based interface with the CPU: one result register per channel
— ADC state machine managi ng three request flows: regular command, hardware injected command, software
injected command
— Selectable priority between software and hardware injected commands
— 4 analog watchdogs comparing ADC results against predefined levels (low, high, range)
— DMA compatible interface
• CTU mode features
— Triggered mode only
— 4 independent result queues (1 16 entries, 2 8 entries, 1 4 entries)
— Result alignment circuitry (left justified; right justified)
— 32-bit read mode allows to have channel ID on one of the 16-bit parts
— DMA compatible interfaces
• Built-in self-test features triggered by software
1.5.34 Cross Triggering Unit (CTU)
The ADC cross triggering unit allows automatic generation of ADC con versio n requests on user selected conditions with out
CPU load during the PWM period and with minimized CPU load for dynamic configuration.
The CTU implements the following features:
• Cro ss triggering between ADC, FlexPWM, eTimer, and external pins
• Dou ble buffered trigger generation unit with as many as 8 indep endent trig gers generated from external triggers
• Maxim um operating frequency less than or equal to 120 MHz
• Trigger generation unit configurable in sequential mode or in triggered mode
• Trigger delay unit to compensate the delay of external low pass filter
MPC5643L Microcontroller Data Sheet, Rev. 9
Introduction
Freescale Semiconductor20
• Dou ble buffered global trigger unit allowing eTimer synchronization and/or ADC command gen e rati on
• Dou ble buffered ADC command list point ers to mi nimize ADC-trigger unit update
• Double buffered ADC conversion command list with as many as 24 ADC commands
• Each trigger capable of gen erating consecutive commands
• ADC conversion command allows control of ADC channel from each ADC, single or synchronous sampling,
independent result queue selection
• DMA support with safety features
1.5.35 Cyclic Redundancy Checker (CRC) Unit
The CRC module is a configurable multiple data flow unit to com pute CRC signatures on data written to its input register.
The CRC unit has the following features:
• 3 sets of registers to allow 3 concurrent contexts with possibly different CRC computations, each with a selectable
polynomial and seed
• Com putes 16- or 32-bit wide CRC on the fly (single-cycle computation) and stores resu lt in internal register.
The following standard CRC polynomials are implemented:
—x
8+x4+x3+x2+ 1 [8-bit CRC]
—x
16 +x
12 +x
5+ 1 [16-bit CRC-CCITT]
—x32 +x26 +x23 +x22 +x16 +x12 +x11 +x10 +x8+x7+x5+x4+x2+x+1
[32-bit CRC-ethernet(32)]
• Key engine to be coupled with communication periphery where CRC application is added to allow implementation of
safe communication protocol
• Offloads core from cycle-consuming CRC and helps checking configuration signature for safe start-up or periodic
procedures
• CRC unit connected as peripheral bus on internal peripheral bus
• DMA support
1.5.36 Redundancy Control and Checker Unit (RCCU)
The RCCU checks all outputs of the sphere of replication (addre sses, data, control signals). It has the following features:
• Dup licated module to guarantee highest po ssible diagnostic coverage (check of checker)
• Multiple times replicated IPs are used as checkers on the SoR outputs
1.5.37 Junction temperature sensor
The junction temperature sensor provides a value via an ADC channel that can be used by software to calculate the device
junction temperature.
The key parameters of the junction temp erature sensor include:
• Nominal temperature range from –40 to 150 °C
• Software temperature alarm via analog ADC comparator possible
1.5.38 Nexus Port Controller (NPC)
The NPC module provides real-time developm ent support capabilities for this device in compliance with the IEEE-ISTO
5001-2003. This developm ent support is supplied for MCUs without requiring ext e rnal address and data pins for internal
visibility.
Introduction
MPC5643L Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor 21
The NPC block interfaces to the host processor and internal buses to provide development support as per the IEEE-ISTO
5001-2003 Class 3+, including selected features from Class 4 standard.
The development support provided includes program trace, data trace, watchpoint trace, ownership trace, run-time access to the
MCUs internal memory map and access to the Power Architecture internal registers during halt. The Nexus interface also
supports a JTAG only mode using only the JTAG pins. The following features are implemented:
• Full and reduced port modes
• MCKO (message clock out) pin
• 4 or 12 MDO (message data out) pins1
•2 MSEO (message start/end out) pins
•EVTO
(event out) pin
— Auxiliary input po rt
•EVTI
(event in) pin
• 5-pin JTAG port (JCOMP, TDI, TDO, TMS, and TCK)
— Supports JTAG mode
• Host processor (e200) development support features
— Data trace via data write messaging (DWM) and data read messaging (DRM). This allows the development tool
to trace reads or writes, or both, to selected internal memory resources.
— Ownership trace via ownership trace messaging (OTM). OTM facilitates owne rship trace by providing visibility
of which process ID or operating system task is activated. An ownership trace message is transmitted when a
new process/task is activated, allowing development tools to trace ownership flow.
— Program trace via branch trace messaging (BTM). Branch trace messaging displays program flow discontinuities
(direct branches, indirect branches, exceptions, etc.), allowing the development tool to in terpolate what
transpires between the discontinuities. Thus, static code may be traced.
— Watchpoint messaging (WPM) via the auxiliary port
— Watchpoint trigger enable of program and/or data trace messaging
— Data tracing of instruction fetches via private opcodes
1.5.39 IEEE 1149.1 JTAG Controller (JTAGC)
The JTAGC block provides the means to test chip functionality and connectivity while remaining transparent to system logic
when not in test mode. All data input to and output from the JTAGC block is communicated in serial format. The JTAGC block
is compliant with the IEEE standard.
The JTAG controller provides the following features:
• IEEE Test Access Port (TAP) interface with 5 pins:
—TDI
—TMS
—TCK
—TDO
—JCOMP
• Selectabl e modes of operation include JTAGC/debug or normal system operation
• 5-bit in struction register that supports the following IEEE 1149.1-2001 defined instructions:
—BYPASS
— IDCODE
1. 4 MDO pins on 144 LQFP package, 12 MDO pins on 257 MAPBGA package.
MPC5643L Microcontroller Data Sheet, Rev. 9
Introduction
Freescale Semiconductor22
—EXTEST
—SAMPLE
— SAMPLE/PRELOAD
• 3 test data registers: a bypass register, a boundary scan register, and a device identification register. The size of the
boundary scan register is parameterized to support a variety of boundary scan chain lengths.
• TAP controller state machine that controls the operation of the data registers, instruction register and associated
circuitry
1.5.40 Voltage regulator / Power Management Unit (PMU)
The on-chip voltage regulator module provides the follo wing features:
• Single external rail required
• Singl e high supp ly required: nominal 3.3 V both for packaged and Known Good Die op tio n
— Packaged option requires external ballast transistor due to reduced dissipation capacity at high temperature but
can use embedded transistor if power dissipation is maintained within package dissipation capacity (lower
frequency of operation)
— Known Good Die option uses embedded bal last tran sistor as dissipation capacity is increased to reduce system
cost
• All I/Os are at same voltage as external supply (3.3 V nominal)
• Duplicated Low-Voltage Detectors (LVD) to guarantee proper operation at all stages (reset, configuration, normal
operation) and, to maximize safety coverage, one LVD can be tested while the other operates (on-line self-testing
feature)
1.5.41 Built-In Self-Test (BIST) capability
This device includes the following pro tecti on against latent faults:
• Boot-time Memory Built-In Self-Test (MBIST)
• Boot-time scan-based Logic Built-In Self-Test (LBIST)
• Run -time ADC Built-In Self-Test (BIST)
• Run -ti me Bui lt-In Self Test of LVDs
Package pinouts and signal descriptions
MPC5643L Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor 23
2 Package pinouts and signal descriptions
2.1 Package pinouts
Figure 2 shows the MPC5643L in the 144 LQFP package.
Figure 2. MPC5643L 144 LQFP pinout (top view)
Figure 3 shows the MPC5643L in the 257 MAPBGA package.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
A[4]
VPP_TEST
F[12]
D[14]
G[3]
C[14]
G[2]
C[13]
G[4]
D[12]
G[6]
VDD_HV_FLA
VSS_HV_FLA
VDD_HV_REG_1
VSS_LV_COR
VDD_LV_COR
A[3]
VDD_HV_IO
VSS_HV_IO
B[4]
TCK
TMS
B[5]
G[5]
A[2]
G[7]
C[12]
G[8]
C[11]
G[9]
D[11]
G[10]
D[10]
G[11]
A[1]
A[0]
D[7]
FCCU_F[0]
VDD_LV_COR
VSS_LV_COR
C[1]
E[4]
B[7]
E[5]
C[2]
E[6]
B[8]
E[7]
E[2]
VDD_HV_ADR0
VSS_HV_ADR0
B[9]
B[10]
B[11]
B[12]
VDD_HV_ADR1
VSS_HV_ADR1
VDD_HV_ADV
VSS_HV_ADV
B[13]
E[9]
B[15]
E[10]
B[14]
E[11]
C[0]
E[12]
E[0]
BCTRL
VDD_LV_COR
VSS_LV_COR
VDD_HV_PMU
A[15]
A[14]
C[6]
FCCU_F[1]
D[2]
F[3]
B[6]
VSS_LV_COR
A[13]
VDD_LV_COR
A[9]
F[0]
VSS_LV_COR
VDD_LV_COR
VDD_HV_REG_2
D[4]
D[3]
VSS_HV_IO
VDD_HV_IO
D[0]
C[15]
JCOMP
A[12]
E[15]
A[11]
E[14]
A[10]
E[13]
B[3]
F[14]
B[2]
F[15]
F[13]
C[10]
B[1]
B[0]
144 LQFP package
NMI
A[6]
D[1]
F[4]
F[5]
VDD_HV_IO
VSS_HV_IO
F[6]
MDO0
A[7]
C[4]
A[8]
C[5]
A[5]
C[7]
VDD_HV_REG_0
VSS_LV_COR
VDD_LV_COR
F[7]
F[8]
VDD_HV_IO
VSS_HV_IO
F[9]
F[10]
F[11]
D[9]
VDD_HV_OSC
VSS_HV_OSC
XTAL
EXTAL
RESET
D[8]
D[5]
D[6]
VSS_LV_PLL0_PLL1
VDD_LV_PLL0_PLL1
MPC5643L Microcontroller Data Sheet, Rev. 9
Package pinouts and signal descriptions
Freescale Semiconductor24
Figure 3. MPC5643L 257 MAPBGA pinout (top view)
Table 3 and Table 4 prov ide the pin function summaries for the 144-pin and 257-pin packages, respectively, listing all the
signals multiplexed to each pin.
1234567891011121314151617
A
V
SS_HV
_IO
V
SS_HV
_IO
V
DD_HV
_IO
H[2] H[0] G[14] D[3] C[15] V
DD_HV
_IO
A[12] H[10] H[14] A[10] B[2] C[10] V
SS_HV
_IO
V
SS_HV
_IO
B
V
SS_HV
_IO
V
SS_HV
_IO
B[6] A[14] F[3] A[9] D[4] D[0] V
SS_HV
_IO
H[12] E[15] E[14] B[3] F[13] B[0] V
DD_HV
_IO
V
SS_HV
_IO
C
V
DD_HV
_IO
NC
1
1NC = Not connected (the pin is physical ly not connected to anything on the device)
V
SS_HV
_IO
FCCU_
F[1] D[2] A[13] V
DD_HV
_REG_2
V
DD_HV
_REG_2
I[0] JCOMP H[11] I[1] F[14] B[1] V
SS_HV
_IO
A[4] F[12]
D
F[5] F[4] A[15] C[6] V
SS_LV_
COR
V
DD_LV_
COR
F[0] V
DD_HV
_IO
V
SS_HV
_IO
NC A[11] E[13] F[15] V
DD_HV
_IO
V
PP
_TEST
D[14] G[3]
E
MDO0 F[6] D[1] NMI NC C[14] G[2] I[3]
F
H[1] G[12] A[7] A[8] V
DD_LV_
COR
V
DD_LV_
COR
V
DD_LV_
COR
V
DD_LV_
COR
V
DD_LV_
COR
V
DD_LV_
COR
V
DD_LV_
COR
NC C[13] I[2] G[4]
G
H[3] V
DD_HV
_IO
C[5] A[6] V
DD_LV_
COR
V
SS_LV_
COR
V
SS_LV_
COR
V
SS_LV_
COR
V
SS_LV_
COR
V
SS_LV_
COR
V
DD_LV_
COR
D[12] H[13] H[9] G[6]
H
G[13] V
SS_HV
_IO
C[4] A[5] V
DD_LV
V
SS_LV
V
SS_LV
V
SS_LV
V
SS_LV
V
SS_LV
V
DD_LV
V
SS_LV
V
DD_HV
_REG_1
V
DD_HV
_FLA
H[6]
J
F[7] G[15] V
DD_HV
_REG_0
V
DD_HV
_REG_0
V
DD_LV
V
SS_LV
V
SS_LV
V
SS_LV
V
SS_LV
V
SS_LV
V
DD_LV
V
DD_LV
V
DD_HV
_REG_1
V
SS_HV
_FLA
H[15]
K
F[9] F[8] C[7] V
DD_LV
V
SS_LV
V
SS_LV
V
SS_LV
V
SS_LV
V
SS_LV
V
DD_LV
NC H[8] H[7] A[3]
L
F[10] F[11] D[9] NC V
DD_LV
V
SS_LV
V
SS_LV
V
SS_LV
V
SS_LV
V
SS_LV
V
DD_LV
NC TCK H[4] B[4]
M
V
DD_HV
_OSC
V
DD_HV
_IO
D[8] NC V
DD_LV
V
DD_LV
V
DD_LV
V
DD_LV
V
DD_LV
V
DD_LV
V
DD_LV
C[11] B[5] TMS H[5]
N
XTAL V
SS_HV
_IO
D[5] V
SS_LV_
PLL
NC C[12] A[2] G[5]
P
V
SS_HV
_OSC
RESET D[6] V
DD_LV_
PLL
V
DD_LV_
COR
V
SS_LV_
COR
B[8] NC V
SS_HV
_IO
V
DD_HV
_IO
B[14] V
DD_LV_
COR
V
SS_LV_
COR
V
DD_HV
_IO
G[10] G[8] G[7]
R
EXTAL FCCU
_F[0] V
SS_HV
_IO
D[7] B[7] E[6] V
DD_HV
_ADR0
B[10] V
DD_HV
_ADR1
B[13] B[15] C[0] BCTRL A[1] V
SS_HV
_IO
D[11] G[9]
T
V
SS_HV
_IO
V
DD_HV
_IO
NC C[1] E[5] E[7] V
SS_HV
_ADR0
B[11] V
SS_HV
_ADR1
E[9] E[10] E[12] E[0] A[0] D[10] V
DD_HV
_IO
V
SS_HV
_IO
U
V
SS_HV
_IO
V
SS_HV
_IO
NC E[4] C[2] E[2] B[9] B[12] V
DD_HV
_ADV
V
SS_HV
_ADV
E[11] NC NC V
DD_HV
_PMU
G[11] V
SS_HV
_IO
V
SS_HV
_IO
1234567891011121314151617
Package pinouts and signal descriptions
MPC5643L Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor 25
Table 3. 144 LQFP pin function summary
Pin # Port/function Peripheral Output function Input function
1NMI —
2 A[6] SIUL GPIO[6] GPIO[6]
DSPI_1 SCK SCK
SIUL — EIRQ[6]
3 D[1] SIUL GPIO[49] GPIO[49]
eTimer_1 ETC[2] ETC[2]
CTU_0 EXT_TGR —
FlexRay — CA_RX
4 F[4] SIUL GPIO[84] GPIO[84]
NPC MDO[3] —
5 F[5] SIUL GPIO[85] GPIO[85]
NPC MDO[2] —
6V
DD_HV_IO —
7V
SS_HV_IO —
8 F[6] SIUL GPIO[86] GPIO[86]
NPC MDO[1] —
9MDO0 —
10 A[7] SIUL GPIO[7] GPIO[7]
DSPI_1 SOUT —
SIUL — EIRQ[7]
11 C[4] SIUL GPIO[36] GPIO[36]
DSPI_0 CS0 CS0
FlexPWM_0 X[1] X[1]
SSCM DEBUG[4] —
SIUL — EIRQ[22]
12 A[8] SIUL GPIO[8] GPIO[8]
DSPI_1 — SIN
SIUL — EIRQ[8]
13 C[5] SIUL GPIO[37] GPIO[37]
DSPI_0 SCK SCK
SSCM DEBUG[5] —
FlexPWM_0 — FAULT[3]
SIUL — EIRQ[23]
MPC5643L Microcontroller Data Sheet, Rev. 9
Package pinouts and signal descriptions
Freescale Semiconductor26
14 A[5] SIUL GPIO[5] GPIO[5]
DSPI_1 CS0 CS0
eTimer_1 ETC[5] ETC[5]
DSPI_0 CS7 —
SIUL — EIRQ[5]
15 C[7] SIUL GPIO[39] GPIO[39]
FlexPWM_0 A[1] A[1]
SSCM DEBUG[7] —
DSPI_0 — SIN
16 VDD_HV_REG_0 —
17 VSS_LV_COR —
18 VDD_LV_COR —
19 F[7] SIUL GPIO[87] GPIO[87]
NPC MCKO —
20 F[8] SIUL GPIO[88] GPIO[88]
NPC MSEO[1] —
21 VDD_HV_IO —
22 VSS_HV_IO —
23 F[9] SIUL GPIO[89] GPIO[89]
NPC MSEO[0] —
24 F[10] SIUL GPIO[90] GPIO[90]
NPC EVTO —
25 F[11] SIUL GPIO[91] GPIO[91]
NPC — EVTI
26 D[9] SIUL GPIO[57] GPIO[57]
FlexPWM_0 X[0] X[0]
LINFlexD_1 TXD —
27 VDD_HV_OSC —
28 VSS_HV_OSC —
29 XTAL —
30 EXTAL —
31 RESET —
Table 3. 144 LQFP pin function summary (continued)
Pin # Port/function Peripheral Output function Input function
Package pinouts and signal descriptions
MPC5643L Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor 27
32 D[8] SIUL GPIO[56] GPIO[56]
DSPI_1 CS2 —
eTimer_1 ETC[4] ETC[4]
DSPI_0 CS5 —
FlexPWM_0 — FAULT[3]
33 D[5] SIUL GPIO[53] GPIO[53]
DSPI_0 CS3 —
FlexPWM_0 — FAULT[2]
34 D[6] SIUL GPIO[54] GPIO[54]
DSPI_0 CS2 —
FlexPWM_0 X[3] X[3]
FlexPWM_0 — FAULT[1]
35 VSS_LV_PLL0_PLL1 —
36 VDD_LV_PLL0_PLL1 —
37 D[7] SIUL GPIO[55] GPIO[55]
DSPI_1 CS3 —
DSPI_0 CS4 —
SWG analog output —
38 FCCU_F[0] FCCU F[0] F[0]
39 VDD_LV_COR —
40 VSS_LV_COR —
41 C[1] SIUL — GPIO[33]
ADC_0 — AN[2]
42 E[4] SIUL — GPIO[68]
ADC_0 — AN[7]
43 B[7] SIUL — GPIO[23]
LINFlexD_0 — RXD
ADC_0 — AN[0]
44 E[5] SIUL — GPIO[69]
ADC_0 — AN[8]
45 C[2] SIUL — GPIO[34]
ADC_0 — AN[3]
46 E[6] SIUL — GPIO[70]
ADC_0 — AN[4]
Table 3. 144 LQFP pin function summary (continued)
Pin # Port/function Peripheral Output function Input function
MPC5643L Microcontroller Data Sheet, Rev. 9
Package pinouts and signal descriptions
Freescale Semiconductor28
47 B[8] SIUL — GPIO[24]
eTimer_0 — ETC[5]
ADC_0 — AN[1]
48 E[7] SIUL — GPIO[71]
ADC_0 — AN[6]
49 E[2] SIUL — GPIO[66]
ADC_0 — AN[5]
50 VDD_HV_ADR0 —
51 VSS_HV_ADR0 —
52 B[9] SIUL — GPIO[25]
ADC_0
ADC_1 —AN[11]
53 B[10] SIUL — GPIO[26]
ADC_0
ADC_1 — AN[12]
54 B[11] SIUL — GPIO[27]
ADC_0
ADC_1 — AN[13]
55 B[12] SIUL — GPIO[28]
ADC_0
ADC_1 — AN[14]
56 VDD_HV_ADR1 —
57 VSS_HV_ADR1 —
58 VDD_HV_ADV —
59 VSS_HV_ADV —
60 B[13] SIUL — GPIO[29]
LINFlexD_1 — RXD
ADC_1 — AN[0]
61 E[9] SIUL — GPIO[73]
ADC_1 — AN[7]
62 B[15] SIUL — GPIO[31]
SIUL — EIRQ[20]
ADC_1 — AN[2]
63 E[10] SIUL — GPIO[74]
ADC_1 — AN[8]
Table 3. 144 LQFP pin function summary (continued)
Pin # Port/function Peripheral Output function Input function
Package pinouts and signal descriptions
MPC5643L Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor 29
64 B[14] SIUL — GPIO[30]
eTimer_0 — ETC[4]
SIUL — EIRQ[19]
ADC_1 — AN[1]
65 E[11] SIUL — GPIO[75]
ADC_1 — AN[4]
66 C[0] SIUL — GPIO[32]
ADC_1 — AN[3]
67 E[12] SIUL — GPIO[76]
ADC_1 — AN[6]
68 E[0] SIUL — GPIO[64]
ADC_1 — AN[5]
69 BCTRL —
70 VDD_LV_COR —
71 VSS_LV_COR —
72 VDD_HV_PMU —
73 A[0] SIUL GPIO[0] GPIO[0]
eTimer_0 ETC[0] ETC[0]
DSPI_2 SCK SCK
SIUL — EIRQ[0]
74 A[1] SIUL GPIO[1] GPIO[1]
eTimer_0 ETC[1] ETC[1]
DSPI_2 SOUT —
SIUL — EIRQ[1]
75 G[11] SIUL GPIO[107] GPIO[107]
FlexRay DBG3 —
FlexPWM_0 — FAULT[3]
76 D[10] SIUL GPIO[58] GPIO[58]
FlexPWM_0 A[0] A[0]
eTimer_0 — ETC[0]
77 G[10] SIUL GPIO[106] GPIO[106]
FlexRay DBG2 —
DSPI_2 CS3 —
FlexPWM_0 — FAULT[2]
Table 3. 144 LQFP pin function summary (continued)
Pin # Port/function Peripheral Output function Input function
MPC5643L Microcontroller Data Sheet, Rev. 9
Package pinouts and signal descriptions
Freescale Semiconductor30
78 D[11] SIUL GPIO[59] GPIO[59]
FlexPWM_0 B[0] B[0]
eTimer_0 — ETC[1]
79 G[9] SIUL GPIO[105] GPIO[105]
FlexRay DBG1 —
DSPI_1 CS1 —
FlexPWM_0 — FAULT[1]
SIUL — EIRQ[29]
80 C[11] SIUL GPIO[43] GPIO[43]
eTimer_0 ETC[4] ETC[4]
DSPI_2 CS2 —
81 G[8] SIUL GPIO[104] GPIO[104]
FlexRay DBG0 —
DSPI_0 CS1 —
FlexPWM_0 — FAULT[0]
SIUL — EIRQ[21]
82 C[12] SIUL GPIO[44] GPIO[44]
eTimer_0 ETC[5] ETC[5]
DSPI_2 CS3 —
83 G[7] SIUL GPIO[103] GPIO[103]
FlexPWM_0 B[3] B[3]
84 A[2] SIUL GPIO[2] GPIO[2]
eTimer_0 ETC[2] ETC[2]
FlexPWM_0 A[3] A[3]
DSPI_2 — SIN
MC_RGM — ABS[0]
SIUL — EIRQ[2]
85 G[5] SIUL GPIO[101] GPIO[101]
FlexPWM_0 X[3] X[3]
DSPI_2 CS3 —
86 B[5] SIUL GPIO[21] GPIO[21]
JTAGC — TDI
87 TMS —
88 TCK —
Table 3. 144 LQFP pin function summary (continued)
Pin # Port/function Peripheral Output function Input function
Package pinouts and signal descriptions
MPC5643L Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor 31
89 B[4] SIUL GPIO[20] GPIO[20]
JTAGC TDO —
90 VSS_HV_IO —
91 VDD_HV_IO —
92 A[3] SIUL GPIO[3] GPIO[3]
eTimer_0 ETC[3] ETC[3]
DSPI_2 CS0 CS0
FlexPWM_0 B[3] B[3]
MC_RGM — ABS[2]
SIUL — EIRQ[3]
93 VDD_LV_COR —
94 VSS_LV_COR —
95 VDD_HV_REG_1 —
96 VSS_HV_FLA —
97 VDD_HV_FLA —
98 G[6] SIUL GPIO[102] GPIO[102]
FlexPWM_0 A[3] A[3]
99 D[12] SIUL GPIO[60] GPIO[60]
FlexPWM_0 X[1] X[1]
LINFlexD_1 — RXD
100 G[4] SIUL GPIO[100] GPIO[100]
FlexPWM_0 B[2] B[2]
eTimer_0 — ETC[5]
101 C[13] SIUL GPIO[45] GPIO[45]
eTimer_1 ETC[1] ETC[1]
CTU_0 — EXT_IN
FlexPWM_0 — EXT_SYNC
102 G[2] SIUL GPIO[98] GPIO[98]
FlexPWM_0 X[2] X[2]
DSPI_1 CS1 —
103 C[14] SIUL GPIO[46] GPIO[46]
eTimer_1 ETC[2] ETC[2]
CTU_0 EXT_TGR —
Table 3. 144 LQFP pin function summary (continued)
Pin # Port/function Peripheral Output function Input function
MPC5643L Microcontroller Data Sheet, Rev. 9
Package pinouts and signal descriptions
Freescale Semiconductor32
104 G[3] SIUL GPIO[99] GPIO[99]
FlexPWM_0 A[2] A[2]
eTimer_0 — ETC[4]
105 D[14] SIUL GPIO[62] GPIO[62]
FlexPWM_0 B[1] B[1]
eTimer_0 — ETC[3]
106 F[12] SIUL GPIO[92] GPIO[92]
eTimer_1 ETC[3] ETC[3]
SIUL — EIRQ[30]
107 VPP_TEST1—
108 A[4] SIUL GPIO[4] GPIO[4]
eTimer_1 ETC[0] ETC[0]
DSPI_2 CS1 —
eTimer_0 ETC[4] ETC[4]
MC_RGM — FAB
SIUL — EIRQ[4]
109 B[0] SIUL GPIO[16] GPIO[16]
FlexCAN_0 TXD —
eTimer_1 ETC[2] ETC[2]
SSCM DEBUG[0] —
SIUL — EIRQ[15]
110 B[1] SIUL GPIO[17] GPIO[17]
eTimer_1 ETC[3] ETC[3]
SSCM DEBUG[1] —
FlexCAN_0 — RXD
FlexCAN_1 — RXD
SIUL — EIRQ[16]
111 C[10] SIUL GPIO[42] GPIO[42]
DSPI_2 CS2 —
FlexPWM_0 A[3] A[3]
FlexPWM_0 — FAULT[1]
112 F[13] SIUL GPIO[93] GPIO[93]
eTimer_1 ETC[4] ETC[4]
SIUL — EIRQ[31]
Table 3. 144 LQFP pin function summary (continued)
Pin # Port/function Peripheral Output function Input function
Package pinouts and signal descriptions
MPC5643L Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor 33
113 F[15] SIUL GPIO[95] GPIO[95]
LINFlexD_1 — RXD
114 B[2] SIUL GPIO[18] GPIO[18]
LINFlexD_0 TXD —
SSCM DEBUG[2] —
SIUL — EIRQ[17]
115 F[14] SIUL GPIO[94] GPIO[94]
LINFlexD_1 TXD —
116 B[3] SIUL GPIO[19] GPIO[19]
SSCM DEBUG[3] —
LINFlexD_0 — RXD
117 E[13] SIUL GPIO[77] GPIO[77]
eTimer_0 ETC[5] ETC[5]
DSPI_2 CS3 —
SIUL — EIRQ[25]
118 A[10] SIUL GPIO[10] GPIO[10]
DSPI_2 CS0 CS0
FlexPWM_0 B[0] B[0]
FlexPWM_0 X[2] X[2]
SIUL — EIRQ[9]
119 E[14] SIUL GPIO[78] GPIO[78]
eTimer_1 ETC[5] ETC[5]
SIUL — EIRQ[26]
120 A[11] SIUL GPIO[11] GPIO[11]
DSPI_2 SCK SCK
FlexPWM_0 A[0] A[0]
FlexPWM_0 A[2] A[2]
SIUL — EIRQ[10]
121 E[15] SIUL GPIO[79] GPIO[79]
DSPI_0 CS1 —
SIUL — EIRQ[27]
Table 3. 144 LQFP pin function summary (continued)
Pin # Port/function Peripheral Output function Input function
MPC5643L Microcontroller Data Sheet, Rev. 9
Package pinouts and signal descriptions
Freescale Semiconductor34
122 A[12] SIUL GPIO[12] GPIO[12]
DSPI_2 SOUT —
FlexPWM_0 A[2] A[2]
FlexPWM_0 B[2] B[2]
SIUL — EIRQ[11]
123 JCOMP — — JCOMP
124 C[15] SIUL GPIO[47] GPIO[47]
FlexRay CA_TR_EN —
eTimer_1 ETC[0] ETC[0]
FlexPWM_0 A[1] A[1]
CTU_0 — EXT_IN
FlexPWM_0 — EXT_SYNC
125 D[0] SIUL GPIO[48] GPIO[48]
FlexRay CA_TX —
eTimer_1 ETC[1] ETC[1]
FlexPWM_0 B[1] B[1]
126 VDD_HV_IO —
127 VSS_HV_IO —
128 D[3] SIUL GPIO[51] GPIO[51]
FlexRay CB_TX —
eTimer_1 ETC[4] ETC[4]
FlexPWM_0 A[3] A[3]
129 D[4] SIUL GPIO[52] GPIO[52]
FlexRay CB_TR_EN —
eTimer_1 ETC[5] ETC[5]
FlexPWM_0 B[3] B[3]
130 VDD_HV_REG_2 —
131 VDD_LV_COR —
132 VSS_LV_COR —
133 F[0] SIUL GPIO[80] GPIO[80]
FlexPWM_0 A[1] A[1]
eTimer_0 — ETC[2]
SIUL — EIRQ[28]
Table 3. 144 LQFP pin function summary (continued)
Pin # Port/function Peripheral Output function Input function
Package pinouts and signal descriptions
MPC5643L Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor 35
134 A[9] SIUL GPIO[9] GPIO[9]
DSPI_2 CS1 —
FlexPWM_0 B[3] B[3]
FlexPWM_0 — FAULT[0]
135 VDD_LV_COR —
136 A[13] SIUL GPIO[13] GPIO[13]
FlexPWM_0 B[2] B[2]
DSPI_2 — SIN
FlexPWM_0 — FAULT[0]
SIUL — EIRQ[12]
137 VSS_LV_COR —
138 B[6] SIUL GPIO[22] GPIO[22]
MC_CGM clk_out —
DSPI_2 CS2 —
SIUL — EIRQ[18]
139 F[3] SIUL GPIO[83] GPIO[83]
DSPI_0 CS6 —
140 D[2] SIUL GPIO[50] GPIO[50]
eTimer_1 ETC[3] ETC[3]
FlexPWM_0 X[3] X[3]
FlexRay — CB_RX
141 FCCU_F[1] FCCU F[1] F[1]
142 C[6] SIUL GPIO[38] GPIO[38]
DSPI_0 SOUT —
FlexPWM_0 B[1] B[1]
SSCM DEBUG[6] —
SIUL — EIRQ[24]
143 A[14] SIUL GPIO[14] GPIO[14]
FlexCAN_1 TXD —
eTimer_1 ETC[4] ETC[4]
SIUL — EIRQ[13]
Table 3. 144 LQFP pin function summary (continued)
Pin # Port/function Peripheral Output function Input function
MPC5643L Microcontroller Data Sheet, Rev. 9
Package pinouts and signal descriptions
Freescale Semiconductor36
144 A[15] SIUL GPIO[15] GPIO[15]
eTimer_1 ETC[5] ETC[5]
FlexCAN_1 — RXD
FlexCAN_0 — RXD
SIUL — EIRQ[14]
1VPP_TEST should always be tied to ground (VSS) for normal operations.
Table 4. 257 MAPBGA pin function summary
Pin # Port/function Peripheral Output function Input function
A1 VSS_HV_IO_RING —
A2 VSS_HV_IO_RING —
A3 VDD_HV_IO_RING —
A4 H[2] SIUL GPIO[114] GPIO[114]
NPC MDO[5] —
A5 H[0] SIUL GPIO[112] GPIO[112]
NPC MDO[7] —
A6 G[14] SIUL GPIO[110] GPIO[110]
NPC MDO[9] —
A7 D[3] SIUL GPIO[51] GPIO[51]
FlexRay CB_TX —
eTimer_1 ETC[4] ETC[4]
FlexPWM_0 A[3] A[3]
A8 C[15] SIUL GPIO[47] GPIO[47]
FlexRay CA_TR_EN —
eTimer_1 ETC[0] ETC[0]
FlexPWM_0 A[1] A[1]
CTU_0 — EXT_IN
FlexPWM_0 — EXT_SYNC
A9 VDD_HV_IO_RING —
A10 A[12] SIUL GPIO[12] GPIO[12]
DSPI_2 SOUT —
FlexPWM_0 A[2] A[2]
FlexPWM_0 B[2] B[2]
SIUL — EIRQ[11]
Table 3. 144 LQFP pin function summary (continued)
Pin # Port/function Peripheral Output function Input function
Package pinouts and signal descriptions
MPC5643L Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor 37
A11 H[10] SIUL GPIO[122] GPIO[122]
FlexPWM_1 X[2] X[2]
eTimer_2 ETC[2] ETC[2]
A12 H[14] SIUL GPIO[126] GPIO[126]
FlexPWM_1 A[3] A[3]
eTimer_2 ETC[4] ETC[4]
A13 A[10] SIUL GPIO[10] GPIO[10]
DSPI_2 CS0 CS0
FlexPWM_0 B[0] B[0]
FlexPWM_0 X[2] X[2]
SIUL — EIRQ[9]
A14 B[2] SIUL GPIO[18] GPIO[18]
LINFlexD_0 TXD —
SSCM DEBUG[2] —
SIUL — EIRQ[17]
A15 C[10] SIUL GPIO[42] GPIO[42]
DSPI_2 CS2 —
FlexPWM_0 A[3] A[3]
FlexPWM_0 — FAULT[1]
A16 VSS_HV_IO_RING —
A17 VSS_HV_IO_RING —
B1 VSS_HV_IO_RING —
B2 VSS_HV_IO_RING —
B3 B[6] SIUL GPIO[22] GPIO[22]
MC_CGM clk_out —
DSPI_2 CS2 —
SIUL — EIRQ[18]
B4 A[14] SIUL GPIO[14] GPIO[14]
FlexCAN_1 TXD —
eTimer_1 ETC[4] ETC[4]
SIUL — EIRQ[13]
B5 F[3] SIUL GPIO[83] GPIO[83]
DSPI_0 CS6 —
Table 4. 257 MAPBGA pin function summary (continued)
Pin # Port/function Peripheral Output function Input function
MPC5643L Microcontroller Data Sheet, Rev. 9
Package pinouts and signal descriptions
Freescale Semiconductor38
B6 A[9] SIUL GPIO[9] GPIO[9]
DSPI_2 CS1 —
FlexPWM_0 B[3] B[3]
FlexPWM_0 — FAULT[0]
B7 D[4] SIUL GPIO[52] GPIO[52]
FlexRay CB_TR_EN —
eTimer_1 ETC[5] ETC[5]
FlexPWM_0 B[3] B[3]
B8 D[0] SIUL GPIO[48] GPIO[48]
FlexRay CA_TX —
eTimer_1 ETC[1] ETC[1]
FlexPWM_0 B[1] B[1]
B9 VSS_HV_IO_RING —
B10 H[12] SIUL GPIO[124] GPIO[124]
FlexPWM_1 B[2] B[2]
B11 E[15] SIUL GPIO[79] GPIO[79]
DSPI_0 CS1 —
SIUL — EIRQ[27]
B12 E[14] SIUL GPIO[78] GPIO[78]
eTimer_1 ETC[5] ETC[5]
SIUL — EIRQ[26]
B13 B[3] SIUL GPIO[19] GPIO[19]
SSCM DEBUG[3] —
LINFlexD_0 — RXD
B14 F[13] SIUL GPIO[93] GPIO[93]
eTimer_1 ETC[4] ETC[4]
SIUL — EIRQ[31]
B15 B[0] SIUL GPIO[16] GPIO[16]
FlexCAN_0 TXD —
eTimer_1 ETC[2] ETC[2]
SSCM DEBUG[0] —
SIUL — EIRQ[15]
B16 VDD_HV_IO_RING —
B17 VSS_HV_IO_RING —
C1 VDD_HV_IO_RING —
Table 4. 257 MAPBGA pin function summary (continued)
Pin # Port/function Peripheral Output function Input function
Package pinouts and signal descriptions
MPC5643L Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor 39
C2 Not connected —
C3 VSS_HV_IO_RING —
C4 FCCU_F[1] FCCU F[1] F[1]
C5 D[2] SIUL GPIO[50] GPIO[50]
eTimer_1 ETC[3] ETC[3]
FlexPWM_0 X[3] X[3]
FlexRay — CB_RX
C6 A[13] SIUL GPIO[13] GPIO[13]
FlexPWM_0 B[2] B[2]
DSPI_2 — SIN
FlexPWM_0 — FAULT[0]
SIUL — EIRQ[12]
C7 VDD_HV_REG_2 —
C8 VDD_HV_REG_2 —
C9 I[0] SIUL GPIO[128] GPIO[128]
eTimer_2 ETC[0] ETC[0]
DSPI_0 CS4 —
FlexPWM_1 — FAULT[0]
C10 JCOMP — — JCOMP
C11 H[11] SIUL GPIO[123] GPIO[123]
FlexPWM_1 A[2] A[2]
C12 I[1] SIUL GPIO[129] GPIO[129]
eTimer_2 ETC[1] ETC[1]
DSPI_0 CS5 —
FlexPWM_1 — FAULT[1]
C13 F[14] SIUL GPIO[94] GPIO[94]
LINFlexD_1 TXD —
C14 B[1] SIUL GPIO[17] GPIO[17]
eTimer_1 ETC[3] ETC[3]
SSCM DEBUG[1] —
FlexCAN_0 — RXD
FlexCAN_1 — RXD
SIUL — EIRQ[16]
C15 VSS_HV_IO_RING —
Table 4. 257 MAPBGA pin function summary (continued)
Pin # Port/function Peripheral Output function Input function
MPC5643L Microcontroller Data Sheet, Rev. 9
Package pinouts and signal descriptions
Freescale Semiconductor40
C16 A[4] SIUL GPIO[4] GPIO[4]
eTimer_1 ETC[0] ETC[0]
DSPI_2 CS1 —
eTimer_0 ETC[4] ETC[4]
MC_RGM — FAB
SIUL — EIRQ[4]
C17 F[12] SIUL GPIO[92] GPIO[92]
eTimer_1 ETC[3] ETC[3]
SIUL — EIRQ[30]
D1 F[5] SIUL GPIO[85] GPIO[85]
NPC MDO[2] —
D2 F[4] SIUL GPIO[84] GPIO[84]
NPC MDO[3] —
D3 A[15] SIUL GPIO[15] GPIO[15]
eTimer_1 ETC[5] ETC[5]
FlexCAN_1 — RXD
FlexCAN_0 — RXD
SIUL — EIRQ[14]
D4 C[6] SIUL GPIO[38] GPIO[38]
DSPI_0 SOUT —
FlexPWM_0 B[1] B[1]
SSCM DEBUG[6] —
SIUL — EIRQ[24]
D5 VSS_LV_CORE_RING —
D6 VDD_LV_CORE_RING —
D7 F[0] SIUL GPIO[80] GPIO[80]
FlexPWM_0 A[1] A[1]
eTimer_0 — ETC[2]
SIUL — EIRQ[28]
D8 VDD_HV_IO_RING —
D9 VSS_HV_IO_RING —
D10 Not connected —
Table 4. 257 MAPBGA pin function summary (continued)
Pin # Port/function Peripheral Output function Input function
Package pinouts and signal descriptions
MPC5643L Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor 41
D11 A[11] SIUL GPIO[11] GPIO[11]
DSPI_2 SCK SCK
FlexPWM_0 A[0] A[0]
FlexPWM_0 A[2] A[2]
SIUL — EIRQ[10]
D12 E[13] SIUL GPIO[77] GPIO[77]
eTimer_0 ETC[5] ETC[5]
DSPI_2 CS3 —
SIUL — EIRQ[25]
D13 F[15] SIUL GPIO[95] GPIO[95]
LINFlexD_1 — RXD
D14 VDD_HV_IO_RING —
D15 VPP_TEST1—
D16 D[14] SIUL GPIO[62] GPIO[62]
FlexPWM_0 B[1] B[1]
eTimer_0 — ETC[3]
D17 G[3] SIUL GPIO[99] GPIO[99]
FlexPWM_0 A[2] A[2]
eTimer_0 — ETC[4]
E1 MDO0 —
E2 F[6] SIUL GPIO[86] GPIO[86]
NPC MDO[1] —
E3 D[1] SIUL GPIO[49] GPIO[49]
eTimer_1 ETC[2] ETC[2]
CTU_0 EXT_TGR —
FlexRay — CA_RX
E4 NMI —
E14 Not connected —
E15 C[14] SIUL GPIO[46] GPIO[46]
eTimer_1 ETC[2] ETC[2]
CTU_0 EXT_TGR —
E16 G[2] SIUL GPIO[98] GPIO[98]
FlexPWM_0 X[2] X[2]
DSPI_1 CS1 —
Table 4. 257 MAPBGA pin function summary (continued)
Pin # Port/function Peripheral Output function Input function
MPC5643L Microcontroller Data Sheet, Rev. 9
Package pinouts and signal descriptions
Freescale Semiconductor42
E17 I[3] SIUL GPIO[131] GPIO[131]
eTimer_2 ETC[3] ETC[3]
DSPI_0 CS7 —
CTU_0 EXT_TGR —
FlexPWM_1 — FAULT[3]
F1 H[1] SIUL GPIO[113] GPIO[113]
NPC MDO[6] —
F2 G[12] SIUL GPIO[108] GPIO[108]
NPC MDO[11] —
F3 A[7] SIUL GPIO[7] GPIO[7]
DSPI_1 SOUT —
SIUL — EIRQ[7]
F4 A[8] SIUL GPIO[8] GPIO[8]
DSPI_1 — SIN
SIUL — EIRQ[8]
F6 VDD_LV_CORE_RING —
F7 VDD_LV_CORE_RING —
F8 VDD_LV_CORE_RING —
F9 VDD_LV_CORE_RING —
F10 VDD_LV_CORE_RING —
F11 VDD_LV_CORE_RING —
F12 VDD_LV_CORE_RING —
F14 Not connected —
F15 C[13] SIUL GPIO[45] GPIO[45]
eTimer_1 ETC[1] ETC[1]
CTU_0 — EXT_IN
FlexPWM_0 — EXT_SYNC
F16 I[2] SIUL GPIO[130] GPIO[130]
eTimer_2 ETC[2] ETC[2]
DSPI_0 CS6 —
FlexPWM_1 — FAULT[2]
F17 G[4] SIUL GPIO[100] GPIO[100]
FlexPWM_0 B[2] B[2]
eTimer_0 — ETC[5]
Table 4. 257 MAPBGA pin function summary (continued)
Pin # Port/function Peripheral Output function Input function
Package pinouts and signal descriptions
MPC5643L Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor 43
G1 H[3] SIUL GPIO[115] GPIO[115]
NPC MDO[4] —
G2 VDD_HV_IO_RING —
G3 C[5] SIUL GPIO[37] GPIO[37]
DSPI_0 SCK SCK
SSCM DEBUG[5] —
FlexPWM_0 — FAULT[3]
SIUL — EIRQ[23]
G4 A[6] SIUL GPIO[6] GPIO[6]
DSPI_1 SCK SCK
SIUL — EIRQ[6]
G6 VDD_LV_CORE_RING —
G7 VSS_LV_CORE_RING —
G8 VSS_LV_CORE_RING —
G9 VSS_LV_CORE_RING —
G10 VSS_LV_CORE_RING —
G11 VSS_LV_CORE_RING —
G12 VDD_LV_CORE_RING —
G14 D[12] SIUL GPIO[60] GPIO[60]
FlexPWM_0 X[1] X[1]
LINFlexD_1 — RXD
G15 H[13] SIUL GPIO[125] GPIO[125]
FlexPWM_1 X[3] X[3]
eTimer_2 ETC[3] ETC[3]
G16 H[9] SIUL GPIO[121] GPIO[121]
FlexPWM_1 B[1] B[1]
DSPI_0 CS7 —
G17 G[6] SIUL GPIO[102] GPIO[102]
FlexPWM_0 A[3] A[3]
H1 G[13] SIUL GPIO[109] GPIO[109]
NPC MDO[10] —
H2 VSS_HV_IO_RING —
Table 4. 257 MAPBGA pin function summary (continued)
Pin # Port/function Peripheral Output function Input function
MPC5643L Microcontroller Data Sheet, Rev. 9
Package pinouts and signal descriptions
Freescale Semiconductor44
H3 C[4] SIUL GPIO[36] GPIO[36]
DSPI_0 CS0 CS0
FlexPWM_0 X[1] X[1]
SSCM DEBUG[4] —
SIUL — EIRQ[22]
H4 A[5] SIUL GPIO[5] GPIO[5]
DSPI_1 CS0 CS0
eTimer_1 ETC[5] ETC[5]
DSPI_0 CS7 —
SIUL — EIRQ[5]
H6 VDD_LV —
H7 VSS_LV —
H8 VSS_LV —
H9 VSS_LV —
H10 VSS_LV —
H11 VSS_LV —
H12 VDD_LV —
H14 VSS_LV —
H15 VDD_HV_REG_1 —
H16 VDD_HV_FLA —
H17 H[6] SIUL GPIO[118] GPIO[118]
FlexPWM_1 B[0] B[0]
DSPI_0 CS5 —
J1 F[7] SIUL GPIO[87] GPIO[87]
NPC MCKO —
J2 G[15] SIUL GPIO[111] GPIO[111]
NPC MDO[8] —
J3 VDD_HV_REG_0 —
J4 VDD_HV_REG_0 —
J6 VDD_LV —
J7 VSS_LV —
J8 VSS_LV —
J9 VSS_LV —
J10 VSS_LV —
J11 VSS_LV —
Table 4. 257 MAPBGA pin function summary (continued)
Pin # Port/function Peripheral Output function Input function
Package pinouts and signal descriptions
MPC5643L Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor 45
J12 VDD_LV —
J14 VDD_LV —
J15 VDD_HV_REG_1 —
J16 VSS_HV_FLA —
J17 H[15] SIUL GPIO[127] GPIO[127]
FlexPWM_1 B[3] B[3]
eTimer_2 ETC[5] ETC[5]
K1 F[9] SIUL GPIO[89] GPIO[89]
NPC MSEO[0] —
K2 F[8] SIUL GPIO[88] GPIO[88]
NPC MSEO[1] —
K3 RDY NPC RDY —
SIUL GPIO[132] GPIO[132]
K4 C[7] SIUL GPIO[39] GPIO[39]
FlexPWM_0 A[1] A[1]
SSCM DEBUG[7] —
DSPI_0 — SIN
K6 VDD_LV —
K7 VSS_LV —
K8 VSS_LV —
K9 VSS_LV —
K10 VSS_LV —
K11 VSS_LV —
K12 VDD_LV —
K14 Not connected —
K15 H[8] SIUL GPIO[120] GPIO[120]
FlexPWM_1 A[1] A[1]
DSPI_0 CS6 —
K16 H[7] SIUL GPIO[119] GPIO[119]
FlexPWM_1 X[1] X[1]
eTimer_2 ETC[1] ETC[1]
Table 4. 257 MAPBGA pin function summary (continued)
Pin # Port/function Peripheral Output function Input function
MPC5643L Microcontroller Data Sheet, Rev. 9
Package pinouts and signal descriptions
Freescale Semiconductor46
K17 A[3] SIUL GPIO[3] GPIO[3]
eTimer_0 ETC[3] ETC[3]
DSPI_2 CS0 CS0
FlexPWM_0 B[3] B[3]
MC_RGM — ABS[2]
SIUL — EIRQ[3]
L1 F[10] SIUL GPIO[90] GPIO[90]
NPC EVTO —
L2 F[11] SIUL GPIO[91] GPIO[91]
NPC — EVTI
L3 D[9] SIUL GPIO[57] GPIO[57]
FlexPWM_0 X[0] X[0]
LINFlexD_1 TXD —
L4 Not connected —
L6 VDD_LV —
L7 VSS_LV —
L8 VSS_LV —
L9 VSS_LV —
L10 VSS_LV —
L11 VSS_LV —
L12 VDD_LV —
L14 Not connected —
L15 TCK —
L16 H[4] SIUL GPIO[116] GPIO[116]
FlexPWM_1 X[0] X[0]
eTimer_2 ETC[0] ETC[0]
L17 B[4] SIUL GPIO[20] GPIO[20]
JTAGC TDO —
M1 VDD_HV_OSC —
M2 VDD_HV_IO_RING —
M3 D[8] SIUL GPIO[56] GPIO[56]
DSPI_1 CS2 —
eTimer_1 ETC[4] ETC[4]
DSPI_0 CS5 —
FlexPWM_0 — FAULT[3]
Table 4. 257 MAPBGA pin function summary (continued)
Pin # Port/function Peripheral Output function Input function
Package pinouts and signal descriptions
MPC5643L Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor 47
M4 Not connected —
M6 VDD_LV —
M7 VDD_LV —
M8 VDD_LV —
M9 VDD_LV —
M10 VDD_LV —
M11 VDD_LV —
M12 VDD_LV —
M14 C[11] SIUL GPIO[43] GPIO[43]
eTimer_0 ETC[4] ETC[4]
DSPI_2 CS2 —
M15 B[5] SIUL GPIO[21] GPIO[21]
JTAGC — TDI
M16 TMS —
M17 H[5] SIUL GPIO[117] GPIO[117]
FlexPWM_1 A[0] A[0]
DSPI_0 CS4 —
N1 XTAL —
N2 VSS_HV_IO_RING —
N3 D[5] SIUL GPIO[53] GPIO[53]
DSPI_0 CS3 —
FlexPWM_0 — FAULT[2]
N4 VSS_LV_PLL0_PLL1 —
N14 Not connected —
N15 C[12] SIUL GPIO[44] GPIO[44]
eTimer_0 ETC[5] ETC[5]
DSPI_2 CS3 —
N16 A[2] SIUL GPIO[2] GPIO[2]
eTimer_0 ETC[2] ETC[2]
FlexPWM_0 A[3] A[3]
DSPI_2 — SIN
MC_RGM — ABS[0]
SIUL — EIRQ[2]
Table 4. 257 MAPBGA pin function summary (continued)
Pin # Port/function Peripheral Output function Input function
MPC5643L Microcontroller Data Sheet, Rev. 9
Package pinouts and signal descriptions
Freescale Semiconductor48
N17 G[5] SIUL GPIO[101] GPIO[101]
FlexPWM_0 X[3] X[3]
DSPI_2 CS3 —
P1 VSS_HV_OSC —
P2 RESET —
P3 D[6] SIUL GPIO[54] GPIO[54]
DSPI_0 CS2 —
FlexPWM_0 X[3] X[3]
FlexPWM_0 — FAULT[1]
P4 VDD_LV_PLL0_PLL1 —
P5 VDD_LV_CORE_RING —
P6 VSS_LV_CORE_RING —
P7 B[8] SIUL — GPIO[24]
eTimer_0 — ETC[5]
ADC_0 — AN[1]
P8 Not connected —
P9 VSS_HV_IO_RING —
P10 VDD_HV_IO_RING —
P11 B[14] SIUL — GPIO[30]
eTimer_0 — ETC[4]
SIUL — EIRQ[19]
ADC_1 — AN[1]
P12 VDD_LV_CORE_RING —
P13 VSS_LV_CORE_RING —
P14 VDD_HV_IO_RING —
P15 G[10] SIUL GPIO[106] GPIO[106]
FlexRay DBG2 —
DSPI_2 CS3 —
FlexPWM_0 — FAULT[2]
P16 G[8] SIUL GPIO[104] GPIO[104]
FlexRay DBG0 —
DSPI_0 CS1 —
FlexPWM_0 — FAULT[0]
SIUL — EIRQ[21]
Table 4. 257 MAPBGA pin function summary (continued)
Pin # Port/function Peripheral Output function Input function
Package pinouts and signal descriptions
MPC5643L Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor 49
P17 G[7] SIUL GPIO[103] GPIO[103]
FlexPWM_0 B[3] B[3]
R1 EXTAL —
R2 FCCU_F[0] FCCU F[0] F[0]
R3 VSS_HV_IO_RING —
R4 D[7] SIUL GPIO[55] GPIO[55]
DSPI_1 CS3 —
DSPI_0 CS4 —
SWG analog output —
R5 B[7] SIUL — GPIO[23]
LINFlexD_0 — RXD
ADC_0 — AN[0]
R6 E[6] SIUL — GPIO[70]
ADC_0 — AN[4]
R7 VDD_HV_ADR0 —
R8 B[10] SIUL — GPIO[26]
ADC_0
ADC_1 — AN[12]
R9 VDD_HV_ADR1 —
R10 B[13] SIUL — GPIO[29]
LINFlexD_1 — RXD
ADC_1 — AN[0]
R11 B[15] SIUL — GPIO[31]
SIUL — EIRQ[20]
ADC_1 — AN[2]
R12 C[0] SIUL — GPIO[32]
ADC_1 — AN[3]
R13 BCTRL —
R14 A[1] SIUL GPIO[1] GPIO[1]
eTimer_0 ETC[1] ETC[1]
DSPI_2 SOUT —
SIUL — EIRQ[1]
R15 VSS_HV_IO_RING —
Table 4. 257 MAPBGA pin function summary (continued)
Pin # Port/function Peripheral Output function Input function
MPC5643L Microcontroller Data Sheet, Rev. 9
Package pinouts and signal descriptions
Freescale Semiconductor50
R16 D[11] SIUL GPIO[59] GPIO[59]
FlexPWM_0 B[0] B[0]
eTimer_0 — ETC[1]
R17 G[9] SIUL GPIO[105] GPIO[105]
FlexRay DBG1 —
DSPI_1 CS1 —
FlexPWM_0 — FAULT[1]
SIUL — EIRQ[29]
T1 VSS_HV_IO_RING —
T2 VDD_HV_IO_RING —
T3 Not connected —
T4 C[1] SIUL — GPIO[33]
ADC_0 — AN[2]
T5 E[5] SIUL — GPIO[69]
ADC_0 — AN[8]
T6 E[7] SIUL — GPIO[71]
ADC_0 — AN[6]
T7 VSS_HV_ADR0 —
T8 B[11] SIUL — GPIO[27]
ADC_0
ADC_1 — AN[13]
T9 VSS_HV_ADR1 —
T10 E[9] SIUL — GPIO[73]
ADC_1 — AN[7]
T11 E[10] SIUL — GPIO[74]
ADC_1 — AN[8]
T12 E[12] SIUL — GPIO[76]
ADC_1 — AN[6]
T13 E[0] SIUL — GPIO[64]
ADC_1 — AN[5]
T14 A[0] SIUL GPIO[0] GPIO[0]
eTimer_0 ETC[0] ETC[0]
DSPI_2 SCK SCK
SIUL — EIRQ[0]
Table 4. 257 MAPBGA pin function summary (continued)
Pin # Port/function Peripheral Output function Input function
Package pinouts and signal descriptions
MPC5643L Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor 51
T15 D[10] SIUL GPIO[58] GPIO[58]
FlexPWM_0 A[0] A[0]
eTimer_0 — ETC[0]
T16 VDD_HV_IO_RING —
T17 VSS_HV_IO_RING —
U1 VSS_HV_IO_RING —
U2 VSS_HV_IO_RING —
U3 Not connected —
U4 E[4] SIUL — GPIO[68]
ADC_0 — AN[7]
U5 C[2] SIUL — GPIO[34]
ADC_0 — AN[3]
U6 E[2] SIUL — GPIO[66]
ADC_0 — AN[5]
U7 B[9] SIUL — GPIO[25]
ADC_0
ADC_1 —AN[11]
U8 B[12] SIUL — GPIO[28]
ADC_0
ADC_1 — AN[14]
U9 VDD_HV_ADV —
U10 VSS_HV_ADV —
U11 E[11] SIUL — GPIO[75]
ADC_1 — AN[4]
U12 Not connected —
U13 Not connected —
U14 VDD_HV_PMU —
U15 G[11] SIUL GPIO[107] GPIO[107]
FlexRay DBG3 —
FlexPWM_0 — FAULT[3]
U16 VSS_HV_IO_RING —
U17 VSS_HV_IO_RING —
1VPP_TEST should always be tied to ground (VSS) for normal operations.
Table 4. 257 MAPBGA pin function summary (continued)
Pin # Port/function Peripheral Output function Input function
MPC5643L Microcontroller Data Sheet, Rev. 9
Package pinouts and signal descriptions
Freescale Semiconductor52
2.2 Supply pins
Table 5. Supply pins
Supply Pin #
Symbol Description 144
pkg 257
pkg
VREG control and power supply pins
BCTRL Voltage regulator external NPN ballast base control pin 69 R13
VDD_LV_COR C ore logic supply 70 VDD_LV1
VSS_LV_COR Core regulator ground 71 VSS_LV2
VDD_HV_PMU Voltage regulator supply 72 U14
ADC_0/ADC_1 reference voltage and ADC supply
VDD_HV_ADR0 ADC_0 high reference voltage 50 R7
VSS_HV_ADR0 ADC_0 low reference voltage 51 T7
VDD_HV_ADR1 ADC_1 high reference voltage 56 R9
VSS_HV_ADR1 ADC_1 low reference voltage 57 T9
VDD_HV_ADV ADC voltage supply for ADC_0 and ADC_1 58 U9
VSS_HV_ADV ADC ground for ADC_0 and ADC_1 59 U10
Power supply pins (3.3 V)
VDD_HV_IO 3.3 V Input/Output supply voltage 6 VDD_HV3
VSS_HV_IO 3.3 V Input/Output ground 7 VSS_HV4
VDD_HV_REG_0 VDD_HV_REG_0 16 J3
VDD_HV_IO 3.3 V Input/Output supply voltage 21 VDD_HV3
VSS_HV_IO 3.3 V Input/Output ground 22 VSS_HV4
VDD_HV_OSC Crystal oscillator amplifier supply voltage 27 M1
VSS_HV_OSC Crystal oscillator amplifier ground 28 P1
VSS_HV_IO 3.3 V Input/Output ground 90 VSS_HV4
VDD_HV_IO 3.3 V Input/Output supply voltage 91 VDD_HV3
VDD_HV_REG_1 VDD_HV_REG_1 95 H15
VSS_HV_FLA VSS_HV_FLA 96 J16
VDD_HV_FLA VDD_HV_FLA 97 H16
VDD_HV_IO VDD_HV_IO 126 VDD_HV3
VSS_HV_IO VSS_HV_IO 127 VSS_HV4
VDD_HV_REG_2 VDD_HV_REG_2 130 C7
Power supply pins (1.2 V)
Package pinouts and signal descriptions
MPC5643L Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor 53
VSS_LV_COR VSS_LV_COR
Decoupling pins for core logic. Decoupling capacitor must be connected
between these pins and the nearest VDD_LV_COR pin.
17 VSS_HV2
VDD_LV_COR VDD_LV_COR
Decoupling pins for core logic. Decoupling capacitor must be connected
between these pins and the nearest VSS_LV_COR pin.
18 VDD_LV1
VSS 1V2 VSS_LV_PLL0_PLL1 /
1.2 V Decoupling pins for on-chip FMPLL modules. Decoupling capacitor
must be connected between this pin and V DD_LV_PLL.
35 N4
VDD 1V2 VDD_LV_PLL0_PLL1
Decoupling pins for on-chip FMPLL modules. Decoupling cap acitor must
be connected between this pin and VSS_LV_PLL.
36 P4
VDD_LV_COR VDD_LV_COR
Decoupling pins for core logic. Decoupling capacitor must be connected
between these pins and the nearest VSS_LV_COR pin.
39 VDD_LV1
VSS_LV_COR VSS_LV_COR
Decoupling pins for core logic. Decoupling capacitor must be connected
between these pins and the nearest VDD_LV_COR pin.
40 VSS_LV2
VDD_LV_COR VDD_LV_COR
Decoupling pins for core lo gic and Regulator feedback. Decoupling
capacitor must be connected between this pins and VSS_LV_REGCOR.
70 VDD_LV1
VSS_LV_COR VSS_LV_REGCOR0
Decoupling pins for core lo gic and Regulator feedback. Decoupling
capacitor must be connected between this pins and VDD_LV_REGCOR.
71 VSS_LV2
VDD_LV_COR VDD_LV_COR
Decoupling pins for core logic. Decoupling capacitor must be connected
between these pins and the nearest VSS_LV_COR pin.
93 VDD_LV1
VSS_LV_COR VSS_LV_COR
/ 1.2 V Decoupling pins for core logic. Decoupl ing capacitor must be
connected between these pins and the nea rest VDD_LV_COR pin.
94 VSS_LV2
VDD 1V2 VDD_LV_COR
Decoupling pins for core logic. Decoupling capacitor must be connected
between these pins and the nearest VDD_LV_COR pin.
131 VDD_LV1
VSS 1V2 VSS_LV_COR
Decoupling pins for core logic. Decoupling capacitor must be connected
between these pins and the nearest VDD_LV_COR pin.
132 VSS_LV2
VDD 1V2 VDD_LV_COR /
Decoupling pins for core logic. Decoupling capacitor must be connected
between these pins and the nearest VDD_LV_COR pin.
135 VDD_LV1
VSS 1V2 VSS_LV_COR /
Decoupling pins for core logic. Decoupling capacitor must be connected
between these pins and the nearest VDD_LV_COR pin.
137 VSS_LV2
1VDD_LV balls are tied together on the 257 MAPBGA substrate.
Table 5. Supply pins (continued)
Supply Pin #
Symbol Description 144
pkg 257
pkg
MPC5643L Microcontroller Data Sheet, Rev. 9
Package pinouts and signal descriptions
Freescale Semiconductor54
2.3 System pins
NOTE
None of system pins (except RESET) provides an open drain output.
2VSS_LV balls are tied together on the 257 MAPBGA substrate.
3VDD_HV balls are tied together on the 257 MAPBGA substrate.
4VSS_HV balls are tied together on the 257 MAPBGA substrate.
Table 6. System pins
Symbol Description Direction
Pin #
144
pkg 257
pkg
Dedicated pins
MDO01
1This pad is configured for Fast (F) pad speed.
Nexus Message Data Output — line Output only 9 E1
NMI2
2This pad contains a weak pull-up.
Non Maskable Interrupt Input only 1 E4
XTAL Input for oscillator amplifier circuit and internal clock generator Input only 29 N1
EXTAL
3
3EXTAL is an "Output" in "crystal" mode, and is an "Input" in "ext clock" mode.
Oscillator amplifier output Input/Output4
4In XOSC Bypass Mode, the analog portion of crystal oscillator (amplifier) is disabled. An external clock can be applied
at EXTAL as an input. In XOSC Normal Mode, EXTAL is an output
30 R1
TMS2JTAG state machine control Input only 87 M16
TCK2JTAG clock Input only 88 L15
JCOMP5
5This pad contains a weak pull-down.
JTAG compliance select Input only 123 C10
Reset pin
RESET
Bidirectional reset with Schmitt-Trigger characteristics and noise filter .
This pin has medium drive strength. Output drive is open drain and
must be terminated by an external resistor of value 1KOhm.
6
6RESET output shall be considered valid only after the 3.3V supply reaches its stable value.
Bidirectional
31 P2
Test pin
VPP TEST
Pin for testing purpose only. To be tied to ground in normal
operating mode. 107 D15
Package pinouts and signal descriptions
MPC5643L Microcon troller Data Sheet, Rev. 9
Freescale Semiconductor 55
2.4 Pin muxing
Table 7 defines the pin list and muxing for this device.
Each entry of Table 7 shows all the possible configurations for each pin, via the alternate functions. The default function assigned to each pin after reset is
indicated by ALT0.
NOTE
Pins labeled “NC” are to be left unconn ected. Any connection to an external circuit or voltage may cause unpredictable
device behavior or damage.
Pins labeled “Reserved” are to be tied to ground. Not doing so may cause unpredictable device behavior.
Table 7. Pin muxing
Port
name PCR Peripheral Alternate
output
function
Output
mux sel Input
functions Input mux
select
Weak pull
config during
reset
Pad speed1Pin #
SRC
=1 SRC
=0 144
pkg 257
pkg
Port A
A[0] PCR[0] SIUL GPIO[0] ALT0 GPIO[0] — — M S 73 T14
eTimer_0 ETC[0] ALT1 ETC[0] PSMI[35];
PADSEL=0
DSPI_2 SCK ALT2 SCK PSMI[1];
PADSEL=0
SIUL — — EIRQ[0] —
A[1] PCR[1] SIUL GPIO[1] ALT0 GPIO[1] — — M S 74 R14
eTimer_0 ETC[1] ALT1 ETC[1] PSMI[36];
PADSEL=0
DSPI_2 SOUT ALT2 — —
SIUL — — EIRQ[1] —
MPC5643L Microcon troller Data Sheet, Rev. 9
Package pinouts and signal descriptions
Freescale Semiconductor56
A[2] PCR[2] SIUL GPIO[2] ALT0 GPIO[2] — Pull down M S 84 N16
eTimer_0 ETC[2] ALT1 ETC[2] PSMI[37];
PADSEL=0
FlexPWM_0 A[3] ALT3 A[3] PSMI[23];
PADSEL=0
DSPI_2 — — SIN PSMI[2];
PADSEL=0
MC_RGM — — ABS[0] —
SIUL — — EIRQ[2] —
A[3] PCR[3] SIUL GPIO[3] ALT0 GPIO[3] — Pull down M S 92 K17
eTimer_0 ETC[3] ALT1 ETC[3] PSMI[38];
PADSEL=0
DSPI_2 CS0 ALT2 CS0 PSMI[3];
PADSEL=0
FlexPWM_0 B[3] ALT3 B[3] PSMI[27];
PADSEL=0
MC_RGM — — ABS[2] —
SIUL — — EIRQ[3] —
A[4] PCR[4] SIUL GPIO[4] ALT0 GPIO[4] — Pull down M S 108 C16
eTimer_1 ETC[0] ALT1 ETC[0] PSMI[9];
PADSEL=0
DSPI_2 CS1 ALT2 — —
eTimer_0 ETC[4] ALT3 ETC[4] PSMI[7];
PADSEL=0
MC_RGM — — FAB —
SIUL — — EIRQ[4] —
Table 7. Pin muxing (continued)
Port
name PCR Peripheral Alternate
output
function
Output
mux sel Input
functions Input mux
select
Weak pull
config during
reset
Pad speed1Pin #
SRC
=1 SRC
=0 144
pkg 257
pkg
MPC5643L Microcon troller Data Sheet, Rev. 9
Package pinouts and signal descriptions
Freescale Semiconductor57
A[5] PCR[5] SIUL GPIO[5] ALT0 GPIO[5] — — M S 14 H4
DSPI_1 CS0 ALT1 CS0 —
eTimer_1 ETC[5] ALT2 ETC[5] PSMI[14];
PADSEL=0
DSPI_0 CS7 ALT3 — —
SIUL — — EIRQ[5] —
A[6] PCR[6] SIUL GPIO[6] ALT0 GPIO[6] — — M S 2 G4
DSPI_1 SCK ALT1 SCK —
SIUL — — EIRQ[6] —
A[7] PCR[7] SIUL GPIO[7] ALT0 GPIO[7] — — M S 10 F3
DSPI_1 SOUT ALT1 — —
SIUL — — EIRQ[7] —
A[8] PCR[8] SIUL GPIO[8] ALT0 GPIO[8] — — M S 12 F4
DSPI_1 — — SIN —
SIUL — — EIRQ[8] —
A[9] PCR[9] SIUL GPIO[9] ALT0 GPIO[9] — — M S 134 B6
DSPI_2 CS1 ALT1 — —
FlexPWM_0 B[3] ALT3 B[3] PSMI[27];
PADSEL=1
FlexPWM_0 — — FAULT[0] PSMI[16];
PADSEL=0
Table 7. Pin muxing (continued)
Port
name PCR Peripheral Alternate
output
function
Output
mux sel Input
functions Input mux
select
Weak pull
config during
reset
Pad speed1Pin #
SRC
=1 SRC
=0 144
pkg 257
pkg
MPC5643L Microcon troller Data Sheet, Rev. 9
Package pinouts and signal descriptions
Freescale Semiconductor58
A[10] PCR[10] SIUL GPIO[10] ALT0 GPIO[10] — — M S 118 A13
DSPI_2 CS0 ALT1 CS0 PSMI[3];
PADSEL=1
FlexPWM_0 B[0] ALT2 B[0] PSMI[24];
PADSEL=0
FlexPWM_0 X[2] ALT3 X[2] PSMI[29];
PADSEL=0
SIUL — — EIRQ[9] —
A[11] PCR[11] SIUL GPIO[11] ALT0 GPIO[11] — — M S 120 D11
DSPI_2 SCK ALT1 SCK PSMI[1];
PADSEL=1
FlexPWM_0 A[0] ALT2 A[0] PSMI[20];
PADSEL=0
FlexPWM_0 A[2] ALT3 A[2] PSMI[22];
PADSEL=0
SIUL — — EIRQ[10] —
A[12] PCR[12] SIUL GPIO[12] ALT0 GPIO[12] — — M S 122 A10
DSPI_2 SOUT ALT1 — —
FlexPWM_0 A[2] ALT2 A[2] PSMI[22];
PADSEL=1
FlexPWM_0 B[2] ALT3 B[2] PSMI[26];
PADSEL=0
SIUL — — EIRQ[11] —
Table 7. Pin muxing (continued)
Port
name PCR Peripheral Alternate
output
function
Output
mux sel Input
functions Input mux
select
Weak pull
config during
reset
Pad speed1Pin #
SRC
=1 SRC
=0 144
pkg 257
pkg
MPC5643L Microcon troller Data Sheet, Rev. 9
Package pinouts and signal descriptions
Freescale Semiconductor59
A[13] PCR[13] SIUL GPIO[13] ALT0 GPIO[13] — — M S 136 C6
FlexPWM_0 B[2] ALT2 B[2] PSMI[26];
PADSEL=1
DSPI_2 — — SIN PSMI[2];
PADSEL=1
FlexPWM_0 — — FAULT[0] PSMI[16];
PADSEL=1
SIUL — — EIRQ[12] —
A[14] PCR[14] SIUL GPIO[14] ALT0 GPIO[14] — — M S 143 B4
FlexCAN_1 TXD ALT1 — —
eTimer_1 ETC[4] ALT2 ETC[4] PSMI[13];
PADSEL=0
SIUL — — EIRQ[13] —
A[15] PCR[15] SIUL GPIO[15] ALT0 GPIO[15] — — M S 144 D3
eTimer_1 ETC[5] ALT2 ETC[5] PSMI[14];
PADSEL=1
FlexCAN_1 — — RXD PSMI[34];
PADSEL=0
FlexCAN_0 — — RXD PSMI[33];
PADSEL=0
SIUL — — EIRQ[14] —
Port B
B[0] PCR[16] SIUL GPIO[16] ALT0 GPIO[16] — — M S 109 B15
FlexCAN_0 TXD ALT1 — —
eTimer_1 ETC[2] ALT2 ETC[2] PSMI[11];
PADSEL=0
SSCM DEBUG[0] ALT3 — —
SIUL — — EIRQ[15] —
Table 7. Pin muxing (continued)
Port
name PCR Peripheral Alternate
output
function
Output
mux sel Input
functions Input mux
select
Weak pull
config during
reset
Pad speed1Pin #
SRC
=1 SRC
=0 144
pkg 257
pkg
MPC5643L Microcon troller Data Sheet, Rev. 9
Package pinouts and signal descriptions
Freescale Semiconductor60
B[1] PCR[17] SIUL GPIO[17] ALT0 GPIO[17] — — M S 110 C14
eTimer_1 ETC[3] ALT2 ETC[3] PSMI[12];
PADSEL=0
SSCM DEBUG[1] ALT3 — —
FlexCAN_0 — — RXD PSMI[33];
PADSEL=1
FlexCAN_1 — — RXD PSMI[34];
PADSEL=1
SIUL — — EIRQ[16] —
B[2] PCR[18] SIUL GPIO[18] ALT0 GPIO[18] — — M S 114 A14
LINFlexD_0 TXD ALT1 — —
SSCM DEBUG[2] ALT3 — —
SIUL — — EIRQ[17] —
B[3] PCR[19] SIUL GPIO[19] ALT0 GPIO[19] — — M S 116 B13
SSCM DEBUG[3] ALT3 — —
LINFlexD_0 — — RXD PSMI[31];
PADSEL=0
B[4]2PCR[20] SIUL GPIO[20] ALT0 GPIO[20] — — F S 89 L17
JTAGC TDO ALT1 — —
B[5] PCR[21] SIUL GPIO[21] ALT0 GPIO[21] — Pull up M S 86 M15
JTAGC — — TDI —
B[6] PCR[22] SIUL GPIO[22] ALT0 GPIO[22] — — F S 138 B3
MC_CGM clk_out ALT1 — —
DSPI_2 CS2 ALT2 — —
SIUL — EIRQ[18] —
Table 7. Pin muxing (continued)
Port
name PCR Peripheral Alternate
output
function
Output
mux sel Input
functions Input mux
select
Weak pull
config during
reset
Pad speed1Pin #
SRC
=1 SRC
=0 144
pkg 257
pkg
MPC5643L Microcon troller Data Sheet, Rev. 9
Package pinouts and signal descriptions
Freescale Semiconductor61
B[7] PCR[23] SIUL — ALT0 GPI[23] — — — — 43 R5
LINFlexD_0 — — RXD PSMI[31];
PADSEL=1
ADC_0 — — AN[0]3—
B[8] PCR[24] SIUL — ALT0 GPI[24] — — — — 47 P7
eTimer_0 — — ETC[5] PSMI[8];
PADSEL=2
ADC_0 — — AN[1]3—
B[9] PCR[25] SIUL — ALT0 GPI[25] — — — — 52 U7
ADC_0
ADC_1 ——AN[11]
3—
B[10] PCR[26] SIUL — ALT0 GPI[26] — — — — 53 R8
ADC_0
ADC_1 — — AN[12]3—
B[11] PCR[27] SIUL — ALT0 GPI[27] — — — — 54 T8
ADC_0
ADC_1 — — AN[13]3—
B[12] PCR[28] SIUL — ALT0 GPI[28] — — — — 55 U8
ADC_0
ADC_1 — — AN[14]3—
B[13] PCR[29] SIUL — ALT0 GPI[29] — — — — 60 R10
LINFlexD_1 — — RXD PSMI[32];
PADSEL=0
ADC_1 — — AN[0]3—
Table 7. Pin muxing (continued)
Port
name PCR Peripheral Alternate
output
function
Output
mux sel Input
functions Input mux
select
Weak pull
config during
reset
Pad speed1Pin #
SRC
=1 SRC
=0 144
pkg 257
pkg
MPC5643L Microcon troller Data Sheet, Rev. 9
Package pinouts and signal descriptions
Freescale Semiconductor62
B[14] PCR[30] SIUL — ALT0 GPI[30] — — — — 64 P11
eTimer_0 — — ETC[4] PSMI[7];
PADSEL=2
SIUL — — EIRQ[19] —
ADC_1 — — AN[1]3—
B[15] PCR[31] SIUL — ALT0 GPI[31] — — — — 62 R11
SIUL — — EIRQ[20] —
ADC_1 — — AN[2]3—
Port C
C[0] PCR[32] SIUL — ALT0 GPI[32] — — — — 66 R12
ADC_1 — — AN[3]3—
C[1] PCR[33] SIUL — ALT0 GPI[33] — — — — 41 T4
ADC_0 — — AN[2]3—
C[2] PCR[34] SIUL — ALT0 GPI[34] — — — — 45 U5
ADC_0 — — AN[3]3—
C[4] PCR[36] SIUL GPIO[36] ALT0 GPIO[36] — — M S 11 H3
DSPI_0 CS0 ALT1 CS0 —
FlexPWM_0 X[1] ALT2 X[1] PSMI[28];
PADSEL=0
SSCM DEBUG[4] ALT3 — —
SIUL — — EIRQ[22] —
Table 7. Pin muxing (continued)
Port
name PCR Peripheral Alternate
output
function
Output
mux sel Input
functions Input mux
select
Weak pull
config during
reset
Pad speed1Pin #
SRC
=1 SRC
=0 144
pkg 257
pkg
MPC5643L Microcon troller Data Sheet, Rev. 9
Package pinouts and signal descriptions
Freescale Semiconductor63
C[5] PCR[37] SIUL GPIO[37] ALT0 GPIO[37] — — M S 13 G3
DSPI_0 SCK ALT1 SCK —
SSCM DEBUG[5] ALT3 — —
FlexPWM_0 — — FAULT[3] PSMI[19];
PADSEL=0
SIUL — — EIRQ[23] —
C[6] PCR[38] SIUL GPIO[38] ALT0 GPIO[38] — — M S 142 D4
DSPI_0 SOUT ALT1 — —
FlexPWM_0 B[1] ALT2 B[1] PSMI[25];
PADSEL=0
SSCM DEBUG[6] ALT3 — —
SIUL — — EIRQ[24] —
C[7] PCR[39] SIUL GPIO[39] ALT0 GPIO[39] — — M S 15 K4
FlexPWM_0 A[1] ALT2 A[1] PSMI[21];
PADSEL=0
SSCM DEBUG[7] ALT3 — —
DSPI_0 — — SIN —
C[10] PCR[42] SIUL GPIO[42] ALT0 GPIO[42] — — M S 111 A15
DSPI_2 CS2 ALT1 — —
FlexPWM_0 A[3] ALT3 A[3] PSMI[23];
PADSEL=1
FlexPWM_0 — — FAULT[1] PSMI[17];
PADSEL=0
C[11] PCR[43] SIUL GPIO[43] ALT0 GPIO[43] — — M S 80 M14
eTimer_0 ETC[4] ALT1 ETC[4] PSMI[7];
PADSEL=1
DSPI_2 CS2 ALT2 — —
Table 7. Pin muxing (continued)
Port
name PCR Peripheral Alternate
output
function
Output
mux sel Input
functions Input mux
select
Weak pull
config during
reset
Pad speed1Pin #
SRC
=1 SRC
=0 144
pkg 257
pkg
MPC5643L Microcon troller Data Sheet, Rev. 9
Package pinouts and signal descriptions
Freescale Semiconductor64
C[12] PCR[44] SIUL GPIO[44] ALT0 GPIO[44] — — M S 82 N15
eTimer_0 ETC[5] ALT1 ETC[5] PSMI[8];
PADSEL=0
DSPI_2 CS3 ALT2 — —
C[13] PCR[45] SIUL GPIO[45] ALT0 GPIO[45] — — M S 101 F15
eTimer_1 ETC[1] ALT1 ETC[1] PSMI[10];
PADSEL=0
CTU_0 — — EXT_IN PSMI[0];
PADSEL=0
FlexPWM_0 — — EXT_SYNC PSMI[15];
PADSEL=0
C[14] PCR[46] SIUL GPIO[46] ALT0 GPIO[46] — — M S 103 E15
eTimer_1 ETC[2] ALT1 ETC[2] PSMI[11];
PADSEL=1
CTU_0 EXT_TGR ALT2 — —
C[15] PCR[47] SIUL GPIO[47] ALT0 GPIO[47] — — SYM S 124 A8
FlexRay CA_TR_EN ALT1 — —
eTimer_1 ETC[0] ALT2 ETC[0] PSMI[9];
PADSEL=1
FlexPWM_0 A[1] ALT3 A[1] PSMI[21];
PADSEL=1
CTU_0 — — EXT_IN PSMI[0];
PADSEL=1
FlexPWM_0 — — EXT_SYNC PSMI[15];
PADSEL=1
Table 7. Pin muxing (continued)
Port
name PCR Peripheral Alternate
output
function
Output
mux sel Input
functions Input mux
select
Weak pull
config during
reset
Pad speed1Pin #
SRC
=1 SRC
=0 144
pkg 257
pkg
MPC5643L Microcon troller Data Sheet, Rev. 9
Package pinouts and signal descriptions
Freescale Semiconductor65
Port D
D[0] PCR[48] SIUL GPIO[48] ALT0 GPIO[48] — — SYM S 125 B8
FlexRay CA_TX ALT1 — —
eTimer_1 ETC[1] ALT2 ETC[1] PSMI[10];
PADSEL=1
FlexPWM_0 B[1] ALT3 B[1] PSMI[25];
PADSEL=1
D[1] PCR[49] SIUL GPIO[49] ALT0 GPIO[49] — — M S 3 E3
eTimer_1 ETC[2] ALT2 ETC[2] PSMI[11];
PADSEL=2
CTU_0 EXT_TGR ALT3 — —
FlexRay — — CA_RX —
D[2] PCR[50] SIUL GPIO[50] ALT0 GPIO[50] — — M S 140 C5
eTimer_1 ETC[3] ALT2 ETC[3] PSMI[12];
PADSEL=1
FlexPWM_0 X[3] ALT3 X[3] PSMI[30];
PADSEL=0
FlexRay — — CB_RX —
D[3] PCR[51] SIUL GPIO[51] ALT0 GPIO[51] — — SYM S 128 A7
FlexRay CB_TX ALT1 — —
eTimer_1 ETC[4] ALT2 ETC[4] PSMI[13];
PADSEL=1
FlexPWM_0 A[3] ALT3 A[3] PSMI[23];
PADSEL=2
Table 7. Pin muxing (continued)
Port
name PCR Peripheral Alternate
output
function
Output
mux sel Input
functions Input mux
select
Weak pull
config during
reset
Pad speed1Pin #
SRC
=1 SRC
=0 144
pkg 257
pkg
MPC5643L Microcon troller Data Sheet, Rev. 9
Package pinouts and signal descriptions
Freescale Semiconductor66
D[4] PCR[52] SIUL GPIO[52] ALT0 GPIO[52] — — SYM S 129 B7
FlexRay CB_TR_EN ALT1 — —
eTimer_1 ETC[5] ALT2 ETC[5] PSMI[14];
PADSEL=2
FlexPWM_0 B[3] ALT3 B[3] PSMI[27];
PADSEL=2
D[5] PCR[53] SIUL GPIO[53] ALT0 GPIO[53] — — M S 33 N3
DSPI_0 CS3 ALT1 — —
FlexPWM_0 — — FAULT[2] PSMI[18];
PADSEL=0
D[6] PCR[54] SIUL GPIO[54] ALT0 GPIO[54] — — M S 34 P3
DSPI_0 CS2 ALT1 — —
FlexPWM_0 X[3] ALT3 X[3] PSMI[30];
PADSEL=1
FlexPWM_0 — — FAULT[1] PSMI[17];
PADSEL=1
D[7] PCR[55] SIUL GPIO[55] ALT0 GPIO[55] — — M S 37 R4
DSPI_1 CS3 ALT1 — —
DSPI_0 CS4 ALT3 — —
SWG analog output — — —
D[8] PCR[56] SIUL GPIO[56] ALT0 GPIO[56] — — M S 32 M3
DSPI_1 CS2 ALT1 — —
eTimer_1 ETC[4] ALT2 ETC[4] PSMI[13];
PADSEL=2
DSPI_0 CS5 ALT3 — —
FlexPWM_0 — — FAULT[3] PSMI[19];
PADSEL=1
Table 7. Pin muxing (continued)
Port
name PCR Peripheral Alternate
output
function
Output
mux sel Input
functions Input mux
select
Weak pull
config during
reset
Pad speed1Pin #
SRC
=1 SRC
=0 144
pkg 257
pkg
MPC5643L Microcon troller Data Sheet, Rev. 9
Package pinouts and signal descriptions
Freescale Semiconductor67
D[9] PCR[57] SIUL GPIO[57] ALT0 GPIO[57] — — M S 26 L3
FlexPWM_0 X[0] ALT1 X[0] —
LINFlexD_1 TXD ALT2 — —
D[10] PCR[58] SIUL GPIO[58] ALT0 GPIO[58] — — M S 76 T15
FlexPWM_0 A[0] ALT1 A[0] PSMI[20];
PADSEL=1
eTimer_0 — — ETC[0] PSMI[35];
PADSEL=1
D[11] PCR[59] SIUL GPIO[59] ALT0 GPIO[59] — — M S 78 R16
FlexPWM_0 B[0] ALT1 B[0] PSMI[24];
PADSEL=1
eTimer_0 — — ETC[1] PSMI[36];
PADSEL=1
D[12] PCR[60] SIUL GPIO[60] ALT0 GPIO[60] — M S 99 G14
FlexPWM_0 X[1] ALT1 X[1] PSMI[28];
PADSEL=1
LINFlexD_1 — — RXD PSMI[32];
PADSEL=1
D[14] PCR[62] SIUL GPIO[62] ALT0 GPIO[62] — — M S 105 D16
FlexPWM_0 B[1] ALT1 B[1] PSMI[25];
PADSEL=2
eTimer_0 — — ETC[3] PSMI[38];
PADSEL=1
Port E
E[0] PCR[64] SIUL — ALT0 GPI[64] — — — — 68 T13
ADC_1 — — AN[5]3—
E[2] PCR[66] SIUL — ALT0 GPI[66] — — — — 49 U6
ADC_0 — — AN[5]3—
Table 7. Pin muxing (continued)
Port
name PCR Peripheral Alternate
output
function
Output
mux sel Input
functions Input mux
select
Weak pull
config during
reset
Pad speed1Pin #
SRC
=1 SRC
=0 144
pkg 257
pkg
MPC5643L Microcon troller Data Sheet, Rev. 9
Package pinouts and signal descriptions
Freescale Semiconductor68
E[4] PCR[68] SIUL — ALT0 GPI[68] — — — — 42 U4
ADC_0 — — AN[7]3—
E[5] PCR[69] SIUL — ALT0 GPI[69] — — — — 44 T5
ADC_0 — — AN[8]3—
E[6] PCR[70] SIUL — ALT0 GPI[70] — — — — 46 R6
ADC_0 — — AN[4]3—
E[7] PCR[71] SIUL — ALT0 GPI[71] — — — — 48 T6
ADC_0 — — AN[6]3—
E[9] PCR[73] SIUL — ALT0 GPI[73] — — — — 61 T10
ADC_1 — — AN[7]3—
E[10] PCR[74] SIUL — ALT0 GPI[74] — — — — 63 T11
ADC_1 — — AN[8]3—
E[11] PCR[75] SIUL — ALT0 GPI[75] — — — — 65 U11
ADC_1 — — AN[4]3—
E[12] PCR[76] SIUL — ALT0 GPI[76] — — — — 67 T12
ADC_1 — — AN[6]3—
E[13] PCR[77] SIUL GPIO[77] ALT0 GPIO[77] — — M S 117 D12
eTimer_0 ETC[5] ALT1 ETC[5] PSMI[8];
PADSEL=1
DSPI_2 CS3 ALT2 — —
SIUL — — EIRQ[25] —
E[14] PCR[78] SIUL GPIO[78] ALT0 GPIO[78] — — M S 119 B12
eTimer_1 ETC[5] ALT1 ETC[5] PSMI[14];
PADSEL=3
SIUL — — EIRQ[26] —
Table 7. Pin muxing (continued)
Port
name PCR Peripheral Alternate
output
function
Output
mux sel Input
functions Input mux
select
Weak pull
config during
reset
Pad speed1Pin #
SRC
=1 SRC
=0 144
pkg 257
pkg
MPC5643L Microcon troller Data Sheet, Rev. 9
Package pinouts and signal descriptions
Freescale Semiconductor69
E[15] PCR[79] SIUL GPIO[79] ALT0 GPIO[79] — — M S 121 B11
DSPI_0 CS1 ALT1 — —
SIUL — — EIRQ[27] —
Port F
F[0] PCR[80] SIUL GPIO[80] ALT0 GPIO[80] — — M S 133 D7
FlexPWM_0 A[1] ALT1 A[1] PSMI[21];
PADSEL=2
eTimer_0 — — ETC[2] PSMI[37];
PADSEL=1
SIUL — — EIRQ[28] —
F[3] PCR[83] SIUL GPIO[83] ALT0 GPIO[83] — — M S 139 B5
DSPI_0 CS6 ALT1 — —
F[4] PCR[84] SIUL GPIO[84] ALT0 GPIO[84] — — F S 4 D2
NPC MDO[3] ALT2 — —
F[5] PCR[85] SIUL GPIO[85] ALT0 GPIO[85] — — F S 5 D1
NPC MDO[2] ALT2 — —
F[6] PCR[86] SIUL GPIO[86] ALT0 GPIO[86] — — F S 8 E2
NPC MDO[1] ALT2 — —
F[7] PCR[87] SIUL GPIO[87] ALT0 GPIO[87] — — F S 19 J1
NPC MCKO ALT2 — —
F[8] PCR[88] SIUL GPIO[88] ALT0 GPIO[88] — — F S 20 K2
NPC MSEO[1] ALT2 — —
F[9] PCR[89] SIUL GPIO[89] ALT0 GPIO[89] — — F S 23 K1
NPC MSEO[0] ALT2 — —
F[10] PCR[90] SIUL GPIO[90] ALT0 GPIO[90] — — F S 24 L1
NPC EVTO ALT2 — —
Table 7. Pin muxing (continued)
Port
name PCR Peripheral Alternate
output
function
Output
mux sel Input
functions Input mux
select
Weak pull
config during
reset
Pad speed1Pin #
SRC
=1 SRC
=0 144
pkg 257
pkg
Package pinouts and signal descriptions
MPC5643L Microcon troller Data Sheet, Rev. 9
Freescale Semiconductor 70
F[11] PCR[91] SIUL GPIO[91] ALT0 GPIO[91] — — M S 25 L2
NPC — ALT2 EVTI —
F[12] PCR[92] SIUL GPIO[92] ALT0 GPIO[92] — — M S 106 C17
eTimer_1 ETC[3] ALT1 ETC[3] PSMI[12];
PADSEL=2
SIUL — — EIRQ[30] —
F[13] PCR[93] SIUL GPIO[93] ALT0 GPIO[93] — — M S 112 B14
eTimer_1 ETC[4] ALT1 ETC[4] PSMI[13];
PADSEL=3
SIUL — — EIRQ[31] —
F[14] PCR[94] SIUL GPIO[94] ALT0 GPIO[94] — — M S 115 C13
LINFlexD_1 TXD ALT1 — —
F[15] PCR[95] SIUL GPIO[95] ALT0 GPIO[95] — — M S 113 D13
LINFlexD_1 — — RXD PSMI[32];
PADSEL=2
FCCU
FCCU_
F[0] — FCCU F[0] ALT0 F[0] — — S S 38 R2
FCCU_
F[1] — FCCU F[1] ALT0 F[1] — — S S 141 C4
Port G
G[2] PCR[98] SIUL GPIO[98] ALT0 GPIO[98] — — M S 102 E16
FlexPWM_0 X[2] ALT1 X[2] PSMI[29];
PADSEL=1
DSPI_1 CS1 ALT2 — —
Table 7. Pin muxing (continued)
Port
name PCR Peripheral Alternate
output
function
Output
mux sel Input
functions Input mux
select
Weak pull
config during
reset
Pad speed1Pin #
SRC
=1 SRC
=0 144
pkg 257
pkg
MPC5643L Microcon troller Data Sheet, Rev. 9
Package pinouts and signal descriptions
Freescale Semiconductor71
G[3] PCR[99] SIUL GPIO[99] ALT0 GPIO[99] — — M S 104 D17
FlexPWM_0 A[2] ALT1 A[2] PSMI[22];
PADSEL=2
eTimer_0 — — ETC[4] PSMI[7];
PADSEL=3
G[4] PCR[100] SIUL GPIO[100] ALT0 GPIO[100] — — M S 100 F17
FlexPWM_0 B[2] ALT1 B[2] PSMI[26];
PADSEL=2
eTimer_0 — — ETC[5] PSMI[8];
PADSEL=3
G[5] PCR[101] SIUL GPIO[101] ALT0 GPIO[101] — — M S 85 N17
FlexPWM_0 X[3] ALT1 X[3] PSMI[30];
PADSEL=2
DSPI_2 CS3 ALT2 — —
G[6] PCR[102] SIUL GPIO[102] ALT0 GPIO[102] — — M S 98 G17
FlexPWM_0 A[3] ALT1 A[3] PSMI[23];
PADSEL=3
G[7] PCR[103] SIUL GPIO[103] ALT0 GPIO[103] — M S 83 P17
FlexPWM_0 B[3] ALT1 B[3] PSMI[27];
PADSEL=3
G[8] PCR[104] SIUL GPIO[104] ALT0 GPIO[104] — — M S 81 P16
FlexRay DBG0 ALT1 — —
DSPI_0 CS1 ALT2 — —
FlexPWM_0 — — FAULT[0] PSMI[16];
PADSEL=2
SIUL — — EIRQ[21] —
Table 7. Pin muxing (continued)
Port
name PCR Peripheral Alternate
output
function
Output
mux sel Input
functions Input mux
select
Weak pull
config during
reset
Pad speed1Pin #
SRC
=1 SRC
=0 144
pkg 257
pkg
Package pinouts and signal descriptions
MPC5643L Microcon troller Data Sheet, Rev. 9
Freescale Semiconductor 72
G[9] PCR[105] SIUL GPIO[105] ALT0 GPIO[105] — — M S 79 R17
FlexRay DBG1 ALT1 — —
DSPI_1 CS1 ALT2 — —
FlexPWM_0 — — FAULT[1] PSMI[17];
PADSEL=2
SIUL — — EIRQ[29] —
G[10] PCR[106] SIUL GPIO[106] ALT0 GPIO[106] — — M S 77 P15
FlexRay DBG2 ALT1 — —
DSPI_2 CS3 ALT2 — —
FlexPWM_0 — — FAULT[2] PSMI[18];
PADSEL=1
G[11] PCR[107] SIUL GPIO[107] ALT0 GPIO[107] — — M S 75 U15
FlexRay DBG3 ALT1 — —
FlexPWM_0 — — FAULT[3] PSMI[19];
PADSEL=2
G[12] PCR[108] SIUL GPIO[108] ALT0 GPIO[108] — — F S — F2
NPC MDO[11] ALT2 — —
G[13] PCR[109] SIUL GPIO[109] ALT0 GPIO[109] — — F S — H1
NPC MDO[10] ALT2 — —
G[14] PCR[110] SIUL GPIO[110] ALT0 GPIO[110] — — F S — A6
NPC MDO[9] ALT2 — —
G[15] PCR[111] SIUL GPIO[111] ALT0 GPIO[111] — — F S — J2
NPC MDO[8] ALT2 — —
Port H
H[0] PCR[112] SIUL GPIO[112] ALT0 GPIO[112] — — F S — A5
NPC MDO[7] ALT2 — —
Table 7. Pin muxing (continued)
Port
name PCR Peripheral Alternate
output
function
Output
mux sel Input
functions Input mux
select
Weak pull
config during
reset
Pad speed1Pin #
SRC
=1 SRC
=0 144
pkg 257
pkg
MPC5643L Microcon troller Data Sheet, Rev. 9
Package pinouts and signal descriptions
Freescale Semiconductor73
H[1] PCR[113] SIUL GPIO[113] ALT0 GPIO[113] — — F S — F1
NPC MDO[6] ALT2 — —
H[2] PCR[114] SIUL GPIO[114] ALT0 GPIO[114] — — F S — A4
NPC MDO[5] ALT2 — —
H[3] PCR[115] SIUL GPIO[115] ALT0 GPIO[115] — — F S — G1
NPC MDO[4] ALT2 — —
H[4] PCR[116] SIUL GPIO[116] ALT0 GPIO[116] — — M S — L16
FlexPWM_1 X[0] ALT1 X[0] —
eTimer_2 ETC[0] ALT2 ETC[0] PSMI[39];
PADSEL=0
H[5] PCR[117] SIUL GPIO[117] ALT0 GPIO[117] — — M S — M17
FlexPWM_1 A[0] ALT1 A[0] —
DSPI_0 CS4 ALT3 — —
H[6] PCR[118] SIUL GPIO[118] ALT0 GPIO[118] — — M S — H17
FlexPWM_1 B[0] ALT1 B[0] —
DSPI_0 CS5 ALT3 — —
H[7] PCR[119] SIUL GPIO[119] ALT0 GPIO[119] — — M S — K16
FlexPWM_1 X[1] ALT1 X[1] —
eTimer_2 ETC[1] ALT2 ETC[1] PSMI[40];
PADSEL=0
H[8] PCR[120] SIUL GPIO[120] ALT0 GPIO[120] — — M S — K15
FlexPWM_1 A[1] ALT1 A[1] —
DSPI_0 CS6 ALT3 — —
H[9] PCR[121] SIUL GPIO[121] ALT0 GPIO[121] — — M S — G16
FlexPWM_1 B[1] ALT1 B[1] —
DSPI_0 CS7 ALT3 — —
Table 7. Pin muxing (continued)
Port
name PCR Peripheral Alternate
output
function
Output
mux sel Input
functions Input mux
select
Weak pull
config during
reset
Pad speed1Pin #
SRC
=1 SRC
=0 144
pkg 257
pkg
MPC5643L Microcon troller Data Sheet, Rev. 9
Package pinouts and signal descriptions
Freescale Semiconductor74
H[10] PCR[122] SIUL GPIO[122] ALT0 GPIO[122] — — M S — A11
FlexPWM_1 X[2] ALT1 X[2] —
eTimer_2 ETC[2] ALT2 ETC[2] —
H[11] PCR[123] SIUL GPIO[123] ALT0 GPIO[123] — — M S — C11
FlexPWM_1 A[2] ALT1 A[2] —
H[12] PCR[124] SIUL GPIO[124] ALT0 GPIO[124] — — M S — B10
FlexPWM_1 B[2] ALT1 B[2] —
H[13] PCR[125] SIUL GPIO[125] ALT0 GPIO[125] — — M S — G15
FlexPWM_1 X[3] ALT1 X[3] —
eTimer_2 ETC[3] ALT2 ETC[3] PSMI[42];
PADSEL=0
H[14] PCR[126] SIUL GPIO[126] ALT0 GPIO[126] — — M S — A12
FlexPWM_1 A[3] ALT1 A[3] —
eTimer_2 ETC[4] ALT2 ETC[4] —
H[15] PCR[127] SIUL GPIO[127] ALT0 GPIO[127] — — M S — J17
FlexPWM_1 B[3] ALT1 B[3] —
eTimer_2 ETC[5] ALT2 ETC[5] —
Port I
I[0] PCR[128] SIUL GPIO[128] ALT0 GPIO[128] — — M S — C9
eTimer_2 ETC[0] ALT1 ETC[0] PSMI[39];
PADSEL=1
DSPI_0 CS4 ALT2 — —
FlexPWM_1 — — FAULT[0] —
Table 7. Pin muxing (continued)
Port
name PCR Peripheral Alternate
output
function
Output
mux sel Input
functions Input mux
select
Weak pull
config during
reset
Pad speed1Pin #
SRC
=1 SRC
=0 144
pkg 257
pkg
MPC5643L Microcon troller Data Sheet, Rev. 9
Package pinouts and signal descriptions
Freescale Semiconductor75
NOTE
Open Drain can be configured by the PCR n for all pin s used as output (except FCCU_F[0] and FCCU_F[1] ).
I[1] PCR[129] SIUL GPIO[129] ALT0 GPIO[129] — — M S — C12
eTimer_2 ETC[1] ALT1 ETC[1] PSMI[40];
PADSEL=1
DSPI_0 CS5 ALT2 — —
FlexPWM_1 — — FAULT[1] —
I[2] PCR[130] SIUL GPIO[130] ALT0 GPIO[130] — — M S — F16
eTimer_2 ETC[2] ALT1 ETC[2] PSMI[41];
PADSEL=1
DSPI_0 CS6 ALT2 — —
FlexPWM_1 — — FAULT[2] —
I[3] PCR[131] SIUL GPIO[131] ALT0 GPIO[131] — — M S — E17
eTimer_2 ETC[3] ALT1 ETC[3] PSMI[42];
PADSEL=1
DSPI_0 CS7 ALT2 — —
CTU_0 EXT_TGR ALT3 — —
FlexPWM_1 — — FAULT[3] —
RDY PCR[132] SIUL GPIO[132] ALT0 GPIO[132] — — F S — K3
NPC RDY ALT2 — —
1Programmable via the SRC (Slew Rate Control) bit in the respective Pad Configuration Register; S = Slow, M = Medium, F = Fast, SYM =
Symmetric (for FlexRay)
2The default function of this pin out of reset is ALT1 (TDO).
3Analog
Table 7. Pin muxing (continued)
Port
name PCR Peripheral Alternate
output
function
Output
mux sel Input
functions Input mux
select
Weak pull
config during
reset
Pad speed1Pin #
SRC
=1 SRC
=0 144
pkg 257
pkg
MPC5643L Microcontroller Data Sheet, Rev. 9
Electrical characteristics
Freescale Semiconductor76
3 Electrical characteristics
3.1 Introduction
This section contains detailed inform at ion on power considerations, DC/AC electrical characteristics, and AC timing
specifications for this device.
This device is designed to operate at 120 MHz. The electrical specifications are preliminary and are from previous designs,
design simulations, or initial evalu a tion. These specifications may not be fully tested or guaranteed at this early stage of the
product life cycle. Finalized specifications will be published after complete characterization and device qualifications have been
completed.
The “Symbol” column of the electrical parameter and timings tables contains an additional column containing “SR”, “CC”, “P”,
“C”, “T”, or “D”.
• “SR” identifies system requirements—co nditions that must be provided to ensure normal device operation. An
example is the input voltage of a voltage regulator.
• “CC” identifies controller characteristics—indicating the characteristics and timing of the signals that the chip
provides.
• “P”, “C”, “T”, or “D” apply only to controller characteristics—specifications that define normal device operation.
They specify how each characteristic is guaranteed.
— P: parameter is guaranteed by production testing of each individual device.
— C: parameter is guaranteed by design characterization. Measurements are taken from a statistically relevant
sample size across process variations.
— T: parameter is guaranteed by de sign characterization on a small sample size from typical devices under typical
conditions unless otherwi se no ted. All val ues are shown in the typical (“typ”) column are within this category.
— D: parameters are derived mainly from simu lations.
3.2 Absolute maximum ratings
Table 8. Absolute maximum ratings1
Symbol Parameter Conditions Min Max Unit
VDD_HV_REG SR 3.3 V voltage regulator su pply voltage — –0.3 3.632, 3 V
VDD_HV_IOx SR 3.3 V input/output supply voltage — –0.3 3.632, 3 V
VSS_HV_IOx SR Input/output ground voltage — –0.1 0.1 V
VDD_HV_FLA SR 3.3 V flash supply voltage — –0.3 3.632, 3 V
VSS_HV_FLA SR Flash memory ground — –0.1 0.1 V
VDD_HV_OSC SR 3.3 V crystal oscillator amplifier supply
voltage —–0.33.63
2, 3 V
VSS_HV_OSC SR 3.3 V crystal oscillator amplifier reference
voltage —–0.10.1V
VDD_HV_ADR03,4
VDD_HV_ADR1
SR 3.3 V / 5.0 V ADC_0 high reference voltage
3.3 V / 5.0 V ADC_1 high reference voltage —–0.36.0V
VSS_HV_ADR0
VSS_HV_ADR1
SR ADC_0 ground and low reference voltage
ADC_1 ground and low reference voltage —–0.10.1V
VDD_HV_ADV SR 3.3 V ADC supply voltage — –0.3 3.632, 3 V
VSS_HV_ADV SR 3.3 V ADC supply ground — –0.1 0.1 V
Electrical characteristics
MPC5643L Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor 77
3.3 Recommended operating conditions
TVDD SR Supply ramp rate — 3.0 × 10-6
(3.0 V/sec) 0.5 V/sV/s
VIN SR Voltage on any pin with respect to ground
(VSS_HV_IOx) —–0.36.0
5V
Relative to VDD –0.3 VDD +0.3
5,6
IINJPAD SR Injected input cu rrent on any pin during
overload condition — –10 10 mA
IINJSUM SR Absolute sum of all injected input currents
during overload condition — –50 50 mA
TSTG SR Storage temperature — –55 150 °C
1Functional operating conditions are given in the DC electrical characteristics. Absolute maximum ratings are stress
ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the listed maxima may affect
device reliability or cause permanent damage to the device.
25.3 V for 10 hours cumulative over lifetime of device, 3.3 V +10% for time remaining.
3Voltage overshoots during a high-to-low or low-to-high transition must not exceed 10 seconds per instance.
46.4 V for 10 hours cumulative time, 6.0 V for time remaining.
5Internal structures hold the input voltage less than the maximum voltage on all pads powered by VDDE supplies, if the
maximum injection current specification is met and VDDE is within the operating voltage specifications.
6Only when VDD < 5.2 V.
Table 9. Recommended operating conditions (3.3 V)
Symbol Parameter Conditions Min1Max Unit
VDD_HV_REG SR 3.3 V voltage regulator supply voltage — 3.0 3.63 V
VDD_HV_IOx SR 3.3 V input/output supply voltage — 3.0 3.63 V
VSS_HV_IOx SR Input/ou tput ground voltage — 0 0 V
VDD_HV_FLA SR 3.3 V flash supply voltage — 3 .0 3.63 V
VSS_HV_FLA SR Flash memory ground — 0 0 V
VDD_HV_OSC SR 3.3 V crystal oscillator amplifier supply voltage — 3.0 3.63 V
VSS_HV_OSC SR 3.3 V crystal oscillator amplifier reference voltage — 0 0 V
VDD_HV_ADR02,3
VDD_HV_ADR1
SR 3.3 V / 5.0 V ADC_0 high reference voltage
3.3 V / 5.0 V ADC_1 high refere nce voltage — 4.5 to 5.5 or
3.0 to 3.63 V
VDD_HV_ADV SR 3.3 V ADC supply voltage — 3.0 3.63 V
VSS_HV_AD0
VSS_HV_AD1
SR ADC_0 ground and low reference voltage
ADC_1 ground and low reference voltage —00V
VSS_HV_ADV SR 3.3 V ADC supply ground — 0 0 V
VDD_LV_REGCOR4SR Internal supply voltage — — — V
VSS_LV_REGCOR5 SR Internal reference voltage — 0 0 V
VDD_LV_CORx2 SR Internal supply voltage — — — V
Table 8. Absolute maximum ratings1 (continued)
Symbol Parameter Conditions Min Max Unit
MPC5643L Microcontroller Data Sheet, Rev. 9
Electrical characteristics
Freescale Semiconductor78
3.4 Thermal characteristics
VSS_LV_CORx3 SR Internal reference voltage — 0 0 V
VDD_LV_PLL2 SR Internal supply voltage — — — V
VSS_LV_PLL3 SR Internal reference voltage — 0 0 V
TASR Ambient temperature under bias
f
CPU
120 MHz
–40 125 °C
TJSR Junc tion temperature under bias — –40 150 °C
1Full functionality cannot be guaranteed when voltage drops below 3.0 V . In particular , ADC electrical characteristics
and I/Os DC electrical specification may not be guaranteed.
2VDD_HV_ADR0 and VDD_HV_ADR1 cannot be operated at different voltages, and need to be supplied by the same
voltage source.
3VDD_HV_ADRx must always be applied and should be stable before LBIST starts. If this supply is not above its
absolute minimum level, LBIST operations can fail.
4Can be connected to emitter of external NPN. Low voltage supplies are not under user control. They are produced
by an on-chip voltage regulator.
5For the device to function properly, the low voltage grounds (VSS_LV_xxx) must be shorted to high voltage grounds
(VSS_HV_xxx) and the low voltage supply pins (VDD_LV_xxx) must be connected to the external ballast emitter , if one
is used.
Table 10. Therma l characteristics for 100 LQFP package1
1Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site
(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board
thermal resistance.
Symbol Parameter Conditions Value Unit
RJA D Thermal resistance, junction-to-ambient natural
convection2
2Junction-to-Ambient thermal resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board
meets JEDEC specification for this package.
Single layer board – 1s 46 °C/W
Four layer board – 2s2p 34
RJMA D T hermal resistance, junction-to-ambient forced
convection at 200 ft/min Single layer board – 1s 36 °C/W
Four layer board – 2s2p 28
RJB D Thermal resistance junction-to-board 3
3Junction-to-Board thermal resistance determined per JEDEC JESD51-8. Thermal test bo ard meets JEDEC
specification for the specified package.
—19°C/W
RJC D Thermal resistance junction-to-case4
4Junction-to-Case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate
temperature is used for the case temperature. Reported value includes the thermal resistance of the interface layer .
—8°C/W
JT D Junction-to-package-top natural convection5
5Thermal characterization parameter indicating the temperature difference between the package top and the
junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization
parameter is written as Psi-JT.
—2°C/W
Table 9. Recommended operating conditions (3.3 V) (continued)
Symbol Parameter Conditions Min1Max Unit
Electrical characteristics
MPC5643L Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor 79
Table 11. Thermal characteristics for 144 LQFP package1
1Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site
(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board
thermal resistance.
Symbol Parameter Conditions Value Unit
RJA D Thermal resistance, junction-to-ambient natural
convection2
2Junction-to-Ambient thermal resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board
meets JEDEC specification for this package.
Single layer board – 1s 44 °C/W
Four layer board – 2s2p 36
RJMA D T hermal resistance, junction-to-ambient forced
convection at 200 ft/min Single layer board – 1s 35 °C/W
Four layer board – 2s2p 30
RJB D Thermal resistance junction-to-board 3
3Junction-to-Board thermal resistance determined per JEDEC JESD51-8. Thermal test bo ard meets JEDEC
specification for the specified package.
—24°C/W
RJC D Thermal resistance junction-to-case4
4Junction-to-Case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate
temperature is used for the case temperature. Reported value includes the thermal resistance of the interface layer .
—8°C/W
JT D Junction-to-package-top natural convection5
5Thermal characterization parameter indicating the temperature difference between the package top and the
junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization
parameter is written as Psi-JT.
—2°C/W
Table 12. Thermal characteristics for 257 MAPBGA package1
1Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site
(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board
thermal resistance.
Symbol Parameter Conditions Value Unit
RJA D T hermal resistance junction-to-ambient natural
convection2
2Junction-to-Ambient thermal resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board
meets JEDEC specification for this package.
Single layer board – 1s 46 °C/W
Four layer board – 2s2p 26
RJMA D T hermal resistance, junction-to-ambient forced
convection at 200 ft/min Single layer board – 1s 37 °C/W
Four layer board – 2s2p 22
RJB D Thermal resistance junction-to-board 3
3Junction-to-Board thermal resistance determined per JEDEC JESD51-8. Thermal test bo ard meets JEDEC
specification for the specified package.
—13°C/W
RJC D Thermal resistance junction-to-case4
4Junction-to-Case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate
temperature is used for the case temperature. Reported value includes the thermal resistance of the interface layer .
—8°C/W
JT D Junction-to-package-top natural convection5
5Thermal characterization parameter indicating the temperature difference between the package top and the
junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization
parameter is written as Psi-JT.
—2°C/W
MPC5643L Microcontroller Data Sheet, Rev. 9
Electrical characteristics
Freescale Semiconductor80
3.4.1 General notes for specifications at maximum junction temperature
An estimation of the chip junction temperature, TJ, can be obtained from Equation 1:
TJ=T
A+(R
JA ×P
D)Eqn. 1
where:
TA= ambient temperature for the package (oC)
RJA = junction to ambient thermal resistance (oC/W)
PD= power dissipation in the package (W)
The junction to ambient thermal resistance is an industry stan dard value that provides a quick and easy estimation of thermal
performance. Unfortunately, there are two values in common usage: the value determined on a single layer board and the value
obtained on a board with two planes. For packages such as the PBGA, these values can be different by a factor of two. Which
value is closer to the application depends on the power dissipated by other components on the board. The value obt ained on a
single layer boar d i s appr opr iate for the tightly packed printed circuit board. The value obtained on the board with the internal
planes is usually appropriate if the board has low power dissipation and the components are well separated.
When a heat sink is used, the thermal resistance is expressed in Equation 2 as the sum of a junction to case thermal resistance
and a case to ambient thermal resistance:
RJA =R
JC + RCA Eqn. 2
where:
RJA = junction to ambient thermal resistance (°C/W)
RJC = junction to case thermal resistance (°C/W)
RCA = case to ambient thermal resistance (°C/W)
RJC is device related and cannot be influenced by the user. The user controls the thermal environment to change the case to
ambient thermal resistance, RCA. For instance, the user can change the size of the heat sink, the air flow around the device, the
interface material, the mounti ng arrangem e nt on prin ted circuit bo ard, or chan ge the thermal dissipation on the printed circuit
board surrounding the device.
To determine the junction temperature of the device in the application when heat sinks are not used, the Thermal
Characterization Parameter (JT) can be used to determine the junction temperature with a measurement of the temperature at
the top center of the package case using Equation 3:
TJ=T
T+(JT ×P
D)Eqn. 3
where:
TT= thermocouple temperature on top of the package (°C)
JT = thermal characterization parameter (°C/W)
PD= power dissipation in the package (W)
The thermal characterization parameter is measured per J ESD51-2 specification using a 40 gauge type T thermocouple epoxied
to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the
package. A small amount of epoxy is placed over the thermocouple junction and over about 1 mm of wire extending from the
junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling ef fects
of the thermocouple wire.
3.4.1.1 References
Semiconductor Equipment and Materials International
3081 Zanker Road
Electrical characteristics
MPC5643L Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor 81
San Jose, CA 95134 USA
(408) 943-6900
MIL-SPEC and EIA/JESD (JEDEC) specifications are available from Global Engineering Documents at 800-854-7179 or
303-397-7956.
JEDEC specifications are available on the WEB at http://www.jedec.org.
1. C.E. Triplett and B. Joiner, “An Experimental Characterization of a 272 PBGA Within an Automotive Engine
Controller Module,” Proceedings of SemiTherm, San Diego, 1998, pp. 47–54.
2. G. Kromann, S. Shidore, and S. Addison, “Thermal Modeling of a PBGA for Air-Cooled Applications,” Electronic
Packaging and Production, pp. 53–58, March 1998.
3. B. Joiner and V. Adams, “Measurement and Simulation of Junction to Board Thermal Resistance and Its Application
in Thermal Modeling,” Proceedings of Sem iTherm , San Diego, 1999, pp. 212 –220.
3.5 Electromagnetic Interference (EMI) characteristics
The characteristics in Table 14 were measured using:
• Devi ce configuration, tet conditions, and EM testing per standard IEC61 967-2
• Suppl y voltage of 3.3 V DC
• Ambient temperature of 25 C
The configuration information referenced in Table 14 is explained in Table 13.
Table 13. EMI configuration summary
Configuration name Description
Configuration A • High emission = all pads have max slew rate, LVDS pads running at 40 MHz
• Oscillator frequency = 40 MHz
• System bus frequency = 80 MHz
• No PLL frequency modulation
• IEC level I (36 dBV)
Configuration B • Reference emission = pads use min, mid and max slew rates, LVDS pads disabled
• Oscillator frequency = 40 MHz
• System bus frequency = 80 MHz
• 2% PLL frequency modulation
• IEC level K(30 dBV)
MPC5643L Microcontroller Data Sheet, Rev. 9
Electrical characteristics
Freescale Semiconductor82
EMC testing was performe d and docum ented according to these standards: [IEC61508-2-7.4.5.1.b, IEC61508-2-7.2.3.2.e,
IEC61508-2-Table-A.17 (partially), IEC61508-2-Table-B.5(partially),SRS2110]
EME testing was performed and documented according to these standards: [IEC 6196 7-2 & -4]
EMS testing was performed and documented according to these standards: [IEC 62132-2 & -4]
Refer MPC5643L for detailed information pertaining to the EMC , EME, and EMS testing and results.
3.6 Electrostatic discharge (ESD) characteristics
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according
to each pin combination. The sample size depends on the number of supply pins in the device (3 parts × (n+ 1) supply pin).
This test conforms to the AEC-Q100-002/-003/-011 standard.
Table 14. EMI emission testing specifications
Symbol Parameter Conditions Min Typ Max Unit
VEME CC Radiated emissions Configuration A; frequency range
150 kHz–50 MHz —16—dBV
Configuration A; frequency range
50–150 MHz —16—
Configuration A; frequency range
150–500 MHz —32—
Configuration A; frequency range
500–1000 MHz —25—
Configuration B; frequency range
50–150 MHz —15—
Configuration B; frequency range
50–150 MHz —21—
Configuration B; frequency range
150–500 MHz —30—
Configuration B; frequency range
500–1000 MHz —24—
Table 15. ESD ratings1, 2
1All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated
Circuits.
2A device will be defined as a failure if after exposure to ESD pulses the device no longe r meets the device
specification requirements. Complete DC parametric and functional testing shall be performed per applicable
device specification at room temperature followed by hot temperature, unless specified otherwise in the device
specification.
No. Symbol Parameter Conditions Class Max value3Unit
1V
ESD(HBM) SR Electrostatic discharge
(Human Body Model) TA=25°C
conforming to AEC-Q100-002 H1C 2000 V
2V
ESD(MM) SR Electrostatic discharge
(Machine Model) TA=25°C
conforming to AEC-Q100-003 M2 200 V
3V
ESD(CDM) SR Electrostatic discharge
(Charged Device Model) TA=25°C
conforming to AEC-Q100-011 C3A 500 V
750 (corners)
Electrical characteristics
MPC5643L Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor 83
3.7 Static latch-up (LU)
Two com pl ementary static tests are required on six parts to assess the latch-up performance:
• A supply overvoltage is applied to each power supply pin.
• A current injection is applied to each input, output and configurable I/O pin.
These tests are compliant with the EIA/JESD 78 IC latch-up standard.
3.8 Voltage regulator electrical characteristics
The voltage regulator is composed of the following blocks:
• Hig h power regu lator HPREG1 (internal ballast to support core current)
• Hig h power regu lator HPREG2 (external NPN to support core current)
• Low vol tage detector (LVD_MAIN_1) for 3.3 V supply to IO (VDDIO)
• Low vol tage detect or (LVD _MAIN_2) for 3.3 V supply (VDDREG)
• Low vol tage detector (LVD_MAIN_3) for 3.3 V flash supply (VDDFLASH)
• Low vol tage detect or (LVD _DIG_MAIN) for 1.2 V digital core supply (HPVDD)
• Low vol tage detect or (LVD _DIG_BKUP) for the self-test of LVD_DIG_MAIN
• Hig h voltage detector (HVD_DIG_MAIN) for 1.2 V digital CORE supply (HPVDD)
• Hig h vol tage detector (HVD_DIG_BKUP) for the self-test of HVD_DIG_MAIN.
•Power on Reset (POR)
HPREG1 uses an internal ballast to support the core current. HPREG2 is used only when external NPN transistor is present on
board to supply core current. The MPC5643L always powers up using HPREG1 if an external NPN transistor is present. Then
the MPC5643L makes a transition from HPREG1 to HPREG2. This transition is dynamic. Once HPREG2 is fully operational,
the controller part of HPREG1 is switched off.
The following bipolar transistors are supported:
• BCP68 from ON Semiconductor
• BCX6 8 from Infineon
3Data based on characterization results, not tested in producti on.
Table 16. Latch-up results
No. Symbol Parameter Conditions Class
1 LU SR Static la tch-up class TA= 125 °C confor ming to JESD 78 II level A
Table 17. Recommended operating characteristics
Symbol Parameter Value Unit
hFE( ) DC current gain (Beta) 85 - 375 —
PDMaximum power dissipation @
TA=25°C1
1derating factor 12mW/degC
1.5 W
ICMaxDC Maximum peak collector current 1.0 A
VCESAT Collector-to-emitter saturation
voltage(Max) 6002mV
VBE Base-to-emitter voltage (Max) 1.0 V
MPC5643L Microcontroller Data Sheet, Rev. 9
Electrical characteristics
Freescale Semiconductor84
The recommended external ballast transistor is the bipolar transistor BCP68 with the gain range of 85 up to 375 (for IC=500mA,
VCE=1V) provided by several supp liers. This includes the gain variations BCP68-10, BCP68-16 and BCP68-25.The most
important parameters for the interoperability with the integrated voltage regulator are the DC current gain (hFE) and the
temperature coefficient of the gain (XTB). While the specified gain range of most BCP68 vendors is the same, there are slight
variations in the temperature coefficient parameter. MPC5643L Voltage regulator operation was simulated against the typical
variation on temperature coefficient and against the specified gain range to have a robust design.
2Adjust resistor at bipolar transistor collector for 3.3V to avoid VCE<VCESAT
Table 18. Voltage regulator electrical specifications
Symbol Parameter Conditions Min
Typ
Max
Unit
C
ext
External decoupling/
stability capacitor Min, max values shall be
granted with respect to
tolerance, voltage,
temperature, and aging
variations.
12
—40µF
SR
Combined ESR of
external capacitor —1
— 100 m
SR
Number of pins for
external de c o up ling/
stability capacitor
—5
———
C
V1V2
SR
Total capacitance on
1.2 V pins Ceramic capacitors,
taking into account
tolerance, aging, voltage
and temperature variation
300
— 900 nF
tSU
Start-up time after m a in
supply stabilization C
load
=10µF×4 —
—2.5ms
—
Main High Voltage Power -
Low Voltage Detection,
upper threshold
——
—2.93V
—
D
Main supply low vo l tage
detector, lower threshold —2.6
——V
—
D
Digital supply high voltage
detector upper threshold Before a destructive reset
initialization phase
completion
1.355
—1.495V
After a destructive reset
initialization phase
completion
1.39
—1.47
—
D
Digital supply high voltage
detector lower threshold Before a destructive reset
initialization phase
completion
1.315
—1.455V
After a destructive reset
initialization phase
completion
1.35
—1.38
Electrical characteristics
MPC5643L Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor 85
—
D
Digital supply low voltage
detector lower threshold
After a destructive reset
initialization phase
completion
1.080
—
1.140
V
—
D
Digital supply low voltage
detector upper threshold
After a destructive reset
initialization phase
completion
1.16
—
1.22
V
—
D
Digital supply low voltage
detector lower threshold
Before a destructive
reset initialization phase
1.080
—
1.226
V
—
D
Digital supply low voltage
detector upper threshold
Before a destructive
reset initialization phase
1.160
—
1.306
V
—
D
POR rising/ falling supply
threshold v oltage —1.6
—2.6V
—
SR
Supply ramp rate —
3 V/s
—
0.5 V/
µs —
—
D
LVD_MAIN: Time
constant of RC filter at
LVD input
3.3V noise rejection at the
input of
LVD comparator
1.1 — — µs
—
D
HVD_DIG: T ime constant
of RC filter at LVD input 1.2V noise rejection at the
input of
LVD comparator
0.1 — — µs
—
D
LVD_DIG: Time constant
of RC filter at LVD input 1.2V noise rejection at the
input of
LVD comparator
0.1 — — µs
Table 18. Voltage regulator electrical specifications (continued)
Symbol Parameter Conditions Min
Typ
Max
Unit
MPC5643L Microcontroller Data Sheet, Rev. 9
Electrical characteristics
Freescale Semiconductor86
Figure 4. BCP68 board schematic example
NOTE
The minimum value of the ESR is constrained by the resonance caused by the external
components, bonding inductance, and internal decoupling. The minimum ESR is required
to avoid the resonance and make the regulator stable.
3.9 DC electrical characteristics
Table 19 gives the DC electrical characteristics at 3.3 V (3.0 V < VDD_HV_IOx<3.6V).
Table 19. DC electrical characteristics1
Symbol Parameter Conditions Min Typ Max Unit
VIL D Minimum low level input voltage — –0.12——V
VIL P Maximum level input voltage — — — 0.35 VDD_HV_IOx V
VIH P Minimum high level input voltage — 0.65 VDD_HV_IOx ——V
VIH D Maximum high level input voltage — — —
V
DD_HV_IOx
+0.1
2
,
3
V
VHYS T Schmitt trigger hysteresis — 0.1 VDD_HV_IOx——V
VOL_S P Slow, low level output voltage IOL =1.5mA — — 0.5 V
VOH_S P Slow, high level output voltage IOH = –1.5 mA VDD_HV_IOx–0.8 — — V
VOL_M P Medium, low level output voltage IOL =2mA — — 0.5 V
BCRTL
Cext
Cint
RbLb
Rs
V1V2 ring on board
VDD
V1V2 pin
ESR
C
v1v2
MPC5643L
BCP68
Electrical characteristics
MPC5643L Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor 87
3.10 Supply current characteristics
Current consumption data is given in Table 20. These specifications are design targets and are subject to change per device
characterization.
VOH_M P Medium, high level output voltage IOH =–2mA V
DD_HV_IOx –0.8 — — V
VOL_F P Fast, high level output voltage IOL =11mA — — 0.5 V
VOH_F P Fast, high level output voltage IOH =–11mA V
DD_HV_IOx–0.8 — — V
VOL_SYM P Symmetric, high level output
voltage IOL =1.5mA — — 0.5 V
VOH_SYM P Symmetric, high level output
voltage IOH =–1.5mA V
DD_HV_IOx–0.8 — — V
IINJ T DC injection current pe r pi n
(all bi-directional ports) —–1—1mA
IPU P Equivalent pull-up current VIN =V
IL –130 — — µA
VIN =V
IH — — –10
IPD P Equivalent pull-down current VIN =V
IL 10 — — µA
VIN =V
IH — — 130
IIL P Input leakage current
(all bidirectional ports) TJ = –40 to
+150 °C -1 — 1 A
Input leakage current
(all ADC input-only ports)4-0.25 — 0.25
Input leakage current
(shared ADC input-only ports) -0.3 — 0.3
VILR P RESET, low level input voltage — –0.12—0.35V
DD_HV_IOxV
VIHR P RESET, high level input voltage — 0.65 VDD_HV_IOx—V
DD_HV_IOx+0.12V
VHYSR D RESET, Schmitt trigger hysteresis — 0.1 VDD_HV_IOx——V
VOLR D RESET, low level output voltage IOL =2mA — — 0.5 V
IPD D RESET, equivalent pull-down
current VIN =V
IL 10 — — µA
VIN =V
IH — — 130
1These specifi ca ti o ns are design targ ets and subject to change per device characterization.
2“SR” parameter values must not exceed the absolute maxi mu m ratings shown in Table 8.
3The max input voltage on the ADC pins is the ADC reference voltage VDD_HV_ADRx.
4Measured values are applicable to all modes of the pad i.e. IBE = 0/1 and / or APC= 0/1.
Table 19. DC electrical characteristics1 (continued)
Symbol Parameter Conditions Min Typ Max Unit
MPC5643L Microcontroller Data Sheet, Rev. 9
Electrical characteristics
Freescale Semiconductor88
Table 20. Current consumption characteristics
Symbol Parameter Conditions1Min Typ Max Unit
IDD_LV_FULL
+I
DD_LV_PLL
T Operating current 1.2 V supplies
TJ=25C
VDD_LV_COR =1.32V
—— 50mA+
2.18 mA*fCPU[MHz] mA
1.2 V supplies
TJ= 150 C
VDD_LV_COR =1.32V
—— 80mA+
2.50 mA*fCPU[MHz]
IDD_LV_TYP
+I
DD_LV_PLL2T Operating current 1.2 V supplies
TJ=25C
VDD_LV_COR =1.32V
—— 26+
2.10 mA*fCPU[MHz] mA
1.2 V supplies
TJ= 150 C
VDD_LV_COR =1.32V
—— 41mA+
2.30 mA*fCPU[MHz]
IDD_LV_BIST
+I
DD_LV_PLL
T Operating current 1.2 V supplies during
LBIST (full LBIST
configuration)
TJ=25C
VDD_LV_COR =1.32V
— — 250 mA
1.2 V supplies during
LBIST (full LBIST
configuration)
TJ= 150 C
VDD_LV_COR =1.32V
— — 290
IDD_LV_TYP
+I
DD_LV_PLL2P Operating current 1.2 V supplies
TJ=25C
VDD_LV_COR =1.32V
LSM mode
— — 279 mA
TJ= 150 C
VDD_LV_COR =1.32V
LSM mode
— — 318 mA
IDD_LV_TYP +
IDD_LV_PLL2T Operating current 1.2V supplies
Tj=105C
VDD_LV_COR = 1.2V
LSM mode
— — 275 mA
1.2V supplies
Tj=125C
VDD_LV_COR = 1.2V
LSM mode
— — 299 mA
Electrical characteristics
MPC5643L Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor 89
IDD_LV_TYP +
IDD_LV_PLL2T Operating current 1.2V supplies
Tj=105C
VDD_LV_COR = 1.2V
DPM Mode
— — 189 mA
1.2V supplies
Tj=125C
VDD_LV_COR = 1.2V
DPM Mode
— — 214 mA
1.2V supplies
Tj=150C
VDD_LV_COR = 1.2V
DPM Mode
— — 235 mA
IDD_LV_STOP T Operating current in
VDD STOP mode TJ=25C
VDD_LV_COR =1.32V —— 20 mA
TT
J=55C
VDD_LV_COR =1.32V —— 57
PT
J= 150 C
VDD_LV_COR =1.32V — — 105
IDD_LV_HALT T Operating current in
VDD HALT mode TJ=25C
VDD_LV_COR =1.32V —— 25 mA
TT
J=55C
VDD_LV_COR =1.32V —— 64
PT
J= 150 C
VDD_LV_COR =1.32V —— 115
IDD_HV_ADC3,4 T Operating current TJ= 150 C
120 MHz
ADC operating at 60 MHz
VDD_HV_ADC =3.6V
—— 10 mA
IDD_HV_AREF4T Operating current TJ= 150 C
120 MHz
ADC operating at 60 MHz
VDD_HV_REF =3.6V
—— 3 mA
TJ= 150 C
120 MHz
ADC operating at 60 MHz
VDD_HV_REF =5.5V
—— 5
Table 20. Current consumption characteristics (continued)
Symbol Parameter Conditions1Min Typ Max Unit
MPC5643L Microcontroller Data Sheet, Rev. 9
Electrical characteristics
Freescale Semiconductor90
3.11 Temperature sensor electrical characteristics
3.12 Main oscillator electrical characteristics
The device provides an oscillator/resonator driver. Figure 5 describes a simple model of th e internal oscillator driver and
provides an example of a connection for an oscillator or a resonator.
IDD_HV_OSC
(oscillator
bypass mode)
T Operating current TJ= 150 C
3.3 V supplies
120 MHz
— — 900 A
IDD_HV_OSC
(crystal oscillator
mode)
D Operating current TJ= 150 C
3.3 V supplies
120 MHz
—— 3.5 mA
IDD_HV_FLASH5T Operating current TJ= 150 C
3.3 V supplies
120 MHz
—— 4 mA
IDD_HV_PMU T Operating current TJ= 150 C
3.3 V supplies
120 MHz
—— 10 mA
1Devices configured for DPM mode, single core only with Core 0 executing typical code at 120 MHz from SRAM and Core 1 in
reset. If core execution mode not specified, the device is configured for LSM mode with both cores executing typical code at
120 MHz from SRAM.
2Enabled Modules in 'Typical mode': FlexPWM0, ETimer0/1/2, CTU, SWG, DMA, FlexCAN0/1, LINFlex, ADC1, DSPI0/1, PIT,
CRC, PLL0/1, I/O supply current excluded. If DPM mode is configured, Core_0 is active while Core_1 is in reset during the
measurements.
3Internal structu re s hold the input voltage less than VDDA + 1.0 V on all pads powered by VDDA supplies, if the maximum
injection current specification is met and VDDA is within the operating voltage specifications.
4This value is the total current for both ADCs.
5VFLASH is only available in the calibration package.
Table 21. Temperature sen sor electrical characteristics
Symbol Parameter Conditions Min Max Unit
— P Accuracy TJ = –40 °C to 150 °C –10 10 °C
TSD Minimum sampli ng period — 4 — µs
Table 20. Current consumption characteristics (continued)
Symbol Parameter Conditions1Min Typ Max Unit
Electrical characteristics
MPC5643L Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor 91
Figure 5. Crystal oscillator and resonator connection scheme
NOTE
XTAL/EXTAL must not be directly used to drive external circuits.
Figure 6. Main oscillator electrical characteristics
CL
CL
Crystal
XTAL
EXTAL
RP
Resonator
XTAL
EXTAL
DEVICE
DEVICE
DEVICE XTAL
EXTAL
I
R
VDD
VXOSCHSOP
TXOSCHSSU
VXTAL
VXOSCHS
valid internal clock
90%
10%
1/fXOSCHS
MTRANS
1
0
MPC5643L Microcontroller Data Sheet, Rev. 9
Electrical characteristics
Freescale Semiconductor92
×
3.13 FMPLL electrical characteristics
Table 22. Main oscillator electrical characteristics
Symbol Parameter Conditions1
1VDD =3.3V±10%, T
J = –40 to +150 °C, unless otherwise specified.
Value Unit
Min Typ Max
fXOSCHS SR Oscillator frequency — 4.0 — 40.0 MHz
gmXOSCHS P Oscillator
transconductance VDD = 3.3 V ±10% 4.5 — 13.25 mA/V
VXOSCHS D Oscillation amplitude fOSC = 4, 8, 10, 12, 16 MHz 1.3 — — V
fOSC =40MHz 1.1 — —
VXOSCHSOP D Oscil l ation operating
point — — 0.82 — V
TXOSCHSSU T Oscillator start-up time fOSC = 4, 8, 10, 12 MHz2
2The recommended configuration for maximizing the oscillator margin are:
XOSC_MARGIN = 0 for 4 MHz quartz
XOSC_MARGIN = 1 for 8/16/40 MHz quartz
—— 6ms
fOSC =16, 40MHz
2—— 2
VIH SR Input high level CMOS
Schmitt Trigger Oscillator bypass mode 0.65 × VDD —V
DD +0.4 V
VIL SR Input low level CMOS
Schmitt Trigger Oscillator bypass mode –0.4 — 0.35 × VDD V
Table 23. FMPLL electrical charact eristics
Symbol Parameter Conditions Min Typ Max Unit
f
REF_CRYSTAL
fREF_EXT
D FMPLL reference frequency
range1Crystal reference 4 — 40 MHz
fPLL_IN D Phase detector input
frequency range (after
pre-divider)
—4—16MHz
fFMPLLOUT D Clock frequency range in
normal mode —4—120
2MHz
fFREE P Free running frequency Measured using clock division
(typically 16) 20 — 150 MHz
fsys D On-chip FMPLL frequency2—16—120MHz
tCYC D System clock period — — — 1 / fsys ns
fLORL
fLORH
D Loss of reference frequency
window3Lower limit 1.6 — 3 .7 MHz
Upper limit 24 — 56
fSCM D S elf-clocked mode
frequency4,5 —20—150MHz
tLOCK P Lock time Stable oscillator (fPLLIN = 4 MHz),
stable VDD
——200 µs
Electrical characteristics
MPC5643L Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor 93
tlpll D FMPLL lock time 6, 7 ———200s
tdc D Duty cycle of reference —40—60%
CJITTER T CLKOUT period jitter8,9,10,11 L ong-term jitter (avg. over 2 ms
interval), fFMPLLOUT maximum –6 — 6 ns
tPKJIT T Single period jitter (peak to
peak) PHI @ 120 MHz,
Input clock @ 4 MHz ——175 ps
PHI @ 100 MHz,
Input clock @ 4 MHz ——185 ps
PHI @ 80 MHz,
Input clock @ 4 MHz ——200 ps
tLTJIT T Long term jitter PHI @ 16 MHz,
Input clock @ 4 MHz ——±6 ns
fLCK D Frequency LOCK range — –6 — 6 % fFMPLLOUT
fUL D Frequency un-LOCK range — –18 — 18 % fFMPLLOUT
fCS
fDS
D Modulation depth Center spread ±0.25 — ±2.0 %
fFMPLLOUT
Down spread –0.5 — -8.0
fMOD D Modulation frequency12 — — — 100 kHz
1Considering operation with FMPLL not bypassed.
2With FM; the value does not include a possible +2% modulation
3“Loss of Reference Frequency” window is the reference frequency range outside of which the FMPLL is in self clocked
mode.
4Self clocked mode frequency is the frequency that the FMPLL operates at when the reference frequency falls outside
the fLOR window.
5fVCO is the frequency at the output of the VCO; its range is 256–512 MHz.
fSCM is the self-clocked mode frequency (free running frequency); its range is 20–150 MHz.
fSYS =f
VCOODF
6This value is determined by the crystal manufacturer and board design. For 4 MHz to 20 MHz crystals specified for this
FMPLL, load capacitors should not exceed these limits.
7This specification applies to the period required for the FMPLL to relock after changing the MFD frequency control bits
in the synthesizer control register (SYNCR).
8This value is determined by the crystal manufacturer and board design.
9Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fSYS.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal.
Noise injected into the FMPLL circuitry via VDDPLL and VSSPLL and variation in crystal oscillator frequency increase the
CJITTER percentage for a given interval.
10 Proper PC board layout procedures must be followed to ac hieve specifications.
11 Values are with frequency modulation disabled . If frequency modulation is enabled, jitter is the sum of CJITTER and
either fCS or fDS (depending on whether center spread or down spread modulation is enabled).
12 Modulation depth is attenuated from depth setting when operating at mo dulation frequencies above 50 kHz.
Table 23. FMPLL electrical characteristics (continued)
Symbol Parameter Conditions Min Typ Max Unit
MPC5643L Microcontroller Data Sheet, Rev. 9
Electrical characteristics
Freescale Semiconductor94
3.14 16 MHz RC oscillator electrical characteristics
3.15 ADC electrical characteristics
The device provides a 12-bit Successive Approximation Register (SAR) Analog-to-Digital Converter.
Figure 7 . ADC characteristics and error definitions
3.15.1 Input Impedance and ADC Accuracy
T o preserve the accuracy of the A/D converter, it is necessary that analog input pins have low AC impedance. Placing a capacitor
with good high frequency characteristics at the input pin of the device can be effective: the capacitor should be as large as
possible, ideally infinite. This capacitor contributes to attenuating the noise present on the input pin; further , it sources charge
during the sampling phase, when the analog signal source is a high-impedance source.
Table 24. 16 MHz RC oscillator electrical characteristics
Symbol C Parameter Conditions Value Unit
Min Typ Max
fRC P RC oscillator frequency TA = 25 °C — 16 — MHz
RCMVAR P Fast internal RC oscillator variation over
temperature and supply with respect to fRC at
TA= 25 °C in high-frequ ency configuration
—6— 6%
(2)
(1)
(3)
(4)
(5)
Offset Erro r OSE
Offset Erro r OSE
Gain Error G E
1 LSB (ideal)
Vin(A) (LSBideal)
(1) Example of an actual transfer curve
(2) The ideal transfer curve
(3) Differential non-linearity error (DNL)
(4) Integral non-linearity error (INL)
(5) Center of a step of the actual transfer
curve
code out
4095
4094
4093
4092
4091
4090
5
4
3
2
1
0
7
6
1 2 3 4 5 6 7 4089 4090 4091 4092 4093 4094 4095
1 LSB ideal =(VrefH-VrefL)/ 4096 =
3.3V/ 4096 = 0.806 mV
Total Unadjusted Error
TUE = +/- 6 LSB = +/- 4.84mV
Electrical characteristics
MPC5643L Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor 95
A real filter can typically be obtained by using a series resistance with a capacitor on the input pin (simple RC filter). The RC
filtering may be limited according to the value of source impedance of the transducer or circuit supplying the analog signal to
be measured. The filter at the input pins must be designed taking into account the dynamic characteristics of the input signal
(bandwidth) and the equivalen t input impedance of the ADC itself.
In fact a current sink contributor is represented by the charge sharing effects with the sampling capacitance: CS and Cp2 being
substantially a switched capacitance, with a frequency equal to the conversion rate of the ADC, it can be seen as a resistive path
to ground. For instance, assuming a conversion rate of 1 MHz, with Cp2 + CS equal to 7.5 pF , a resistance of 133 k is obtained
(REQ = 1 / (fS*(Cp2+CS)), where fS represents the conversion rate at the considered channel). To minimize the error induced
by the voltage partitioning between this resistance (sampled voltage on Cs) and the sum of RS+R
F, the external circuit must be
designed to respect the Equation 4:
Eqn. 4
Equation 4 generates a constraint for external network design, in particular on resi st iv e path. Internal switch resistances (RSW
and RAD) can be neglected with respect to external resistances.
Figure 8. Input Equivalent Circuit
A second aspect involving the capacitance network shall be considered. Assuming the three capacitances CF, CP1 and CP2 are
initially charged at the source volta ge VA (refer to the equivalent circuit reported in Figure 8): A charge sharing phenomenon is
installed when the sampling phase is started (A/D switch close).
VA
RSRF
+
REQ
---------------------
1
2
---LSB
RF
CF
RSRLRSW1
CP2
VDD Sampling
Source Filter Current Limiter
EXTERNAL CIRCUIT INTERNAL CIRCUIT SCHEME
RS Source Impedance
RF Filter Resistance
CF Filter Capacitance
RL Current Limiter Resistance
RSW1 Channel Selection Switch Impedance
RAD Sampling Switch Impedance
CP Pin Capacitance (two contributions, CP1 and CP2)
CS Sampling Capacitance
CP1
RAD
Channel
Selection
VACS
MPC5643L Microcontroller Data Sheet, Rev. 9
Electrical characteristics
Freescale Semiconductor96
Figure 9. Transient Behavior during Sampling Phase
In particular two different transient periods can be distinguished:
• A first and quick charge transfer from the internal capacitance CP1 and CP2 to the sampling capacitance CS occurs (CS
is supposed initially completely discharged): considering a worst case (since the time constant in reality would be
faster) in which CP2 is reported in parallel to CP1 (call CP = CP1 + CP2), the two capacitances CP and CS are in series,
and the time constant is
Eqn. 5
Equation 5 can again be simplified considering only CS as an additional worst condition. In reality, the transient is
faster , but the A/D converter circuitry has been designed to be robust also in the very worst case: the sampling time TS
is always much longer than the internal time constant:
Eqn. 6
The charge of CP1 and CP2 is redistributed also on CS, determining a new value of the voltage VA1 on the capacitance
according to Equation 7:
Eqn. 7
• A second charge transfer involves also CF (that is typically bigger than the on-chip capacitance) through the resistance
RL: again considering the worst case in which CP2 and CS were in parallel to CP1 (since the time constant in reality
would be faster), the time constant is:
Eqn. 8
In this case, the time constant depends on the external circuit: in particular imposing that the transient is completed
well before the end of sampling time TS, a constraints on RL sizing is obtained:
Eqn. 9
VA
VA1
VA2
t
TS
VCS Voltage Transient on CS
V <0.5 LSB
12
1 < (RSW + RAD) CS << TS
2
= R
L
(C
S
+ C
P1
+ C
P2
)
1RSW RAD
+=CPCS
CPCS
+
---------------------
1RSW RAD
+CSTS
«
VA1 CSCP1 CP2
++VACP1 CP2
+=
2RL
CSCP1 CP2
++
10 2
10 RLCSCP1 CP2
++=T
S
Electrical characteristics
MPC5643L Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor 97
Of course, RL shall be sized also according to the current limitation constraints, in combination with RS (source
impedance) and RF (filter resistance). Being CF definitively bigger than CP1, CP2 and CS, then the final voltage VA2
(at the end of the charge transfer transient) will be much higher than VA1. Equation 10 must be respected (charge
balance assuming now CS already charged at VA1):
Eqn. 10
The two transients above are not influenced by the voltage source that, due to the presence of the RFCF filter, is not able to
provide the extra charge to compensate the voltage drop on CS with respect to the ideal source VA; the time constant RFCF of
the filter is very high with respect to the sampling time (TS). The filter is typically designed to act as anti-aliasing.
Figure 10. Spectral representation of input signal
Calling f0 the bandwidth of the source signal (and as a consequence the cut-off frequency of the anti-aliasing filter, fF),
according to the Nyquist theorem the conversion rate fC must be at least 2f0; it means that the constant time of the filter is greater
than or at least equal to twice the conversion period (TC). Again the conversion period TC is longer than the sampling time TS,
which is just a portion of it, even when fixed channel continuous conversion mode is sel ected (fastest conversion rate at a
specific channel): in conclusion it is evident that the time constant of the filter RFCF is definitively much higher th an the
sampling time TS, so the charge level on CS cannot be modified by the analog signal source during the time in which the
sampling switch is closed.
The considerations above lead to impose new constraints on the external circuit, to reduce the accuracy error due to the voltage
drop on CS; from the two charge balance equations above, it is simple to derive Equation 11 between the ideal and real sampled
voltage on CS:
Eqn. 11
From this formula, in the worst case (when VA is maximum, that is for instance 5 V), assuming to accept a maximum error of
half a count, a constraint is evident on CF value:
Eqn. 12
VA2 CSCP1 CP2 CF
+++VACF
VA1
+C
P1 CP2
+C
S
+=
f0f
Analog Source Bandwidth (VA)
f0f
Sampled Signal Spectrum (fC = conversion Rate)
fC
f
Anti-Aliasing Filter (fF = RC Filter pole)
fF
2 f0 fC (Nyquist)
fF f0 (Anti-aliasing Filtering Condition)
TC 2 RFCF (Conversion Rate vs. Filter Pole)
Noise
VA2
VA
------------CP1 CP2
+C
F
+
CP1 CP2
+C
FCS
++
--------------------------------------------------------=
CF8192 CS
MPC5643L Microcontroller Data Sheet, Rev. 9
Electrical characteristics
Freescale Semiconductor98
Table 25. ADC conversion characteristics
Symbol Parameter Conditions1
1TJ = –40 to +150 °C, unless otherwise specified and analog input voltage from VAGND to VAREF.
Min Typ Max Unit
fCK SR ADC Clock frequency (depends on ADC
configuration)
(The duty cycle depends on AD_CK2
frequency)
2AD_CK clock is always half of the ADC module input clock defined via the auxiliary clock divider for the ADC.
—3—60MHz
fsSR Sampling frequency — — — 983.6
3
3This is the maximum frequency that the analog portion of the ADC can attain. A sustained conversion at this frequency is not
possible.
KHz
tsample D Sample time460 MHz 383 — — ns
teval D Evaluation time5 60 MHz 600 — — ns
CS6D ADC input sampling capacitance — — — 7.32 pF
CP16D ADC input pin capacitance 1 — — — 5(7) pF
CP26D ADC input pin capacitance 2 — — — 0.8 pF
RSW16D Internal resistance of analog source VREF range = 4.5 to 5.5 V — — 0.3 k
VREF range = 3.0 to 3.6 V — — 875
RAD6D Internal resistance of analog source — — — 825
INL P Integral non linearity — –3 — 3 LSB
DNL P Differential non linearity8—–1—2LSB
OFS T Offset error — –6 — 6 LSB
GNE T Gain error — –6 — 6 LSB
IS1WINJ (single ADC channel)
C Max positive/negative injection –3 — 3 mA
IS1WWINJ (double ADC channel)
C Max positive/negati ve injection |Vref_ad0 - Vref_ad1| <
150mV –3.6 — 3.6 mA
SNR T Signal-to-noise ratio Vref = 3.3V 67 — — dB
SNR T Signal-to-noise ratio Vref = 5.0V 69 — — dB
THD T Total harmonic distortion — -65 — — dB
SINAD T Signal-to-noise an d distortion — 65 — — dB
ENOB T Effective number of bits — 10.5 — — bits
TUEIS1WINJ T T otal unadjusted error for IS1WINJ (single ADC
channels) Without current injection –6 — 6 LSB
With current injection –8 — 8 LSB
TUEIS1WWINJ P Total unadjusted error for IS1WW INJ (double
ADC channels) Without current injection –8 — 8 LSB
T With current injection –10 — 10 LSB
Electrical characteristics
MPC5643L Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor 99
3.16 Flash memory electrical characteristics
4During the sample time the input capacitance CS can be charged/discharged by the external source. The internal resistance
of the analog source must allow the capacitance to reach its final voltage level within tsample. After the end of the sample time
tsample, changes of the analog input voltage have no effect on the conversion result. Values for the sample clock tsample depend
on programming.
5This parameter does not include the sample time Tsample, but only the time for determining the digital result.
6See Figure 8.
7For the 144-pin package
8No missing codes
Table 26. Flash memory prog ram an d eras e el ec tric a l spec if ic at io n s
No. Symbol Parameter Typ1
1Typical program and erase times represent the median performance and assume nominal supply values
and operation at 25C. These values are characterized, but not tested.I
Initial
Max2
2Initial Max program and erase times provide guidance for time-out limits used in the factory and apply for
<100 program/erase cycles, nominal supply values and operation at 25C. These values are verified at
production test.
Lifetime
Max3
3Lifetime Max program and erase times apply across the voltage, temperature, and cycling range of product
life. These values are characterized, but not tested.
Unit
1T
DWPROGRAM *4
4Program times are actual hardware programming times and do not include software overhead.
Double word (64 bits) program time4 30 — 500 µs
2T
PPROGRAM *4Page(128 bits) program time440 160 500 µs
3T
16KPPERASE *416 KB block pre-program and era s e time 250 1000 5000 ms
4T
48KPPERASE *448 KB block pre-program and era s e time 400 1500 5000 ms
5T
64KPPERASE *464 KB block pre-program and era s e time 450 1800 5000 ms
6T
128KPPERASE *4128 KB block pre-program and erase time 800 2600 7500 ms
7T
256KPPERASE *4256 KB block pre-prog ram and erase time 1400 5200 15000 ms
Table 27. Flash memory timing
Symbol Parameter Value Unit
Min Typ Max
TRES D Time from clearing the MCR-ESUS or PSUS bit with EHV = 1
until DONE goes low — — 100 ns
TDONE D Time from 0 to 1 transition on the MCR-EHV bit initiating a
program/erase until the MCR-DONE bit is cleared —— 5ns
TPSRT D T ime between program suspend resume and the next program
suspend request.1100 — — s
TESRT D Time between erase suspend resume and the next erase
suspend request.210 ms
MPC5643L Microcontroller Data Sheet, Rev. 9
Electrical characteristics
Freescale Semiconductor100
3.17 SWG electrical characteristics
1Repeated suspend s at a high frequency may result in the operation timing out, and the flash module will
respond by completing the operation with a fail code (MCR[PEG] = 0), or the operation not able to finish
(MCR[DONE] = 1 during Program operation). The minimum time between suspends to ensure this does not
occur is TPSRT.
2If Erase suspend rate is less than TESRT, an increase of slope voltage ramp occurs
during erase pulse. This improves erase time but reduces cycling figure due to
overstress
Table 28. Flash memory module life
No. Symbol Parameter
Value
Unit
Minimu
mTypical Maximum
1 P/E C Number of program/erase cycles per block for 16 KB, 48 KB,
and 64 KB blocks over the operating temper ature range1
1Operating temperature range is TJfrom –40 °C to 150 °C. Typical endurance is evaluated at 25 C. Product qualification
is performed to the minimum specification. For additional information on the Freescale definition of T ypical Endurance,
please refer to Eng i n ee ri n g Bul l e ti n EB619, Typical Endurance for Nonvolatile Memory.
100000 — — cycles
2 P/E C Number of program/erase cycles per block for 128 KB and
256 KB blocks over the operating temperature range11000 1000002
2Typical P/E cycles is 100,000 cycles for 128 KB and 256 KB blocks. For additional information on the Freescale
definition of T ypical Endurance, please refer to Engineering Bulletin EB619, T ypical Endurance for Nonvolatile Memory .
— cycles
3 Retention C
Minimum data retention at 85 °C average ambient temperature
3
Blocks with 0–1,000 P/E cycles
Blocks with 1,001–10,000 P/E cycles
Blocks with 10,001–100,00 0 P/E cycles
3Ambient temperature averaged over duration of applica ti on, not to exceed product operating temperature rang e.
20
10
5
—
—
—
—
—
—
years
Table 29. MPC5643L SWG Specifications
Symbol Parameter Value
Minimum Typical Maximum
T Input clock 12 MHz 16 MHz 20 MHz
T Frequency Range 1kHz — 50 kHz
T Peak to Peak10.4 V — 2.0V
T Peak to Peak variation2-6% — 6%
T Common Mode3— 1.3 V —
T Common Mode variation -6% — 6%
Electrical characteristics
MPC5643L Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor 101
3.18 AC specifications
3.18.1 Pad AC specifications
TSiNAD
445 dB — —
T Load C 25 pF — 100 pF
T Load I 0 A — 100 A
T ESD Pad Resistance5230 — 360
1Peak to Peak value is measured with no R or I load.
2Peak to Peak excludes noise, SiNAD must be considered.
3Common mode value is measured with no R or I load.
4SiNAD is measured at Max Peak to Peak voltage.
5Internal device routing resistance. ESD pad resistance is in series and must be considered for max Peak to Peak
voltages, depending on application I load and/or R load.
Table 30. Pad AC specifications (3.3 V , IPP_HV E = 0 )1
1Propagation delay from VDD_HV_IOx/2 of internal signal to Pchannel/Nchannel switch-on condition.
No. Pad
Tswitchon1
(ns) Rise/Fall2
(ns)
2Slope at rising/falling edge.
Frequency
(MHz) Current slew3
(mA/ns)
3Data based on characterization results, not tested in production.
Load drive
(pF)
Min Typ Max Min Typ Max Min Typ Max Min Typ Max
1 Slow T3 —40——40—— 40.01— 2 25
3 —40——50—— 20.01— 2 50
3 — 40 — — 75 — — 2 0.01 — 2 100
3 — 40 — — 100 — — 2 0.01 — 2 200
2 Medium T 1 — 15 — — 12 — — 40 2.5 — 7 25
1 — 15 — — 25 — — 20 2.5 — 7 50
1 — 15 — — 40 — — 13 2.5 — 7 100
1 — 15 — — 70 — — 7 2.5 — 7 200
3 Fast T 1 — 6 — — 4 — — 72 3 — 40 25
1—6——7——557—40 50
1—6——12——407—40 100
1—6——18——257—40 200
4SymmetricT1 — 8 ——5——50 3 —25 25
Table 29. MPC5643L SWG Specifications
Symbol Parameter Value
Minimum Typical Maximum
MPC5643L Microcontroller Data Sheet, Rev. 9
Electrical characteristics
Freescale Semiconductor102
Figure 11. Pad output delay
3.19 Reset sequence
This section shows the duration for different reset sequences. It describes the dif ferent reset se quences and it s pecifies the start
conditions and the end indication for the reset sequences.
3.19.1 Reset sequence duration
Table 31 specifies the minimum and the maximum reset sequence duration for the five different reset sequences described in
Section 3.19.2, Reset sequence description.
3.19.2 Reset sequence description
The figures in this section show the internal states of the chip during the five different reset sequences. The doted lines in the
figures indicate the starting point and the end point for which the duration is specified in Table 31. The start point and end point
Table 31. RESET sequences
No. Symbol Parameter Conditions TReset Unit
Min Typ Max1
1The maximum value is applicable only if the reset sequence duration is not prolonged by an extended assertion of RESET
by an external reset generator.
1T
DRB CC Destructive Reset Sequence, BIST enabled 28 34 39 ms
2T
DR CC Destructive Reset Sequence, BIST disabled — 500 4200 50 00 s
3T
ERLB CC External Reset Sequence Long, BIST enabled 28 32 37 ms
4T
FRL CC Functional Reset Sequence Long — 35 150 400 s
5T
FRS CC Functional Reset Sequence Short — 1 4 10 s
VDDE/2
VOH
VOL
Rising
Edge
Output
Delay
Falling
Edge
Output
Delay
Pad
Data Input
Pad
Output
Electrical characteristics
MPC5643L Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor 103
conditions as well as the reset trigger mappin g to the different reset sequences is specified in Section 3.19.3, Reset sequence
trigger mapping.
With the beginning of DRUN mode the first instruction is fetched and executed. At this point application execution starts and
the internal reset sequence is finished.
The figures below show the internal states of the chip during the execution of the reset sequence and the possible states of the
signal pin RESET.
NOTE
RESET is a bidirectional pin. The voltage level on this pin can either be driven low by an
external reset generator or by the chip internal reset circuitry. A high level on this pin can
only be generated by an external pull up resistor which is stro ng enough to overdrive the
weak internal pull down resistor. The rising edge on RESET in the followin g fig ures
indicates the time when the device stops driving it low. The reset sequence durations given
in table Table 31 are applicable only if the intern al reset sequence is not prolonged by an
external reset generator keeping RESET asserted low beyond the last PHASE3.
Figure 12. Destructive Reset Sequence, BIST enabled
Figure 13. Destructive Reset Sequence, BIST disabled
PHASE3 BISTPHASE1,2PHASE0 PHASE1,2 PHASE3
Establish IRC
and PWR Flash init Device
Config Self Test
Setup
DRUN
LBISTMBIST Flas h i nit Device
Config Application
Execution
TDRB, min < TReset < TDRB, max
Reset Sequence Start Condition
Reset Sequence Trigger
RESET_B
RESET
PHASE3PHASE1,2PHASE0
Establish IRC
and PWR Flash init Device
Config
DRUN
Application
Execution
TDR, min < T Reset < TDR, max
Reset Sequence Trigger
Reset Sequence Start Condition
RESET_B
RESET
MPC5643L Microcontroller Data Sheet, Rev. 9
Electrical characteristics
Freescale Semiconductor104
Figure 14. External Reset Sequence Long, BIST enabled
Figure 15. Functional Reset Sequence Long
Figure 16. Functional Reset Sequence Short
PHASE3 BISTPHASE1,2 PHASE1,2 PHASE3
Flash init Device
Config Self Test
Setup
DRUN
LBISTMBIST Flash ini t Device
Config Application
Execution
TERLB, min < TReset < TERLB, max
Reset Sequ ence Trigger
Reset Sequence Start Condition
RESET_B
RESET
PHASE3PHASE1,2
Flash init Device
Config
DRUN
Application
Execution
TFRL, min < TReset < TFRL, max
Reset Sequence Trigger
Reset Sequence Start Condition
RESET_B
RESET
PHASE3 DRUN
Application
Execution
TFRS, min < TReset < TFRS, max
Reset Sequence Trigger
Reset Sequence Start Condit ion
RESET_B
RESET
Electrical characteristics
MPC5643L Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor 105
The reset sequences shown in Figure 15 and Figure 16 are triggered by function al reset events. RESET is driven low during
these two reset sequences only if the corresponding functional reset source (which triggered the reset sequence) was enabled to
drive RESET low for the duration of the internal reset sequence1.
3.19.3 Reset sequence trigger mapping
The following table shows the possible trigger events for the different reset sequences. It specifies the reset sequence start
conditions as well as the reset sequence end indications that are the basis fo r the timing data provided in Table 31.
1.See RGM_FBRE register for more details.
Table 32. Reset sequence trigger — reset sequence
Reset
Sequence
Trigger
Reset
Sequence
Start
Condition
Reset
Sequence
End
Indication
Reset Sequence
Destructiv
e Reset
Sequence,
BIST
enabled1
1Whether BIST is executed or not depends on the chip configuration data stored in the shadow sector of the NVM.
Destructiv
e Reset
Sequence,
BIST
disabled1
External
Reset
Sequenc
e Long,
BIST
enabled
Functiona
l Reset
Sequenc
e Long
Functiona
l Reset
Sequenc
e Short
All internal
destructive reset
sources
(LVDs or internal
HVD during
power-up and
during
operation)
Section 3.1
9.4.1,
Destructive
reset
Release of
RESET2
2End of the internal reset sequence (as specified in Table 31) can only be observed by release of RESET if it is not
held low externally beyo nd the end of the internal sequence which would prolong the internal reset PHASE3 till
RESET is released externally.
triggers cannot
trigger cannot
trigger cannot
trigger
Assertion of
RESET3
3The assertion of RESET can only trigger a reset sequence if the device was running (RESET released) before.
RESET does not gate a Destructive Reset Sequence, BIST enabled or a Destructive Reset Sequence, BIST
disabled. However, it can prolong these sequences if RESET is held low externally beyond the end of the internal
sequence (beyond PHASE3).
Section 3.1
9.4.2,
External
reset via
RESET
cannot trigger triggers4triggers5triggers6
All internal
functional reset
sources
configured for
long reset
Sequence
starts with
internal
reset
trigger
Release of
RESET7cannot trigger can not
trigger triggers cannot
trigger
All internal
functional reset
sources
configured for
short reset
cannot trigger cannot
trigger cannot
trigger triggers
MPC5643L Microcontroller Data Sheet, Rev. 9
Electrical characteristics
Freescale Semiconductor106
3.19.4 Reset sequence — start condition
The impact of the voltage thresholds on the starting point of the internal reset sequence are becoming important if the voltage
rails / signals ramp up with a very slow slew rate compared to the overall reset sequence duration.
3.19.4.1 Destructive reset
Figure 17 shows the voltage threshold that determines the start of the Destructive Reset Sequence, BIST enabled and the start
for the Destructive Reset Sequence, BIST disabled.
Figure 17. Reset sequence start for Destructive Resets
3.19.4.2 External reset via RESET
Figure 18 shows the voltage th resholds that determine the start of the reset sequences initiated by the assertion of RESET as
specified in Table 32.
4If RESET is configured for long reset (default) and if BIST is enabled via chip configuration data stored in the
shadow sector of the NVM.
5If RESET is configured for long reset (default) and if BIST is disabled via chip configuration data stored in the
shadow sector of the NVM.
6If RESET is configured for short reset
7Internal reset sequence can only be observed by state of RESET if bidirectional RESET functionality is enabled for
the functional reset source which triggered the reset sequence.
Table 33. Voltage Thresholds
Variable name Value
Vmin Refer to Table 18
Vmax Refer to Table 18
Supply Rail VDD_HV_PMU
TReset, max starts here
TReset, min starts here
Supply Rail
Vmax
t
V
Vmin
Electrical characteristics
MPC5643L Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor 107
Figure 18. Reset sequence start via RESET assertion
3.19.5 External watchdog window
If the application design requires the use of an external watchdog the data provided in Section 3.19, Reset sequence can be used
to determine the correct positioning of the trigger window for the external watchdog. Figure 19 shows the relationships between
the minimum and the maximum duration of a given reset sequence and the position of an external watchdog trigg e r window.
Figure 19. Reset sequence - External watchdog trigger window position
3.20 AC timing characteristics
AC Test Timing Conditions: Unless otherwise noted, all test conditions are as follows:
• TJ = –40 to 150 C
• Supply voltages as specified in Table 9
TReset, max starts here
TReset, min starts here
RESET_B
0.65 * VDD_HV_IO
t
V
0.35 * VDD_HV_IO
RESET
External Watchdog Window Closed
Earliest
Application
Start
Latest
Application
Start
Internal Reset Sequence
Start condition (signal or voltage rail)
External Watchdog Window Open
TReset, min
TReset, max
TWDStart, min
TWDStart, max External Watchdog Window Closed
External Watchdog Window Open
Basic Application Init
Basic Application Init
Application time required to
prepare watchdog trigger
Watchdog needs to be triggered within this window
Watchdog trigger
Application Running
Application Running
MPC5643L Microcontroller Data Sheet, Rev. 9
Electrical characteristics
Freescale Semiconductor108
• Input conditions: All Inp uts: tr, tf = 1 ns
• Output Loading: All Outputs: 50 pF
3.20.1 RESET pin characteristics
The MPC5643L implements a dedicated bidirectional RESET pin.
Figure 20. Start-up reset requirements
Figure 21. Noise filtering on reset signal
VIL
VDD
device reset forced by RESET
VDDMIN
RESET
VIH
device start-up ph ase
VRESET
VIL
VIH
VDD
filtered by
hysteresis filtered by
lowpass filter
WFRST WNFRST
hw_rst
‘1’
‘0’
filtered by
lowpass filter
WFRST
unknown reset
state device under hardware reset
Electrical characteristics
MPC5643L Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor 109
3.20.2 WKUP/NMI timing
3.20.3 IEEE 1149.1 JTAG interface timing
Table 34. RESET electrical characteristics
No. Symbol Parameter Conditions1
1VDD = 3.3 V ± 10%, TJ = –40 to +150 °C, unless otherwise specified
Min Typ Max Unit
1T
tr D Output transition time output pin2
2CL includes device and package capacitance (CPKG <5pF).
CL= 25pF — — 12 ns
CL= 50pF — — 25
CL= 100pF — — 40
2W
FRST P nRESET input filtered pulse — — — 40 ns
3W
NFRST P nRESET input not filtered pulse — 500 — — ns
Table 35. WKUP/NMI glitch filter
No. Symbol Parameter Min Typ Max Unit
1W
FNMI D NMI pulse width that is rejected — — 45 ns
2W
NFNMI D NMI pulse width that is passed 205 — — ns
Table 36. JTAG pin AC electrical characteristics
No. Symbol Parameter Conditions Min Max Unit
1t
JCYC D TCK cycle time — 62.5 — ns
2t
JDC D TCK clock pulse width (measured at VDDE/2) — 40 60 %
3t
TCKRISE D TCK rise and fall times (40%–70%) — — 3 ns
4t
TMSS, tTDIS D TMS, TDI data setup time — 5 — ns
5t
TMSH, tTDIH D TMS, TDI data hold time — 25 — ns
6t
TDOV D TCK low to TDO data valid — — 20 ns
7t
TDOI D TCK low to TDO data invalid — 0 — ns
8t
TDOHZ D TCK low to TDO high impedance — — 20 ns
11 tBSDV D TCK falling edge to output valid — — 50 ns
12 tBSDVZ D TCK falling edge to output valid out of high impedance — — 50 ns
13 tBSDHZ D TCK falling ed ge to output high impedance — — 50 ns
14 tBSDST D Boundary scan input valid to TCK rising edge — 50 — ns
15 tBSDHT D TCK rising edge to boundary scan input invalid — 50 — ns
MPC5643L Microcontroller Data Sheet, Rev. 9
Electrical characteristics
Freescale Semiconductor110
Figure 22. JTAG test clock input timing
Figure 23. JTAG test access port timing
TCK
1
2
2
3
3
TCK
4
5
6
78
TMS, TDI
TDO
Electrical characteristics
MPC5643L Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor 111
Figure 24. JTAG boundary scan timing
3.20.4 Nexus timing
Table 37. Nexus debug port timing1
1JTAG specifications in this table apply when used for debug functionality. All Nexus timing relative to MCKO is
measured from 50% of MCKO and 50% of the respective signal.
No. Symbol Parameter Conditions Min Max Unit
1t
MCYC D MCKO Cycle Time — 15.6 — ns
2t
MDC D MCKO Duty Cycle — 40 60 %
3t
MDOV D MCKO Low to MDO, MSEO, EVTO Data Valid2
2For all Nexus modes except DDR mode, MDO, MSEO, and EVT O data is held valid until next MCKO low cycle.
— –0.1 0.25 tMCYC
4t
EVTIPW DEVTI Pulse Width — 4.0 — tTCYC
5t
EVTOPW DEVTO Pulse Width — 1 tMCYC
6t
TCYC D TCK Cycle Time3— 62.5 — ns
7t
TDC D TCK Duty Cycle — 40 60 %
8t
NTDIS, tNTMSS D TDI, TMS Data Setup Time — 8 — ns
9
t
NTDIH,
t
NTMSH
D TDI, TMS Data Hold Time 5 — ns
10 tJOV D TCK Low to TDO/RDY Data Valid 0 25 ns
TCK
Output
Signals
Input
Signals
Output
Signals
11
12
13
14
15
MPC5643L Microcontroller Data Sheet, Rev. 9
Electrical characteristics
Freescale Semiconductor112
Figure 25. Nexus output timing
Figure 26. Nexus EVTI Input Pulse Width
3The system clock frequency needs to be fou r times faster than the TCK frequency.
1
2
MCKO
MDO
MSEO
EVTO Output Data Valid
3
5
4
EVTI
Electrical characteristics
MPC5643L Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor 113
Figure 27. Nexus Double Data Rate (DDR) Mode output timing
MCKO
MDO, MSEO
MDO/MSEO data are valid during MCKO rising and falling edge
MPC5643L Microcontroller Data Sheet, Rev. 9
Electrical characteristics
Freescale Semiconductor114
Figure 28. Nexus TDI, TMS, TDO timing
3.20.5 External interrupt timing (IRQ pin)
Table 38. External interrupt timing
No. Symbol Parameter Conditions Min Max Unit
1t
IPWL D IRQ pulse width low — 3 — tCYC
2t
IPWH D IRQ pulse width high — 3 — tCYC
3t
ICYC D IRQ edge to edge ti me1
1Applies when IRQ pins are configured for rising edge or falling edge events, but not both.
—6—t
CYC
TDO/RDY
8
9
TMS, TDI
10
TCK
6
7
Electrical characteristics
MPC5643L Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor 115
Figure 29. External interrupt timing
3.20.6 DSPI timing
Table 39. DSPI timing
No. Symbol Parameter Conditions Min Max Unit
1t
SCK D DSPI cycle time Master (MTFE = 0) 62 — ns
DSlave (MTFE=0)
62 —
D Slave Receive Only Mode116 —
2t
CSC D PCS to SCK delay — 16 — ns
3t
ASC D Aft er SCK delay — 16 — ns
4t
SDC D SCK duty cycle — tSCK/2 - 10 tSCK/2 + 10 ns
5t
AD Slave access time SS active to SOUT valid — 40 ns
6t
DIS D Slave SOUT disable time SS inactive to SOUT High-Z or invalid — 10 ns
7t
PCSC D PCSx to PCSS time — 13 — ns
8t
PASC DPCSS to PCSx time — 13 — ns
9t
SUI D Data setup time for inputs Master (MTFE = 0) 20 — ns
Slave 2—
Master (MTFE = 1, CPHA = 0) 5—
Master (MTFE = 1, CPHA = 1) 20 —
10 tHI D Data hold time for inputs Master (MTFE = 0) –5 — ns
Slave 4 —
Master (MTFE = 1, CPHA = 0) 11 —
Master (MTFE = 1, CPHA = 1) –5 —
11 tSUO D Data valid (after SCK edge) Master (MTFE = 0) — 4 ns
Slave — 23
Master (MTFE = 1, CPHA = 0) — 12
Master (MTFE = 1, CPHA = 1) — 4
IRQ
1
2
3
MPC5643L Microcontroller Data Sheet, Rev. 9
Electrical characteristics
Freescale Semiconductor116
Figure 30. DSPI classic SPI timing — master, CPHA = 0
12 tHO D Data hold time for outputs Master (MT FE = 0) –2 — ns
Slave 6 —
Master (MTFE = 1, CPHA = 0) 6 —
Master (MTFE = 1, CPHA = 1) –2 —
1Slave Receive Only Mode can operate at a maximum frequency of 60 MHz. In this mode, the DSPI can receive data
on SIN, but no valid data is transmitted on SOUT.
Ta bl e 39. DSPI timing (con t in u ed )
No. Symbol Parameter Conditions Min Max Unit
Data Last Data
First Data
First Data Data Last Data
SIN
SOUT
PCSx
SCK Output 4
9
12
1
11
10
4
SCK Output
(CPOL=0)
(CPOL=1)
3
2
Note: The numbers shown are referenced in Table 39.
Electrical characteristics
MPC5643L Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor 117
Figure 31. DSPI classic SPI timing — master, CPHA = 1
Figure 32. DSPI classic SPI timing — slave, CPHA = 0
Data Last Data
First Data
SIN
SOUT
12 11
10
Last Data
Data
First Data
SCK Output
SCK Output
PCSx
9
(CPOL=0)
(CPOL=1)
Note: The numbers shown are referenced in Table 39.
Last Data
First Data
3
4
1
Data
Data
SIN
SOUT
SS
4
5 6
9
11
10
12
SCK Input
First Data Last Data
SCK Input
2
(CPOL=0)
(CPOL=1)
Note: The numbers shown are referenced in Table 39.
MPC5643L Microcontroller Data Sheet, Rev. 9
Electrical characteristics
Freescale Semiconductor118
Figure 33. DSPI classic SPI timing — slave, CPHA = 1
Figure 34. DSPI modified transfer format timing — master, CPHA = 0
5 6
9
12
11
10
Last Data
Last Data
SIN
SOUT
SS
First Data
First Data
Data
Data
SCK Input
SCK Input
(CPOL=0)
(CPOL=1)
Note: The numbers shown are referenced in Table 39.
PCSx 3
1
4
10
4
9
12 11
SCK Output
SCK Output
SIN
SOUT
First Data Data Last Data
First Data Data Last Data
2
(CPOL=0)
(CPOL=1)
Note: The numbers shown are referenced in Table 39.
Electrical characteristics
MPC5643L Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor 119
Figure 35. DSPI modified transfer format timing — master, CPHA = 1
Figure 36. DSPI modified transfer format timing – slave, CPHA = 0
PCSx
10
9
12 11
SCK Output
SCK Output
SIN
SOUT
First Data Data Last Data
First Data Data Last Data
(CPOL=0)
(CPOL=1)
Note: The numbers shown are referenced in Table 39.
Last Data
First Data
3
4
1
Data
Data
SIN
SOUT
SS
4
5 6
9
11
10
SCK Input
First Data Last Data
SCK Input
2
(CPOL=0)
(CPOL=1)
12
Note: The numbers shown are referenced in Table 39.
MPC5643L Microcontroller Data Sheet, Rev. 9
Package characteristics
Freescale Semiconductor120
Figure 37. DSPI modified transfer format timing — slave, CPHA = 1
Figure 38. DSPI PCS strobe (PCSS) timing
4 Package characteristics
4.1 Package mechanical data
5 6
9
12
11
10
Last Data
Last Data
SIN
SOUT
SS
First Data
First Data
Data
Data
SCK Input
SCK Input
(CPOL=0)
(CPOL=1)
Note: The numbers shown are referenced in Table 39.
PCSx
78
PCSS
Note: The numbers shown are referenced in Table 39.
Package characteristics
MPC5643L Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor 121
Figure 39. 144 LQFP package mechanic al drawing (1 of 2)
MPC5643L Microcontroller Data Sheet, Rev. 9
Package characteristics
Freescale Semiconductor122
Figure 40. 144 LQFP package mechanic al drawing (2 of 2)
Package characteristics
MPC5643L Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor 123
Figure 41. 257 MAPBGA package mechanic al drawing (1 of 2)
MPC5643L Microcontroller Data Sheet, Rev. 9
Package characteristics
Freescale Semiconductor124
Figure 42. 257 MAPBGA package mechanical drawing (2 of 2)
Ordering information
MPC5643L Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor 125
5 Ordering information
Figure 43. Commercial product code structure
Table 40. Orderable part number summary
Part number1Flash/SRAM Package Speed
(MHz)2Other features
SPC5643LFF2MLQ1 1 MB/128 KB 144 LQFP (Pb free) 120 FlexRay
–40–125 C
SPC5643LFF2MMM1 1 MB/128 KB 257 MAPBGA (Pb free) 120 FlexRay
–40–125 C
SPC5643LF2MLQ1 1 MB/128 KB 144 LQFP (Pb free) 120 No FlexRay
–40–125 C
SPC5643LF2MMM1 1 MB/128 KB 257 MAPBGA (Pb free) 120 No FlexRay
–40–125 C
SPC5643LFF2VLQ1 1 MB/128 KB 144 LQFP (Pb free) 120 FlexRay
–40–105 C
SPC5643LFF2VMM1 1 MB/128 KB 257 M APBGA (Pb free) 120 FlexRay
–40–105 C
SPC5643LF2VLQ1 1 MB/128 KB 144 LQFP (Pb free) 120 No FlexRay
–40–105 C
SPC5643LF2VMM1 1 MB/128 KB 257 MAPBGA (Pb free) 120 No FlexRay
–40–105 C
SPC5643LFF2MLQ8 1 MB/128 KB 144 LQFP (Pb free) 80 FlexRay
–40–125 C
SPC5643LFF2MMM8 1 MB/128 KB 257 MAPBGA (Pb free) 80 FlexRay
–40–125 C
5643LMPC F LQ
1
Note: Not all options are available on all devices. See Table 40.
F2
Qualification status
Core code (Power Architecture)
Device number
F=FlexRay
Fab and mask identifier
Package identifier
Tape and reel status
Temperature range
M = –40 °C to 125 °C
Package identifier
LQ = 144 LQFP
Operating frequency
1=120MHz
Tape and reel status
R = Tape and reel
(blank) = Trays
Qualification status
P = Pre-qualification
M = Fully spec. qualified, general market flow
S = Fully spec. qualified, automotive flow
(blank) = No FlexRay
M
Temperature range
V = –40 °C to 105 °C MM = 257 MAPBGA
R
Operating frequency
8=80MHz
MPC5643L Microcontroller Data Sheet, Rev. 9
Document revision history
Freescale Semiconductor126
6 Document revision history
Table 41 summarizes revisions to this document.
SPC5643LF2MLQ8 1 MB/128 KB 144 LQFP (Pb free) 80 No FlexRay
–40–125 C
SPC5643LF2MMM8 1 MB/128 KB 257 MAPBGA (Pb free) 80 No FlexRay
–40–125 C
SPC5643LFF2VLQ8 1 MB/128 KB 144 LQFP (Pb free) 80 FlexRay
–40–105 C
SPC5643LFF2VMM8 1 MB/128 KB 257 MAPBGA (Pb free) 80 FlexRay
–40–105 C
SPC5643LF2VLQ8 1 MB/128 KB 144 LQFP (Pb free) 80 No FlexRay
–40–105 C
SPC5643LF2VMM8 1 MB/128 KB 257 MAPBGA (Pb free) 80 No FlexRay
–40–105 C
1All packaged devices are SPC, rather than MPC or SPC, until product qualifications are complete.
The unpackaged device prefix is PCC, rather than SCC, until product qualification is comple te.
Not all configurations are available in the SPC parts.
2This speed rating doe s not include the ±2% for frequency modulation.
Table 41. Revision history
Revision Date Description of chan ges
1 2 Mar 2009 Initial release.
2 5 May 2009 Updated, Advance Information.
—Revised SINAD/SNR specifications.
— Updated pinout and pin multiplexing information.
3 5 Oct 2009 Updated, Advance Information, Public release.
— Throughout this document, added information for 257 MAPBGA package.
— Updated Table 1, MPC5643L device summary.
— Updated Section 1.3, Feature Details.
— Updated pin-out and pin mu ltiplexing tables.
— In Section 3, Electrical characteristics, added symbols for signal characterization
methods.
— In Table 8, updated maximum ratings.
— In Table 10 and Table 11, removed moving-air thermal characteristics.
— Updated Section 3.8, Voltage regulator electrical characteristics.
— Updated Section 3.14, ADC electrical characteristics.
— Updated Section 3.15, Flash memory electrical characteristics.
— Updated Section 3.17.1, RESET pin characteristics.
— Removed External interrupt timing (IRQ pin) timing specifications.
— Updated Section 3.17.6, DSPI timing.
— Updated Section 5, Ordering info rmation.
Table 40. Orderable part number summary (continued)
Part number1Flash/SRAM Package Speed
(MHz)2Other features
Document revision history
MPC5643L Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor 127
4 2 Mar 2010 Editorial changes and improvements.
Revised the 257-pin package pin pitch (was 1.4 mm, is 0.8 mm).
In the Overview section:
• Renamed the peripheral bridge to “PBRIDGE”.
• Revised the information for FlexRay.
• Revised the “Clock, reset, power, mode and test control module” section.
• Revised the “Platform memory access time summary” table and replaced TBDs by
meaningful values.
Extensive revisions to signal descriptions and pi n muxing information.
In the “ conditions (3.3 V)” table, changed the specification for VDD_HV_ADR0 and
VDD_HV_ADR1 (was “...3.3 V”, is “...3.6 V”).
Revised the “EMI testing specifications” table.
In the “HPREG1, HPREG2, Main LVDs, Digital HVD, and Digital LVD electrical
specifications” table, added a specification for the digital low voltage detector upper
threshold.
Revised the “FMPLL electrical characteristics” table.
In the “Main oscillator electrical characteristics” table, changed the maximum specification
for gmXOSCHS (was 11 mA/V, is 11.8 mA/V).
Revised the “ADC el ect r i cal characteristics” section.
In the “ADC conversion characteristics” table:
• Changed the tADC_S specification (was TBD, is minimum of 383 ns).
• Added the footnote “No missing codes” to the DNL specification.
• Added specifications for SNR, THD, SINAD, and ENOB.
Revised the “Ordering information” section.
Table 41. Revision history (continued)
Revision Date Description of chan ges
MPC5643L Microcontroller Data Sheet, Rev. 9
Document revision history
Freescale Semiconductor128
5 31 Aug 2010 Editorial changes and improvements.
Revised the Overview section.
Replaced references to PowerPC with references to Power Architecture.
In the feature summary , changed “As much as 128 KB on-chip SRAM” to “128 KB on-chip
SRAM”.
In the “Feature details” section:
• In the “On-chip SRAM with ECC” section, added information about required RAM wait
states.
• In the PIT section, deleted “32-bit counter for real time interrupt, clocke d from main
external oscillator” (not supported on this device).
• In the flash-memory section, changed “16 KB Test” to “16 KB test sector”, revise d the
wait state information, and deleted the associated Review_Q&A content.
• In the SRAM section, revised the wait state information.
In the 144-pin pinout diagram:
• Renamed pin 58 (was VDD_HV_ADV0_ADV1, is VDD_HV_ADV).
• Renamed pin 59 (was VSS_HV_ADV0_ADV1, is VSS_HV_ADV).
In the “144 LQFP pin function summary” table, for pin 39, changed VSS_LV_COR to
VDD_LV_COR.
In the “Supply pins” table:
• Changed the description for VDD_LV_COR (was “Voltage regulator supply voltage”, is
“Core logic supply”).
• Changed the description for VDD_HV_PMU (was “Core regulator supply”, is “Voltage
regulator supply”).
In the “Pin muxing” table:
• In the “Pad speed” column headings, changed “SRC = 0” to “SRC = 1” and “SRC = 1”
to “SRC = 0”
• For port B[6], changed the pad speed for SRC=0 (was M, is F).
In the “Thermal characteristics” section, added meaningful values to the
thermal-characteristics tables.
Added the “SWG electrical specifications” section.
In the “Voltage regulator electrical characteristics” section, changed the table title (was
“HPREG1, HPREG2, Main LVDs, Digital HVD, and Digital LVD electrical
specifications”, is “Voltage regulator electrical characteristics”) and revised the table.
In the “BCP68 board schematic example” figure, removed the resistor at the base of the
BCP68 transistor.
In the “DC electrical characteristics” table:
• Changed the guarantee parameter for IINJ (was P, is T).
• Added a specification for input leakage current for shared ADC input-only ports.
Revised the “Flash memory module life” table.
In the “FMPLL electrical characteristics” table, revised the footnote defining fSCM and
fVCO.
In the “Main oscillator electrical characteristics” table:
• Changed the max specification for gmXOSCHS (was 11.8 mA/V, is 13.25 mA/V).
• Revised the conditions for TXOSCHSSU.
In the ‘RC oscillator electrical characteristics” table, deleted the specification for
RCMTRIM.
Revised the “ADC conversion characteristics” table.
5
(cont.) 31 Aug 2010
(cont.) In the “RESET pin characteristics” section, changed “nRSTIN” to “RESET”.
Added the “Reset sequence” section.
Revised the footnotes in the “Nexus debug port timing” table.
In the “Orderable part number summary” table, added a footnote about frequency
modulation to the “Speed (MHz)” column heading.
Table 41. Revision history (continued)
Revision Date Description of chan ges
Document revision history
MPC5643L Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor 129
6 11 Mar 2011 Editorial changes.
In the “Document overview” section, added in formation about how content specific to
silicon versions (“cut1” and “cu t2”) is presented.
In the isomet ri c min i at ure package drawin gs on the front pag e, removed the third
dimension.
Changed Symbol from P to D for “Conversion Time” in “ADC conversion characteristics”
table.
Added classification symbol “D” to seven entries in “Voltage regulator electrical
specifications“ table.
Removed irrelevant Flexcan specs.
Updated Table “Voltage Thresholds” to reference values specified in Table “Voltage
Regulator Electrical Specifications”.
RDY pin added for cut2.
In the “System pins” table, added a footnote about the MDO0 pad speed.
Updated Rsw1 values.
Added TUE-related spec information for single and double ADC channels.
Added AC Test Timing Conditions to the “AC timing characteristics” section.
Added a statement on the first page describing cut1 versus cut2.
Moved the first paragraph from the “Description” section to the beginning of the
“Document overview” section.
Changed pad speed from “M” to “SYM” for FlexRay pins in the “Pin Muxing” table and
added this pad type to the footnote.
Moved the newly added device current specification entries from the “DC electrical
characteristics“ table into a newly created “Supply current characteristics“ table.
Added symbol “CC” to the description in the “Introduction” section.
Updated “Input leakage curre nt” specs in the “DC electrical characteristics” table.
Changed TADC_S to Tsample and TADC_C toTconv in the “ADC conversion characteristics”
table and footnotes.
Removed “IINJ” from the “ADC conversion characteristics” table as this is included in
IS1WIKNJ and IS1WWiNJ.
Changed RESET_B to RESET in the "Reset sequence " section.
Added the “Flash memory timing” table.
Added cut2 specs for TDRB and TERLB to the “Reset sequences” table.
Table 41. Revision history (continued)
Revision Date Description of chan ges
MPC5643L Microcontroller Data Sheet, Rev. 9
Document revision history
Freescale Semiconductor130
6
(cont.) 11 Mar 2011
(cont.) Added “WKUP/NMI Timing” subsection and “WKUP/NMI Glitch Filter” table to the “AC
timing characteristics” section.
Added “Nexus DDR Mode output timing” table to the “Nexus timing” section.
Removed the “CLKOUT” diagram from the “External interrupt timing (IRQ pin)” section as
it is not relevant.
Corrected an error in the IRQ timing in the “External interrupt timing” figure.
Updated the tSDC parameters in the “DSPI timing” table.
Renamed the “Electromagnetic Interference (EMI) characteristics” sectio n (is
“Electromagnetic Interference (EMI) characteristics (cut1)”) and revised all information
in that section.
In the “Voltage regulator elec trical characteristics” section, added the BCX68 from
Infineon to the list of supported transistors.
Revised the “Voltage regulator electrical specifications” table to include cut1 and cut2
information.
Renamed the “Supply current characteristics” section (is “Supply current characteristics
(cut2)”) and revised it to show meaningful data.
In the footnotes of the “Main oscillator electrical characteristics” table, changed
SELMARGIN to XOSC_MARGIN.
In the “ADC conversion characteristics” table:
• Changed “LSB” to “Counts”.
• Created separate rows for the TUE specifications.
Added bullet regarding HAL T and STOP in the “Clock, reset, power, mode and test control
modules (MC_CGM, MC_RGM, MC_PCU, and MC_ME)“ subsection of the “Features“
section.
In the “Analog-to-Digital Converter module“ subsection of th e “Feature Details” section,
changed “Motor control mode“ to “CTU mode“ to be consistent with the nomenclature
used in the Reference Manual.
Updated the JCOMP entries in the “Pi n function summary“ table.
Added footnotes regarding pad pull devices to NMI, TMS, TCK, and JCOMP in the
“System pins“ table.
Added “T ime constant of RC filter at LVD input”
parameters to the “Main supply LVD (LVD
Main) specifications“ table.
In the “Supply current characteristics (cut2)“ table:
• Changed “IDD_LV_MAX” to “IDD_LV_MAX“;
• Removed all “40-120 MHz” frequency ranges from the “Conditions” column;
• Updated the “Max” values column;
• Added parameter “IDD_LV_TYP +I
DD_LV_PLL“ with “P” classification and special footnote;
• Changed all “25C“ temp erature conditions to “ambient”;
• Added “TJ=150C“ condition to parameters IDD_HV_ADC, IDD_HV_AREF., IDD_HV_OSC,
and IDD_HV_FLASH.
Changed the timing diagram in the “Main oscillator electrical characte ristics” section to
reference MTRANS assertion instead of VDDMIN.
Updated the jitter specs in the “FMPLL electrical characteristics“ table.
In the “ADC conversion characteristics“ table, changed all parameters with units of
“counts” to units of “LSB” and updated Min/Max values.
Changed IDD_LV_BIST + IDD_LV_PLL operating current (for both cases) to TBD.
In the “Supply current characteristics (cut2)” section, added a footnote that IDD_HV_ADC
and IDD_HV_AREF represent the total current of both ADCs in the “Current consumption
characteristics” table.
Table 41. Revision history (continued)
Revision Date Description of chan ges
Document revision history
MPC5643L Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor 131
6
(cont.) 11 Mar 2011
(cont.) In the “ADC conversion characteristics” table:
• Changed DNL min from -2 to -1.
• Changed OFS min from -2 to -6.
• Changed OFS max from 2 to 6.
• Changed GNE min from -2 to -6.
• Changed GNE max from 2 to 6.
• Changed SNR min from 69 to 67.
• Changed TUE min (without current injection) from -6 to -8.
• Changed TUE max (without current injection) from 6 to 8.
• Changed TUE min (with current injection) from -8 to -10.
• Changed TUE max (with current injection) from 8 to 10.
7 25 Mar 2011 In the “Description” section, changed the first paragraph and its bullets to paragraph form
only.
In the “Voltage regulator electrical specifications“ table, changed the CV1V2 Min value from
“—“ to 300 nF, and changed the Max value from 300 nF to 900 nF.
In the “Supply current characteristics (cut2)“ table, corrected the “IDD_LV_TYP
+I
DD_LV_PLL“ values as follows:
• Changed the maximum value for “TJ= ambient“ from “279 mA+
2.10 mA*fCPU“ to “279 mA”.
• Changed the maximum value for “TJ= 150 C“ from “318 mA+
2.30 mA*fCPU“ to 318 mA.
• Changed the frequency multiplier “fCPU” in the max value to read “fCPU[MHz]“ for
“IDD_LV_FULL +I
DD_LV_PLL“ and “IDD_LV_TYP +I
DD_LV_PLL“.
In the “JTAG pin AC electrical char acteristics“ table:
• Changed tJCYC min from 100ns to 62.5ns.
• Changed tJDC units from “ns” to “%”.
In the “Nexus debug port timing“ table:
• Changed tTCYC min from 40ns to 62.5 ns.
• Changed tJOV parameter description from “TCK Low to TDO Data Valid“ to “TCK Low
to TDO/RDY Data Valid“.
Changed “DDR” to “Double Data Rate (DDR)“ in the “Nexus DDR Mode output timing“
figure.
Changed “TDO” to “TDO/RDY” in the “Nexus TDI, TMS, TDO timing“ figure.
Removed “fmax” from the “DSPI timing” table.
Table 41. Revision history (continued)
Revision Date Description of chan ges
MPC5643L Microcontroller Data Sheet, Rev. 9
Document revision history
Freescale Semiconductor132
8 27 April 2012 Editorial change s.
In the “Device comparison” section, changed “Ambient temperature range using external
ballast transistor (BGA)“ from TBD to “–40 to 125 °C“.
In the “Block diagram” section, removed one PMU from the figure.
In the 257-pin pinout figure, changed cut2 to cut2/3 in Notes.
In the pin function summary table, changed cut2 to cut2/3.
In the “System pins” table:
• Added Note regarding Open Drain Enable.
• Added description to RESET pin.
In the pin-muxing table:
• Added Note about Open Drain.
• Changed cut2 to cut2/3.
• Changed all entries of column 'Weak pull config during reset’ to ' - ' , except for PCR[2],
PCR[3], PCR[4] and PCR[21].
In the “Absolute maximum ratings” table:
• Removed the “VSS_HV_REG” row.
• Added the footnote “Internal structures hold the input voltage...” to the VIN maximum
specifications.
In the “ conditions” table, removed the “VSS_HV_REG” row.
In the “Thermal characteristics” section:
• Added the “Thermal characteristics for 100 LQFP package“ table.
• Updated value s an d footnote 1 in the 144 package table.
• Updated footnote 1 in th e 257 package table.
In the “Supply current characteristics“ table:
• Added footnote 1 to parameter “IDD_LV_TYP + IDD_LV_PLL“ (symbol “T”).
• Changed “IDD_LV_STOP” at 150C from 80mA to 72mA.
• Changed “IDD_LV_HALT” at 150C from 72mA to 80mA.
In the “FMPLL electrical characteristics” table:
• Deleted the footnote “This value is true when operating at frequencies above 60 MHz...”
from the specification for fCS and fDS.
• Changed “fSYS” to “fFMPLLOUT” in the entries for the CJITTER, fLCK, fUL, fCS, and fDS
specifications.
In the “ADC conversion characteristics” table:
• Revised the entry for TUEIS1WINJ (was P/T and “Total unadjusted error for IS1WINJ”, is
T and “Total unadjusted error for IS1WINJ (single ADC channels)”).
• Revised the entry for TUEIS1WWINJ (was “Total unadjusted error for IS1WWINJ”, is
“Total unadjusted error for IS1WWINJ (double ADC channels)”).
In the “Temperature sensor electrical characteristics“ table, for TJ = T A to 125 °C, changed
Min/Max from values -7/+7 to -10/+10.
In the “Input Impedance and ADC Accuracy“ section:
• Changed CS in the text from 3 pF to 7.5 pF.
• Changed Req in the text from 330 k to 133 k.
• Removed RL, RSW, and RAD from the external network design constraint equation and
the sentence immediately preceding it.
• Changed the CF constraint value equation constant from 2048 to 8192.
• In the “ADC conversion characteristics“ table, changed INL Min/Max values from -2/+2
to -3/+3.
Table 41. Revision history (continued)
Revision Date Description of chan ges
Document revision history
MPC5643L Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor 133
•In Section 1.5.31, “eT imer module” changed text from “The MPC5643L provides three
eTimer modules on the 257 MAPBGA device, and two eTimer modules on the 144
LQFP package” to “The MPC5643L provides three eTimer modules (on the LQFP
package eTimer_2 is avai lable internally only without any external I/O access)”.
•In Section 3.5, “Electromagnetic Interference (EMI) characteristics”,added additional
information at the end of this section.
•In Section 3.8, Voltage regulator electrical characteristics , added text related to
external ballast transistor.
•In Table 3 and Table 4 (257 MAPBGA pin function summary), moved EVTI from output
function to input function.
•In Table 6 (System pins), changed the direction for EXTAL from “Output Only” to
“Input/Output”.
•InTable 6, added table footnote for symbol “EXTAL”.
• Changed the row (TVdd) in Table 8 (Absolute maximum ratings).
•In Table 8, Maximum value for “VDD_HV_IOX” and “VDD_HV_FLA” changed from “3.6” to
“4.0”.
•In Table 20 (Current consumption characteristics), added max value 250 and 290 mA
for symbol IDD_LV_BIST+IDD_LV_PLL .
• Added five additional RunIDD parameters in Table 20 (Current consumption
characteristics).
•In Table 21 (Temperature sensor electrical characteristics), changed condition for
parameter “Accuracy” from “-40°C to 25°C” to “-40°C to 150°C”
•In Table 23 (FMPLL electrical characteristics),added ‘150’ to the max value for ‘fSCM’ In
Table 24 (16 MHz RC oscillator electrical characteristics),changes done are:
fRC symbol- Added min value ‘15.04’ and max value ‘16.96’.Removed condition “TJ=25°C”
Removed row co ntaining RCMVAR symbol.
•In Figure 8, added the name ‘CS’ to the capacitor in the internal circuit scheme.
• Removed references to Cut1 and Cut2:
Renamed Section ”Electromagnetic Interference (EMI) characteristics (cut1)” to
“Electromagneti c Interference (EMI) characteristics” .
In Table 25 (ADC conversion characteristics), removed reference to cut2 only for symbol
‘IS1WINJ’ and ‘TUEIS1WWINJ’.
In Section 1.1, Docu ment overview, modified text to remove references to ‘Cut1’.
•In Table 25 (ADC conversion characteristics), for tCONV added ‘60 MHz’ to ‘conditions’
and ‘600’ to the ‘Min’ value.
Separated SNR into two specifications with conditions Vref 3.3 V and 5.0 V respectively.
Changed min value to ‘-72’ for symbol ‘THD’.
•In Table 25 (ADC conversion characteristics), changed ADC specification parameter
‘THD’ minimum limit from -72 to -65dB.
•In Table 26 (Flash memory program and erase electrical specifications), changes done
are as follows:
TDWPROGRAM, changed typical value from ‘39’ to ‘38’.
TPPROGRAM, changed typical value from ‘48’ to ‘45’ and intial max value from ‘100’ to ‘160’.
T16KPPERASE, inserted typical value ‘270’ and factory avg ‘1000’.
T48KPPERASE, inserted typical value ‘625’ and factory avg ‘1500’.
T64KPPERASE, inserted typical value ‘800’ and factory avg ‘1800’.
T128KPPERASE, inserted typical value ‘1500’ and factory avg ‘260 0’.
T256KPPERASE, inserted typical value ‘3000’ and factory avg ‘5200’.
Updated table footnote and removed min column in Table 26 (Flash memory program and
erase electrical specifications)
•In Table 27 (Flash memory timing), added symbol TPSRT ,TESRT and added table
footnote for TPSRT ,TESRT .
Table 41. Revision history (continued)
Revision Date Description of chan ges
MPC5643L Microcontroller Data Sheet, Rev. 9
Document revision history
Freescale Semiconductor134
• Added Table 29 (MPC5643L SWG Specifications)
•In Table 29 (MPC5643L SWG Specifications)
Added table footnote for Common Mode.
Changed text from “internal device pad resist ance” to “internal device routing resistance”.
• Added Figure 26 in Section 3.20.4, “Nexus timing”.
•In Table 30 (Pad AC specifications (3.3 V , IPP_HVE = 0 )), removed the row of pad
“Pull Up/Downc(3.6 V max)”.
•In Table 40 (Orderable part number summary) and Figure 43, updated part numbers
(changed ‘PPC’ to ‘SPC’ and ‘F0’ to ‘F2’).
• Replaced Figure 39, Figure 40, Figure 41, Figure 42 with the new versions.
•InTable 18 (Voltage regulator electrical specifications),changed the symbol of spec
external decoupling capacitor from SR to Cext.
In Figure 4, changed the ESR range in note text to 1 mW to 100 mW from 30 mW to
150 mW.
•In Section 1.5.32, “Sine W ave Generator (SWG)” removed the following text:
Frequency range from 1kHz to 50kHz.
Sine wave amplitude from 0.47 V to 2.26 V.
•In Table 20 (Current consumption characteristics)”,changed symbol from ‘C’ to ‘T’ ,
added “operating current” to the parameter and updated the maximum value for five
additional RunIDD parameters.
•In Table 20 (Current consumption characteristics), changed “Conditions” from ‘1.2 V
supplies’ to ‘1.2 V supplies during LBIST (full LBIST configuration)’ for all the
parameters.
• Removed Table “SWG electrical characteristics”.
•In Table 18 (Voltage regulator electrica l specifications), changed the “Digital supply
high voltage detector upper threshold low limit (After a destructive reset initialization
phase completion)” from 1.43V to 1.38V.
• Added Table 17 (Recommended operating characteristics).
• Updated the IDD values in Table 20 (Current consumption characteristics). Changed
conditions text from “1.2 supplies during LBIST (full LBIST configuration)” to “1.2 V
supplies” for all the IDD parameters except IDD_LV_BIST+IDD_LV_PLL. Added footnote in
“Conditions” for the DPM mode.
• Removed Cut references from the whole document.
•In Table 25 (ADC conversion characteristics), changed the sampling frequency value
from ‘1 MHz’ to ‘983.6 KHz’.
8.1 07 May 2012 • Deleted the Footer "Preliminary-Subject to Change Without Notice" label.
Table 41. Revision history (continued)
Revision Date Description of chan ges
Document revision history
MPC5643L Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor 135
9 12 June 2013 • Updated Table 18
— added Digital supply low voltage detector lower threshold and Digital supply
low voltage detector upper threshold
— Updated Main High Voltage Power-Low Voltage Detection value to 2.93 V
• Replaced IEC with ISO26262 in Section 1.1, “Document overview
• Table 1-removed KGD
• Table 24 modified fRC values
• Updated Table 26
• Updated Table 25-tconv to teval and associated footnote
• Updated Table 19
— added VIH footnote
— Updated IOL, IOH value for Fast pads
• Updated Table 31-TDRB and TELRB
• Updated Table 18-combined ESR of external capacitor values
• Updated Section 3.15.1, “Input Impedance and ADC Accuracy -replaced fc by fs
• Table 6-added footnote to RESET pin about weak pull down
• Updated Injection current information in Table 19-IINJ, Table 8-footnote 4
• Updated Table 20 for the following:
— specified oscillator bypass mode and crystal oscillator mode
— Updated STOP and HALT mode values
— Added IDD_HV_PMU
— footnote 2, footnote 3
• Added footnote VDD_HV_ADRx must always be applied and should be stable before
LBIST starts. to Table 9
• Added footnote to Section 5, “Ordering information
• Edit changes to Section 3.5, “Electromagnetic Interference (EMI) characteristics
• Updated Equation 16
Table 41. Revision history (continued)
Revision Date Description of chan ges
Document Number: MPC5643L
Rev. 9
6/2013
Information in this document is provide d solely to enable system and software
implementers to use Freescale products. There are no express or implied copyright
licenses granted h ereunder t o desi gn or f abricate any inte grated circuits based on the
information in this document .
Freescale reserves the right to make changes without further notice to any products
herein. Freescale makes no warranty, represent ation, or guarantee regarding the
suitabil i ty of its products for any particular purpo se, nor does Freescale assume any
liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liabil i ty, including without limitation conse quential or incidental
damages. “Typical” parameters t hat may b e pro vi ded i n Freescale data sheets and/or
specifications can and do vary in dif ferent applications, and actual performance may
vary over time. All operating pa rameters, including “typicals,” must be validated for
each customer application by customer’s technical expert s. Freescale does not convey
any license under its patent rights nor the rights of others. Freescale sells products
pursuant to st andard terms an d conditions of sale, which can be found at the following
address: http://www.reg.net/v2/webservices/Freescale/Docs/TermsandConditions.htm
How to Reach Us:
Home Page:
freescale.com
Web Support:
freescale.com/support
Freescale™ and the Freescale logo are trademarks of Freescale
Semiconductor, Inc. All other product or service names are the property
of their respective owners.
© 2009–2013 Freescale Semiconductor, Inc.
