SC1405B High Speed Synchronous Power MOSFET Smart Driver with 7V Drive POWER MANAGEMENT Description Features u u u u u u u u u u u u u The SC1405B is a Dual-MOSFET Driver with an internal Overlap Protection Circuit to prevent shoot-through. Each driver is capable of driving a 3000pF load in 15ns rise/ fall time and has ULTRA-LOW propagation delay from input transition to the gate of the power FETs. The Overlap Protection circuit ensures that the synchronous FET does not turn on until the top FET source has reached a voltage low enough to prevent shoot-through. The delay between the bottom gate going low to the top gate transitioning high is externally programmable via a capacitor for optimal reduction of switching losses at the operating frequency. The bottom FET may be disabled at light loads by keeping S_MOD low to trigger asynchronous operation, thus saving the bottom FETs gate drive current and inductor ripple current. An internal voltage reference allows threshold adjustment for an Output Over-Voltage protection circuitry, independent of the PWM feedback loop. Under-Voltage-Lock-Out circuit is included to guarantee that both driver outputs are low when the 5V logic level is less than or equal to 4.4V (typ) at supply ramp up (4.35V at supply ramp down). A CMOS output provides status indication of the 5V supply. A low enable input places the IC in stand-by mode thereby reducing supply current to less than 10A. SC1405B is offered in a high pitch (.025 lead spacing) TSSOP package. Fast rise and fall times (15ns with 3000pf load) 14ns max. Propagation delay (BG going with low) Adaptive/programmable shoot-through protection 7V supply operation for lower Rds_on Wide input voltage range (4.5-25V) Programmable delay between MOSFETs Power saving asynchronous mode control Output overvoltage protection/overtemp shutdown Under-Voltage lock-out and power ready signal Less than 10A stand-by current (EN=low) Power ready output signal Improved drive version of SC1405TS High frequency (to 1.2MHz) operation allows use of small inductors and low cost caps in place of electrolytics Applications u High Density/Fast transient power supplies u Motor Drives/Class-D amps u High efficiency portable computers Typical Application Circuit Revision 1, December 2000 1 www.semtech.com SC1405B POWER MANAGEMENT Absolute Maximum Ratings Parameter Sy mbol Maximum U nits VMAXSV 8 V BST to PGND VMAXBST-PGND 30 V BST to D RN VMAXBST-DRN 8 V D RN to PGND VMAXDRN-PGN 25 V VMAXOVP S- 10 V -0.3 to 8.3 V 0.66 2.56 W VCC Supply Voltage OVP_S to PGND C onditions PGND Input Pi n CO C onti nuous Power D i ssi pati on Pd Thermal Impedance Juncti on to C ase q JC 40 C /W Thermal Impedance Juncti on to Ambi ent q JA 150 C /W Operati ng Temperature Range TJ 0 to +125 C Storage Temperature Range TSTG -65 to +150 C Lead Temperature (Solderi ng) 10 Sec. TLEAD 300 C Tamb = 25oC , TJ = 125oC Tcase = 25oC , TJ = 125oC NOTE: (1) Specification refers to application circuit in Figure 1. Electrical Characteristics - DC Operating Specifications Unless specified: -0 < qJ < 125C; VCC = 7V; 4V < VBST < 26V Parameter Sy mbol C onditions Min Ty p Max U nits 4.15 5 7.0 V 10 A Power Supply Supply Voltage Qui escent C urrent V CC Iq_stby E N = 0V Iq_op VCC = 5V, C O = 0V Hi gh Level Output Voltage VOH VCC = 4.6V, lload = 10mA Low Level Output Voltage VOL VCC < UVLO threshold, lload = 10A Qui escent C urrent, operati ng TBD mA TBD V PR D Y a 2000 Semtech Corp. 2 TBD 0.1 0.2 V www.semtech.com SC1405B POWER MANAGEMENT Electrical Characteristics - DC Operating Specifications Parameter Sy mbol C onditions Min Hi gh Level Output Voltage VOH VCC = 4.6V, C load = 100pF 4.15 Low Level Output Voltage VOL VCC = 4.6V, C load = 100pF Ty p Max U nits D S P S _D R V 0.05 V 4.6 V U nder Voltage Lockout Start Threshold Hysteresi s Logi c Acti ve Threshold VSTART 4.2 VhysUVLO 4.4 0.05 V AC T V 1.5 V 1.255 V Ov erv oltage Protection Tri p Threshold Hysteresi s VTRIP 1.145 1.2 0.8 VhysOVP V S_MOD Hi gh Level Input Voltage VIH Low Level Input Voltage VIL 2.0 V 0.8 V Enable Hi gh Level Input Voltage VIH Low Level Input Voltage VIL 2.0 V 0.8 V CO Hi gh Level Input Voltage VIH Low Level Input Voltage VIL 2.0 V 0.8 V Thermal Shutdown Over Temperature Tri p Poi nt TOTP 165 o C Hysteresi s THYST 10 o C IPKH 3 A 1 W H igh-Side D riv er Peak Output C urrent Output Resi stance RsrcTG Rsi nkTG duty cycle < 2%, tpw < 100s, TJ = 125C , VBST - VDRN = 4.5V, VTG = 4.0V (src)+VDRN or VTG = 0.5V (si nk)+VD RN .7 Low-Side D riv e Peak Output C urrent Output Resi stance IPKL RsrcBG Rsi nkBG a 2000 Semtech Corp. duty cycle < 2%, tpw < 100s, TJ = 125C , VV S = 4.6V, VBG = 4V (src) or VLOWDR = 0.5V (si nk) 3 3 A 1.2 W 1.0 www.semtech.com SC1405B POWER MANAGEMENT Electrical Characteristics - AC Operating Specifications Parameter Sy mbol C onditions ri se ti me trTG1 fall ti me Min Ty p Max U nits C I = 3nF, VBST - VDRN = 4.6V, 14 23 ns tfTG C I = 3nF, VBST - VDRN = 4.6V, 12 19 ns propagati on delay ti me, TG goi ng hi gh tpdhTG C I = 3nF, VBST - VDRN = 4.6V, C -delay =0 20 32 ns propagati on delay ti me, TG goi ng low tpdlTG C I = 3nF, VBST - VDRN = 4.6V, 15 24 ns H igh Side D riv er Low-Side D riv er ri se ti me trBG C I = 3nF, V V S = 4.6V, 15 24 ns fall ti me trBG C I = 3nF, V V S = 4.6V, 13 21 ns propagati on delay ti me, BG goi ng hi gh tpdhBGHI C I = 3nF, VBST - VDRN = 4.6V, C -delay =0 12 19 ns propagati on delay ti me, TG goi ng low tpdlBG C I = 3nF, V V S = 4.6V, D RN <1V 7 12 ns V_5 rampi ng up tpdhUVLO EN i s Hi gh 10 us V_5 rampi ng down tpdhUVLO EN i s Hi gh 10 us EN i s transi ti oni ng from low to hi gh tpdhPRD Y V_5 >UVLO threshold, D elay measured from EN > 2.0V to PRD Y > 3.5V 10 s EN i s transi ti oni ng fro hi gh to low tpdhUVLO V_5 >UVLO threshold, D elay measured from EN < 0.8V to PRD Y < 10% of V_5V 500 s trDSPS DR. C I = 100 pf, V_5 = 4.6V 20 ns propagati on delay, D SPS_D R goi ng hi gh tpdhDSPS DR S_MOD goes hi gh and BG goes hi gh or S_MOD goes low 10 ns propagati on delay, D SPS_D R goes low tpdlDSPS DR S_MOD goes hi gh and BG goes low 10 ns tpdhOVP S V_5 + 4.6V, TJ = 125OC , OVP_S > 1.2V to BG > 90% of V _5 1 s U nder-Voltage Lockout PR D Y D S P S _D R ri se/fall ti me Ov erv oltage Protection propagati on delay a 2000 Semtech Corp. 4 www.semtech.com SC1405B POWER MANAGEMENT Timing Diagrams a 2000 Semtech Corp. 5 www.semtech.com SC1405B POWER MANAGEMENT Pin Configuration Ordering Information D ev ice Top View (1) SC 1405B.TR P ackag e Temp R ange (TJ) TSSOP-14 0 to 125C Note: (1) Only available in tape and reel packaging. A reel contains 2500 devices. (14-Pin TSSOP) Pin Descriptions Pin # Pin N ame Pin Function 1 OVP_S 2 EN 3 GND 4 CO 5 S_MOD 6 D ELAY_C The capaci tance connected between thi s pi n and GND sets the addi ti onal propagati on delay for BG goi ng low to TG goi ng hi gh. Total propagati on delay =20ns + 1ns/pF. If no capaci tor i s connected, the propragati on delay = 20ns. 7 PRD Y Thi s pi n i ndi cates the status of VC C . When VC C i s less than the UVLO threshold, thi s output i s dri ven low. When VC C i s greater than or equals to the UVLO threshold thi s output goes hi gh. Thi s output has a 10mA dri ve capabi li ty and 10A si nk capabi li ty. 8 VC C Input supply of 5 - 7V. A .22-1F cerami c capaci tor should be connected from VC C to PGND very close to the chi p. 9 BG 10 PGND 11 D S P S _D R D ynami c Set Poi nt Swi tch D ri ve. TTL level output si gnal. When S-MOD i s hi gh, thi s pi n follows the BG dri ver pi n voltage. 12 D RN Thi s pi n connects to the juncti on of the swi tchi ng and synchronous MOSFET's. Thi s pi n can be subjected to a -2V mi ni mum relati ve to PGND wi thout affecti ng operati on. 13 TG 14 BST Overvoltage protecti on sense. External scali ng resi stors requi red to set protecti on threshold. When hi gh, thi s pi n enables the i nternal ci rcui try of the devi ce. When low, TG, BG, and PRD Y are forced low and the supply current (5V) i s less than 10A. Logi c GND . TTL-level i nput si gnal to the MOSFET dri vers. When low, thi s si gnal forces BG to be low, tri ggeri ng asynchronous operati on. When hi gh, BG i s not a functi on of thi s si gnal. Output dri ve for the synchrounous (bottom) MOSFET. Power ground. C onnect to the synchronous FET source pi n (power ground). Output gate dri ve for the swi tchi ng (hi gh-si de) MOSFET. Bootstrap pi n. A capaci tor i s connected between BST and D RN pi ns to develop the floati ng bootstrap voltage for the hi gh-si de MOSFET. The capaci tor value i s typi cally between 0.1F and 1F (cerami c). NOTE: (1) All logic level inputs and outputs are open collector TTL compatible. a 2000 Semtech Corp. 6 www.semtech.com SC1405B POWER MANAGEMENT Block Diagram Applications Information SC1405B is the higher speed version of the SC1405. It is designed to drive Low Rds_On power MOSFETs with ultra-low rise/fall times and propagation delays. As the switching frequency of PWM controllers is increased to reduce power supply and Class-D amplifier volume and cost, fast rise and fall times are necessary to minimize switching losses (TOP MOSFET) and reduce Dead-time (BOTTOM MOSFET) losses. While Low Rds_On MOSFETs present a power saving in I2R losses, the MOSFETs die area is larger and thus the effective input capacitance of the MOSFET is increased. Often a 50% decrease in Rds_On more than doubles the effective input gate charge, which must be supplied by the driver. The Rds_On power savings can be offset by the switching and deadtime losses with a suboptimum driver. While discrete solution can achieve reasonable drive capability, implementing shoot-through, programmable delay and other housekeeping functions necessary for safe operation can become cumbersome and costly. The SC1405 family of parts presents a total solution for the high-speed, high power density =applications. Wide input supply range of 4.5V-25V allows use in battery powered applications, new high voltage, distributed power servers as well as ClassD amplifiers. of events by which the top and bottom drive signals are applied. The shoot-through protection is implemented by holding the bottom FET off until the voltage at the phase node (intersection of top FET source, the output inductor and the bottom FET drain) has dropped below 1V. This assures that the top FET has turned off and that a direct current path does not exist between the input supply and ground, a condition which both the top and bottom FETs are on momentarily. The top FET is also prevented from turning on until the bottom FET is off. This time is internally set to 20ns (typical) and may be increased by adding a capacitor from the C-Delay pin to GND. The delay is approximately 1ns/pf in addition to the internal 20ns delay. The external capacitor may be needed if multiple High input capacitance MOSFETs are used in parallel and the fall time is substantially greater than 20ns. Theory of Operation As with any high speed , high current circuit, proper layout is critical in achieving optimum performance of the SC1405B. The Evaluation board schematic (Refer to figure 3) shows a dual phase synchronous design with all surface mountable components. The control input (CO) to the SC1405B is typically supplied by a PWM controller that regulates the power supply output. (See Application Evaluation Schematic, Figure 3). The timing diagram demonstrates the sequence a 2000 Semtech Corp. It must be noted that increasing the dead-time by high values of C-Delay capacitor will reduce efficiency since the parallel Schottky or the bottom FET body diode will have to conduct during dead-time. Layout Guidelines 7 www.semtech.com SC1405B POWER MANAGEMENT Applications Information the Miller feedback and thus reduces Vspike. Also MOSFETs with higher Turn-on threshold voltages will conduct at a higher voltage and will not turn on during the spike. The MOSFET shown in the schematic (figure 4) has a 2 volt threshold and will require approximately 5 volts Vgs to be conducting, thus reducing the possibility of shoot-through. A zero ohm bottom FET gate resistor will obviously help keeping the gate voltage low. While components connecting to C-Delay, OVP_S, EN,SMOD, DSPS_DR and PRDY are relatively non-critical, tight placement and short,wide traces must be used in layout of The Drives, DRN, and especially PGND pin. The top gate driver supply voltage is provided by bootstrapping the +5V supply and adding it the phase node voltage (DRN). Since the bootstrap capacitor supplies the charge to the TOP gate, it must be less than .5 away from the SC1405. Ceramic X7R capacitors are a good choice for supply bypassing near the chip. The Vcc pin capacitor must also be less than .5 away from the SC1405. The ground node of this capacitor, the SC1405 PGND pin and the Source of the bottom FET must be very close to each other, preferably with common PCB copper land and multiple vias to the ground plane (if used). The parallel Shottkey must be physically next to the Bottom FETS Drain and source. Any trace or lead inductance in these connections will drive current way from the Shottkey and allow it to flow through the FETs Body diode, thus reducing efficiency. Ultimately, slowing down the top FET by adding gate resistance will reduce di/dt which will in turn make the effective impedance of the capacitors higher, thus allowing the BG driver to hold the bottom gate voltage low. Ringing on the Phase Node The top MOSFET source must be close to the bottom MOSFET drain to prevent ringing and the possibility of the phase node going negative. This frequency is determined by: 1 Fring = (2 O* Sqrt(Lst*Coss)) Preventing Inadvertent Bottom FET Turn-on Where: At high input voltages, (12V and greater) a fast turn-on of the top FET creates a positive going spike on the Bottom FETs gate through the Miller capacitance, Crss of the bottom FET. The voltage appearing on the gate due to this spike is: Lst = The effective stray inductance of the top FET added to trace inductance of the connection between top FETs source and the bottom FETs drain added to the trace resistance of the bottom FETs ground connection. Vspike= Vin*crss (Crass+ciss) Coss=Drain to source capacitance of bottom FET. If there is a Shottkey used, the capacitance of the Shottkey is added to the value. Where Ciss is the input gate capacitance of the bottom FET. This is assuming that the impedance of the drive path is too high compared to the instantaneous impedance of the capacitors. (since dV/dT and thus the effective frequency is very high). If the BG pin of the SC1405B is very close to the bottom FET, Vspike will be reduced depending on trace inductance, rate if rise of current,etc. Although this ringing does not pose any power losses due to a fairly high Q, it could cause the phase node to go too far negative, thus causing improper operation, double pulsing or at worst driver damage. This ringing is also an EMI nuisance due to its high resonant frequency. Adding a capacitor, typically 1000-2000pf, in parallel with Coss can often eliminate the EMI issue. If double pulsing is caused due to excessive ringing, placing 4.7-10 ohm resistor between the phase node and the DRN pin of the SC1405 should eliminate the double pulsing. Proper layout will guarantee minimum ringing and eliminate the need for external components. Use of SO8 or other surface mount MOSFETs will reduce lead inductance and their parasitic effects. While not shown in Figure 4, a capacitor may be added from the gate of the Bottom FET to its source, preferably less than .5 away. This capacitor will be added to Ciss in the above equation to reduce the effective spike voltage, Vspike. The selection of the bottom MOSFET must be done with attention paid to the Crss/Ciss ratio. A low ratio reduces a 2000 Semtech Corp. 8 www.semtech.com SC1405B POWER MANAGEMENT Applications Information (Cont.) ASYNCHRONOUS OPERATION DSPS DR The SC1405B can be configured to operate in Asynchronous mode by pulling S-MOD to logic LOW, thus disabling the bottom FET drive. This has the effect of saving power at light loads since the bottom FETs gate capacitance does not have to charged at the switching frequency. There can be a significant savings since the bottom driver can supply up to 2A pulses to the FET at the switching frequency. There is an additional efficiency benefit to operating in asynchronous mode. When operating in synchronous mode, the inductor current can go negative and flow in reverse direction when the bottom FET is on and the DC load is less than 1/2 inductor ripple current. At that point, the inductor core and wire losses, depending on the magnitude of the ripple current, can be quite significant. Operating in asynchronous mode at light loads effectively only charges the inductor by as much as needed to supply the load current, since the inductor never completely discharges at light loads. DC regulation can be an issue depending on the type of controller used and minimum load required to maintain regulation. If there are no Shottkeys used in parallel with bottom FET, the FETs body diode will need to conduct in asynchronous mode. The high voltage drop of this diode must be considered when determining the criteria for this mode of operation. This pin produces an output which is a logical duplicate of the bottom FETs gate drive, if S-MOD is held LOW. a 2000 Semtech Corp. OVP_S/OVER TEMP SHUTDOWN Output over-voltage protection may be implemented on the SC1405 independent of the PWM controller . A voltage divider from the output is compared with the internal bandgap voltage of 1.2V (typical). Upon exceeding this voltage, the overvoltage comparator disables the top FET, while turning on the bottom FET to allow discharge of the output capacitors excessive voltage through the output inductor. There should be sufficient RC time constant as well as voltage headroom on the OVP_S pin to assure it does not enter overvoltage mode inadvertently. The SC1405 will shutdown if its Tj exceeds 165C. 9 www.semtech.com SC1405B POWER MANAGEMENT Typical Characteristics Performance diagrams, Application Evaluation Board. Figure 1: PWM input and Gate drive switching waveforms. The MOSFETs driven are FDB7030BL . See Figure 4 (Evaluation Board Schematic) Ch1: PWM input signal Ch2: Top Gate Drive Ch3: Phase (Switching) Node Ch4: Bottom Gate PIN Descriptions Figure 2: PWM input and Gate drive and phase node switching waveforms with time scale expanded. The MOSFETs driven are FDB7030BL . See Figure 4 (Evaluation Board Schematic) Ch1: PWM input signal Ch2: Top Gate Drive Ch3: Phase (Switching) Node Ch4: Bottom Gate Figure 3: PWM input and Gate drive and phase node switching waveforms with time scale expanded. The MOSFETs driven are FDB7030BL . See Figure 4 (Evaluation Board Schematic) Ch1: PWM input signal Ch2: Top Gate Drive Ch3: Phase (Switching) Node Ch4: Bottom Gate a 2000 Semtech Corp. 10 www.semtech.com a 2000 Semtech Corp. C7 INPUT 6 5 4 3 2 1 J1 1u,16V All VIDs OFF disables the SC2422 Controller. 1000uf,16V 3 4 Vid2 Vid1 11 1K 120K 7.5K R16 26.1k R15 C24 220pf R11 R10 RREF FB 13K R2 U? 10 GND UVLO OC- OUT2 OUT1 OC+ BGOUT VCC .002 R1 VCORE C11 1uf SC2422-P ERROUT VID0 VID1 VID2 VID3 VID4 R14 8 7 6 5 2 Vid3 Vid0 1 33uf,OS C2 Vid4 C8 10u,CE R C1 +12V 5-7V 9 10 11 12 13 14 15 16 10k R4 EN 3.6K R20 C26 C21 7.5K 5 7 2 4 6 1 8 3 5 7 2 4 6 1 8 3 OVP Vcc 10uf C12 Vcc 10uf 10nf 10 R3 R8 C9 10nf TG BS T TG BS T 1 R17 SC1405B PRDY DRN EN CO BG DELAY_C OVP_S DSPS_DR S_MO D PGND Vcc GND U3 5819 D4 SC1405B 11 10 9 12 13 14 11 10 9 12 13 14 10u,CE R C4 PRDY DRN EN CO BG DELAY_C OVP_S DSPS_DR S_MO D PGND Vcc GND 5819 U1 D2 1uf C3 R19 7.5K 10u,CE R C5 R13 0 R9 0 VIN Q4 FDB 7030 Q3 FDB 6035 Q2 FDB 7030 Q1 C30 .1 R6 0 R5 0 Vin FDB 6035 1uf C6 7.5K R18 .1 C20 .1 C14 C27 .01 2.2 R12 L2 PIT1103_1uh R7 2.2 L1 C16 .01 PIT1103_1uh 10u,CER C29 10u,CER C28 10u,CER C25 10u,CER C23 10u,CER C22 10u,CER C19 10u,CER C18 10u,CER C17 10u,CER C15 820u f,OS C13 820u f,OS C10 SC1405B POWER MANAGEMENT Evaluation Board Schematic Figure 4 - APPLICATION EVALUATION BOARD SCHEMATIC www.semtech.com SC1405B POWER MANAGEMENT Evaluation Board Bill of Materials Item Qty. R eference Value Manufacturer 1 12 C 1, C 4, C 5, C 15, C 17, C 18, C 19, C 22, C 23, C 25, C 28, C 29 01u, C er. Murata, TD K 2 1 C2 33uf, OS Sanyo 3 3 C 3, C 6, C 11 1uF 4 1 C7 1u, 16V 5 1 C8 1000uf, 16V 6 2 C 9, C 26 10nf 7 2 C 10, C 13 820uf, OS 8 2 C 21, C 12 10uf 9 3 C 14, C 20, C 30 .1 10 2 C 16, C 27 .01 11 1 C 24 220pf 12 2 D 4, D 2 5819 13 1 J1 INPUT 14 2 L2, L1 PIT1103_luh Falco (Falcousa.com) 15 2 Q1, Q3 F D B 6035 Fai rchi ld 16 2 Q2, Q4 F D B 7030 Fai rchi ld 17 1 R1 .002 D ale 18 2 R3, R2 10 19 1 R4 10k 20 4 R5, R6, R9, R13 0 21 2 R12, R7 2.2 22 4 R8, R16, R18, R19 7.5K 23 1 R10 120K 24 1 R11 1K 25 1 R14 13K 26 1 R15 26.1k 27 1 R17 1 28 1 R20 3.6K 29 1 U? S C 2422 30 2 U1, U3 S C 1405B a 2000 Semtech Corp. 12 Panasoni c Sanyo www.semtech.com SC1405B POWER MANAGEMENT Outline Drawing -TSSOP-14 Contact Information Semtech Corporation Power Management Products Division 652 Mitchell Rd., Newbury Park, CA 91320 Phone: (805)498-2111 FAX (805)498-3804 a 2000 Semtech Corp. 13 www.semtech.com