EWCS8022E.B0-900229 - REALTEK SEMICONDUCTOR

TSM1285

Page 1

FEATURES

 Alternate Source for MAX1285 and higher-speed

upgrade to MAX1240 and MAX1241

 Single-Supply Operation: +2.7V to +3.6V

 DNL & INL: ±1LSB (max)

 300ksps Sampling Rate

 Low Conversion-Mode Supply Current:

2.5mA @ 300ksps

 Low Supply Current in Shutdown: 2µA

 Internal Track-and-Hold

 Internal +2.5V Reference

 SPI

/QSPI™/MICROWIRE™ 3-Wire Serial-

Interface

 8-Pin SOIC Package

APPLICATIONS

Process Control and Factory Automation

Data and Low-frequency Signal Acq uisition

Portable Data Logging

Pen Digitizers & Tablet Computers

Medical Instrumentation

Battery-powered Instruments

SPI and QSPI are trademarks of Motorola, Inc.

MICROWIRE is a trademark of National

Semiconductor Corporation.

DESCRIPTION

The TSM1285 – a single-supply, single-channel, 12-

bit analog-to-digital converter (ADC) - is an alternate

source for the MAX1285 and a higher-speed upgrade

to the MAX1240 and MAX1240 ADCs. The TSM1285

combines a high-bandwidth track-and-hold (T/H), a

high-speed serial digital interface, an internal +2.5V

reference, and low conversion-mode power

consumption. The TSM1285 operates from a single

+2.7V to+3.6V supply and draws less than 2.5mA at

300ksps.

Connecting directly to any SPI, QSPI, M IC R OWIR E™

microcontrollers and other interface-compatible

computing devices, the TSM1285’s 3-wire serial

interface is easy to use and doesn’t require separate,

external logic. An external serial-interface clock

controls the TSM1285’s conversion process and its

output shift register operation.

In PCB-space-conscious, low-power remote-sensor

and data-acquisition applications, the TSM1285 is an

excellent choice for its low-power, ease-of-use, and

small-package-footprint attributes.

The TSM1285BC is fully specified over the

0°C to +70°C temperature range. TSM1285BE is fully

specified over the -40°C to +85°C temperature range.

Both products are availabl e in a 8-pin SOIC package.

A 300ksps, Single-supply, Low-Power 12-Bit Serial-output ADC

FUNCTIONAL BLOCK DIAGRAM

TSM1285

Page 2 TSM1285 Rev. 1.0

ABSOLUTE MAXIMUM RATINGS

to GND.................................................................... -0.3V to +6V

AIN to GND ...................................................... -0.3V to (V

+ 0.3V)

REF to GND ..................................................... -0.3V to (V

+ 0.3V)

Digital Inputs to GND ....................................... -0.3V to (V

+ 0.3V)

DOUT to GND .................................................. -0.3V to (V

+ 0.3V)

DOUT Current ........................................................................ ±25mA

Continuous Power Dissipation (T

= +70°C):

8-Pin SOIC (Derate 5.88mW/°C above +70°C) .............. 471mW

Operating Temperature Ranges:

TSM1285BC ........................................................... 0°C to +70°C

TSM1285BE ....................................................... -40°C to +85°C

Storage Temperature Range .................................. -60°C to +150°C

Lead Temperature (Soldering, 10s ) ....................................... +300°C

Soldering Temperature (Reflow) ........................................... +260°C

Electrical and thermal stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These

are stress ratings only and functional operation of the device at these or any other condition beyond those indicated in the operational sections

of the specifications is not implied. Exposure to any absolute maximum rating conditions for extended periods may affect device reliability and

lifetime.

PACKAGE/ORDERING INFORMATION

ORDER NUMBER PART MARKING TEMPERATURE

RANGE CARRIER QUANTITY

TSM1285BCSA+ T1285B 0ºC to 70ºC Tube 97

TSM1285BCSA+T Tape

& Reel 2500

TSM1285BESA+ T1285BE -40ºC to +85ºC Tube 97

TSM1285BESA+T Tape

& Reel 2500

Lead-free Program: Silicon Labs supplies only lead-free packagi ng.

Consult Silicon Labs for products specified with wider operating temperature ranges.

TSM1285

TSM1285 Rev. 1.0 Page 3

ELECTRICAL SPECIFICATIONS

VDD = +2.7V to +3.6V; fSCLK = 4.8MHz, 50% duty cycle, 16 clocks/conversion cycle, 300ksps; 4.7μF capacit or at

REF; TA = -40ºC to +85ºC, unless otherwise noted. T y pical values apply at TA = +25°C.

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

DC ACCURACY (See Note 1)

Resolution 12 Bits

Relative Accuracy INL See Note 2 ±1.0 LSB

Differential Nonlinearity DNL No missing codes over temperature ±1.0 LSB

Offset Error ZE ±6.0 LSB

Gain Error GE See Note 3 ±6.0 LSB

Gain-Error Temperature Coefficient TCGE ±1.6 ppm/°C

DYNAMIC SPECIFICATIONS (fIN = 75kHz sine wave, 2.5VPP, fSAMPLE = 300ksps, fSCLK = 4.8MHz)

Signal-to-Noise

Plus Distortion Ratio SINAD 70 dB

Total Harmonic Distortion THD Including the 5th harmonic -80 dB

Spurious-Free Dynamic Range SFDR 80 dB

Intermodulation Distortion IMD f

= 73kHz, fB = 77kHz 76 dB

Full-Power Bandwidth FPBW -3dB point 3 MHz

Full-Linear Bandwidth FLBW SINAD > 68dB 250 kHz

CONVERSION RATE

Conversion Time tCONV See Note 4 3.3 μs

Track/Hold Acquisition Time t

CQ 625 ns

Aperture Delay t

D 10 ns

Aperture Jitter t

J < 50 ps

Serial Clock Frequency tSCLK 0.5 4.8 MHz

Duty Cycle 40 60 %

ANALOG INPUT (AIN)

Input Voltage Range VIN 0 2.5 V

Input Capacitance CIN

10 pF

INTERNAL REFERENCE

REF Output Voltage VREF 2.48 2.50 2.52 V

REF Short-Circuit Current T

= +25°C 15 mA

REF Output Tempco TCVREF ±15 ppm/°C

Load Regulation See Note 5; 0 to 0.75mA output load 0.1 2.0 mV/mA

Capacitive Bypass at REF 4.7 10 μF

DIGITAL INPUTS (SCLK, CS, SHDN)

Input High Voltage VINH 2.0 V

Input Low Voltage VINL 0.8 V

Input Hysteresis VHYST 0.2 V

Input Leakage IIN V

INL = 0V or VINH = VDD ±1 μA

Input Capacitance CIND 15 pF

DIGITAL OUTP UT (DOU T)

Output Voltage Low VOL I

SINK = 5mA 0.4 V

Output Voltage High VOH I

SOURCE = 0.5mA VDD - 0.5 V

Three-State Leakage Current IL VCS = +3V ±10 μA

Three-State Output Capacitance COUT VCS = +3V 15 pF

POWER SUPPLY

Positive Supply Voltage VDD See Note 6 2.7 3.6 V

Positive Supply Current IDD See Note 7; VDD = +3.6V 2.5 3.5 mA

Shutdown Supply Current ISHDN SCLK = VDD, SHDN = GND 2 10 μA

Power-Supply Rejection PSR VDD = +2.7V to 3.6V, midscale input ±0.5 mV

TSM1285

Page 4 TSM1285 Rev. 1.0

TIMING SPECIFICATIONS

VDD = +2.7V to +3.6V, TA = -40ºC to +85ºC, unless otherwise noted.

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

SCLK Period tCP 208 ns

SCLK Pulse-Width High tCH 83 ns

SCLK Pulse-Width Low tCL 83 ns

CS Fall to SCLK Rise Setup tCSS 45

SCLK Rise to CS Rise Hold tCSH 0

SCLK Rise to CS Fall Ignore tCSO 45

CS Rise to SCLK Rise Ignore tCS1 45

SCLK Rise to DOUT Hold tDOH C

LOAD = 20pF 13 ns

SCLK Rise to DOUT Valid tDOV C

LOAD = 20pF 100 ns

CS Rise to DOUT Disable tDOD C

LOAD = 20pF; Refer to Figure 2 13 85

CS Fall to DOUT Enable tDOE C

LOAD = 20pF; Refer to Figure 1

85 ns

CS Pulse-Width High tCSW 100

Note 1: Tested at VDD = VDD(MIN).

Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has been

calibrated.

Note 3: Internal reference, offset, and reference errors nulled.

Note 4: Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.

Note 5: External load should not change during conversion for specified accuracy. Guaranteed specification limit of 2mV/mA because of

production test limitations.

Note 6: Electrical characteristics are guaranteed from VDD(MIN) to VDD(MAX). For operations beyond this range, see Typical Operating

Characteristics.

Note 7: TSM1285 tested with 20pF on DOUT and fSCLK = 4.8MHz, 0 to 3V. DOUT = full scale.

TSM1285

TSM1285 Rev. 1.0 Page 5

TYPICAL PERFORMANCE CHARACTERISTICS

= +3V

;

SCLK

= 4.8MHz

;

LOAD

= 20

;

4.7

F ca

acitor at REF

;

= 25ºC

unless otherwise noted.

Integral Nonlinearity

INL - LSB

DIGITAL OUTPUT CODE

-0.4

-0.3

-0.2

-0.1

0.1

1k 2k

0 3k

Offset Error vs Supply Voltage

POWER SUPPLY VOLTAGE - Volt

OFFSET ERROR - LSB

-0.2

-0.8

-1.4

-1.8 2.7 3.06 3.24 3.42 2.88

TEMPERATURE - ºC

-15 35 60 85 10

-0.5

-1

-2

-1.5

1.2

0.8

0.6

-0.2

0.2

Differential Nonlinearit y

DNL - LSB

DIGITAL OUTPUT CODE

4k 5k 1k 2k

0 3k 4k 5k

0.2

0.3

0.4

-0.25

-0.2

-0.15

-0.1

0.2

0.25

-0.05

0.05

0.2

0.15

3.6

OFFSET ERROR - LSB

Offset Error vs Temperature

-40

0.5

0.6

0.4

0.2

-0.2

Gain Error vs Supply Voltage

POWER SUPPLY VOLTAGE - Volt

GAIN ERROR - LSB

Gain Error vs Temperature

TEMPERATURE - ºC

-15 35 60 85 10

GAIN ERROR - LSB

-40

-0.4

-0.6

-1

-1.2

-1.6

2.7 3.06 3.24 3.42 2.88 3.6

1.2

0.8

0.4

-0.4

TSM1285

Page 6 TSM1285 Rev. 1.0

Internal Reference Output vs Supply Voltage

REFERENCE OUTPUT - V

Power Supply Current vs Power Supply Voltage Power Supply Current vs Temperature

SUPPLY CURENT - mA

2.494

2.496

2.498

2.5

2.502

2.506

1.4

1.2

0.5

TYPICAL PERFORMANCE CHARACTERISTICS

= +3V

;

SCLK

= 4.8MHz

;

LOAD

= 20

;

4.7

F ca

acitor at REF

;

= 25ºC

unless otherwise noted.

POWER SUPPLY VOLTAGE - Volt TEMPERATURE - ºC

-15 35 60 85 10

-40

POWER SUPPLY VOLTAGE - Volt

2.7 3.06 3.24 3.42

2.88 3.6

TEMPERATURE - ºC

-15 35 60 85 10

-40

0.8

0.6

CODE = 1111 1111 1111

LOAD

= ∞

LOAD

= 10pF

CONVERTING

SCLK = 4.8MHz

STATIC

1.2

1.1

0.9

0.5

0.8

0.6

SUPPLY CURENT - mA

STATIC, V

= 3V

CONVERTING, V

= 3V

2.504

Internal Reference Output vs Temperature

REFERENCE OUTPUT - V

2.498

2.5

2.502

2.504

2.506

2.510

2.508

2.7 3.06 3.24 3.42

2.88 3.6

1.3

1.1

0.7

0.9

0.7

TSM1285

TSM1285 Rev. 1.0 Page 7

PIN FUNCTIONS

PIN NAME FUNCTION

1 VDD Power Supply Voltage, +2.7V to +3.6V.

2 AIN Analog Signal Input; Unipolar, 0 to VREF input rang e.

3 SHDN Active-Low Shutdown Input. Toggling SHDN high-to-low powers down the TSM1285 and

reduces the supply current to 2μA (typ).

4 REF

Reference Voltage for Analog-to-Digital Conversion – an internal 2.5V reference output. Bypass

with a good-quality 4.7μF capacitor.

5 GND

Analog and Digital Ground. Connect the TSM1285’s GND pin at one and only one point to the

system analog ground plane.

6 DOUT

Serial-Data Output. DOUT toggles state on SCLK’s rising edge and is high impedance when CS

is logic high.

7 CS Active-Low Chip Select. The CS signal initiates the conversion process on its falling edge. When

the CS input is logic high, DOUT is high impedance.

8 SCLK

Serial-Clock Input. The SCLK signal controls the conversion process and transfers output data

at rates up to 4.8MHz.

Figure 1: Output Loading Circuits for DOUT Ena ble Time (t

DOE

Figure 2: Output Loading Circuits for DOUT Disable Time (t

DOD

TSM1285

Page 8 TSM1285 Rev. 1.0

DESCRIPTION OF OPERATION

Converter Operation

The TSM1285 uses an input track-and-hold (T/H ) and

a successive-approximation register (SAR) circuitry to

convert an analog input signal to a digital 12-bit

output. No external-hold capacitor is needed for the

track/hold circuit. Figure 3 illustrates the TSM1285 in

its simplest configuration. The TSM1285 converts

input signals within the 0V to V

REF

range in 3.3μs

including the track-and-hold’s acquisition time. The

serial interface requires only three digital lines (SCLK,

CS, and DOUT) and provides an easy interface to

microprocessors (μPs) and microcontrollers (μCs).

The TSM1285 has two operating modes: normal and

shutdown. Toggling (or driving) the SHDN pin low

shuts down the ADCs and reduces supply current

below 1 μA when V

≤ 3.6V. Open-circuiting or

toggling (or driving) the SHDN pin high or places the

ADCs into operational mode. Toggling the CS pin to

logic low initiates a conversion where the conversion

result is available at DOUT in unipolar serial format.

The serial data stream consists of three leading zeros

followed by the data bits with the MSB first. All

transitions on the DOUT pin occur within 20ns after

the low-to-high transition of SCLK. Serial interface

timing details of the TSM1285 are illustrated in

Figures 8 and 9.

Analog Input

Figure 4 illustrates the sampling architecture of the

analog-to-digital converter’s comparator. The full-

scale input voltage is set by the TSM1285’s internal

2.5-V reference.

Track-and-Hold Operation

During track mode, the analog signal is acquired and

stored on the internal hold capacitor. During hold

mode, the track/hold switches SW1 and SW2 are

opened thereby maintaining a constant input level to

the converter’s SAR subcircuit.

During the acquisition phase with SW1 and SW2 on

TRACK, the input capacitor, C

HOLD

, is charged to the

analog input (AIN). Toggling the CS pin low causes

the acquisition process to stop. At this instant,

track/hold switches SW1 and SW2 are moved to

HOLD position and the input side of C

HOLD

is then

switched to GND. Unbalancing Node ZERO at the

comparator’s input, the retained charge on C

HOLD

represents a sample of the input signal applied to the

converter.

In hold mode and to restore Node ZERO to 0V within

the limits of the converter’s 12- bit resolution, the

output of the capacitive digital-to-analog converter

(the CDAC) is adjusted during the remainder of the

conversion cycle. In other words, the stored charge

on C

HOLD

is transferred to the binary-weighted CDAC

where it is converted into a digital representation of

the analog input signal. At end of the conversion

Figure 3: TSM1285 Typical Application

Circuit.

Figure 4: TSM1285 Equivalent Input Circuit

Details.

TSM1285

TSM1285 Rev. 1.0 Page 9

process, the input side of CHOLD is switched back to

AIN so as to be charged to the input signal again.

An ADC’s acquisition time is function of how fast its

input capacitance can be charged. If an input signal’s

driving-point source impedance is high, the

acquisition time is lengthened and more time must be

allowed between conversions. The acquisition time

(tACQ) is the maximum time the ADC requires to

acquire the signal and is also the minimum time

needed for the signal to be acquired. The TSM1285’s

acquisition time is calculated from the following

expression:

tACQ = 9 x (RS + RIN) x 10pF

where RIN = 100Ω (the TSM1285’s internal track/hold

switch resistance), RS = the input signal’s source

impedance, and tACQ is never less than 625ns.

Because of the input structure of the TSM1285,

sources with output impedances of 1kΩ or less do not

affect significantly the AC performance of the

TSM1285. The TSM1285 can still be used in

applications where the source impedance is higher so

long as a 0.01μF capacitor is connected between the

analog input and GND. Limiting the ADC’s input

signal bandwidth, the use of an external, input

capacitor forms an RC filter with the input’s source

impedance.

Input Bandwidth Conside rations

Since the TSM1285’s input track-and-hold circuit

exhibits a 10 MHz small-signal bandwidth, it is

possible to measure periodic signals and to digitize

high-speed transient events with signal bandwidths

higher than the TSM1285’s sampling rate by using

undersampling techniques. To avoid the aliasing of

high-frequency signals into the frequency band of

interest, the use of external anti-alias filter circuits

(discrete or integrated) is recommended. The time

constant of the external anti-alias filter should be set

so as not to interfere with the desired signal

bandwidth.

Analog Input Protection

The TSM1285 incorporates internal protection diodes

that clamp the analog input between VDD and GND.

These internal protection diodes allow the AIN pin to

swing from GND - 0.3V to VDD + 0.3V without causing

damage to the TSM1285. However, for accurate

conversions near full scale, the input signal must not

exceed VDD by more than 50mV or be lower than

GND by 50mV.

If the analog inputs can exceed 50mV beyond the

supplies, then the current in the forward-biased

protection diodes should be limited to less than

2mA since large fault currents can affect

conversion results.

Internal Reference Considerations

The TSM1285 has an internal voltage reference that

is factory-trimmed to 2.5V. The internal reference

output is connected to the REF pin and is also

connected to the ADC’s internal CDAC. The REF

output can be used as a reference voltage source for

other components external to the ADC and can

source up to 750μA. To maintain conversion

accuracy to within 1 LSB, a 4.7μF capacitor from the

REF pin to GND is recommended. While larger-

valued capacitors can be used to further reduce

reference wide-band noise, larger capacitor values

can increase the TSM1285’s wake-up time when

exiting from shutdown mode (see the “Using SHDN to

Reduce Operating Supply Current” section for more

information). When in shutdown (that is, when

SHDN = 0), the TSM1285’s internal 2.5-V reference

is disabled.

Serial Digital Interface

Initialization after Power-Up and Starting a

Conversion

If the SHDN pin is not driven low upon an initial, cold-

start condition, it may take up to 2.5ms for a fully-

discharged 4.7μF reference bypass capacitor to

provide adequate charge for specified conversion

accuracy. As a result, conversions should not be

initiated during this reference capacitor charge-up

delay. To initiate a conversion, the CS pin is toggled

(or driven) low. At the CS’s falling edge, the

TSM1285’s internal track-and-hold is placed in hold

mode and a conversion is initiated. Data can then be

transferred out of the ADC using an external serial

clock.

TSM1285

Page 10 TSM1285 Rev. 1.0

Figure 6: TSM1285 Shutdown Operation.

Using the ADC’s SHDN to Reduce Operating

Supply Current

Power consumption can be reduced significantly by

turning off the TSM1285 in between conversions.

Figure 5 illustrates the TSM1285’s average supply

current versus conversion rate. The wake-up delay

time (t

WAKE

) is the time from when the SHDN pin is

deasserted to the time when a conversion may be

initiated (Refer to Figure 6). This delay time depends

on how long the ADC was in shutdown (Refer to

Figure 7) because the external 4.7μF reference

bypass capacitor is discharged slowly when

SHDN = 0.

Timing and Control Details

The CS and SCLK digital inputs control the

TSM1285’s conversion-start and data-read

operations. The ADC’s serial-interface operations are

illustrated in Figures 8 and 9.

A CS high-to-low transition initiates the conversion

sequence - the input track-and-hold samples the input

signal level, the ADC begins to convert, and the

DOUT pin changes state from high impedance to

logic low. The external SCLK signal is used to drive

the conversion process and is also used to transfer

the converted data out of the ADC as each bit of

conversion is determi ned.

The SCLK signal transfers data after a low-to-high

transition of the third (3

) SCLK pulse. After each

subsequent SCLK rising edge, transitions on the

DOUT pin occur in 20ns. The third rising clock edge

produces the MSB of the conversion at DOUT,

followed by the remaining bits. Since there are twelve

data bits and three leading zeros, at least fifteen

rising clock edges are needed to transfer the entire

data stream. Extra SCLK pulses occurring after the

conversion result has been completely transferred out

and, before to a new, low-to-high transition on CS,

produce a string trailing zeros at DOUT. In addition,

the extra SCLK pulses have no effect on converter

operation.

Minimum conversion cycle time can be accomplished

by: (a) toggling the CS pin high after reading the

conversion result’s LSB; and (b), after the specified

minimum time defined by t

has elapsed, toggling

the CS pin low again to initiate the next conversion.

Output Data Coding and Transfer Fun ction

Conversion results at the TSM1285’s DOUT pin are

straight binary data. Figure 10 illustrates the nominal

transfer function where code transitions occur halfway

between successive integer LSB values. If

REF

= +2.500V, then 1 LSB = 610μV or 2.500V/4096.

CONVERSION RATE - ksps

SUPPLY CURENT - mA

= 3V

DOUT = FS

= ∞

= 10pF

100

0.1 0.1 1 100 1k

Figure 5: TS M1285 Supply Current vs Conversion Rate

TSM1285

TSM1285 Rev. 1.0 Page 11

Figure 8: TSM1285 Serial Interface Tim i ng Sequence

Figure 9: TSM1285 Serial Interface Timing Specifications in Detail.

APPLICATIONS INFORMATION

Connection to Industry-Stand ard Serial Interfaces

The TSM1285’s serial interface is fully compatible

with SPI/QSPI and MICROWIRE standard serial

interfaces (Refer to Figure 11). For serial interface

operation with these standards, the CPU’s serial

interface should be set to master mode so the CPU

then generates the serial clock. Second, the CPU’s

serial clock should be configured to operate up to

4.8MHz. The process to configure the serial clock and

data transfer operation is as follows:

1) Using a general-p urpose I/O line from the CPU, the

CS pin is driven low to start a conversion. DOUT

transitions from high impedance to logic low. The

SCLK polarity should be low to start the conversion

process corre ctly .

2) Next, SCLK is activated for a minimum of 15 SCLK

cycles where the first two SCLKs produce zeros at

the DOUT pin. Data at DOUT is formatted MSB first

and DOUT transitions occur 20ns after the third (3

)

SCLK low-to-high transition. Once the low-to-high

SCLK transition has occurred, data is valid at DOUT

TIME IN SHUTDOWN MODE - sec

REFERENCE POWER-UP DELAY TIME - ms

REF

= 4.7µF

0.5

0 0.1m 10m 1 10

100m

2.5

1.5

Figure 7: T S M1285 Reference Power-Up Delay

vs Duration in Shutdown Mode

TSM1285

Page 12 TSM1285 Rev. 1.0

according to the t

DOV

(SCLK Rise to DOUT Valid)

timing specification. Valid output data can then be

transferred into µP or µCs on SCLK low-to-high

transitions.

3) At or after the 15th SCLK low-to-high transition, the

CS pin can be toggled high to halt the transfer

process. If the CS pin remains low and the SCLK is

still active, trailing zeros are transferred out after the

LSB.

4) Once the CS pin is held at logic high for at least

, a new conversion cycle is started when the CS

pin is toggled low. If a conversion is aborted by

toggling the CS pin high before the current

conversion has completed, a new conversion cycle

can only be started after a the ADC has acquired the

signal (t

ACQ

The CS pin must be held low and SCLK active until

all data bits are transferred out of the ADC. As shown

in Figure 8, data can be transferred in two 8-bit bytes

or continuously. The bytes contain the result of the

conversion padded with three leading 0s in the first 8-

bit byte and 1 trailing 0 in the second 8-bit byte.

SPI and MICROWIRE Interface Details

When using an SPI or MICROWIRE interface, setting

[CPOL:CPHA] = [0:0] configures the microcontroller’s

serial clock and sampling edge for the TSM1285. The

conversion commences on a high-to-low transition of

the CS pin. The DOUT pin transitions from a high-

impedance state to a logic low, indicating a

conversion is in progress. Two consecutive 1-byte

data reads are required to transfer the full 12-bit

result from the ADC. DOUT output data transitions

occur on the SCLK’s low-to-high transition and are

transferred into the downstream microcontroller on

the SCLK’s low-to-high transition.

The first byte contains three leading 0s and then five

bits of the conversion result. The second byte

contains the remaining seven bits of the conversion

result and one trailing zero. Refer to Figure 11 for the

circuit connections and to Figure 12 for all timing

details.

QSPI Details

Using a QSPI microcontroller, setting

[CPOL:CPHA] = [0:1] configures the microcontroller’s

serial clock and sampling edge for the TSM1285.

Unlike the SPI, which requires two 1-byte reads to

transfer all 12 bits of data from the ADC, the QSPI

allows a minimum number of clock cycles necessary

to transfer data from the ADC to the microcontroller.

Thus, the TSM1285 requires 15 SCLK clock cycles

from the microcontroller to transfer the 12 bits of data

with no trailing zeros. As shown in Figure 13, the

conversion results contain two leading 0s followed by

the MSB-first-formatted, 12-bit data stream.

Figure 10: ADC Unipolar Transfer Function

for Straight Binary Digital Data.

Figure 11: TSM1285 Circuit Connections to

Industry-Standard Serial

Interfaces.

TSM1285

TSM1285 Rev. 1.0 Page 13

Figure 12: SPI/MICROWIRE-TSM1285 Serial Interface Timing Details with [CPOL:CPHA] = [0:0].

Figure 13: QSPI-TSM1285 Serial Interface Timing Details with [CPOL:CPHA] = [0:1].

PCB Layout, Ground Plane Management, and

Capacitive Bypassing

For best performance, printed circuit boards should

always be used and wire-wrap boards are not

recommended. Good PC board layout techniques

ensure that digital and analog signal lines are kept

separate from each other, analog and digital

(especially clock) lines are not routed parallel to one

another, and high-speed digital lines are not routed

underneath the ADC package.

A recommended system ground connection is

illustrated in Figure 14. A single-point analog ground

(star ground point) should be created at the ADC’s

GND and separate from the logic ground. All analog

grounds as well as the ADC’s GND pin should be

connected to the star ground. No other digital system

ground should be connected to this ground. For

lowest-noise operation, the ground return to the star

ground’s power supply should be low impedance and

as short as possible.

High-frequency noise on the V

power supply may

affect the ADC’s high-speed comparator. Therefore, it

is necessary to bypass the V

supply pin to the star

ground with 0.1μF and 1μF capacitors in parallel and

placed close to the ADC’s Pin 1. Component lead

lengths should be very short for optimal supply-noise

rejection. If the power supply is very noisy, an

optional 10-Ω resistor can be used in conjunction with

the bypass capacitors to form a low-pass filter as

shown in Figure 14.

Figure 14: Recommended Power Supply

Bypassing and Star Ground

Configuration.

TSM1285

Page 14 Silicon Laboratories, Inc. TSM1285 Rev. 1.0

400 West Cesar Chavez, Austin, TX 78701

+1 (512) 416-8500 ▪ www.silabs.com

PACKAGE OUTLINE DRAWING

8-Pin SOIC Package Outline Drawing

(N.B., Drawings are not to scale)

Patent Notice

Silicon Labs invests in research and development to help our customers differentiate in the market with innovative low-power, small size,

analog-intensive mixed-signal solutions. Silicon Labs' extensive patent portfolio is a testament to our unique approach and world-class

engineering team.

The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.

Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the

use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or

parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty,

representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any

liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation

consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended

to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where

personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized

application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.

Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc.

Other products or brandnames mentioned herein are trademarks or registered trademarks of their re spective holders.

Disclaimer

Silicon Laboratories intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers

using or intending to use the Silicon Laboratories products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific

device, and "Typical" parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Laboratories

reserves the right to make changes without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy

or completeness of the included information. Silicon Laboratories shall have no liability for the consequences of use of the information supplied herein. This document does not imply

or express copyright licenses granted hereunder to design or fabricate any integrated circuits. The products must not be used within any Life Support System without the specific

written consent of Silicon Laboratories. A "Life Support System" is any product or system intended to support or sustain life and/or health, which, if it fails, can be reasonably expected

to result in significant personal injury or death. Silicon Laboratories products are generally not intended for military applications. Silicon Laboratories products shall under no

circumstances be used in weapons of mass destruction including (but not limited to) nuclear, biological or chemical weapons, or missiles capable of delivering such weapons.

Trademark Information

Silicon Laboratories Inc., Silicon Laboratories, Silicon Labs, SiLabs and the Silicon Labs logo, CMEMS®, EFM, EFM32, EFR, Energy Micro, Energy Micro logo and combinations

thereof, "the world’s most energy friendly microcontrollers", Ember®, EZLink®, EZMac®, EZRadio®, EZRadioPRO®, DSPLL®, ISOmodem ®, Precision32®, ProSLIC®, SiPHY®,

USBXpress® and others are trademarks or registered trademarks of Silicon Laboratories Inc. ARM, CORTEX, Cortex-M3 and THUMB are trademarks or registered trademarks of

ARM Holdings. Keil is a registered trademark of ARM Limited. All other products or brand names mentioned herein are trademarks of their respective holders.

http://www.silabs.com

Silicon Laboratories Inc.

400 West Cesar Chavez

Austin, TX 78701

USA

Smart.

Connected.

Energy-Friendly

Products

www.silabs.com/products Quality

www.silabs.com/quality Support and Community

community.silabs.com