SPMC68CK338CPV14 - Motorola / Freescale Semiconductor

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MOTOROLA

SEMICONDUCTOR

TECHNICAL DATA

MC68CK338

Technical Summar y

32-Bit Modular Microcontroller

1 Introduction

The MC68CK338, a highly-integrated 32-bit microcontroller, combines high-performance data manipu-

lation capabilities with powerful peripheral subsystems. The MCU is built up from standard modules that

interface through a common intermodule bus (IMB). Standardization facilitates rapid development of

devices tailored for specific applications.

The MCU incorporates a low-power 32-bit CPU (CPU32L), a low-power system integration module

(SIML), a queued serial module (QSM), and a configurable timer module 6 (CTM6).

The MCU clock can either be synthesized from an external reference or input directly. Operation with a

32.768 kHz reference frequency is standard. The maximum system clock speed is 14.4 MHz. System

hardware and software allow changes in clock rate during operation. Because MCU operation is fully

static, register and memory contents are not affected by clock rate changes.

High-density complementary metal-oxide semiconductor (HCMOS) architecture and 3V nominal oper-

ation make the basic power consumption of the MCU low. Power consumption can be minimized by

either stopping the system clock, or alternatively, stopping the system clock only at the CPU32L, and

allowing the other modules to continue operation. The CPU32 instruction set includes a low-power stop

(LPSTOP) command that allows either of these power saving modes.

The CTM6 includes new features such as a port I/O submodule, a 64-byte RAM submodule and a real

time clock submodule.

Refer to the Motorola Microcontroller Technologies Group Web page at http://www.mcu.sps.mot.com

for the most current listing of device errata and customer information.

Table 1 Ordering Information

Package Type Frequency

(MHz) Voltage Temperature Package

Order

Quantity

Order Number

144–Pin TQFP 14.4 MHz 2.7V to 3.6V – 40 to + 85

C 2 pc tray

60 pc tray

300 pc tray

SPMC68CK338CPV14

MC68CK338CPV14

MC68CK338CPV14B1

Section Page

MOTOROLA MC68CK338

2 MC68CK338TS/D

1 Introduction

1.1 Features ......................................................................................................................................3

1.2 Block Diagram .............................................................................................................................4

1.3 Pin Assignments ..........................................................................................................................5

1.4 Address Map ...............................................................................................................................6

1.5 Intermodule Bus ..........................................................................................................................6

2 Signal Descriptions

2.1 Pin Characteristics ......................................................................................................................7

2.2 MCU Power Connections ............................................................................................................8

2.3 MCU Driver Types .......................................................................................................................8

2.4 Signal Characteristics ..................................................................................................................9

2.5 Signal Function ..........................................................................................................................10

3 Low-Power System Integration Module

3.1 Overview ...................................................................................................................................12

3.2 System Configuration Block ......................................................................................................14

3.3 System Clock ............................................................................................................................16

3.4 System Protection Block ...........................................................................................................22

3.5 External Bus Interface ...............................................................................................................26

3.6 Chip-Selects ..............................................................................................................................30

3.7 General-Purpose Input/Output ..................................................................................................38

3.8 Resets .......................................................................................................................................41

3.9 Interrupts ...................................................................................................................................44

3.10 Factory Test Block .....................................................................................................................47

4 Low-Power Central Processor Unit

4.1 Overview ...................................................................................................................................48

4.2 Programming Model ..................................................................................................................48

4.3 Status Register ..........................................................................................................................50

4.4 Data Types ................................................................................................................................51

4.5 Addressing Modes .....................................................................................................................51

4.6 Instruction Set Summary ...........................................................................................................51

4.7 Background Debugging Mode ...................................................................................................56

5 Queued Serial Module

5.1 Overview ...................................................................................................................................57

5.2 Address Map .............................................................................................................................58

5.3 Pin Function ..............................................................................................................................59

5.4 QSM Registers ..........................................................................................................................59

5.5 QSPI Submodule .......................................................................................................................64

5.6 SCI Submodule .........................................................................................................................72

6 Configurable Timer Module 6

6.1 Overview ...................................................................................................................................78

6.2 Address Map .............................................................................................................................80

6.3 Time Base Bus System .............................................................................................................82

6.4 Bus Interface Unit Submodule (BIUSM) ....................................................................................84

6.5 Counter Prescaler Submodule (CPSM) ....................................................................................85

6.6 Clock Sources for Counter Submodules ...................................................................................87

6.7 Free-Running Counter Submodule (FCSM) ..............................................................................87

6.8 Modulus Counter Submodule (MCSM) .....................................................................................90

6.9 Single Action Submodule (SASM) .............................................................................................93

6.10 Double-Action Submodule (DASM) ...........................................................................................97

6.11 Real-Time Clock Submodule (RTCSM) with Low-Power Oscillator ........................................104

6.12 Parallel Port I/O Submodule (PIOSM) .....................................................................................107

6.13 Static RAM Submodule (RAMSM) ..........................................................................................108

6.14 RTCSM and RAMSM Standby Operation ...............................................................................108

6.15 CTM6 Interrupts ......................................................................................................................109

7 Electrical Characteristics

111

TABLE OF CONTENTS

MC68CK338 MOTOROLA

MC68CK338TS/D 3

1.1 Features

• Modular Architecture

• Low-Power Central Processing Unit (CPU32L)

— Virtual memory implementation

— Loop mode of instruction execution

— Improved exception handling for controller applications

— Table lookup and interpolate instruction

— CPU-only LPSTOP operation/normal MCU LPSTOP operation

• Low-Power System Integration Module (SIML)

— External bus support

— Twelve programmable chip-select outputs

— System protection logic

— On-chip PLL for system clock

— Watchdog timer, clock monitor, and bus monitor

— Expanded LPSTOP operation

• Queued Serial Module (QSM)

— Enhanced serial communication interface (SCI)

— Queued serial peripheral interface (QSPI)

— Dual function I/O ports

• Configurable Timer Module 6 (CTM6)

— One bus interface unit submodule (BIUSM)

— One counter prescaler submodule (CPSM)

— Three modulus counter submodules (MCSM)

— One free-running counter submodule (FCSM)

— Eleven double action submodules (DASM)

— Four (eight channels) single action submodules (SASM)

— One real time clock submodule (RTCSM)

— One port I/O submodule (PIOSM)

— Two 32-byte RAM submodules (RAMSM)

MOTOROLA MC68CK338

4 MC68CK338TS/D

1.2 Block Diagram

Figure 1 MC68CK338 Block Diagram

1 FCSM

3 MCSM

11 DASM

4 SASM

338 BLOCK

PQS5/PCS2

PQS7/TXD

PQS4/PCS1

PQS6/PCS3

CPU32LQSM

IMB

CTM6

PQS0/MISO

PQS1/MOSI

PQS2/SCK

PORTQS

TXD

PCS2

SCK

MISO

MOSI

CONTROL

PCS1

PQS3/PCS0/SS PCS0

RXD

PCS3

CONTROL

BKPT/DSCLK

IFETCH/DSI

IPIPE/DSO

FREEZE

DSI

DSO

DSCLK

IPIPE

IFETCH

BKPT

IRQ[7:1]

ADDR[23:0]

CONTROL

PORT F

CONTROL

FC2

FC1

FC0

BGACK

MODCLK

ADDR[23:19]

CLOCK

EBI

CS[10:0]

BR/CS0

BG/CS1

BGACK/CS2

R/W

RESET

HALT

BERR

CLKOUT

XTAL

EXTAL

CHIP

SELECTS CSBOOT

ADDR[18:0]

DATA[15:0]DATA[15:0]

QUOT

TEST

FREEZE/QUOT

TSC

CONTROL

TSC

PC0/FC0/CS3

PC1/FC1/CS4

PC2/FC2/CS5

PC3/ADDR19/CS6

PC4/ADDR20/CS7

PC5/ADDR21/CS8

PC6/ADDR22/CS9

ADDR23/CS10

PF7/IRQ7

PF6/IRQ6

PF5/IRQ5

PF4/IRQ4

PF3/IRQ3

PF2/IRQ2

PF1/IRQ1

PF0/MODCLK

CONTROL

PORT E

SIZ1 PE7/SIZ1

SIZ0 PE6/SIZ0

DSACK0 PE0/DSACK0

DSACK1 PE1/DSACK1

AVEC PE2/AVEC

RMC PE3/RMC

AS PE5/AS

DS PE4/DS

CTD[10:4]

CTM31L

CTS18B

CTD[29:26]

XRTC

CTIO[5:0]

CTM31L

CTD[10:4]

CTIO[5:0]

XRTC

CTS18B

CTS18A CTS18A

CTD[29:26]

PORT C

XFC

VDDSYN

EXRTC EXRTC

VRTC VRTC

1 PIOSM

64 BYTES

1 RTCSM

2 RAMSM

CTS24B CTS24B

CTS24A CTS24A

CTS14B CTS14B

CTS14A CTS14A

PORT CT

VSSRTCOSC VSSRTCOSC

MC68CK338 MOTOROLA

MC68CK338TS/D 5

1.3 Pin Assignments

Figure 2 MC68CK338 Pin Assignments

MC68CK338

VSSE

CTD5

CTD4

VSSRTCOSC

XRTC

EXRTC

VSSRTCOSC

CTIO2

CTIO3

CTS14B

CTS14A

CTIO4

CTIO5

CTS18B

CTS18A

CTS24B

CTS24A

VSSI

VDDI

CTD29

CTD28

CTD27

CTD26

CTM31L

ADDR23/CS10

ADDR22/CS9

ADDR21/CS8

ADDR20/CS7

ADDR19/CS6

FC2/CS5

FC1/CS4

VSSE

ADDR17

ADDR18

IPIPE/DSO

IFETCH/DSI

BKPT/DSCLK

TSC

FREEZE/QUOT

VSSI

XTAL

VDDSYN

EXTAL

VDDI

XFC

VDDE

CLKOUT

VSSE

RESET

HALT

BERR

IRQ7

IRQ6

IRQ5

IRQ4

IRQ3

IRQ2

IRQ1

MODCLK

R/W

VSSE

VDDE

FC0/CS3

BGACK/CS2

BG/CS1

BR/CS0

CSBOOT

DATA0

DATA1

DATA2

DATA3

DATA4

DATA5

DATA6

DATA7

VSSI

DATA8

DATA9

DATA10

DATA11

DATA12

DATA13

DATA14

DATA15

ADDR0

DSACK0

DSACK1

AVEC

RMC

SIZ0

SIZ1

VDDE

CTD6

CTD7

CTD8

CTD9

CTD10

CTIO1

CTIO0

VRTC

MISO

MOSI

SCK

PCS0/SS

PCS1

PCS2

PCS3

TXD

VSSI

RXD

ADDR1

ADDR2

ADDR3

ADDR4

ADDR5

ADDR6

ADDR7

ADDR8

ADDR9

ADDR10

ADDR11

ADDR12

ADDR13

ADDR14

ADDR15

ADDR16

VDDE

144

143

142

141

140

139

138

137

136

135

134

133

132

131

130

129

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

104

103

102

101

100

338 144-PIN QFP

MOTOROLA MC68CK338

6 MC68CK338TS/D

1.4 Address Map

Figure 3

shows a map of the MCU internal addresses. Unimplemented blocks are mapped externally.

Figure 3 MC68CK338 Address Map

1.5 Intermodule Bus

The IMB is a standardized bus developed to facilitate design and operation of modular microcontrollers.

It contains circuitry that supports exception processing, address space partitioning, multiple interrupt

levels, and vectored interrupts. The standardized modules in the MCU communicate with one another

and with external components via the IMB. The IMB uses 24 address lines and 16 data lines.

338 ADDRESS MAP

$YFFDFF

$YFFC00

$YFFA7F

$YFFA00

$YFF5FF

$YFF400

SIML

QSM

CTM6

Y = M111, WHERE M IS THE STATE OF THE MODULE MAPPING (MM) BIT IN THE SIML CONFIGURATION REGISTER.

512 BYTES

128 BYTES

512 BYTES

MC68CK338 MOTOROLA

MC68CK338TS/D 7

2 Signal Descriptions

2.1 Pin Characteristics

Table 2

shows MCU pins and their characteristics. All inputs detect CMOS logic levels. All inputs can

be put in a high-impedance state, but the method of doing this differs depending upon pin function. Re-

fer to

Table 4

for a description of output drivers. An entry in the discrete I/O column of

Table 2

indicates

that a pin has an alternate I/O function. The port designation is given when it applies. Refer to

Figure

for information about port organization.

Table 2 MCU Pin Characteristics

Mnemonic Output

Driver Input

Synchronized Input

Hysteresis Discrete

I/O Port

Designation

ADDR23/CS10 A Yes No — —

ADDR[22:19]/CS[9:6] A Yes No O PC[6:3]

ADDR[18:0] A Yes No — —

AS B Yes No I/O PE5

AVEC B Yes No I/O PE2

BERR B Yes

No — —

BG/CS1 B— ———

BGACK/CS2 B Yes No — —

BKPT/DSCLK — Yes Yes — —

BR/CS0 B Yes No — —

CLKOUT A — — — —

CSBOOTB— ———

CTD[29:26] Ao Yes Yes I/O —

CTD[10:4] Ao Yes Yes I/O —

CTIO[5:0] A Yes Yes I/O —

CTM31L A Yes Yes I —

CTS24[B:A] A Yes Yes I/O —

CTS18[B:A] A Yes Yes I/O —

CTS14[B:A] A Yes Yes I/O —

DATA[15:0] Aw Yes

No — —

DS B Yes No I/O PE4

DSACK[1:0] B Yes No I/O PE[1:0]

DSI/IFETCH A Yes Yes — —

DSO/IPIPE A— ———

EXRTC — — Yes — —

EXTAL — — Yes — —

FC[2:0]/CS[5:3] A Yes No O PC[2:0]

FREEZE/QUOT A — — — —

HALT Bo Yes

No — —

IRQ[7:1] B Yes Yes I/O PF[7:1]

MISO Bo Yes

Yes I/O PQS0

MODCLK B Yes

No I/O PF0

MOSI Bo Yes

Yes I/O PQS1

MOTOROLA MC68CK338

8 MC68CK338TS/D

2.2 MCU Power Connections

2.3 MCU Driver Types

NOTES:

1. HALT and BERR synchronized only if late HALT or BERR.

2. DATA[15:0] synchronized during reset only. MODCLK and QSM pins synchronized only if used as port I/O pins.

PCS0/SS Bo Yes

Yes I/O PQS3

PCS[3:1] Bo Yes

Yes I/O PQS[6:4]

RESET Bo Yes Yes — —

RMC A Yes Yes I/O PE3

R/W A Yes No — —

RXD — No Yes — —

SCK Bo Yes

Yes I/O PQS2

SIZ[1:0] B Yes No I/O PE[7:6]

TSC — Yes Yes — —

TXD Bo Yes

Yes I/O PQS7

XFC — — — — —

XRTC — — — — —

XTAL — — — — —

Table 3 MCU Power Connections

DDSYN

Clock Synthesizer

DDE

, V

SSE

External periphery power (source and drain)

DDI

, V

SSI

Internal module power (source and drain)

RTC

RTCSM/RAMSM standby power

SSRTCOSC

Ground connection for real-time clock oscillator

Table 4 MCU Output Driver Types

Type Description

A Output-only signals that are always driven; no external pull-up required

Ao Type A output that can be operated in an open drain mode

Aw Type A output with weak P-channel pull-up during reset

BThree-state output that includes circuitry to pull up output before high impedance

is established, to ensure rapid rise time. An external holding resistor is required to

maintain logic level while the pin is in the high-impedance state.

Bw Type B output with weak P-channel pull-up during reset

Bo Type B output that can be operated in an open-drain mode

Table 2 MCU Pin Characteristics (Continued)

Mnemonic Output

Driver Input

Synchronized Input

Hysteresis Discrete

I/O Port

Designation

MC68CK338 MOTOROLA

MC68CK338TS/D 9

2.4 Signal Characteristics

Table 5 MCU Signal Characteristics

Signal Name MCU Module Signal Type Active State

ADDR[23:0] SIML Bus —

AS SIML Output 0

AVEC SIML Input 0

BERR SIML Input 0

BG SIML Output 0

BGACK SIML Input 0

BKPT CPU32L Input 0

BR SIML Input 0

CLKOUT SIML Output —

CS[10:0] SIML Output 0

CSBOOT SIML Output 0

CTD[29:26] CTM6 Input/Output —

CTD[10:4] CTM6 Input/Output —

CTIO[5:0] CTM6 Input/Output —

CTM31L CTM6 Input —

CTS24[B:A] CTM6 Input/Output —

CTS18[B:A] CTM6 Input/Output —

CTS14[B:A] CTM6 Input/Output —

DATA[15:0] SIML Bus —

DS SIML Output 0

DSACK[1:0] SIML Input 0

DSCLK CPU32L Input Serial Clock

DSI CPU32L Input —

DSO CPU32L Output —

EXRTC CTM6 Input —

EXTAL SIML Input —

FC[2:0] SIML Output —

FREEZE SIML Output 1

HALT SIML Input/Output 0

IFETCH CPU32L Output —

IPIPE CPU32L Output —

IRQ[7:1] SIML Input 0

MISO QSM Input/Output —

MODCLK SIML Input —

MOSI QSM Input/Output —

PC[6:0] SIML Output —

PCS[3:0] QSM Input/Output —

PE[7:0] SIML Input/Output —

PF[7:0] SIML Input/Output —

PQS[7:0] QSM Input/Output —

QUOT SIML Output —

MOTOROLA MC68CK338

10 MC68CK338TS/D

2.5 Signal Function

RESET SIML Input/Output 0

RMC SIML Output 0

R/W SIML Output 0

RXD QSM Input —

SCK QSM Input/Output —

SIZ[1:0] SIML Output —

SS QSM Input 0

TSC SIML Input —

TXD QSM Output —

XFC SIML Input —

XRTC CTM6 Output —

XTAL SIML Output —

Table 6 MCU Signal Function

Signal Name Mnemonic Function

Address Bus ADDR[23:0] 24-bit address bus

Address Strobe AS Indicates that a valid address is on the address bus

Autovector AVEC Requests an automatic vector during interrupt acknowledge

Bus Error BERR Signals a bus error to the CPU

Bus Grant BG Indicates that the MCU has relinquished the bus

Bus Grant

Acknowledge BGACK Indicates that an external device has assumed bus mastership

Breakpoint BKPT Signals a hardware breakpoint to the CPU

Bus Request BR Indicates that an external device requires bus mastership

System Clockout CLKOUT System clock output

Chip Selects CS[10:0] Select external devices at programmed addresses

Boot Chip Select CSBOOT Chip select for external boot startup ROM

Configurable Timer

Double-Action CTD[29:26],

CTD[10:4] Double-action submodule (DASM) signals.

Can also be used as general purpose I/O pins

Configurable Timer

Modulus Counter

Load CTM31L External load for modulus counter.

Can also be used as general purpose input

RTC Configurable

Timer Oscillator EXRTC, XRTC CTM real time clock oscillator input/output

Configurable Timer

Port Input/Output CTIO[5:0] General-purpose I/O pins

Configurable Timer

Single-Action

CTS24[B:A]

CTS18[B:A]

CTS14[B:A]

Single-action submodule (SASM) signals.

Can also be used as general purpose I/O pins

Crystal Oscillator EXTAL, XTAL Connections for clock synthesizer circuit reference; a crystal or an

external oscillator can be used

Data Bus DATA[15:0] 16-bit data bus

Table 5 MCU Signal Characteristics (Continued)

Signal Name MCU Module Signal Type Active State

MC68CK338 MOTOROLA

MC68CK338TS/D 11

Data Strobe DS Indicates that an external device should place valid data on the data bus

during a read cycle and that valid data has been placed on the bus by

the CPU during a write cycle

Data and Size

Acknowledge DSACK[1:0] Acknowledges to the SIML that data has been received for a write cycle,

or that data is valid on the data bus for a read cycle

Development Serial

In, Out, Clock DSI, DSO,

DSCLK Serial I/O and clock for background debugging mode

Function Codes FC[2:0] Identify processor state and current address space

Freeze FREEZE Indicates that the CPU has entered background mode

Halt HALT Suspend external bus activity

Instruction Pipeline IFETCH, IPIPE Indicate instruction pipeline activity

Interrupt Request

Level IRQ[7:1] Request interrupt service from the CPU

Master In Slave Out MISO Serial input to QSPI in master mode;

serial output from QSPI in slave mode

Clock Mode Select MODCLK Selects system clock source

Master Out Slave In MOSI Serial output from QSPI in master mode;

serial input to QSPI in slave mode

Port C PC[6:0] SIML digital output signals

Peripheral Chip

Select PCS[3:0] QSPI peripheral chip selects

Port E PE[7:0] SIML digital input or output port signals

Port F PF[7:0] SIML digital input or output port signals

Port QS PQS[7:0] QSM digital I/O port signals

Quotient Out QUOT Provides the quotient bit of the polynomial divider

Reset RESET System reset

Read-Modify-Write

Cycle RMC Indicates an indivisible read-modify-write instruction

Read/Write R/W Indicates the direction of data transfer on the bus

SCI Receive Data RXD Serial input to the SCI

QSPI Serial Clock SCK Clock output from QSPI in master mode;

clock input to QSPI in slave mode

Size SIZ[1:0] Indicates the number of bytes to be transferred during a bus cycle

Slave Select SS Causes serial transmission when QSPI is in slave mode.

Causes mode fault in master mode

Three-State Control TSC Places all output drivers in a high-impedance state

SCI Transmit Data TXD Serial output from the SCI

External Filter

Capacitor XFC Connection for external phase-locked loop filter capacitor

Table 6 MCU Signal Function (Continued)

Signal Name Mnemonic Function

MOTOROLA MC68CK338

12 MC68CK338TS/D

3 Low-Power System Integration Module

The low-power system integration module (SIML) consists of five functional blocks that control system

startup, initialization, configuration, and the external bus.

Figure 4

shows the SIML block diagram.

Figure 4 SIML Block Diagram

3.1 Overview

The system configuration block controls MCU configuration and operating mode.

The clock synthesizer generates clock signals used by the SIML, other IMB modules, and external de-

vices. In addition, a periodic interrupt generator supports execution of time-critical control routines.

The system protection block provides bus and software watchdog monitors.

The chip-select block provides eleven general-purpose chip-select signals and a boot ROM chip-select

signal. Both general-purpose and boot ROM chip-select signals have associated base address regis-

ters and option registers.

The external bus interface handles the transfer of information between IMB modules and external ad-

dress space.

The system test block incorporates hardware necessary for testing the MCU. It is used to perform fac-

tory tests, and its use in normal applications is not supported.

Table 7

shows the SIML address map, which occupies 128 bytes. Unused registers within the 128-byte

address space return zeros when read. The “Access” column indicates which registers are accessible

only at the supervisor privilege level and which can be assigned to either the supervisor or user privilege

level, according to the value of the SUPV bit in the SIMLCR.

338 S(C)IM BLOCK

SYSTEM CONFIGURATION

CLOCK SYNTHESIZER

CHIP-SELECTS

EXTERNAL BUS INTERFACE

FACTORY TEST

CLKOUT

EXTAL

MODCLK

CHIP-SELECTS

EXTERNAL BUS

RESET

TSC

FREEZE/QUOT

XTAL

SYSTEM PROTECTION