ADS-937
3
® ®
+25°C 0 to +70°C –55 to +125°C
ANALOG OUTPUT MIN. TYP. MAX. MIN. TYP. MAX. MIN. TYP. MAX. UNITS
Internal Reference
Voltage +4.95 +5.0 +5.05 +4.95 +5.0 +5.05 +4.95 +5.0 +5.05 Volts
Drift —±30 — — ±30 — — ±30 —ppm/°C
External Current —1— — 1— — 1—mA
DIGITAL OUTPUTS
Logic Levels
Logic "1" +2.4 — — +2.4 ——+2.4 — — Volts
Logic "0" — — +0.4 — — +0.4 — — +0.4 Volts
Logic Loading "1" — — –4— — –4— — –4mA
Logic Loading "0" — — +4 — — +4 — — +4 mA
Output Coding Complementary Binary / Complementary Offset Binary
POWER REQUIREMENTS
Power Supply Ranges
+15V Supply +14.5 +15.0 +15.5 +14.5 +15.0 +15.5 +14.5 +15.0 +15.5 Volts
–15V Supply –14.5 –15.0 –15.5 –14.5 –15.0 –15.5 –14.5 –15.0 –15.5 Volts
+5V Supply +4.75 +5.0 +5.25 +4.75 +5.0 +5.25 +4.75 +5.0 +5.25 Volts
–5V Supply –4.75 –5.0 –5.25 –4.75 –5.0 –5.25 –4.75 –5.0 –5.25 Volts
Power Supply Currents
+15V Supply —+7 +9 —+7 +9 —+7 +9 mA
–15V Supply —–8 –10 —–8 –10 —–8 –10 mA
+5V Supply —+133 +145 —+133 +145 —+133 +145 mA
–5V Supply —–72 –80 —–72 –80 —–72 –80 mA
Power Dissipation —1.25 1.35 —1.25 1.35 —1.25 1.35 Watts
Power Supply Rejection — — ±0.01 — — ±0.01 — — ±0.01 %FSR/%V
THERMAL REQUIREMENTS
All DATEL sampling A/D converters are fully characterized and
specified over operating temperature (case) ranges of 0 to
+70°C and –55 to +125°C. All room-temperature (TA = +25°C)
production testing is performed without the use of heat sinks or
forced-air cooling. Thermal impedance figures for each device
are listed in their respective specification tables.
These devices do not normally require heat sinks, however,
standard precautionary design and layout procedures should be
used to ensure devices do not overheat. The ground and power
planes beneath the package, as well as all pcb signal runs to
and from the device, should be as heavy as possible to help
conduct heat away from the package. Electrically-insulating,
thermally-conductive "pads" may be installed underneath the
package. Devices should be soldered to boards rather than
"socketed", and of course, minimal air flow over the surface can
greatly help reduce the package temperature.
TECHNICAL NOTES
1. Obtaining fully specified performance from the ADS-937
requires careful attention to pc-card layout and power
supply decoupling. The device's analog and digital ground
systems are not connected to each other internally. For
optimal performance, tie all ground pins (2, 12 and 13)
directly to a large analog ground plane beneath the
package.
Bypass all power supplies and the +5V REFERENCE
OUTPUT (pin 5) to ground with 4.7µF tantalum capacitors in
parallel with 0.1µF ceramic capacitors. Locate the bypass
capacitors as close to the unit as possible. Tie a 47µF
capacitor between COMPENSATION (pin 7) and ground
(See figure 2.).
2. The ADS-937 achieves its specified accuracies without the
need for external calibration. If required, the device's small
initial offset and gain errors can be reduced to zero using
the adjustment circuitry shown in Figure 2. When using this
circuitry, or any similar offset and gain calibration hardware,
make adjustments following warm-up. To avoid interaction,
always adjust offset before gain. Float pins 4 and 6 if not
using offset and gain adjust circuits.
Footnotes:
➄This is the time required before the A/D output data is valid once the analog input
is back within the specified range.
6.02
(SNR + Distortion) – 1.76 + 20 log Full Scale Amplitude
Actual Input Amplitude
➀All power supplies must be on before applying a start convert pulse. All
supplies and the clock (START CONVERT) must be present during warm-up
periods. The device must be continuously converting during this time.
➁Contact DATEL for other input voltage ranges.
➂A 1MHz clock with a 500nsec positive pulse width (50% duty cycle) is used for
all production testing. Any duty cycle may be used as long as a minimum
positive pulse width of 20nsec is maintained. For applications requiring lower
sampling rates, clock frequencies less than 1MHz may be used.
➃Effective bits is equal to:
3. Applying a start convert pulse while a conversion is in
progress (EOC = logic "1") will initiate a new and inaccurate
conversion cycle. Data for the interrupted and subsequent
conversions will be invalid.