PCF85103C-2T/00,118\"\" - NXP SEMICONDUCTORS

PCF85103C-2

256 × 8-bit CMOS EEPROM with I2C-bus interface

Rev. 04 — 22 October 2004 Product data

1. Description

The PCF85103C-2 is a ﬂoating gate Electrically Erasable Programmable Read Only

Memory (EEPROM) with 2 kbits (256 ×8-bit) non-volatile storage. By using an

internal redundant storage code, it is fault tolerant to single bit errors. This feature

dramatically increases the reliability compared to conventional EEPROMs. Power

consumption is low due to the full CMOS technology used. The programming voltage

is generated on-chip, using a voltage multiplier.

Data bytes are received and transmitted via the serial I2C-bus. Up to eight

PCF85103C-2 devices may be connected to the I2C-bus. Chip select is accomplished

by three address inputs (A0, A1 and A2).

The PCF85103C-2 is identical to PCF85102C-2 except for the ﬁxed I2C address,

allowing up to eight PCF85102C-2 and eight PCF85103C-2 on the same I2C-bus.

2. Features

■Low power CMOS:

◆2.0 mA maximum operating current

◆maximum standby current 10 µA (at 6.0 V), typical 4 µA

■Non-volatile storage of 2 kbits organized as 256 ×8-bit

■Single supply with full operation down to 2.5 V

■On-chip voltage multiplier

■Serial input/output I2C-bus

■Write operations:

◆byte write mode

◆8-byte page write mode (minimizes total write time per byte)

■Read operations:

◆sequential read

◆random read

■Internal timer for writing (no external components)

■Internal power-on reset

■0 kHz to 100 kHz clock frequency

■High reliability by using a redundant storage code

■Endurance: 1,000,000 Erase/Write (E/W) cycles at Tamb =22°C

■10 years non-volatile data retention time

■Pin compatible to: PCF8570, PCF8571, PCF8572, PCA8581, PCF8582, and

PCF85102

Philips Semiconductors PCF85103C-2

256 × 8-bit CMOS EEPROM with I2C-bus interface

Product data Rev. 04 — 22 October 2004 2 of 20

■ESD protection exceeds 2000 V HBM per JESD22-A114, 150 V MM per

JESD22-A115, and 1000 V CDM per JESD22-C101

■Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA

■Offered in DIP8 and SO8 packages.

3. Quick reference data

4. Ordering information

4.1 Ordering options

Table 1: Quick reference data

Symbol Parameter Conditions Min Typ Max Unit

VDD supply voltage 2.5 - 6.0 V

IDDR supply current read fSCL = 100 kHz

VDD = 2.5 V - - 60 µA

VDD =6V - - 200 µA

IDDW supply current E/W fSCL = 100 kHz

VDD = 2.5 V - - 0.6 mA

VDD = 6 V - - 2.0 mA

IDD(stb) standby supply current VDD = 2.5 V - - 3.5 µA

VDD =6V - - 10 µA

Table 2: Ordering information

Type number Package

Name Description Version

PCF85103C-2P/00 DIP8 plastic dual in-line package; 8 leads (300 mil) SOT97-1

PCF85103C-2T/00 SO8 plastic small outline package 8 leads (straight);

body width 3.9 mm SOT96-1

Table 3: Ordering options

Type number Topside mark

PCF85103C-2P/00 PCF85103C2

PCF85103C-2T/00 85103C2

xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx

xxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx

xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx

xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x

Philips Semiconductors PCF85103C-2

256 × 8-bit CMOS EEPROM with I2C-bus interface

Product data Rev. 04 — 22 October 2004 3 of 20

5. Block diagram

Fig 1. Block diagram.

002aaa250

TEST MODE DECODER

POWER-ON-RESET

I2C-BUS CONTROL LOGIC

SEQUENCER

ADDRESS

HIGH

BYTE

COUNTER DIVIDER

( 128)

CONTROL

TIMER

( 16)

EEPROM

ADDRESS

POINTER

BYTE

LATCH

(8 bytes)

SHIFT

ADDRESS

SWITCH

INPUT

FILTER

OSCILLATOR

PCF85103C-2

VSS

VDD

SCL

SDA

Philips Semiconductors PCF85103C-2

256 × 8-bit CMOS EEPROM with I2C-bus interface

Product data Rev. 04 — 22 October 2004 4 of 20

6. Pinning information

6.1 Pinning

6.2 Pin description

7. Device addressing

[1] The Most Signiﬁcant Bit (MSB) ‘b7’ is sent ﬁrst.

A2, A1, A0 are hardware selectable pins.

A system could have up to eight PCF85103C-2 devices on the same I2C-bus,

equivalent to a 16 kbit EEPROM or 8 pages of 256 bytes of memory.

The eight addresses are deﬁned by the state of the A0, A1, A2 inputs (logic level ‘1’

when connected to VDD, logic level ‘0’ when connected to GND). Figure 3 shows the

various address combinations.

Fig 2. Pin conﬁguration.

VSS SDA

SCL

N.C.

VDD

PCF85103C-2

002aaa251

Table 4: Pin description

Symbol Pin Description

A0 1 address input 0

A1 2 address input 1

A2 3 address input 2

VSS 4 negative supply voltage

SDA 5 serial data input/output (I2C-bus)

SCL 6 serial clock input (I2C-bus)

N.C. 7 no connect

VDD 8 positive supply voltage

Table 5: Device address code

Selection Device code Chip Enable R/W

Bit b7[1] b6 b5 b4 b3 b2 b1 b0

Device 0 0 1 0 A2 A1 A0 R/W

Philips Semiconductors PCF85103C-2

256 × 8-bit CMOS EEPROM with I2C-bus interface

Product data Rev. 04 — 22 October 2004 5 of 20

Fig 3. Device addressing.

002aaa252

256-BYTE PAGE

PCF85103C-2

DEVICE 1

256-BYTE PAGE

PCF85103C-2

DEVICE 2

256-BYTE PAGE

PCF85103C-2

DEVICE 3

256-BYTE PAGE

PCF85103C-2

DEVICE 4

256-BYTE PAGE

PCF85103C-2

DEVICE 5

256-BYTE PAGE

PCF85103C-2

DEVICE 6

256-BYTE PAGE

PCF85103C-2

DEVICE 7

256-BYTE PAGE

PCF85103C-2

DEVICE 8

I2C-BUS A2

Philips Semiconductors PCF85103C-2

256 × 8-bit CMOS EEPROM with I2C-bus interface

Product data Rev. 04 — 22 October 2004 6 of 20

8. Functional description

8.1 I2C-bus protocol

The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The

serial bus consists of two bidirectional lines; one for data signals (SDA), and one for

clock signals (SCL).

Both the SDA and SCL lines must be connected to a positive supply voltage via a

pull-up resistor.

The following protocol has been deﬁned:

•Data transfer may be initiated only when the bus is not busy.

•During data transfer, the data line must remain stable whenever the clock line is

HIGH. Changes in the data line while the clock line is HIGH will be interpreted as

control signals.

8.1.1 Bus conditions

The following bus conditions have been deﬁned:

Bus not busy — Both data and clock lines remain HIGH.

Start data transfer — A change in the state of the data line, from HIGH-to-LOW,

while the clock is HIGH, deﬁnes the START condition.

Stop data transfer — A change in the state of the data line, from LOW-to-HIGH,

while the clock is HIGH, deﬁnes the STOP condition.

Data valid — The state of the data line represents valid data when, after a START

condition, the data line is stable for the duration of the HIGH period of the clock

signal. There is one clock pulse per bit of data.

8.1.2 Data transfer

Each data transfer is initiated with a START condition and terminated with a STOP

condition. The number of the data bytes, transferred between the START and STOP

conditions is limited to 7 bytes in the E/W mode and 8 bytes in the Page E/W mode.

Data transfer is unlimited in the read mode. The information is transmitted in bytes

and each receiver acknowledges with a ninth bit.

Within the I2C-bus speciﬁcations, a standard-speed mode (100 kHz clock rate) and a

fast speed mode (400 kHz clock rate) are deﬁned. The PCF85103C-2 operates in

only the standard-speed mode.

By deﬁnition, a device that sends a signal is called a ‘transmitter’, and the device

which receives the signal is called a ‘receiver’. The device which controls the signal is

called the ‘master’. The devices that are controlled by the master are called ‘slaves’.

Each byte is followed by one acknowledge bit. This acknowledge bit is a HIGH level,

put on the bus by the transmitter. The master generates an extra acknowledge related

clock pulse. The slave receiver which is addressed is obliged to generate an

acknowledge after the reception of each byte.

Philips Semiconductors PCF85103C-2

256 × 8-bit CMOS EEPROM with I2C-bus interface

Product data Rev. 04 — 22 October 2004 7 of 20

The master receiver must generate an acknowledge after the reception of each byte

that has been clocked out of the slave transmitter.

The device that acknowledges has to pull down the SDA line during the acknowledge

clock pulse in such a way that the SDA line is stable LOW during the HIGH period of

the acknowledge related clock pulse.

Set-up and hold times must be taken into account. A master receiver must signal an

end of data to the slave transmitter by not generating an acknowledge on the last byte

that has been clocked out of the slave. In this event, the transmitter must leave the

data line HIGH to enable the master generation of the STOP condition.

8.1.3 Device addressing

Following a START condition, the bus master must output the address of the slave it

is accessing. The address of the PCF85103C-2 is shown in Figure 4. To conserve

power, no internal pull-up resistors are incorporated on the hardware selectable pins

and they must be connected to either VDD or VSS.

The last bit of the slave address deﬁnes the operation to be performed. When set to

logic 1, a read operation is selected, while a logic 0 selects a write operation.

8.1.4 Write operations

Byte/word write: For a write operation, the PCF85103C-2 requires a second

address ﬁeld. This address ﬁeld is a word address providing access to the 256 words

of memory. Upon receipt of the word address, the PCF85103C-2 responds with an

acknowledge and awaits the next eight bits of data, again responding with an

acknowledge. Word address is automatically incremented. The master can now

terminate the transfer by generating a STOP condition or transmit up to six more

bytes of data and then terminate by generating a STOP condition.

After this STOP condition, the E/W cycle starts and the bus is free for another

transmission. Its duration is 10 ms per byte.

During the E/W cycle the slave receiver does not send an acknowledge bit if

addressed via the I2C-bus.

Fig 4. Slave address.

002aaa253

0010A2A1A0R/W

FIXED HARDWARE

SELECTABLE

Philips Semiconductors PCF85103C-2

256 × 8-bit CMOS EEPROM with I2C-bus interface

Product data Rev. 04 — 22 October 2004 8 of 20

Page write: The PCF85103C-2 is capable of an eight-byte page write operation. It is

initiated in the same manner as the byte write operation. The master can transit eight

data bytes within one transmission. After receipt of each byte, the PCF85103C-2 will

respond with an acknowledge. The typical E/W time in this mode is

9×3.5 ms = 31.5 ms. Erasing a block of 8 bytes in page mode takes typical 3.5 ms

and sequential writing of these 8 bytes another typical 28 ms.

After the receipt of each data byte, the three low-order bits of the word address are

internally incremented. The high-order ﬁve bits of the address remain unchanged.

The slave acknowledges the reception of each data byte with an ACK. The I2C-bus

data transfer is terminated by the master after the 8th byte with a STOP condition. If

the master transmits more than eight bytes prior to generating the STOP condition,

no acknowledge will be given on the ninth (and following) data bytes and the whole

transmission will be ignored and no programming will be done. As in the byte write

operation, all inputs are disabled until completion of the internal write cycles.

Fig 5. Auto-increment memory word address; two byte write.

S0A

SLAVE ADDRESS WORD ADDRESS AADATA P

acknowledge

from slave acknowledge

from slave

ADATA

R/W auto increment

word address auto increment

word address

MBA701

Fig 6. Page write operation; eight bytes.

S0ASLAVE ADDRESS WORD ADDRESS A A

DATA N

acknowledge

from slave acknowledge

from slave

R/W auto increment

word address

acknowledge

from slave

DATA N + 1

auto increment

word address

002aaa245

acknowledge

from slave

ADATA N + 7

auto increment

word address

last byte

Philips Semiconductors PCF85103C-2

256 × 8-bit CMOS EEPROM with I2C-bus interface

Product data Rev. 04 — 22 October 2004 9 of 20

8.1.5 Read operations

Read operations are initiated in the same manner as write operations with the

exception that the LSB of the slave address is set to logic 1.

There are three basic read operations: current address read, random read, and

sequential read.

Remark: The lower 8 bits of the word address are incremented after each

transmission of a data byte (read or write). The MSB of the word address, which is

deﬁned in the slave address, is not changed when the word address count overﬂows.

Thus, the word address overﬂows from 255 to 0, and from 511 to 256.

Fig 7. Master reads PCF85103C-2 slave after setting word address (write word address; read data);

sequential read.

S0ASLAVE ADDRESS WORD ADDRESS A A

SLAVE ADDRESS

acknowledge

from slave acknowledge

from slave

R/W

acknowledge

from master

DATA

auto increment

word address

MBA703

no acknowledge

from master

1DATA

auto increment

word address

last byte

R/W

n bytes

at this moment master

transmitter becomes

master receiver and

EEPROM slave receiver

becomes slave transmitter

Fig 8. Master reads PCF85103C-2 immediately after ﬁrst byte (read mode); current address read.

S1A

SLAVE ADDRESS DATA A1DATA

acknowledge

from slave acknowledge

from master no acknowledge

from master

R/W auto increment

word address

MBA704 - 1

auto increment

word address

n bytes last bytes

Philips Semiconductors PCF85103C-2

256 × 8-bit CMOS EEPROM with I2C-bus interface

Product data Rev. 04 — 22 October 2004 10 of 20

9. Limiting values

10. Characteristics

Table 6: Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

VDD supply voltage −0.3 +6.5 V

Viinput voltage on any input pin |Zi|> 500 ΩVSS −0.8 +6.5 V

Iiinput current on any input pin - 1 mA

Iooutput current - 10 mA

Tstg storage temperature −65 +150 °C

Tamb operating ambient temperature −40 +85 °C

Table 7: Characteristics

= 2.5 to 6.0 V; V

=0V; T

amb

−

40 to +85

C; unless otherwise speciﬁed.

Symbol Parameter Conditions Min Typ Max Unit

Supplies

VDD supply voltage 2.5 - 6.0 V

IDDR supply current read fSCL = 100 kHz

VDD = 2.5 V - - 60 µA

VDD = 6.0 V - - 200 µA

IDDW supply current E/W fSCL = 100 kHz

VDD = 2.5 V - - 0.6 mA

VDD = 6.0 V - - 2.0 mA

IDD(stb) standby supply current VDD = 2.5 V - - 3.5 µA

VDD = 6.0 V - - 10 µA

SCL input (pin 6)

VIL LOW level input voltage −0.8 - 0.3VDD V

VIH HIGH level input voltage 0.7VDD - +6.5 V

ILI input leakage current VI=V

DD or VSS --±1µA

fSCL clock input frequency 0 - 100 kHz

Ciinput capacitance VI=V

SS --7 pF

SDA input/output (pin 5)

VIL LOW level input voltage −0.8 - 0.3VDD V

VIH HIGH level input voltage 0.7VDD - +6.5 V

VOL LOW level output voltage IOL = 3 mA; VDD(min) - - 0.4 V

ILO output leakage current VOH =V

DD --1 µA

Ciinput capacitance VI=V

SS --7 pF

Data retention time

tSdata retention time Tamb =55°C10−− years

Philips Semiconductors PCF85103C-2

256 × 8-bit CMOS EEPROM with I2C-bus interface

Product data Rev. 04 — 22 October 2004 11 of 20

11. I2C-bus characteristics

[1] The hold time required (not greater than 300 ns) to bridge the undeﬁned region of the falling edge of SCL must be internally provided by

a transmitter.

Table 8: I2C-bus characteristics

All of the timing values are valid within the operating supply voltage and ambient temperature range and refer to V

and V

with an input voltage swing from V

to V

; see Figure 9.

Symbol Parameter Conditions Min Max Unit

fSCL clock frequency 0 100 kHz

tBUF bus free time between a STOP and

START condition 4.7 −µs

tHD;STA START condition hold time after

which ﬁrst clock pulse is generated 4.0 −µs

tLOW LOW level clock period 4.7 −µs

tHIGH HIGH level clock period 4.0 −µs

tSU;STA set-up time for START condition repeated start 4.7 −µs

tHD;DAT data hold time

for bus compatible masters 5 −µs

for bus devices [1] 0−ns

tSU;DAT data set-up time 250 −ns

trSDA and SCL rise time −1µs

tfSDA and SCL fall time −300 ns

tSU;STO set-up time for STOP condition 4.0 −µs

P = STOP condition; S = START condition.

Fig 9. Timing requirements for the I2C-bus.

MBA705

tBUF

HD;STA

SCL

SDA

P S

tLOW

trHD;DAT

tSU;DAT

tHIGH

HD;STA

SU;STA

tSU;STO

Philips Semiconductors PCF85103C-2

256 × 8-bit CMOS EEPROM with I2C-bus interface

Product data Rev. 04 — 22 October 2004 12 of 20

12. Write cycle limits

Table 9: Write cycle limits

Selection of the chip address is achieved by connecting the A0, A1 and A2 inputs to either V

or V

Symbol Parameter Conditions Min Typ Max Unit

E/W cycle timing

tE/W E/W cycle time internal oscillator −7−ms

external clock 4 −10 ms

Endurance

NE/W E/W cycle per byte Tamb =−40 to +85 °C 100000 −−cycles

Tamb =22°C 1000000 −cycles

Philips Semiconductors PCF85103C-2

256 × 8-bit CMOS EEPROM with I2C-bus interface

Product data Rev. 04 — 22 October 2004 13 of 20

13. Package outline

Fig 10. DIP8 package outline (SOT97-1).

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

SOT97-1 99-12-27

03-02-13

UNIT A

max. 12 b1(1) (1) (1)

b2cD E e M Z

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

min. A

max. bmax.

1.73

1.14 0.53

0.38 0.36

0.23 9.8

9.2 6.48

6.20 3.60

3.05 0.2542.54 7.62 8.25

7.80 10.0

8.3 1.154.2 0.51 3.2

inches 0.068

0.045 0.021

0.015 0.014

0.009

1.07

0.89

0.042

0.035 0.39

0.36 0.26

0.24 0.14

0.12 0.010.1 0.3 0.32

0.31 0.39

0.33 0.0450.17 0.02 0.13

050G01 MO-001 SC-504-8

(e )

seating plane

0 5 10 mm

scale

Note

1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

pin 1 index

DIP8: plastic dual in-line package; 8 leads (300 mil) SOT97-1

Philips Semiconductors PCF85103C-2

256 × 8-bit CMOS EEPROM with I2C-bus interface

Product data Rev. 04 — 22 October 2004 14 of 20

Fig 11. SO8 package outline (SOT96-1).

UNIT A

max. A1A2A3bpcD

(1) E(2) (1)

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

inches

1.75 0.25

0.10 1.45

1.25 0.25 0.49

0.36 0.25

0.19 5.0

4.8 4.0

3.8 1.27 6.2

5.8 1.05 0.7

0.6 0.7

0.3 8

0.25 0.10.25

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Notes

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

1.0

0.4

SOT96-1

detail X

vMA

(A )

pin 1 index

076E03 MS-012

0.069 0.010

0.004 0.057

0.049 0.01 0.019

0.014 0.0100

0.0075 0.20

0.19 0.16

0.15 0.05 0.244

0.228 0.028

0.024 0.028

0.012

0.010.010.041 0.004

0.039

0.016

0 2.5 5 mm

scale

SO8: plastic small outline package; 8 leads; body width 3.9 mm SOT96-1

99-12-27

03-02-18

Philips Semiconductors PCF85103C-2

256 × 8-bit CMOS EEPROM with I2C-bus interface

Product data Rev. 04 — 22 October 2004 15 of 20

14. Soldering

14.1 Introduction

This text gives a very brief insight to a complex technology. A more in-depth account

of soldering ICs can be found in our

Data Handbook IC26; Integrated Circuit

Packages

(document order number 9398 652 90011).

There is no soldering method that is ideal for all IC packages. Wave soldering is often

preferred when through-hole and surface mount components are mixed on one

printed-circuit board. Wave soldering can still be used for certain surface mount ICs,

but it is not suitable for ﬁne pitch SMDs. In these situations reﬂow soldering is

recommended. Driven by legislation and environmental forces the worldwide use of

lead-free solder pastes is increasing.

14.2 Through-hole mount packages

14.2.1 Soldering by dipping or by solder wave

Typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250 °C or

265 °C, depending on solder material applied, SnPb or Pb-free respectively.

The total contact time of successive solder waves must not exceed 5 seconds.

The device may be mounted up to the seating plane, but the temperature of the

plastic body must not exceed the speciﬁed maximum storage temperature (Tstg(max)).

If the printed-circuit board has been pre-heated, forced cooling may be necessary

immediately after soldering to keep the temperature within the permissible limit.

14.2.2 Manual soldering

Apply the soldering iron (24 V or less) to the lead(s) of the package, either below the

seating plane or not more than 2 mm above it. If the temperature of the soldering iron

bit is less than 300 °C it may remain in contact for up to 10 seconds. If the bit

temperature is between 300 and 400 °C, contact may be up to 5 seconds.

14.3 Surface mount packages

14.3.1 Reﬂow soldering

Reﬂow soldering requires solder paste (a suspension of ﬁne solder particles, ﬂux and

binding agent) to be applied to the printed-circuit board by screen printing, stencilling

or pressure-syringe dispensing before package placement.

Several methods exist for reﬂowing; for example, convection or convection/infrared

heating in a conveyor type oven. Throughput times (preheating, soldering and

cooling) vary between 100 and 200 seconds depending on heating method.

Typical reﬂow peak temperatures range from 215 to 270 °C depending on solder

paste material. The top-surface temperature of the packages should preferably be

kept:

•below 225 °C (SnPb process) or below 245 °C (Pb-free process)

–for all the BGA and SSOP-T packages

Philips Semiconductors PCF85103C-2

256 × 8-bit CMOS EEPROM with I2C-bus interface

Product data Rev. 04 — 22 October 2004 16 of 20

–for packages with a thickness ≥2.5 mm

–for packages with a thickness < 2.5 mm and a volume ≥350 mm3 so called

thick/large packages.

•below 240 °C (SnPb process) or below 260 °C (Pb-free process) for packages with

a thickness < 2.5 mm and a volume < 350 mm3 so called small/thin packages.

Moisture sensitivity precautions, as indicated on packing, must be respected at all

times.

14.3.2 Wave soldering

Conventional single wave soldering is not recommended for surface mount devices

(SMDs) or printed-circuit boards with a high component density, as solder bridging

and non-wetting can present major problems.

To overcome these problems the double-wave soldering method was speciﬁcally

developed.

If wave soldering is used the following conditions must be observed for optimal

results:

•Use a double-wave soldering method comprising a turbulent wave with high

upward pressure followed by a smooth laminar wave.

•For packages with leads on two sides and a pitch (e):

–larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be

parallel to the transport direction of the printed-circuit board;

–smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the

transport direction of the printed-circuit board.

The footprint must incorporate solder thieves at the downstream end.

•For packages with leads on four sides, the footprint must be placed at a 45° angle

to the transport direction of the printed-circuit board. The footprint must

incorporate solder thieves downstream and at the side corners.

During placement and before soldering, the package must be ﬁxed with a droplet of

adhesive. The adhesive can be applied by screen printing, pin transfer or syringe

dispensing. The package can be soldered after the adhesive is cured.

Typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250 °C or

265 °C, depending on solder material applied, SnPb or Pb-free respectively.

A mildly-activated ﬂux will eliminate the need for removal of corrosive residues in

most applications.

14.3.3 Manual soldering

Fix the component by ﬁrst soldering two diagonally-opposite end leads. Use a low

voltage (24 V or less) soldering iron applied to the ﬂat part of the lead. Contact time

must be limited to 10 seconds at up to 300 °C.

When using a dedicated tool, all other leads can be soldered in one operation within

2 to 5 seconds between 270 and 320 °C.

Philips Semiconductors PCF85103C-2

256 × 8-bit CMOS EEPROM with I2C-bus interface

Product data Rev. 04 — 22 October 2004 17 of 20

14.4 Package related soldering information

[1] For more detailed information on the BGA packages refer to the

(LF)BGA Application Note

(AN01026); order a copy from your Philips Semiconductors sales ofﬁce.

[2] All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the

maximum temperature (with respect to time) and body size of the package, there is a risk that internal

or external package cracks may occur due to vaporization of the moisture in them (the so called

popcorn effect). For details, refer to the Drypack information in the

Data Handbook IC26; Integrated

Circuit Packages; Section: Packing Methods

[3] For SDIP packages, the longitudinal axis must be parallel to the transport direction of the

printed-circuit board.

[4] Hot bar soldering or manual soldering is suitable for PMFP packages.

[5] These transparent plastic packages are extremely sensitive to reﬂow soldering conditions and must

on no account be processed through more than one soldering cycle or subjected to infrared reﬂow

soldering with peak temperature exceeding 217 °C±10 °C measured in the atmosphere of the reﬂow

oven. The package body peak temperature must be kept as low as possible.

[6] These packages are not suitable for wave soldering. On versions with the heatsink on the bottom

side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with

the heatsink on the top side, the solder might be deposited on the heatsink surface.

[7] If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave

direction. The package footprint must incorporate solder thieves downstream and at the side corners.

[8] Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it

is deﬁnitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

[9] Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than

0.65 mm; it is deﬁnitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

Table 10: Suitability of IC packages for wave, reﬂow and dipping soldering methods

Mounting Package[1] Soldering method

Wave Reﬂow[2] Dipping

Through-hole

mount DBS, DIP, HDIP, RDBS,

SDIP, SIL suitable[3] −suitable

Through-hole-

surface mount PMFP[4] not suitable not

suitable −

Surface mount BGA, LBGA, LFBGA,

SQFP, SSOP-T[5],

TFBGA, VFBGA

not suitable suitable −

DHVQFN, HBCC, HBGA,

HLQFP, HSQFP, HSOP,

HTQFP, HTSSOP,

HVQFN, HVSON, SMS

not suitable[6] suitable −

PLCC[7], SO, SOJ suitable suitable −

LQFP, QFP, TQFP not recommended[7][8] suitable −

SSOP, TSSOP, VSO,

VSSOP not recommended[9] suitable −

Philips Semiconductors PCF85103C-2

256 × 8-bit CMOS EEPROM with I2C-bus interface

Product data Rev. 04 — 22 October 2004 18 of 20

15. Revision history

Table 11: Revision history

Rev Date CPCN Description

04 20041022 - Product data (9397 750 14218).

Modiﬁcations:

•Section 8.1.2 “Data transfer” on page 6, third paragraph: changed ‘high-speed mode’ to

‘standard-speed mode’ (2 places).

03 20031008 - Product data (9397 750 12044). ECN 853-2342 30407 dated 02 October 2003.

02 20020509 - Product data (9397 750 09646); ECN 853-2342 28170 dated 2002 May 09; supersedes

data in data sheet

PCF85102C-2; PCF85103C-2

dated 2000 Feb 15 (9397 750 06682).

01 20000215 - Product data; initial version (as

PCF85102C-2; PCF85103C-2

, 9397 750 06682).

9397 750 14218

Philips Semiconductors PCF85103C-2

256 × 8-bit CMOS EEPROM with I2C-bus interface

Product data Rev. 04 — 22 October 2004 19 of 20

Contact information

For additional information, please visit http://www.semiconductors.philips.com.

For sales ofﬁce addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com.Fax: +31 40 27 24825

16. Data sheet status

[1] Please consult the most recently issued data sheet before initiating or completing a design.

[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at

URL http://www.semiconductors.philips.com.

[3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

17. Deﬁnitions

Short-form speciﬁcation — The data in a short-form speciﬁcation is

extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook.

Limiting values deﬁnition — Limiting values given are in accordance with

the Absolute Maximum Rating System (IEC 60134). Stress above one or

more of the limiting values may cause permanent damage to the device.

These are stress ratings only and operation of the device at these or at any

other conditions above those given in the Characteristics sections of the

speciﬁcation is not implied. Exposure to limiting values for extended periods

may affect device reliability.

Application information — Applications that are described herein for any

of these products are for illustrative purposes only. Philips Semiconductors

make no representation or warranty that such applications will be suitable for

the speciﬁed use without further testing or modiﬁcation.

18. Disclaimers

Life support — These products are not designed for use in life support

appliances, devices, or systems where malfunction of these products can

reasonably be expected to result in personal injury. Philips Semiconductors

customers using or selling these products for use in such applications do so

at their own risk and agree to fully indemnify Philips Semiconductors for any

damages resulting from such application.

Right to make changes — Philips Semiconductors reserves the right to

make changes in the products - including circuits, standard cells, and/or

software - described or contained herein in order to improve design and/or

performance. When the product is in full production (status ‘Production’),

relevant changes will be communicated via a Customer Product/Process

Change Notiﬁcation (CPCN). Philips Semiconductors assumes no

responsibility or liability for the use of any of these products, conveys no

licence or title under any patent, copyright, or mask work right to these

products, and makes no representations or warranties that these products are

free from patent, copyright, or mask work right infringement, unless otherwise

speciﬁed.

19. Licenses

Level Data sheet status[1] Product status[2][3] Deﬁnition

I Objective data Development This data sheet contains data from the objective speciﬁcation for product development. Philips

Semiconductors reserves the right to change the speciﬁcation in any manner without notice.

II Preliminary data Qualiﬁcation This data sheet contains datafrom the preliminary speciﬁcation.Supplementary datawill be published

at a later date. Philips Semiconductors reserves the right to change the speciﬁcation without notice, in

order to improve the design and supply the best possible product.

III Product data Production This data sheet contains data from the product speciﬁcation. Philips Semiconductors reserves the

right to make changes at any time in order to improve the design, manufacturing and supply. Relevant

changes will be communicated via a Customer Product/Process Change Notiﬁcation (CPCN).

Purchase of Philips I2C components

Purchase of Philips I2C components conveys a license

under the Philips’ I2C patent to use the components in the

I2C system provided the system conforms to the I2C

speciﬁcation deﬁned by Philips. This speciﬁcation can be

ordered using the code 9398 393 40011.

© Koninklijke Philips Electronics N.V. 2004.
Printed in the U.S.A.
All rights are reserved. Reproduction in whole or in part is prohibited without the prior
written consent of the copyright owner.
The information presented in this document does not form part of any quotation or
contract, is believed to be accurate and reliable and may be changed without notice. No
liability will be accepted by the publisher for any consequence of its use. Publication
thereof does not convey nor imply any license under patent- or other industrial or
intellectual property rights.
Date of release: 22 October 2004 Document order number: 9397 750 14218
Contents
Philips Semiconductors PCF85103C-2
× 8-bit CMOS EEPROM with I2C-bus interface
Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . .  1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  1
Quick reference data . . . . . . . . . . . . . . . . . . . . .  2
Ordering information. . . . . . . . . . . . . . . . . . . . .  2
1 Ordering options. . . . . . . . . . . . . . . . . . . . . . . .  2
Block diagram  . . . . . . . . . . . . . . . . . . . . . . . . . .  3
Pinning information. . . . . . . . . . . . . . . . . . . . . .  4
1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  4
2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . .  4
Device addressing. . . . . . . . . . . . . . . . . . . . . . .  4
Functional description  . . . . . . . . . . . . . . . . . . .  6
1 I2C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . .  6
1.1 Bus conditions  . . . . . . . . . . . . . . . . . . . . . . . . .  6
1.2 Data transfer. . . . . . . . . . . . . . . . . . . . . . . . . . .  6
1.3 Device addressing  . . . . . . . . . . . . . . . . . . . . . .  7
1.4 Write operations . . . . . . . . . . . . . . . . . . . . . . . .  7
1.5 Read operations . . . . . . . . . . . . . . . . . . . . . . . .  9
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . .  10
Characteristics. . . . . . . . . . . . . . . . . . . . . . . . .  10
I2C-bus characteristics . . . . . . . . . . . . . . . . . .  11
Write cycle limits . . . . . . . . . . . . . . . . . . . . . . .  12
Package outline . . . . . . . . . . . . . . . . . . . . . . . .  13
Soldering  . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  15
1 Introduction  . . . . . . . . . . . . . . . . . . . . . . . . . .  15
2 Through-hole mount packages. . . . . . . . . . . .  15
2.1 Soldering by dipping or by solder wave . . . . .  15
2.2 Manual soldering  . . . . . . . . . . . . . . . . . . . . . .  15
3 Surface mount packages . . . . . . . . . . . . . . . .  15
3.1 Reﬂow soldering. . . . . . . . . . . . . . . . . . . . . . .  15
3.2 Wave soldering. . . . . . . . . . . . . . . . . . . . . . . .  16
3.3 Manual soldering  . . . . . . . . . . . . . . . . . . . . . .  16
4 Package related soldering information . . . . . .  17
Revision history. . . . . . . . . . . . . . . . . . . . . . . .  18
Data sheet status. . . . . . . . . . . . . . . . . . . . . . .  19
Deﬁnitions  . . . . . . . . . . . . . . . . . . . . . . . . . . . .  19
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . .  19
Licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  19