ADC10662,ADC10664
ADC10662/ADC10664 10-Bit 360 ns A/D Converter with Input Multiplexer and
Sample/Hold
Literature Number: SNAS076D
ADC10662/ADC10664
10-Bit 360 ns A/D Converter with Input Multiplexer and
Sample/Hold
General Description
NOTE: The ADC10661 and ADC10662 are obsolete. They
are described here for reference only.
Using an innovative, patented multistep* conversion tech-
nique, these 10-bit CMOS analog-to-digital converters offer
sub-microsecond conversion times yet dissipating a maxi-
mum of only 235 mW. These converters perform 10-bit con-
versions in two lower-resolution “flashes”, yielding a fast A/D
without the cost, power consumption, and other problems
associated with true flash approaches. In addition to stan-
dard static performance specifications (Linearity, Full-Scale
Error, etc.), dynamic performance (THD, S/N) is guaranteed.
The analog input voltage ADC is sampled and held by an
internal sampling circuit. Input signals at frequencies from
DC to over 250 kHz can therefore be digitized accurately
without the need for an external sample-and-hold circuit.
Connecting an external resistor between the “speed-up” pin
and ground reduces the typical conversion time to as little as
360 ns for a small linearity sacrifice.
For ease of interface to microprocessors, the ADC10662 and
ADC10664 have been designed to appear as a memory
location or I/O port without the need for external interface
logic.
Features
nBuilt-in sample-and-hold
nSingle +5V supply
nNo external clock required
nSpeed Adjust pin for faster conversions
Key Specifications
nConversion Time 360 ns (typical)
nMax. Sampling Rate: 1.5 MHz (min)
nLow Power Consumption 235 mW (max)
nTotal harmonic distortion (50 kHz): −60 dB (max)
nNo Missing Codes Over Temperature
Applications
nDigital signal processor front ends
nInstrumentation
nDisk drives
nMobile telecommunications
Simplified Block Diagram
01119209
*ADC10664 Only
*U.S. Patent Number 4918449
TRI-STATE®is a registered trademark of National Semiconductor Corporation.
April 2006
ADC10662/ADC10664 10-Bit 360 ns A/D Converter with Input Multiplexer and Sample/Hold
© 2006 National Semiconductor Corporation DS011192 www.national.com
Ordering Information
ADC10662
Industrial
(−40˚C ≤T
A
≤+85˚C) Channels Package
ADC10662CIWM * 2 M24B Small Outline
ADC10662CIWMX * 2 M24B Small Outline Tape & Reel
ADC10664CIWM 4 M28B Small Outline
ADC10664CIWMX 4 M28B Small Outline Tape & Reel
* The ADC10662 is obsolete; shown for reference only.
Connection Diagrams
01119210
Top View
01119211
Top View
NOTE: The ADC10662 is obsolete; shown for reference only.
ADC10662/ADC10664
www.national.com 2
Pin Descriptions
Pin Function Description
DV
CC
,AV
CC
Digital and analog positive supply voltage inputs. Connect both to the same voltage source, but
bypass separately with a 0.1 µF ceramic capacitor in parallel with a 10 µF tantalum capacitor to
ground at each pin.
INT Active low interrupt output. INT goes low at the end of each conversion, and returns high
following the rising edge of RD .
S/H Sample/Hold control input. When this pin is forced low (and CS is low), the analog input signal to
be sampled and initiates a new conversion.
RD Active low Read control input. When this RD and CS are low, any data present in the output
registers will be placed on the data bus.
CS Active low Chip Select control input. When low, this pin enables the RD and S/H pins.
S0, S1 These pins select the analog input that will be connected to the A/D during the conversion. The
input is selected based on the state of S0 and S1 when S/H makes its High-to-Low transition
(See the Timing Diagrams). The ADC10664 includes both S0 and S1. The ADC10662 includes
just S0.
V
REF−
,V
REF+
Reference voltage inputs. They may be placed at any voltage between GND and V
CC
, but V
REF+
must be greater than V
REF−
. An input voltage equal to V
REF−
produces an output code of 0, and
an input voltage equal to (V
REF+
− 1 LSB) produces an output code of 1023.
V
IN0
,V
IN1
,
V
IN2
,V
IN3
Analog input pins. The ADC10662 has two inputs (V
IN0
and V
IN1
) and the ADC10664 has four
inputs (V
IN0
,V
IN1
,V
IN2
and V
IN3
). The impedance of the source should be less than 500Ωfor
best accuracy and conversion speed. For accurate conversions, no input pin (even one that is
not selected) should be driven more than 50 mV above V
CC
or 50 mV below ground.
GND, AGND,
DGND
Power supply ground pins. The ADC10662 and ADC10664 have separate analog and digital
ground pins (AGND and DGND) for separate bypassing of the analog and digital supplies. The
ground pins should be connected to a stable, noise-free system ground. Both pins should be
returned to the same potential.
DB0–DB9 TRI-STATE output pins.
SPEEDADJ By connecting a resistor between this pin and ground, the conversion time can be reduced. The
specifications listed in the table of Electrical Characteristics apply for a speed adjust resistor
(R
SA
) equal to 14.0 kΩ(Mode 1) or 8.26 kΩ(Mode 2). See the Typical Performance Curves and
the table of Electrical Characteristics.
ADC10662/ADC10664
www.national.com3
Absolute Maximum Ratings
(Notes 1, 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
+
=AV
CC
=DV
CC
) −0.3V to +6V
Voltage at Any Input or Output −0.3V to V
+
+ 0.3V
Input Current at Any Pin (Note 3) 5 mA
Package Input Current (Note 3) 20 mA
Power Dissipation (Note 4) 875 mW
ESD Susceptibility (Note 5) 2000V
Soldering Information (Note 6)
N Package (10 Sec) 260˚C
SO Package:
Vapor Phase (60 Sec) 215˚C
Infrared (15 Sec) 220˚C
Storage Temperature Range −65˚C to +150˚C
Junction Temperature 150˚C
Operating Ratings (Notes 1, 2)
Temperature Range T
MIN
≤T
A
≤T
MAX
=
−40˚C ≤T
A
≤+85˚C
Supply Voltage Range +4.5V to +5.5V
Package Thermal Resistance
Device θ
JA
(˚C/W)
ADC10662CIWM 82
ADC10664CIWM 78
Converter Characteristics
The following specifications apply for V
+
= +5V, V
REF(+)
= +5V, V
REF(−)
= GND, and Speed Adjust pin connected to ground
through a 14.0 kΩresistor (Mode 1) or an 8.26 kΩresistor (Mode 2) unless otherwise specified. Boldface limits apply for T
A
=T
J
=T
Min
to T
Max
;all other limits T
A
=T
J
= +25˚C.
Symbol Parameter Conditions Typical
(Note 7)
Limit
(Note 8)
Units
(Limit)
Resolution 10 Bits
Integral Linearity Error ±0.5 ±1.0/±1.5 LSB (max)
Offset Error ±1.5 LSB (max)
Full-Scale Error ±1LSB (max)
Total Unadjusted Error ±0.5 ±1.5/±2.2 LSB
Missing Codes 0(max)
Power Supply Sensitivity V
+
=5V±5%, V
REF
= 4.5V ±1/16 LSB
V
+
=5V±10%, V
REF
= 4.5V ±
1
⁄
8
LSB
THD Total Harmonic Distortion (Note 10)
f
IN
= 1 kHz, 4.85 V
P-P
f
IN
= 50 kHz, 4.85 V
P-P
f
IN
= 100 kHz, 4.85 V
P-P
f
IN
= 240 kHz, 4.85 V
P-P
−68
−66
−62
−58
−60
dB
dB (max)
dB
dB
SNR Signal-to-Noise Ratio (Note 10)
f
IN
= 1 kHz, 4.85 V
P-P
f
IN
= 50 kHz, 4.85 V
P-P
f
IN
= 100 kHz, 4.85 V
P-P
61
60
60
58
dB
dB (min)
dB
ENOB Effective Number of Bits (Note 10) f
IN
= 1 kHz, 4.85 V
P-P
f
IN
= 50 kHz, 4.85 V
P-P
9.6
9.5 9
Bits
Bits (min)
R
REF
Reference Resistance 650 400
900
Ω(min)
Ω(max)
V
REF(+)
V
REF(+)
Input Voltage V
+
+ 0.05 V (max)
V
REF(−)
V
REF(−)
Input Voltage GND − 0.05 V (min)
V
REF(+)
V
REF(+)
Input Voltage V
REF(−)
V (min)
V
REF(−)
V
REF(−)
Input Voltage V
REF(+)
V (max)
V
IN
Input Voltage V
+
+ 0.05 V (max)
V
IN
Input Voltage GND − 0.05 V (min)
OFF Channel Input Leakage Current CS = V
+
,V
IN
=V
+
0.01 3µA (max)
ON Channel Input Leakage Current CS = V
+
,V
IN
=V
+
±1−3 µA (max)
ADC10662/ADC10664
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DC Electrical Characteristics
The following specifications apply for V
+
= +5V, V
REF(+)
=5VV
REF(−)
= GND, and Speed Adjust pin connected to ground
through a 14.0 kΩresistor (Mode 1) or an 8.26 kΩresistor (Mode 2) unless otherwise specified. Boldface limits apply for T
A
=T
J
=T
MIN
to T
MAX
;all other limits T
A
=T
J
= +25˚C.
Symbol Parameter Conditions Typical
(Note 7)
Limit
(Note 8)
Units
(Limits)
V
IN(1)
Logical “1” Input Voltage V
+
= 5.5V 2.0 V (min)
V
IN(0)
Logical “0” Input Voltage V
+
= 4.5V 0.8 V (max)
I
IN(1)
Logical “1” Input Current V
IN(1)
= 5V 0.005 3.0 µA (max)
I
IN(0)
Logical “0” Input Current V
IN(0)
0V −0.005 −3.0 µA (max)
V
OUT(1)
Logical “1” Output Voltage V
+
= 4.5V, I
OUT
= −360 µA
V
+
= 4.5V, I
OUT
= −10 µA
2.4
4.25
V (min)
V (min)
V
OUT(0)
Logical “0” Output Voltage V
+
= 4.5V, I
OUT
= 1.6 mA 0.4 V (max)
I
OUT
TRI-STATE®Output Current V
OUT
=5V
V
OUT
=0V
0.1
−0.1
50
−50
µA (max)
µA (max)
DI
CC
DV
CC
Supply Current CS = S/H = RD = 0 1.0 2mA (max)
AI
CC
AV
CC
Supply Current CS = S/H = RD = 0 30 45 mA (max)
AC Electrical Characteristics
The following specifications apply for V
+
= +5V, t
r
=t
f
= 20 ns, V
REF(+)
= 5V, V
REF(−)
= GND, and Speed Adjust pin connected
to ground through a 14.0 kΩresistor (Mode 1) or an 8.26 kΩresistor (Mode 2) unless otherwise specified. Boldface limits ap-
ply for T
A
=T
J
=T
MIN
to T
MAX
;all other limits T
A
=T
J
= +25˚C.
Symbol Parameter Conditions Typical
(Note 7)
Limit
(Note 8)
Units
(Limits)
t
CONV
Mode 1 Conversion Time from
Rising Edge of S/H to Falling Edge
of INT
360 466 ns (max)
t
CRD
Mode 2 Conversion Time 470 610 ns (max)
t
ACC1
Access Time (Delay from Falling
Edge of RD to Output Valid) Mode 1; C
L
= 100 pF 30 50 ns (max)
t
ACC2
Access Time (Delay from Falling
Edge of RD to Output Valid) Mode 2; C
L
= 100 pF 475 616 ns (max)
t
SH
Minimum Sample Time Mode 1 (Figure 1 ) ; (Note 9) 150 ns (max)
t
1H
,t
0H
TRI-STATE Control (Delay from
Rising Edge of RD to High-Z State) R
L
= 1k, C
L
=10pF 30 60 ns (max)
t
INTH
Delay from Rising Edge of RD to
Rising Edge of INT C
L
= 100 pF 25 50 ns (max)
t
P
Delay from End of Conversion to
Next Conversion 50 ns (max)
t
MS
Multiplexer Control Setup Time 10 75 ns (max)
t
MH
Multiplexer Hold Time 10 40 ns (max)
C
VIN
Analog Input Capacitance 35 pF (max)
C
OUT
Logic Output Capacitance 5 pF (max)
C
IN
Logic Input Capacitance 5 pF (max)
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional. These ratings do not guarantee specific performance limits, however. For guaranteed specifications and test conditions, see the Electrical Characteristics.
The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the
listed test conditions.
Note 2: All voltages are measured with respect to GND, unless otherwise specified.
Note 3: When the input voltage (VIN) at any pin exceeds the power supply rails (VIN <GND or VIN >V+) the absolute value of current at that pin should be limited
to 5 mA or less. The 20 mA package input current limits the number of pins that can safely exceed the power supplies with an input current of 5 mA to four.
Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX,θJA and the ambient temperature, TA. The maximum
allowable power dissipation at any temperature is PD=(T
JMAX −T
A)/θJA or the number given in the Absolute Maximum Ratings, whichever is lower. In most cases,
the maximum derated power dissipation will be reached only during fault conditions. For these devices, TJMAX for a board-mounted device can be found in the
Package Thermal Table.
Note 5: Human body model, 100 pF discharged through a 1.5 kΩresistor.
ADC10662/ADC10664
www.national.com5
AC Electrical Characteristics (Continued)
Note 6: See AN-450 “Surface Mounting Methods and Their Effect on Product Reliability” or the section titled “Surface Mount” found in a current National
Semiconductor Linear Data Book for other methods of soldering surface mount devices.
Note 7: Typical figures represent most likely parametric norm.
Note 8: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 9: Accuracy may degrade if tSH is shorter than the value specified. See curves of Accuracy vs. tSH.
Note 10: THD, SNR, and ENOB are tested in Mode 1. Measuring these quantities in Mode 2 yields similar values.
TRI-STATE Test Circuits and Waveforms
01119203
01119204
01119205
01119206
ADC10662/ADC10664
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Timing Diagrams
01119207
FIGURE 1. Mode 1. The conversion time (t
CONV
) is set by the internal timer.
01119208
FIGURE 2. Mode 2 (RD Mode). The conversion time (t
CRD
) includes the
sampling time and is determined by the internal timer.
ADC10662/ADC10664
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Typical Performance Characteristics
Zero (Offset) Error
vs. Reference Voltage
Linearity Error
vs. Reference Voltage
01119214 01119215
Analog Supply Current
vs. Temperature
Digital Supply Current
vs. Temperature
01119216 01119217
Conversion Time
vs. Temperature
Conversion Time
vs. Temperature
01119218 01119219
ADC10662/ADC10664
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Typical Performance Characteristics (Continued)
Conversion Time vs.
Speed-Up Resistor
Conversion Time vs.
Speed-Up Resistor
01119220 01119221
Spectral Response with
100 kHz Sine Wave Input
Spectral Response with
100 kHz Sine Wave Input
01119222 01119223
Signal-to-Noise + THD Ratio
vs. Signal Frequency
Linearity Change
vs. Speed-Up Resistor
01119224 01119225
ADC10662/ADC10664
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Typical Performance Characteristics (Continued)
Linearity Change vs.
Speed-Up Resistor
Linearity Error Change
vs. Sample Time
01119226 01119227
ADC10662/ADC10664
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Functional Description
The ADC10662 is obsolete. It is discussed here for ref-
erence only.
The ADC10662 and ADC10664 digitize an analog input sig-
nal to 10 bits accuracy by performing two lower-resolution
“flash” conversions. The first flash conversion provides the
six most significant bits (MSBs) of data, and the second flash
conversion provides the four least significant bits LSBs).
Figure 3 is a simplified block diagram of the converter. Near
the center of the diagram is a string of resistors. At the
bottom of the string of resistors are 16 resistors, each of
which has a value 1/1024 the resistance of the whole resistor
string. These lower 16 resistors (the LSB Ladder) therefore
have a voltage drop of 16/1024, or 1/64 of the total reference
voltage (V
REF+
−V
REF−
) across them. The remainder of the
resistor string is made up of eight groups of eight resistors
connected in series. These comprise the MSB Ladder. Each
section of the MSB Ladder has
1
⁄
8
of the total reference
voltage across it, and each of the LSB resistors has 1/64 of
the total reference voltage across it. Tap points across these
resistors can be connected, in groups of sixteen, to the
sixteen comparators at the right of the diagram.
On the left side of the diagram is a string of seven resistors
connected between V
REF+
and V
REF−
. Six comparators com-
pare the input voltage with the tap voltages on this resistor
string to provide a low-resolution “estimate” of the input
voltage. This estimate is then used to control the multiplexer
that connects the MSB Ladder to the sixteen comparators on
the right. Note that the comparators on the left needn’t be
very accurate; they simply provide an estimate of the input
voltage. Only the sixteen comparators on the right and the
six on the left are necessary to perform the initial six-bit flash
conversion, instead of the 64 comparators that would be
required using conventional half-flash methods.
To perform a conversion, the estimator compares the input
voltage with the tap voltages on the seven resistors on the
left. The estimator decoder then determines which MSB
Ladder tap points will be connected to the sixteen compara-
tors on the right. For example, assume that the estimator
determines that V
IN
is between 11/16 and 13/16 of V
REF
. The
estimator decoder will instruct the comparator MUX to con-
nect the 16 comparators to the taps on the MSB ladder
between 10/16 and 14/16 of V
REF
. The 16 comparators will
then perform the first flash conversion. Note that since the
comparators are connected to ladder voltages that extend
beyond the range indicated by the estimator circuit, errors in
the estimator as large as 1/16 of the reference voltage
(64 LSBs) will be corrected. This first flash conversion pro-
duces the six most significant bits of data — four bits in the
flash itself, and 2 bits in the estimator.
The remaining four LSBs are now determined using the
same sixteen comparators that were used for the first flash
conversion. The MSB Ladder tap voltage just below the input
voltage (as determined by the first flash) is subtracted from
the input voltage and compared with the tap points on the
sixteen LSB Ladder resistors. The result of this second,
four-bit flash conversion is then decoded, and the full 10-bit
result is latched.
Note that the sixteen comparators used in the first flash
conversion are reused for the second flash. Thus, the multi-
step conversion technique used in the ADC10662 and
ADC10664 needs only a small fraction of the number of
comparators that would be required for a traditional flash
converter, and far fewer than would be used in a conven-
tional half-flash approach. This allows the ADC10662 and
ADC10664 to perform high-speed conversions without ex-
cessive power drain.
01119212
FIGURE 3. Block Diagram of the Multistep Converter Architecture
ADC10662/ADC10664
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Functional Description (Continued)
SIMILAR PRODUCT DIFFERENCES
The ADC1006x, ADC1046x and ADC1066x (where "x" indi-
cates the number of multiplexer inputs) are similar devices
with different specification limits. The differences in these
device families are summarized below.
Device
Family
ILE, TUE,
PSS
THD, SNR,
ENOB
Max.
Conversion
Time
ADC1006x Guaranteed - 900ns
ADC1046x - Guaranteed 900ns
ADC1066x - Guaranteed 466ns
Applications Information
1.0 MODES OF OPERATION
The ADC10662 and ADC10664 have two basic digital inter-
face modes. Figure 1 and Figure 2 are timing diagrams for
the two modes. The ADC10662 and ADC10664 have input
multiplexers that are controlled by the logic levels on pins S
0
and S
1
when S/H goes low. Table 1 and Table 2 are truth
tables showing how the input channels are assigned.
Mode 1
In this mode, the S/H pin controls the start of conversion. S/H
is pulled low for a minimum of 150 ns. This causes the
comparators in the “coarse” flash converter to become ac-
tive. When S/H goes high, the result of the coarse conver-
sion is latched and the “fine” conversion begins. After 360 ns
(typical), INT goes low, indicating that the conversion results
are latched and can be read by pulling RD low. Note that CS
must be low to enable S/H or RD. CS is internally “ANDed”
with S/H and RD; the input voltage is sampled when CS and
S/H are low, and data is read when CS and RD are low. INT
is reset high on the rising edge of RD.
TABLE 1. Input Multiplexer Programming
ADC10664
S
1
S
0
Channel
00V
IN0
01V
IN1
10V
IN2
11V
IN3
TABLE 2. Input Multiplexer Programming
ADC10662
S
0
Channel
0V
IN0
1V
IN1
Mode 2
In Mode 2, also called “RD mode”, the S/H and RD pins are
tied together. A conversion is initiated by pulling both pins
low. The A/D converter samples the input voltage and
causes the coarse comparators to become active. An inter-
nal timer then terminates the coarse conversion and begins
the fine conversion. 470 ns (typical) after S/H and RD are
pulled low, INT goes low, indicating that the conversion is
completed. Approximately 20 ns later the data appearing on
the TRI-STATE output pins will be valid. Note that data will
appear on these pins throughout the conversion, but until
INT goes low the data at the output pins will be the result of
the previous conversion.
2.0 REFERENCE CONSIDERATIONS
The ADC10662 and ADC10664 each have two reference
inputs. These inputs, V
REF+
and V
REF−
, are fully differential
and define the zero to full-scale range of the input signal.
The reference inputs can be connected to span the entire
supply voltage range (V
REF−
=0V,V
REF+
=V
CC
) for ratio-
metric applications, or they can be connected to different
voltages (as long as they are between ground and V
CC
)
when other input spans are required.
Reducing the overall V
REF
span to less than 5V increases
the sensitivity of the converter (e.g., if V
REF
= 2V, then 1 LSB
= 1.953 mV). Note, however, that linearity and offset errors
become larger when lower reference voltages are used. See
the Typical Performance Curves for more information. For
this reason, reference voltages less than 2V are not recom-
mended.
In most applications, V
REF−
will simply be connected to
ground, but it is often useful to have an input span that is
offset from ground. This situation is easily accommodated by
the reference configuration used in the ADC10662 and
ADC10664. V
REF−
can be connected to a voltage other than
ground as long as the voltage source connected to this pin is
capable of sinking the converter’s reference current (12.5
mA Max @V
REF
= 5V). If V
REF−
is connected to a voltage
other than ground, bypass it with multiple capacitors.
Since the resistance between the two reference inputs can
be as low as 400Ω, the voltage source driving the reference
inputs should have low output impedance. Any noise on
either reference input is a potential cause of conversion
errors, so each of these pins must be supplied with a clean,
low noise voltage source. Each reference pin should be
bypassed with a 10 µF tantalum and a 0.1 µF ceramic.
3.0 THE ANALOG INPUT
The ADC10662 and ADC10664 sample the analog input
voltage once every conversion cycle. When this happens,
the input is briefly connected to an impedance approximately
equal to 600Ωin series with 35 pF. Short-duration current
spikes can be observed at the analog input during normal
operation. These spikes are normal and do not degrade the
converter’s performance.
Large source impedances can slow the charging of the
sampling capacitors and degrade conversion accuracy.
Therefore, only signal sources with output impedances less
than 500Ωshould be used if rated accuracy is to be
achieved at the minimum sample time (250 ns maximum). If
the sampling time is increased, the source impedance can
be larger. If a signal source has a high output impedance, its
output should be buffered with an operational amplifier. The
operational amplifier’s output should be well-behaved when
driving a switched 35 pF/600Ωload. Any ringing or voltage
shifts at the op-amp’s output during the sampling period can
result in conversion errors.
Correct conversion results will be obtained for input voltages
greater than GND − 50 mV and less than V
+
+ 50 mV. Do not
allow the signal source to drive the analog input pin beyond
ADC10662/ADC10664
www.national.com 12
Applications Information (Continued)
the Absolute Maximum Rating. If an analog input pin is
forced beyond these voltages, the current flowing through
the pin should be limited to 5 mA or less to avoid permanent
damage to the IC. The sum of all the overdrive currents into
all pins must be less than the Absolute Maximum Rating for
Package Input Current. When the input signal is expected to
extend beyond this limit, an input protection scheme should
be used. A simple input protection network using diodes and
resistors is shown in Figure 4. Note the multiple bypass
capacitors on the reference and power supply pins. If V
REF−
is not grounded, it should also be bypassed to analog ground
using multiple capacitors (see 5.0 “Power Supply Consider-
ations”). AGND and DGND should be at the same potential.
V
IN0
is shown with an input protection network.
4.0 INHERENT SAMPLE-AND-HOLD
Because the ADC10662 and ADC10664 sample the input
signal once during each conversion, they are capable of
measuring relatively fast input signals without the help of an
external sample-hold. In a non-sampling successive-
approximation A/D converter, regardless of speed, the input
signal must be stable to better than ±1/2 LSB during each
conversion cycle or significant errors will result. Conse-
quently, even for many relatively slow input signals, the
signals must be externally sampled and held constant during
each conversion if a SAR with no internal sample-and-hold is
used.
Because they incorporate a direct sample/hold control input,
the ADC10662 and ADC10664 are suitable for use in DSP-
based systems. The S/H input allows synchronization of the
A/D converter to the DSP system’s sampling rate and to
other ADC10662s, and ADC10664s.
5.0 POWER SUPPLY CONSIDERATIONS
The ADC10662 and ADC10664 are designed to operate
from a +5V (nominal) power supply. There are two supply
pins, AV
CC
and DV
CC
. These pins allow separate external
bypass capacitors for the analog and digital portions of the
circuit. To guarantee accurate conversions, the two supply
pins should be connected to the same voltage source, and
each should be bypassed with a 0.1 µF ceramic capacitor in
parallel with a 10 µF tantalum capacitor. Depending upon the
circuit board layout and other system considerations, more
bypassing may be necessary.
The ADC10662 and ADC10664 have separate analog and
digital ground pins for separate bypassing of the analog and
digital supplies. Their ground pins should be connected to
the same potential, and all grounds should be “clean” and
free of noise.
In systems with multiple power supplies, careful attention to
power supply sequencing may be necessary to avoid over-
driving inputs. The A/D converter’s power supply pins should
be at the proper voltage before digital or analog signals are
applied to any of the other pins.
6.0 LAYOUT AND GROUNDING
In order to ensure fast, accurate conversions from the
ADC10662 and ADC10664, it is necessary to use appropri-
ate circuit board layout techniques. The analog ground re-
turn path should be low-impedance and free of noise from
other parts of the system. Noise from digital circuitry can be
especially troublesome.
All bypass capacitors should be located as close to the
converter as possible and should connect to the converter
and to ground with short traces. The analog input should be
isolated from noisy signal traces to avoid having spurious
signals couple to the input. Any external component (e.g., a
filter capacitor) connected across the converter’s input
should be connected to a very clean ground return point.
Grounding the component at the wrong point will result in
reduced conversion accuracy.
7.0 DYNAMIC PERFORMANCE
Many applications require the A/D converter to digitize AC
signals, but conventional DC integral and differential nonlin-
earity specifications don’t accurately predict the A/D convert-
er’s performance with AC input signals. The important speci-
fications for AC applications reflect the converter’s ability to
digitize AC signals without significant spectral errors and
without adding noise to the digitized signal. Dynamic char-
acteristics such as signal-to-noise ratio (SNR) and total har-
monic distortion (THD), are quantitative measures of this
capability.
01119213
FIGURE 4. Typical Connection
ADC10662/ADC10664
www.national.com13
Applications Information (Continued)
An A/D converter’s AC performance can be measured using
Fast Fourier Transform (FFT) methods. A sinusoidal wave-
form is applied to the A/D converter’s input, and the trans-
form is then performed on the digitized waveform. The re-
sulting spectral plot might look like the ones shown in the
typical performance curves. The large peak is the fundamen-
tal frequency, and the noise and distortion components (if
any are present) are visible above and below the fundamen-
tal frequency. Harmonic distortion components appear at
whole multiples of the input frequency. Their amplitudes are
combined as the square root of the sum of the squares and
compared to the fundamental amplitude to yield the THD
specification. Guaranteed limits for THD are given in the
table of Electrical Characteristics.
Signal-to-noise ratio is the ratio of the amplitude at the
fundamental frequency to the rms value at all other frequen-
cies, excluding any harmonic distortion components. Guar-
anteed limits are given in the Electrical Characteristics table.
An alternative definition of signal-to-noise ratio includes the
distortion components along with the random noise to yield a
signal-to-noise-plus-distortion ration, or S/(N + D).
The THD and noise performance of the A/D converter will
change with the frequency of the input signal, with more
distortion and noise occurring at higher signal frequencies.
One way of describing the A/D’s performance as a function
of signal frequency is to make a plot of “effective bits” versus
frequency. An ideal A/D converter with no linearity errors or
self-generated noise will have a signal-to-noise ratio equal to
(6.02n + 1.76) dB, where n is the resolution in bits of the A/D
converter. A real A/D converter will have some amount of
noise and distortion, and the effective bits can be found by:
where S/(N + D) is the ratio of signal to noise and distortion,
which can vary with frequency.
As an example, an ADC10662 with a 4.85 V
P-P
, 100 kHz
sine wave input signal will typically have a signal-to-noise-
plus-distortion ratio of 59.2 dB, which is equivalent to 9.54
effective bits. As the input frequency increases, noise and
distortion gradually increase, yielding a plot of effective bits
or S/(N + D) as shown in the typical performance curves.
8.0 SPEED ADJUST
The speed adjust pin is connected to an on-chip current
source that determines the converter’s internal timing. By
connecting a resistor between the speed adjust pin and
ground as shown in Figure 4, the internal programming
current is increased, which reduces the conversion time. The
ADC10662 and ADC10664 are specified and guaranteed for
operation with R
SA
= 14.0 kΩ(Mode 1) or R
SA
= 8.26k (Mode
2). Smaller resistors will result in faster conversion times, but
linearity will begin to degrade as R
SA
becomes smaller (see
curves).
ADC10662/ADC10664
www.national.com 14
Physical Dimensions inches (millimeters) unless otherwise noted
Order Number ADC10662CIWM
NS Package Number M24B
Order Number ADC10664CIWM
NS Package Number M28B
ADC10662/ADC10664
www.national.com15
Notes
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves
the right at any time without notice to change said circuitry and specifications.
For the most current product information visit us at www.national.com.
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS
WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body, or
(b) support or sustain life, and whose failure to perform when
properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to result
in a significant injury to the user.
2. A critical component is any component of a life support
device or system whose failure to perform can be reasonably
expected to cause the failure of the life support device or
system, or to affect its safety or effectiveness.
BANNED SUBSTANCE COMPLIANCE
National Semiconductor manufactures products and uses packing materials that meet the provisions of the Customer Products
Stewardship Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification (CSP-9-111S2) and contain
no ‘‘Banned Substances’’ as defined in CSP-9-111S2.
Leadfree products are RoHS compliant.
National Semiconductor
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Support Center
Email: new.feedback@nsc.com
Tel: 1-800-272-9959
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www.national.com
ADC10662/ADC10664 10-Bit 360 ns A/D Converter with Input Multiplexer and Sample/Hold
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