IBIS5-B-1300 CYII5FM1300AB
1.3 MP CMOS Image Sensor
Cypress Semiconductor Corporation • 198 Champion Court • San Jose
,
CA 95134-1709 • 408-943-2600
Document #: 38-05710 Rev. *F Revised April 1, 2010
Features
■
1280 x 1024 Active Pixels
■
6.7 μm x 6.7 μm Square Pixels
■
S/N ratio: 64 dB
■
Full well charge: 62500e
-
■
Temporal noise: 40e
-
■
7.22 mV/s Dark cur r en t
■
Sensitivity: 8.4 V/lux.s at 650 nm
■
2/3” Optical Format
■
Global and Rolling Shutter
■
40 MPS/40 MHz Maximum Data Rate/Master Clock
■
27 fps (1280 x 1024) and 106 fps (640 x 480)
■
On-Chip 10-Bit ADCs
■
Supply Voltage
❐
Analog: 3.0V to 4.5V
❐
Digital: 3.3V
❐
I/O: 3.3V
■
Power Consumption: 175 mW
■
–30°C to +65°C Operating Temperature Range
■
84-Pin LCC Package
Applications
■
Machine vision
■
Inspection
■
Robotics
■
Traffic monitoring
Description
The IBIS5-B-1300 is a solid state CMOS image sensor that
integrates the functionality of complete analog image acquisition,
digitizer, and digital signal processing system on a single chip.
This 1.3-mega pixel (1280 x 1024) CMOS active pixel sensor
dedicated to industrial vision applications features both rolling
and snapshot (or global) shutter. Full frame readout time is 36 ms
(max. 27.5 fps), and readout speed are boosted by windowed
region of interest (ROI) readout. Another feature includes the
double and multiples slope functionality to capture high dynamic
range scenes. The sensor is available in a Monochrome version
or Bayer (RGB) patterned color filter array.
User programmable row and column start/stop positions allow
windowing down to a 2x1 pixel window for digital zoom. Sub
sampling or viewfinder mode reduces resolution while
maintaining the constant field of view and an increased frame
rate. An on-chip analog signal pipeline processes the analog
video output of the pixel array. Double sampling (DS) eliminates
the fixed pattern noise. The programmable gain and offset
amplifier maps the signal swing to the ADC input range. A 10-bit
ADC converts the analog data to a 10-bit digital word stream. The
sensor uses a 3-wire serial peripheral (SPI) interface, or a 16-bit
parallel interface. It operates with a 3.3V power supply and
requires only one master clock for operation up to 40 MHz. It is
housed in an 84-pin ceramic LCC package.
Figure 1. 1.3 MPixel CMOS Image Sensor
Ordering Information
Marketing Part Number Description Package
CYII5SM1300AB-QDC Mono with Glass
84 pin LCC
CYII5SM1300AB-QWC Mono without Glass
CYII5SC1300AB-QDC Color with Glass
CYII5FM1300AB-QDC Mono with thicker Epi with Glass
CYII5FM1300AB-QWC Mono with thicker Epi without Glass
CYII5SM1300-EVAL Mono Demo Kit Demo kitCYII5SC1300-EVAL Color Demo Kit
CYII5FM1300-EVAL Mono with thicker Epi Demo Kit
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IBIS5-B-1300 CYII5FM1300AB
Document #: 38-05710 Rev. *F Page 2 of 41
Contents
Features ............................................................................... 1
Applications ........................................................................1
Description ..........................................................................1
Ordering Information ..........................................................1
Contents ..............................................................................2
Architecture and Operation ...............................................3
Floor Plan ......................................................................3
Pixel ............................................................................... 3
Frame Rate ...................................................................5
Image Core Operation .................. ... ..............................5
X-Addressing .................................................................8
Y-addressing .................................................................8
Output Amplifier .............................................................9
Analog to Digital Converter .........................................10
Electronic Shutter Types .............................................12
Sequencer ...................................................................12
Timing Diagrams ..............................................................18
Timing Requirements ............. ................. ................. ...18
Synchronous Shutter: Single Slope Integration ...........18
Synchronous Shutter: Pixel Readout ..........................19
Synchronous Shutter: Multiple Slope Integration ........20
Rolling Shutter Operation ............................................21
Windowing in X-direction .............................................21
Windowing in Y-direction .............................................22
Initialization (Start-Up Behavio r) ..................................22
Pin List ........................ ... .............. .. ............... .....................23
Specifications ...................................................................26
General Specifications. ...............................................26
Electro-Optical Specifications ........ ................. .............26
Features and General Specifications ..................... ... ..29
Electrical Specifications ...............................................29
Pad position and Packaging ............................................31
Bare Die ............................................................ ... .......31
IBIS5-B-1300 in 84-pin LCC Package .........................32
Cover Glass .................................................................36
Handling Precautions .......................................................37
Handling and Soldering Conditions .............................37
Limited Warranty ..............................................................37
Return Material Authorization (RMA) ..........................37
RoHS (Pb-free) Compliance ........................................38
Appendix A: IBIS5 Demo Kit ............................................39
Appendix B: IBIS5-1300 Revision Overview ..................40
Document History Page ...................................................41
Sales, Solutions, and Legal Information ........................41
Worldwide Sales and Design Support .........................41
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Document #: 38-05710 Rev. *F Page 3 of 41
Architecture and Operation
This section presents detailed information about the most important sensor blocks.
Floor Plan
Figure 2 shows the architecture of the IBIS5-B-1300 image
sensor. It consists basically of a pixel array, one X- and two
Y-addressing registers for the readout in X- and Y-direction,
column amplifiers that correct for the fixed pattern noise, an
analog multiplexer, and an analog output amplifier.
Use the left Y-addressing register for readout operation. Use the
right Y-addressing register for reset of pixel rows. In multiple
slope synchronous shutter mode, the right Y-addressing register
resets the whole pixel core with a lowered reset voltage. In rolling
curtain shutter mode, use the right Y- addressing reg ister for the
reset pointer in single and double slope operation to reset one
pixel row.
The on-chip sequencer generates most of the signals for the
image core. Some basic signals (like start/stop integration, line
and frame sync signals, and others.) are generated externally.
A 10-bit ADC is implemented on chip but electrically isolated
from the image core. You must route the analog pixel output to
the analog ADC input on the outside.
Pixel
A description of the pixel architecture and the color filter array
follows.
Architecture
The pixel architecture used in the IBIS5-B-1300 is a 4-transistor
pixel as shown in Figure 3. Implement the pixel using the high fill
factor technique as patented by Cypress (US patent No.
6,225,670 and others). The 4T-pixel features a snapshot shutter
but can also emulate the 3T-pixel by continuously closing
sampling switch M2. Using M2 as a glob al sample tra nsistor for
all pixels enables the snapshot shutter mode. Due to this pixel
architecture, integration during read out is not possible in
synchronous shutter mode.
X-addressing
Analog multiplexe
r
Column amp li fiers
Pixel core
Pixel
Output
amplifier
Ima
g
er co re
ADC
Sequencer
Senso
r
Y-
lef
t
addressing Y-right
addressing
External
connection
System clo ck
40 MHz
Reset
Sample
Select
Column output
C
Figure 2. Block Diagram of IBIS5-B-1300 Image Sensor
reset
sample
mux
column
output
C
M1
M2 M3 M4
Figure 3. Architecture of the 4T-pixel
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Document #: 38-05710 Rev. *F Page 4 of 41
Color Filter Array
The IBIS5-B-1300 is also processed with a Bayer RGB color
pattern. Pixel (0,0) has a green filter and is situated on a
green-blue row. Green1 and green2 have a slightly different
spectral response due to cross talk from neighboring pixels.
Green1 pixels are located on a blue-green row, green2 pixels are
located on a green-red row. Figure 5 shows the response of the
color filter array as function of the wavelength. Note that this
response curve includes the optical cross talk of the pixels.
Blue
Red
Green1
Pixel 0,0
Green2
Blue
Red
Green1
Green2
Blue
Red
Green1
Green2
Figure 4. Color Filter Arrangement on the Pixels
Wavelength (nm)
Figure 5. Color Filter Respon se
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Document #: 38-05710 Rev. *F Page 5 of 41
Frame Rate
The pixel rate for this sensor is h igh enough to support a frame
rate of >100 Hz for a window size of 640 x 480 pixels (VGA
format). Taking into account a row blanking time of 3.5 µs (as
baseline, see also Internal clock granularities (bits 4, 5, 6 and 7).
on page 15), this requires a minimum pixel rate of nearly 40 MHz.
The final band width of the column amplifiers, outpu t stage, and
others is determined by external bias resistors. With a nominal
pixel rate of 40 MHz, a full frame rate of a little more than 27
frames per second is obtained.
The frame period of the IBIS5-B-1300 sensor depends on the
shutter type.
Rolling Shutter
=> Frame period = (Nr . Lines * (RBT + pixel period * Nr . Pixels))
with:
Nr. Lines Number of lines read out each frame (Y)
Nr. Pixels Number of pixels read out each line (X)
RBT Row blanking time = 3.5 µs (typical)
Pixel period 1/40 MHz = 25 ns
Example Read out time of the full resolution at nominal speed
(40-MHz pixel rate):
=> Frame period = (1024 * (3.5 µs + 25 ns * 1280)) = 36.4 ms
=> 27.5 fps
Snapshot shutter
=> Frame period = T int + Tread out
= Tint + (Nr. Lines * (RBT + pixel period * Nr. Pixels))
with: Tint ..................................... Integration (exposure) time
Nr. Lines Number of lines read out each frame (Y)
Nr. Pixels Number of pixels read out each line (X)
RBT Row blanking time = 3.5 µs (typical)
Pixel period 1/40 MHz = 25 ns
Example Read out time of the full resolution at nominal speed
(40 MHz pixel rate) with an integration time of 1 ms:
=> Frame period = 1 ms + (1024 * (3.5 µs + 25 ns * 1280)) =
37.4 ms => 26.8 fps
Region-Of-Interest (ROI) Read Out
Windowing is easily achie ved by uploading the starting point of
the X- and Y-shift registers in the sensor registers using the
various interfaces. This downloaded starting point initiates the
shift register in the X- and Y-direction triggered by the Y_ST AR T
(initiates the Y-shift register) and the Y_CLK (initiates the X-shift
register) pulse. The minimum step size for the x-add ress is two
(only even start addresses are chosen) and one for the
Y-address (every line is addressable). The frame rate increases
almost linearly when fewer pixels are read out. Table 1 gives an
overview of the achieva ble frame rates (in rolli ng shutter mode)
with various ROI dimensions.
Image Core Operation
Image Core Operation and Si gnalling
Figure 6 is a functional representation of the image core without
sub-sampling and column/row swapping circuits. Most of the
signals involved are not available from the outside because they
are generated by the X-sequence r and SS-sequencer blocks.
The integration of the pixels is controlled by internal signals such
as reset, sample, and hold whi ch are generated by the on-chip
SS-sequencer that is controlled with the external signals
SS_START and SS_STOP. Reading out the pixel array starts
by applying a Y_START together with a Y_CLOCK signal; inter-
nally this is followed by a calibration sequence to calibrate the
output amplifiers (during the row blanking time). Signals
necessary to do this calibration are generated by the on-chip
X-sequencer. This calibration sequence takes typically 3.5 μs
and is necessary to remove ‘Fixed Pattern Noise’ of the pixels
and of the column amp lifiers themselves by means of a double
sampling technique. After the row blanking time, the pixels are
fed to the output amplifier. The pixel rate is equal to the
SYS_CLOCK frequency.
Image Core Supply Considerations
The image sensor has several supply voltages:
VDDH is the voltage that controls the sample switch es. Do not
apply a higher voltage than this to the chip.
The VDDR_LEFT voltage is the highest (nominal) reset voltage
of the pixel core.
Table 1. Frame Rate vs. Resolution
Image
Resolution
(X*Y) Frame Rate
[frames/s] Frame
Readout Time
[ms] Comment
1280 x 1024 27 36 Full resolution.
640 x 480 100 10 ROI read out.
100 x 100 1657 0.6 ROI read out.
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IBIS5-B-1300 CYII5FM1300AB
Document #: 38-05710 Rev. *F Page 6 of 41
Y_START
SAMPLE
HOLD
Y_CLOC
K
Y
-left addressin
g
Y
-ri
g
ht addressin
g
BUS_
A
Y_CLOCK
Pixel row
Pi xel column
X
addressin
g
Column amplifiers
BUS_B
SYS_CLOC
K
Read-pointe
r
Y_START
RESET
VDDH
VDDR_LEFT VDDR_RIGHT
Vddreset
VDDC
Output amplifier
PXL_OUT
Pixel
A
Pixel
B
Figure 6. Image Core
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IBIS5-B-1300 CYII5FM1300AB
Document #: 38-05710 Rev. *F Page 7 of 41
The VDDR_RIGHT vo ltage is generated from the VDDR_LEFT
voltage using a circuit that is programmed with the
KNEEPOINT_LSB/MSB bits in the sequencer register (see also
“Pixel reset knee-point for multiple slope operation (bits 8, 9, and
10).” on page 16). You can disconnect the VDDR_RIGHT pin
from the circuit and apply an external voltage to supply the
multiple slope reset voltage by setting the VDDR_RIGHT_EXT
bit in the SEQUENCER register. When no external voltage is
applied (recommended), connect the VDDR_RIGHT pin to a
capacitor (recommended value = 1µF). VDDC is the pixel core
supply. VDDA is the image core and periphery analog supply.
VDDD is the image core and periphe ry di gital supply.
Note that the IBIS5-B-1300 image sensor has no on-chip power
rejection circuitry . As a consequence all variations on the analog
supply voltages can contribute to random variations (noise) on
the analog pixel signal, which is seen as random noise in the
image. During the camera design, take precautions to supply the
sensor with very stable supply voltages to avoid this additional
noise. The pixel array (VDDR _LEFT, VD DH and VDDC ) analog
supplies are especially vulnerable to this.
Snapshot Shutter Supply Considerations
The recommended supply voltage settings listed in Table 2 are
used when the IBIS5-B-1300 sensor is in snapshot shutter mode
only.
Dual Shutter Supply Considerations
If you analyze the supply setti ngs listed in Table 2, you can see
some fixed column non-uniformities (FPN) when operating in
rolling shutter mode. If a dual shutter mode (both rolling and
snapshot shutter) is required during operation, you must apply
the supply settings listed in Table 3 to achieve the best possible
image quality.
Image Core Biasing Signals
Table 4 summarizes the biasing signals required to drive the
IBIS5-B-1300. For optimizations reason s, with respect to speed
and power dissipation of all internal blocks, several biasing
resistors are needed.
Each biasing signal determines the operation of a corresponding
module in the sense that it controls the speed and powe r dissi-
pation. The tolerance on the DC-level of the bias levels can vary
±150 mV due to process variations.
T able 2. Snapshot Shutter Recommended Supply Settings
Parameter Description Typ Unit
VDDH Voltage on HOLD switch es. +4.5 V
VDDR_LEFT Highest reset voltage. +4.5 V
VDDC Pixel core voltage. +3.3 V
VDDA Analog supply voltage of the
image core. +3.3 V
VDDD Digital supply voltage of the
image core. +3.3 V
GNDA Analog ground. 0 V
GNDD Digital ground. 0 V
GND_AB Anti-blooming ground. 0 V
Table 3. Dual Shutter Recommended Su pp ly Settings
Parameter Description Typ Unit
VDDH Voltage on HOLD switches. +4.5 V
VDDR_LEFT Highest reset voltage. +4.5 V
VDDC Pixel core voltage. +3.0 V
VDDA Analog supply voltage of the
image core. +3.3 V
VDDD Digital supply voltage of the
image core. +3.3 V
GNDA Analog ground. 0 V
GNDD Digital ground. 0 V
GND_AB Anti-blooming ground. 0 V
Table 4. Overview of Bias Signals
Signal Comment Related module DC-Level
DEC_CMD Connect to VDDA with R = 50 k
Ω
and decouple to GNDA with C = 100 nF. Decoder stage. 1.0V
DAC_VHIGH Connect to VDDA w ith R = 0
Ω
. High level of DAC. 3.3V
DAC_VLOW Connect to GNDA with R = 0
Ω
. Low level of DAC. 0.0V
AMP_CMD Connect to VDDA with R = 50 k
Ω
and decouple to GNDA with C = 100 nF. Output amplifier stage. 1.2V
COL_CMD Connect to VDDA with R = 50 k
Ω
and decouple to GNDA with C = 100 nF. Columns amplifiers st age. 1.0V
PC_CMD Connect to VDDA with R = 25 k
Ω
and decouple to GNDA with C = 100 nF. Pre-charge of column
busses. 1.1V
ADC_CMD Connect to VDDA with R = 50 k
Ω
and decouple to GNDA with C = 100 nF. Analog stage of ADC. 1.0V
ADC_VHIGH Connect to VDDA with R = 360
Ω
and decouple to GNDA with C = 100 nF. High level of ADC. 2.7V
ADC_VLOW Connect to GNDA with R = 1200
Ω
and decouple to GNDA with C = 100 nF. Low level of ADC. 1.8V
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IBIS5-B-1300 CYII5FM1300AB
Document #: 38-05710 Rev. *F Page 8 of 41
X-Addressing
Because of the high pixel rate, the X-shift register selects two
columns at a time for readout, so it runs at half the system clock
speed. All even columns are connected to bus A; all odd columns
to bus B. In the output amplifier, bus A and bus B are combined
into one stream of pixel data at system clock speed.
At the end of the row blanking time, the X_SYNC switch is closed
while all other swi tches are open and the decoder output is fed
to the register. The decoder loads a logical one in one of the
registers and a logical zero in the rest. This defines the starting
point of the windo w in the X direction. As soon as the X_SYNC
signal is released, the register starts shifting from the start
position.
When no sub-sampling is required, X_SUB is inactive. The
pointer in the shift-register moves one bit at a time.
When sub-sampling is enabled, X_SUB is activated. The shift
register moves two bits at a time. Taking into account that every
register selects two columns, hence two pixels sub-sampling
results in the pattern ’XXOOXXOO’ when eight pixels are
considered. Suppose the columns are numbered from left to right
starting with 0 (zero) and sub-sampling is enabled:
If columns 1 and 2, 5 and 6, 9 and 10 … are swapped using the
SWAP_12 switches, a normal sub-sampling pattern of
’XOXOXOXO’ is obtained.
If columns 3 and 4, 7 and 8, 1 1 and 12 … are swapped using the
SWAP_30 switches, the pattern is ’OXOXOXOX’.
If both the SWAP_12 and SWAP_30 switches are closed, pattern
’OOXXOOXX’ is obtain e d.
Because every register addresses two columns at a time, the
addressable pixels range in sub-sample mode is from zero to half
the maximum number of pixe ls in a row (on ly even values). For
instance: 0, 2, 4, 6, 8… 638.
Y-addressing
For symmetry reasons, the sub-sampling modes in the
Y-direction are the same as in X-di rection.
Reg(n+1) Reg(n+2)Reg(n)
X_SYNC
X_SUB
A B A B Column
amplifiers
BA
BUS_
A
BUS_B
X_S
WAP30
X_SWAP12
COL(i) COL(i+2)
COL(i+1) COL(i+3)
DEC(n+1) DEC(n+2)
1/2
SYS_CLOC
K
Output
amplifier
Figure 7. Column Structure
Table 5. X–Sub-sample Patterns
X_SUB X_SWAP12 X_SWAP30 Sub-Sample Pattern
0 0 0 XXXXXXXX
1 0 0 XXOOXXOO
1 1 0 XOXOXOXO
1 0 1 OXOXOXOX
1 1 1 OOXXOOXX
Table 6. Y–Sub-Sample Patterns
Y_SUB Y_SWAP12 Y_SWAP30 Sub-Sample Pattern
0 0 0 XXXXXXXX
1 0 0 XXOOXXOO
1 1 0 XOXOXOXO
1 0 1 OXOXOXOX
1 1 1 OOXXOOXX
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Document #: 38-05710 Rev. *F Page 9 of 41
In normal mode, the pointer for the pi xel row is shifted one at a
time.
When sub-sampling is enabled, Y_SYNC is activated. The
Y-shift register shifts 2 succeeding bits and skips the 2 next bits.
This results in pattern ’XXOOXXOO’.
Activating Y_SWAP12 results in p attern ’XOXOXOXO’.
Activating Y_SWAP30 results in pattern ’OXOXOXOX’.
Activating both Y_SWAP12 and Y_SWAP30 results in pattern
’OOXXOOXX’.
The addressable pixel range when Y -sub sampling is enabled is:
0–1, 4–5, 8–9, 12–13, … 1020–1021
Output Amplifier
Architecture and Settings
The output amplifier stage is user programmable for gain and
offset level. Gain is controlled by 4-bit wide word; offset by a 7-bit
wide word. Gain settings are on an exponential scale. Offset is
controlled by a 7-bit w ide DAC, which sele cts the offset voltage
between two reference voltages (DAC_VHIGH and
DAC_VLOW) on a linear scale.
The amplifier is designed to match the specifications of the
imager array output. This signal has a data rate of 40 MHz. The
output impedance of the ampl ifier is 260 O hms.
At unity gain and with a mid-range offset value, the amplifier
outputs a signal in between 1.59V (ligh t) and 2.70V (dark). T his
analog range must fi t to the input ran ge of the AD C, exte rnal o r
internal. The output swing in unity gain is approximately 1.11V
and it is maximum 1.78V at the highest gain settings. So, the
effective signal range is between 1.17V and 2.95V, depending
on the gain and offset settings of the amplifier.
Figure 9 on page 10 shows the architecture of the output
amplifier . The odd and even column amplifiers sample both pixel
and reset value to perform a double sampling FPN correction.
Y ou can adjust two different offsets using the on-chip DAC (7 bit):
DAC_FINE and DAC_RAW. DAC_FINE is used to tune the
difference between odd and even column s; DAC_RAW is used
to add a common (both even and odd columns) to the FPN
corrected pixel value. This p ixel va lue i s fe d to the first amplifier
stage which has an adjustable gain, controlled by a 4-bit word
(’GAIN [0…3]’).
After this, a unity feedback amplifier buffers the signal and the
signal leaves the chip. This second amplifier stage determines
the maximal readout speed, that is, th e bandwi dth and the slew
rate of the outpu t signal. The whole amplifier chain is designed
for a data rate of 40 Mpix/s (@20 pF).
The analog output of the IBIS5-B-1300 image sensor is not
designed to drive very large loads on the PCB. Therefore, it is
advised that the PXL_OUT is connected to the ADC_IN right
below the sensor in the top layer with a thick track. It is better not
to have vias on this trace. If there is a socket being used, then it
is advised that we buffer the PXL_OUT close to the sensor
output pin and then take the signal to the ADC_IN.
Output Amplifier Gain Control
The output amplifier gain is cont rolled by a 4-bit wo rd set in the
AMPLIFIER register (see section Amplifier Register (6:0) on
page 17). An overview of the gain settings is given in Table 7.
Setting of the DAC Reference Voltage
In the output amplifier, the offset is trimmed by loading register s
DACRAW_REG and DACFINE_REG. DAC_RAW is used to
adjust the offset of the output amplifier a nd DAC_FINE is used
to tune the offset between the even and odd columns. These
registers are inputs for two DACs (see Figure 10 on page 10) that
operate on the same resistor that is connected between pins
Reg(n)
Reg(n+1)
Reg(n+2)
Reg(n+3)
Reg(n+4)
Y_SWAP12
SRH
SRH
SRH
SRH
ROW(n+1)
ROW
(
n+2
)
ROW(n+3)
ROW
(
n+4
)
Y_SWAP30Y_SYNC Y_SUB
DEC
(
n+1
)
DEC(n+2)
DEC
(
n+3
)
DEC(n+4)
Figure 8. Row Structure
Table 7. Overview Gain Settings
Bits DC Gain Bits DC Gain
0000 1.37 1000 6.25
0001 1.62 1001 7.89
0010 1.96 1010 9.21
0011 2.33 1011 11.00
0100 2.76 1100 11.37
0101 3.50 1101 11.84
0110 4.25 1110 12.32
0111 5.20 1111 12.42
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IBIS5-B-1300 CYII5FM1300AB
Document #: 38-05710 Rev. *F Page 10 of 41
DAC_VHIGH and DAC_VLOW . The range of the DAC is defined
using a resistive division with R
VHIGH
, R
DAC
and R
VLOW
.
The internal resistor R
DAC
has a value of approximately 7.88 k
Ω
.
The recommend resistor values for both DAC_VLOW and
DAC_VHIGH are 0
Ω
.
Analog to Digital Converter
The IBIS5-B-1300 has a 10-bit flash analog digital converter
running nominally at 40 Msamples/s. The ADC is electrically
separated from the image sensor. Tie the input of the ADC
(ADC_IN; pin 69) externally to the output (PXL_OUT1; pin 28) of
the output am plifier.
ADC Timing
At the rising edge of SYS_CLOCK, the next pixel is fed to the
input of the output amplifier. Due to internal delays of the
SYS_CLOCK signal, it takes approximately 20 ns before the
output amplifier outputs the analog value o f the pixel as shown
in Figure 11 on page 11.
The ADC converts the pixel data on the rising edge of the
ADC_CLOCK, but it takes two clock cycles before this pixel data
is at the output of the ADC. Figure 11 shows this pipeline delay.
Due to these delays, it is advisable that a variable phase
difference is foreseen between the ADC_CLOCK and the
SYS_CLOCK to tune the optimal sample moment of the ADC.
A
GAIN [0…3]
unity gain
1
S
R
S
R
odd
even
+
+
DAC_VHIGH
DAC_VLOW
DAC_RAW [6:0]
DAC_FINE [6:0]
DAC_RAW
DAC_FINE
PXL_OUT
Figure 9. Output Structure
R
DAC_VHIGH
DAC_VLOW = 0
V
DAC_VHIGH = 3.3
V
R
DAC_VLOW
R
DAC
externa
l
interna
l
externa
l
7.88 kΩ
interna
l
Figure 10. In- and External DAC Connections
Table 8. ADC Sp ec ifications
Input range 1–3V
[1]
Quantization 10 Bits
Nominal data rate 40 Msamples/s
DNL (linear conversion mode) Typ. < 0.5 LSB
INL (linear conversion mode) Typ. < 3 LSB
Input capacitance < 20 pF
Power dissipation @ 40 MHz Typ. 45 mA * 3.3V = 150 mW
Conversion law Linear / Gamma-corrected
Note
1. The internal ADC range is typically 100 mV lower then the external applied ADC_VHIGH and ADC_VLOW voltages due to voltage drops over parasitic internal resistors
in the ADC.
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IBIS5-B-1300 CYII5FM1300AB
Document #: 38-05710 Rev. *F Page 11 of 41
Setting of the ADC Reference Voltages
The internal resistor R
ADC
has a value of approximately 585
Ω
.
This results in the following values for the external resistors:
Note that the recommended ADC resistor values yield in a
conversion of the full analog output swing at unity gain
(V
DARK_ANALOG
< ADC_VHIGH and V
LIGHT_ANALOG
>
ADC_VLOW).
The values of the resistors depend on the value of R
ADC
. To
assure proper working of the ADC, make certain the voltage
difference between ADC_VLOW and ADC_VHIGH is at least
1.0V.
Non-linear and Linear Conversion Mode—’gamma’ Correction
Figure 13 on page 12 shows the ADC transfer characteristic. The
non-linear (exponential) ADC conversion is intended for
gamma-correction of the images. It increases contrast in dark
areas and reduces contrast in bright areas. The non-linear
transfer function is given by:
With:
a = 5
b = 0.027
x = digital output code
Sensor Digital Outputs
The digital outputs of the IBIS5-B-1300 sensor are not designed
to drive large loads. Hence, the outputs cannot be used to
directly drive cables or long traces on the PCB. If it is required to
drive traces more than 5 inches long, it is advisable to use a
buffer for all the digital signals given out by the sensor.
Sensor Clock Inputs
The ADC_CLOCK and the SYS_CLOCK of the sensor are
typically 180 phase shifted from each other . However , depending
on the board layo ut, it is possible that there may b e a variation
(increased phase shift of ADC_CLOCK with respect to
SYS_CLOCK) in the phase shift between the clocks.
So, it is recommended that the phase shift between the clocks is
maintained programmable.
Clock Jitter Requirements:
Min low time: 11.00ns
Min high time 11.00ns
max rise time 5ns
max fall time 5ns
Max Duty cycle: 47%-53%
Max period jitter: 150ps
It is important that the clock is stable, reproduci ble and has low
jitter. SYS_CLOCK and ADC_CLOCK are the most critical
clocks, both clock interact in the readout path and influence the
sensor performance.
Resistor Value (O)
R
ADC_VHIGH
360
R
ADC
585
R
ADC_VLOW
1200
Figure 11. ADC Timing
Figure 12. In- and External ADC Connections
R
ADC_VHIGH
ADC_VLOW ~ 1.8
V
ADC_VHIGH ~ 2.7
V
R
ADC_VLOW
R
ADC
externa
l
interna
l
externa
l
Vin ADC_VHIGH ADC_VHIGH ADC_VLOW–() * a*x b*x
2
+
a*1023 b*1023
2
+
-----------------------------------------------+=
[+] Feedback
IBIS5-B-1300 CYII5FM1300AB
Document #: 38-05710 Rev. *F Page 12 of 41
Electronic Shutter Types
The IBIS5-B-1300 has two different shutter types: a rolling
(curtain) shutter and a snapshot (synchronous) shutter.
Rolling (Curtain) Shutter
The name is due to the fact that the effect is similar to a curtain
shutter of a SLR film camera. Although it is a pure electronic
operation, the shutter seems to slide over the image. A rolling
shutter is easy and elegant to implement in a CMOS sensor.
Notice that in Figure 14 on page 13, there are two Y-shift
registers. One of them points to the row that is currently being
read out. The other shift register points to the row that is currently
being reset. Both pointers are shifted by the same Y-clo ck and
move over the focal plane. The integration time is set by the
delay between both pointers.
Figure 14 on page 13 graphically displays the relative shift of the
integration times for different lines during the rolling shutter
operation. Each line is rea d and reset in a seq uential way. The
integration time is the same for all lines, but is shifted in time. Y ou
can vary the integration time through th e INT_TIME register (in
number of lines).
This indicates that all pixels are light sensitive at another period
of time, and can cause so me blurring if a fast moving object is
captured.
When the sensor is set to rol ling shutter mode, make certain to
hold the input SS_START and SS_STOP low.
Snapshot (Synchronous) Shutter
A synchronous (global, snapshot) shutter solves the inconve-
nience found in the rolling shutter. Light integration takes place
on all pixels in parallel, although subsequent readout is
sequential.
Figure 15 shows the integration and read out sequence for the
synchronous shutter. All pixels are light sensitive at the same
period of time. The whole pixel core is reset simultaneously and
after the integration time all pixel values are sampled together on
the storage node inside each pixel. The pixel core is read out line
by line after integration. Note that the integration and read out
cycle is carry-out in serial; that causes that no integration is
possible during read out.
During synchronous shutter mode, the input pins SS_START
and SS_STOP are used to start and stop the synchronous
shutter.
Sequencer
Figure 6 on page 6 shows a number o f control signals that are
needed to operate the sensor in a particular sub-sampling mode
with a certain integration time, o utput amplifier gain, a nd so on.
Most of these signals are generated on-chip by the sequencer
that uses only a few control signals. Make certain that these
control signals are generated by the external system:
■
SYS_CLOCK (X-clock) defines the pixel rate
■
Y_START pulse indicates the start of a new frame read out
■
Y_CLOCK selects a new row and starts the row blanking
sequence, including the synchronization and loading of the
X-register
■
SS_START and SS_STOP control the integration period in
snapshot shutter mode.
The relative position of the pulses is determined by a number of
data bits that are uploaded in internal registers through the serial
or parallel interface.
Figure 13. Linear and Non-linear ADC Conversion Characteristic
[+] Feedback
IBIS5-B-1300 CYII5FM1300AB
Document #: 38-05710 Rev. *F Page 13 of 41
Reset line
Read line
x
y x
y
Tim e axis
Line number
Reset sequence
Frame time Integration time
Figure 14. Rolling Shutter Operation
Time axis
Line number
Integration time Burst Readout time
COMMON RESET
COMMON SAMPLE&HOLD
Flash could occur here
Figure 15. Synchronous Shutter Operat io n
[+] Feedback
IBIS5-B-1300 CYII5FM1300AB
Document #: 38-05710 Rev. *F Page 14 of 41
Internal Registers
Table 9 on page 14 shows a list of the internal registers with a
short description. In the next section, the registers are explained
in more det ail . On power-o n, al l registe rs in the sensor a re reset
to zero. To start operating the sensor, we must first load all the
registers using the parallel or serial-3-wire interface. The value
to be loaded in each register on power-on is given in the table
below.
Table 9. Internal Registers
Register Bit Name Description
0 (0000) 11:0 SEQUENCER register Default value <11:0>: ’000011000100’
0 SHUTTER_TYPE 1 = rolling shutter
0 = synchronous shutter
1 FRAME_CAL_MODE 0 = fast
1 = slow
2 LINE_CAL_MODE 0 = fast
1 = slow
3 CONT_CHARGE 1 = ’Continuous’ precharge enabled
4 GRAN_X_SEQ_LSB Granulari ty of the X sequencer clock
5 GRAN_X_SEQ_MSB
6 GRAN_SS_SEQ_LSB Granularity of the SS sequencer clock
7 GRAN_SS_SEQ_MSB
8 KNEEPOINT_LSB Sets reset voltage for multiple slope operation
9 KNEEPOINT_MSB
10 KNEEPOINT_ENABLE 1 = Enables multiple slope operation in synchronous shutter mode
11 VDDR_RIGHT_EXT 1 = Disables circuit that generates VDDR_R IGHT voltage; this allows
the application of an external voltage
1 (0001) 11:0 NROF _PIXELS Number of pixels to count (maximum 1280/2)
Default value <11:0>: ’001001111111’
2 (0010) 11:0 NROF _LINES Number of lines to count
Default value <11:0>: ’001111111111’
3 (0011) 11:0 INT_TIME Integration time
Default value <11:0>: ’111111111111’
4 (0100) 10:0 X_REG X start position (maximum 1280/2)
Default value <10:0>: ’00000000000’
5 (0101) 10:0 YL_REG Y-left start position
Default value <10:0>: ’00000000000’
6 (0110) 10:0 YR_REG Y-right start position
Default value <10:0>: ’00000000000’
7 (0111) 7:0 IMAGE CORE register Default value <7:0> : ’0 0000 000’
0 TEST_EVEN Test even columns
1 TEST_ODD Test odd columns
2 X_SUBSAMPLE Enable sub-sampling in X-direction
3 X_SWAP12 Swap columns 1-2, 5-6, …
4 X_SWAP30 Swap columns 3-4, 7-8, …
5 Y_SUBSAMPLE Enable sub-sampling in Y-direction
6 Y_SWAP12 Swap rows 1-2, 5-6, …
7 Y_SWAP30 Swap rows 3-4, 7-8, …
[+] Feedback
IBIS5-B-1300 CYII5FM1300AB
Document #: 38-05710 Rev. *F Page 15 of 41
Detailed Description of the Internal Registers
Sequencer register (7:0)
1. Shutter type (bit 0).
The IBIS5-B-1300 image sensor has tw o shutter types:
0 = synchronous shutter.
1 = rolling shutter.
2. Output amplifier calibration (bits 1 and 2).
Bits FRAME_CAL_MODE and LINE_CAL_MODE define the
calibration mode of the output amplifier.
During every row-blanking period, a calibration is done of the
output amplifier. There are two calibration modes. The FAST
mode (= 0) forces a calibration in one cycle but is not so ac-
curate and suffers from KTC noise. The SLOW mode (= 1)
only makes incremental adjustments and is noise free.
Approximately 200 or more ’slow’ calibrations have the same
effect as one ’fast’ calibration.
Different calibration modes are set at the beginning of the
frame (FRAME_CAL_MODE bit) and for every subsequent
line that is read (LINE_CAL_MODE bit). The Y_START input
defines the beginning of a frame, Y_CLOCK defines the be-
ginning of a new row.
3. Continuous charge (bit 3).
Some applications may require the use continuous charg ing
of the pixel columns instead of a pre-charge on every line
sample operation.
Setting bit CONT_CHARGE to ’1’ activates this function. The
resistor connected to p in PC_CMD controls the current level
on every pixel column.
4. Internal clock granularities (bits 4, 5, 6 and 7).
The system clock is divided several times on-chip.
Half the system clock rate clocks the X-shift -register that con-
trols the column/pi xel readout. Odd and even pixel columns
are switched to two separate buses. In the output amplifier the
pixel signals on the two buses are combined into one pixel
stream at the same frequency as SYS_CLOCK.
Use the bits GRAN_SS_SEQ_MSB (bit 7) and
GRAN_SS_SEQ_LSB (bit 6) to program the clock that drives
the ’snapshot’ or synchronous shutter sequencer.
This way the integration time in synchronous shutter mode is
a multiple of 32, 64, 128, or 256 times the system clock period.
To overcome global reset issues, use the longest SS granu-
larity (bits 6 and 7 set to '1').
.
8 (1000) 6:0 AMPLIFIER register Default value <6:0>: ’1010000’
0 GAIN<0> Output amplifier gain setting
1GAIN<1>
2GAIN<2>
3GAIN<3>
4 UNITY 1 = Amplifier in unity gain mode
5 DUAL_OUT 1 = Activates second output
6 STA NDBY 0 = Amplifier in standby mode
9 (1001) 6:0 DACRAW_REG Amplifier DAC raw offset
Default value <6:0>: ’1000000’
10 (1010) 6 :0 DACFINE_REG Amp lifier DAC fine offset
Default value <6:0>: ’1000000’
11 (1011) 2:0 ADC registe r Default value <2:0>: ’011’
0 TRISTATE_OUT 0 = Output bus in tri-state
1 GAMMA 0 = Gamma-correction on
2 BIT_INV 1 = Bit inversion on outpu t bu s
12 (1100) Reserved
13 (1101) Reserved
14 (1110) Reserved
15 (1111) Reserved
Table 9. Internal Registers (continued)
Register Bit Name Description
Table 10. SS Sequencer Clock Granularities
GRAN_SS_SEQ_MSB/
LSB SS-Sequencer
Clock Integration
Time Step
[2]
00 32 x SYS_CLOCK 800 ns
01 64 x SYS_CLOCK 1.6
μ
s
10 128 x SYS_CLOCK 3.2
μ
s
11 256 x SYS_CLOCK 6.4
μ
s
Note
2. Using a SYS_CLOCK of 40 MHz (25 ns period).
[+] Feedback
IBIS5-B-1300 CYII5FM1300AB
Document #: 38-05710 Rev. *F Page 16 of 41
The clock that drives the X-sequencer is a multiple of 4, 8, 16, or
32 times the system clock. Clock ing the X-sequencer at a slower
rate (longer row blanking time; pixel read out speed is always
equal to the SYSTEM_CLO CK) results in more sign al swing for
the same light conditions.
5. Pixel reset knee-point for multiple slope operation (bits 8, 9,
and 10).
In normal (single slope) mode the pixel reset is controlled from
the left side of the image core using the voltage applied on pin
VDDR_LEFT as pixel reset voltage.
In multiple slope o peration, apply one or more variable p ixel
reset voltages.
Bits KNEE_POINT_MSB and KNEE_POINT_LSB select the
on chip-generated pixel reset voltage.
Bit KNEE_POINT_ENABLE set to ’1’ switches control to the
right side of the image core so the pixel reset voltage
(VDDR_RIGHT), selected by bits KNEE_POINT_MSB/LSB,
is used.
Use bit KNEE_POINT_ENABLE only for multiple slope oper-
ation in synchronous shutter mode. In rolling shutter mode,
use only the bits KNEE_POINT_MSB/LSB to select the sec-
ond knee-point in dual slope operation. The actual knee-point
depends on VDDH, VDDR_LEFT and VDDC applied to the
sensor.
6. External Pixel Reset Voltage for Multiple Slope (bit 11)
Setting bit VDDR_RIGHT_EXT to ’1’ di sables the circui t that
generates the variable pixel reset vo ltage and uses the volt-
age externally applied to pin VDDR_RIGHT as the dou-
ble/multiple slope reset voltage.
Setting bit VDDR_RIGHT_EXT to ’0’ allows you to monitor the
variable pixel reset voltage (used for multiple slope operation)
on pin VDDR_RIGHT.
NROF_PIXELS Register (11:0)
After the internal x_sync is generated (start of the pixel readout
of a particular row), the PIXEL_VALID signal goes high. The
PIXEL_VALID signal goes low when the pixel counter reaches
the value loaded in the NROF_PIXEL register. Due to the fact
that two pixels are read at the same clock cycle, you must divide
this number by 2 (NROF_PIXELS = (width of ROI / 2) – 1).
ROF_LINES Register (11:0)
After the internal yl_sync is generated (start of the frame readout
with Y_START), the line counter increases with each Y_CLOCK
pulse until it reaches the value loaded in the NROF_LINES
register and generates a LAST_LINE pulse. It must be noted that
the value loaded in the register must be (Number of lines
required - 1).
INT_TIME Register (11:0)
Use the INT_TIME register to set the integration time of the
electronic shutter. The interpre tatio n of the INT_TIME depends
on the chosen shutter typ e (rolling or synchronous).
1. Synchronous shutter.
After the SS_START pulse is applied an internal counter
counts the number of SS granulated clock cycles until it
reaches the value loaded in the INT_TIME register and gen-
erates a TIME_OUT pulse. Use this TIME_OUT pulse to gen-
erate the SS_STOP pulse to stop the integratio n. When the
INT_TIME register is used, the maximum inte gration time is:
TINT_MAX = 212 * 256 (maximum granularity) * (40 MHZ) – 1
= 26.2 ms.
You can increase this maximum time if you use an external
counter to trigger SS_STOP. Ten is the minimal value that you
can load into th e IN T_TI ME register (see al so “In ternal cl ock
granularities (bits 4, 5, 6 and 7).” on page 15).
2. Rolling shutter.
When the Y_ST AR T pulse is applied (start of the frame read-
out), the sequencer generates the yl_sync pulse for the left
Y-shift register (read out Y-shift register). This loads the left
Y-shift register with the pointer loaded in YL_REG register . At
each Y_CLOCK pulse, the pointer shifts to the next row and
the integration time counter increases until it reaches the val-
ue loaded in the INT_T IME register. At that moment, the se-
quencer generates the yr_sync pulse for the right Y-shift reg-
ister; it loads the right Y-shift register (reset Y-shift register)
with the pointer loa ded in YR_REG registe r (see Figure 16).
The integrat ion time counter is reset when th e sync for the left
Y-shift register, yl_sync is asserted. Both shift registers keep
moving until the next sync is asserted, i.e., the yl_sync for the
left Y-shift register (generated by Y_START) and the yr_sync
for the right Y-shift register (generated when the integration
time coun ter reaches th e INT_TIME value)..
T reg_int Difference between the left and right pointer = value
set in the INT_TIME register (number of lines).
The actual integration time is give n by
Tint Integration time [# lines] = NROF_LINES register
– INT_TIME register.
Tint Integration time [# lines] = NROF_LINES register
– INT_TIME register.
X_REG Register (10:0)
The X_REG register determines the start position of the window
in the X-direction. In this direction, there are 640 possible starting
positions (two pixels are addressed at the same time in one clock
Table 11. X Sequencer Clock G ran ularities
GRAN_X_SEQ_MSB/
LSB X-Sequencer
Clock Row Blanking
Time
[2]
00 4 x SYS_CLOCK 3.5
μ
s
01 8 x SYS_CLOCK 7
μ
s
10 16 x SYS_CLOCK 14
μ
s
11 32 x SYS_CLOCK 28
μ
s
Table 12. Multiple Slope Register Settin gs
KNEE_POINT Pixel Reset V oltage
(V)VDDR_RIGHT Knee-point
(V)
MSB/LSB ENABLE
00 0 or 1 VDDR_LEFT 0
01 1 VDDR_LEFT – 0.76 + 0.76
10 1 VDDR_LEFT – 1.52 + 1.52
11 1 VDDR_LEFT – 2.28 + 2.28
[+] Feedback
IBIS5-B-1300 CYII5FM1300AB
Document #: 38-05710 Rev. *F Page 17 of 41
cycle). If sub sampling is enabled, only the even pixels are set
as starting position (for instance: 0, 2, 4, 6, 8… 638).
YL_REG (10:0) and YR_REG (10:0)
The YL_REG and YR_REG registers determine the start position
of the window in the Y-direction. In this direction, there are 1024
possible starting positions. In rolling shutter mode the YL_REG
register sets the start position of the read (left) pointer and the
YR_REG sets the start position of the reset (right) pointer. For
both shutter types YL_REG is always equal to YR_REG.
Image Core Register (7:0)
Bits 1:0 of the IMAGE_CORE register define the test mode of the
image core. Setting 00 is the default and normal operation mode.
In case the bit is set to ‘1’, the odd (bit 1) or even (bit 0) columns
are tight to the reset level. If the internal ADC is used, bits 0 and
1 are used to create test pa ttern to test the sample moment of
the ADC. If the ADC sample moment is not chosen correctly , the
created test pattern is not black-white-black-etc. (IMAGE_CORE
register set at 1 or 2) or black-black-white-white-black-black
(IMAGE_CORE register set at 9) but grey shadings if the sensor
is saturated.
Bits 7:2 of the IMAGE_CORE register define the sub-sampling
mode in the X-direction (bits 4:2) and in the Y-direction (bits 7:5).
The sub-sampling modes and corresponding bit setting are
given in Table 5 on page 8 and Table 6 on page 8.
Amplifier Register (6:0)
1. GAIN (bits 3:0)
The gain bits determine the gain setting of the output amplifi-
er. They are only effective if UNITY = 0. The gains and corre-
sponding bit setting are given in Table 7 on page 9.
2. UNITY (bit 4)
In case UNITY = 1, the gain setting of GAIN is bypassed and
the gain amplifier is put in unity feedback.
3. DUAL_OUT (bit 5)
If DUAL_OUT = 1, the two output amplifiers are active. If
DUAL_OUT = 0, the signals from the two buses are multi-
plexed to output PXL_OUT1 which connects to ADC_IN. The
gain amplifier and output driver of the second path are put in
standby.
4. STANDBY
If ST ANDBY = 0, the com plete output amplifier is put in stand-
by. For normal use, set STANDBY to ‘1’.
DAC_RAW Register (6:0) and DAC_FINE (6:0) Register
These registers determine the black reference level at the output
of the output amplifier. Bit setting 1111111 for the DAC_RAW
register gives the highest o ffset voltage. Bit setting 0000 000 for
the DAC_RAW register gives the lowest of fset voltage. Ideally, if
the two output paths have no offset mismatch, the DAC_FINE
register is set to 1000000. Deviation from this value is used to
compensate the internal mismatch (see Output Amplifier on
page 9).
ADC Register (2:0)
1. TRISTATE_OUT (bit 0)
In case TRISTATE = 0, the ADC_D<9:0> outputs are in
tri-state mode. TRISTATE = 1 for normal operation mode.
2. GAMMA (bit 1)
If GAMMA is set to ‘1’, the ADC input to output conversion is
linear; otherwise the conversion follows a 'gamma' law (more
contrast in dark parts of the window, lower contrast in the
bright parts).
3. BIT_INV (bit 2)
If BIT_INV = 1, 0000000000 is the conversion of the lowest
possible input voltage, otherwise the bits are inverted.
Data Interfaces
Two different data interfaces are implemented. They are
selected using pins IF_MODE (pin 12) and SER_MODE (pin 6).
Parallel Interface
The parallel interface uses a 16-bit parallel input (P_DATA
(15:0)) to upload new register values. Asserting P_WRITE loads
the parallel data into the internal register of the IBIS5-B-1300
where it is decoded. (See Figure 17. P_DATA (15:12) address
bits REG_ADDR (3:0); P_DATA (11:0) data bits REG_DATA
(11:0)).
Serial 3-Wire Interface
The serial 3- wi re in terface (or serial-to-parallel Interface) uses a
serial input to shift the data in the register buffer. When the
complete data word is shifted into the register buffer the data
word is loaded into the internal register where it is decoded. (See
Sync of left
shift-register Sync of right
shift-register
Line n
T
reg_int
Last line, followed by
sync of left shift-register
T
int
Syn
c
Figure 16. Sy nchronization of the Shi ft Regis ters in Rolling Shutte r Mode
Table 13. Serial and Para llel Interface Selection
IF_MODE SER_MODE Selected interface
1 X Parallel
0 1 Serial 3 Wire
[+] Feedback
IBIS5-B-1300 CYII5FM1300AB
Document #: 38-05710 Rev. *F Page 18 of 41
Figure 17. S_DATA (15:12) address bits REG_ADDR (3:0);
S_DATA (11:0) data bits REG_DATA (11:0). When S_EN is
asserted the parallel data is loaded into the in ternal registers of
the IBIS5-B-1300. The maximum tested frequency of S_DA TA is
2.5 MHz.)
Serial 2-Wire Interface
The serial 2-wire interface is not operational in the IBIS5-B-1300
image sensor. Please use the 3-wire SPI interface for loading the
sensor registers.
Timing Diagrams
Timing Requirements
There are six control signals that operate the image sensor:
• SS_START
• SS_STOP
• Y_CLOCK
•Y_START
• X_LOAD
• SYS_CLOCK
The external system generates these control signals with
following time constraints to SYS_ CLOCK (rising edge = active
edge):
T
SETUP
>7.5 ns
T
HOLD
> 7.5 ns
It is important that these signals are free of any glitches.
Figure 18 shows a recommended schematic for generati ng the
basic signals and to avoid any timing problems.
Synchronous Shutter: Single Slope Integration
SS_START and SS_STOP must change on the falling edge of
the SYS_CLOCK (Tsetup and Thold > 7.5 ns). Make cert ain that
the pulse width of both signals is a min imum of 1 SYS_CLOCK
cycle. As long as SS_START or SS_STOP are asserted, the
sequencer stays in a suspended state. (See Figure 20.)
Figure 17. Parallel Interface Timing
FF
SYS_CLOCK_N
SYS_CLOCK
SS_START
SS_STOP
Y_CLOCK
Y_START
X_LOAD
Figure 18. Recommended Schematic for Generating
Basic Signals
Figure 19. Relativ e Timing of the 5 Sequen cer Control Signal
Figure 20. Synchronous Shutter: Single Slope Integration
[+] Feedback
IBIS5-B-1300 CYII5FM1300AB
Document #: 38-05710 Rev. *F Page 19 of 41
T
1
—Time counted by the integration timer until the value of
INT_TIME register is reached. The integration timer is clocked
by the granulated SS-sequencer clock.
T
2
—TIME_OUT signal stays high for one granulated
SS-sequencer clock period.
T
3
—There are no constrai nts for this time. Use the TIME_OUT
signal to trigger the SS_STOP pin (or use an external counter to
trigger SS_STOP); you cannot tie both signals together.
T
4
—During this time, the SS-sequencer applies the control
signals to reset the image core and start integration. This takes
four granulated SS-sequencer clock periods. The integration
time counter starts counting at the first rising edge after the falling
edge of SS_START.
T
5
—The SS-sequencer puts the image core in a readable state.
It takes two granulated SS-sequencer clock periods.
T
int
—The ’real’ integration or exposure time.
Synchronous Shutter: Pixel Readout
Basic Operation
Y_ST AR T and Y_CLOCK must change on the falling edge of the
SYS_CLOCK (Tsetup and Thold > 7.5 ns). Make certain t hat the
pulse width is a minimum of one clock cycle for Y_CLOCK and
three clock cycles for Y_ST ART. As long as Y_CLOCK is applied,
the sequencer stays in a suspended state. (See Figure 21.)
T
1
—Row blanking time: During this period, the X-sequencer
generates the control signals to sample the pixel signal and pixel
reset levels (double sampling fpn-correction), and starts the
readout of one line. The row blanking time depends on the granu-
larity of the X-sequencer clock (see Table 14).
T
2
—Pixels counted by pixel counter until the value of
NROF_PIXELS register is reached. PIXEL_VALID goes high
when the internal X_SYNC signal is generated, in other words
when the readout of the pixels is started. PIXEL_V ALID goes low
when the pixel counter reaches the value loaded in the
NROF_PIXELS register (after a complete row read out).
T
3
—LAST_LINE goes high when the line counter reaches the
value loaded in the NROF_LINES register and stays high for one
line period (until the next falling edg e of Y-CLOCK).
On Y_START the left Y-shift-register of the image core is loaded
with the YL-pointer that is loaded in to register YL_REG.
Advanced Operation:
It was observed during characterization of the IBIS5-B-1300
image sensor that there are column non-uniformities in the
image in syncronous shutter mode, when the Y-read out pointer
is still selecting a lin e d uring the g lobal re set for the next frame.
To avoid this problem, an advanced timing has been generated
for the syncronous shutter mode. Please look into application
note - F AQ for IBIS5-1300 image sensor (AN6004 - question 12)
for more informa tion. The application note discusses the cause
and corrective action for this problem.
Pixel Output
The pixel signal at the PXL_OUT1 output becomes valid after
five SYS_CLOCK cycles when the internal X_SYNC (= start of
PIXEL_VALID output or external X_LOAD pulse) pulse is
asserted. (See Figure 22.)
T
1
—Row blanking time (see Table 14).
T
2
—5 SYS_CLOCK cycles.
T
3
—Time for new X-pointer position upload in X_REG register
(see Windowing in X-direction on page 21 for more details).
Table 14. Row Blanking Time as Function of X-Sequencer
Granularity
Granularity
N
GRAN
T
1
(µs)
= 35 x N
GRAN
x T
SYS_CLOCK
GRAN_X_SEQ
MSB/LSB
x 4 140 x T
SYS_CLOCK
= 3.5 00
x 8 280 x T
SYS_CLOCK
= 7.0 01
x 16 560 x T
SYS_CLOCK
= 14.0 1 0
x 32 1120 x T
SYS_CLOCK
= 28.0 11
Figure 21. Synchron ous Shutter: Pixel Read Out
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Document #: 38-05710 Rev. *F Page 20 of 41
Synchronous Shutter: Multiple Slope Integration
Use up to four different pixel reset voltages during multiple slope
operation in synchronous shutter mode. This is done by
uploading new values to register bits
KNEEPOINT_MSB/LSB/ENABLE before a new SS_START
pulse is applied.
Set bit KNEEPOINT_ENABLE high to do a pixel reset with a
lower voltage.
Set bits KNEEPOINT_MSB/LSB/ENABLE back t o ‘0’ before the
SS_STOP pulse is applied. Every time an SS_START pulse is
applied, the integration time counter is reset.
The TIME_OUT si gnal cannot be used in multi -slope operation
to determine the location of the next SS_START or SS_STOP
pulse. External counters must be used for generating these
signals. Upload the register after time T
stable
, otherwise, the change
affects the SS-sequencer resulting in a bad pixel reset. T
stable
depends on the granularity of the SS-sequencer clock (see
Table 16).
Figure 22. Pixel Output
Figure 23. Multiple Slope Integration
Table 15. Multiple Slope Register Settings
Kneepoint
MSB/LSB Enable
Initial Setup 00 0
1st Register Upload 01 1
2nd Register Upload 10 1
3th Register Upload 11 1
4th Register Upload 00 0
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Document #: 38-05710 Rev. *F Page 21 of 41
T
upload
depends on the interface mode used to upload the
registers.
Rolling Shutter Operation
The integration of the light in the image sensor is done during
readout of the other lines.
The only difference with synchronous shutter is that the
TIME_OUT pin is used to indicate when the Y_SYNC pulse for
the right Y-shift-register (reset Y-shift register) is generated. This
loads the right Y- shift-register with the pointer loa ded in registe r
YR_REG. The Y_SYNC pulse for the left Y-shift register (read
Y-shift register) is generated with Y_START.
The INT_TIME register defines how many lines to co unt before
the Y_SYNC of the right Y-shift-register is generated, hence
defining the integration time. See also INT_TIME Register (11:0)
on page 16 for a detailed description of the rolling shutter
operation.
T
int
Integration time [# lines] = register(NROF_LINES) –
register(INT_TIME)
Note For normal operation the values of the YL_REG and
YR_REG registers are equal.
Windowin g in X-di rec ti on
An X_LOAD pulse overrides the internal X_SYNC signal, loading
a new X-pointer (stored in the X_REG register) into the
X-shift-register.
The X_LOAD pulse has to appear on the falling edge of
SYS_CLOCK and has to remain high for two SYS_CLOCK
cycles overlapping two rising edges of SYS_CLOCK. The new
X-pointer is loaded on one of the two rising edges of
SYS_CLOCK.
The available time to upload the register is T
load
; it is defined
from the previous register load to the rising edge of X_LOAD. It
depends on the settling ti me of the register and the X-decoder.
The actual time to load the register itself depends on the
interface mode that is used.
The parallel interface is the fastest.
Table 16. T
stable
for Different Granularity Settings
Granularity
N
GRAN
T
stable
(µs)
= 5 x N
GRAN
x T
SYS_CLOCK
GRAN_SS_SEQ
MSB/LSB
x 32 160 x T
SYS_CLOCK
= 4 00
x 64 320 x T
SYS_CLOCK
= 8 01
x 128 640 x T
SYS_CLOCK
= 16 10
x 256 1280 x T
SYS_CLOCK
= 32 11
Table 17 . T
upload
for Different Interface Modes
Interface Mode T
upload
(µs)
Parallel 1
Serial 3-wire 8
Figure 24. Rolling Shutter Operation
Figure 25. Windowin g in the X-Direction
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Document #: 38-05710 Rev. *F Page 22 of 41
Windowing in Y-direction
Reapply the Y_ST AR T pulse after loading a new Y-pointer value
into the YL_REG and YR_REG registers to load a new Y-pointer
into the Y-shift-register.
Every time a Y_START pulse appears, a frame calibration of the
output ampli fier occurs.
Initialization (Start-Up Behavior)
To avoid any high current consumption at start-up, apply the
SYS_CLOCK signal as soon as possible after or even before
power on of the image sensor.
After power on of the image sensor, apply SYS_RESET for a
minimum of five SYS_CLOCK periods to ensure a proper reset
of the on-chip sequencer and timing circuitry. All internal
registers are set to ‘0’ after SYS_RESET is applied.
Since all the IBIS5-B-1300 control signals are active high, apply
a low level (before SYS_RESET occurs) to these pins at start up
to avoid latch up.
Table 18. T
load
for Different Interfaces
Interface Mode T
load
(µs)
Parallel interface 1 (about 40 SYS_CLOCK cycles)
Serial 3 Wire 16 (at 2.5 MHz data rate)
Figure 26. Windowing in the Y-Direction
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IBIS5-B-1300 CYII5FM1300AB
Document #: 38-05710 Rev. *F Page 23 of 41
Pin List
The IBIS5-B-1300 image sensor is packaged in a leadless ceramic carrier (LCC package). Table 19 lists all the pins and their functions.
There are 84 pins total.
Table 19. Pin List
[3, 4, 5]
Pin Pin Name Pin Type Pin Description
1 P_DATA<8> Input Digital input. Data parallel interface.
2 P_WR Input D igital input (active high). Parallel write.
3 S_CLK Input Digital input. Clock signal of serial interface.
4 S_DATA Input Digital input/output. Data of serial interface.
5 S_EN Input D igital input (active low). Enable of serial 3-wire interface.
6 SER_MODE Input Digital input. Serial mode enable (1 = Enable serial 3-wire).
7 VDDC Suppl y Analog supply voltage. Supply voltage of the pixel core [3.3V].
8 VDDA Supply Analog supply voltage. Analog supply voltage of the image sen sor [3.3V].
9 GNDA Ground Analog ground. Analog ground of the image senso r.
10 GNDD Ground Digital ground. Digital ground of the image sensor.
11 VDDD Suppl y Digital supply voltage. Digital supply voltage of the image sensor [3.3V].
12 IF_MODE Inp ut Digital input. Interface mode (1 = parallel; 0 = serial).
13 DEC_CMD Input Analog input. Biasing of decoder stage. Connect to VDDA with R = 50 k
Ω
and decouple with
C = 100 nF to GNDA.
14 Y_START Input D igital input (active high). Start frame read out.
15 Y_CLOCK Input D igital input (active high). Line clock.
16 LAST_LINE Output Digital output. Generates a high level when the last line is read out.
17 X_LOAD Input Digital input (active high). Loads new X-position during read out.
18 SYS_CLOCK Input Digital input. System (pixel) clock (40 MHz).
19 PXL_VALID O utput Digital output. Generates high level during pixel read out.
20 SS_START Input Digital input (active high). Start synchronous shutter operation.
21 SS_STOP Input Digital input (active high). Stop synchronous shutter operation.
22 TIME_OUT Output Digital output.
Synchronous shutter: pulse when timeout reached. It is used to trigger SS_STOP; do not tie
both signals together.
Rolling shutter: pulse when seco nd Y-sync appears.
23 SYS_RESET Input Digital input (active high). Global system reset.
24 EL_BLACK Input Digital input (active high). Enables electrical black in output amplifier.
25 EOSX Output Digital output. Diagnostic end-of-scan of X-register.
26 DAC_VHIGH Input Analog reference input. Biasing of DAC for output dark level. Use this to set the output range
of DAC.
Default: Connect to VDDA with R = 0
Ω
.
27 DAC_VLO W Input Analog refere nce input. Biasing of DAC fo r output dark level. Use this to set the output range
of DAC.
Default: Connect to GND A with R = 0
Ω
.
28 PXL_OUT1 Output Analog output. Analog pixel output 1.
Notes
3. You can connect all pins with the same name together.
4. All digital input are active high (unless mentioned otherwise).
5. Tie all digital inputs that are not used to GND (inactive level).
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IBIS5-B-1300 CYII5FM1300AB
Document #: 38-05710 Rev. *F Page 24 of 41
29 PXL_OUT2 Output Analog output. Analog pixel out put 2. Leave not connected if not used.
30 AMP_CMD Input Analog input. Biasing of the output amplifier . Connect to VDDA with R = 50 k
Ω
and decouple
with C = 100 nF to GNDA.
31 COL_CMD Input Analog input. Biasing of the column amplifiers. Connect to VDDA with R = 50 k
Ω
and decouple
with C = 100 nF to GNDA.
32 PC_CMD Input Analog input. Pre-ch arge bias. Connect to VDDA wi th R = 25 k
Ω
and decouple with C = 100
nF to GNDA.
33 VDDD Su ppl y Digital supply. Digital supply voltage of the image sensor [3.3V].
34 GNDD Ground Digital ground. Digital ground of the image sensor.
35 GNDA Ground An alog ground. Analog ground of the image senso r.
36 VDDA Supply Analog supply voltage. Analog sup ply voltage of the image sensor [3.3V].
37 VDDC Su ppl y A n alog supply voltage. Supply voltage of the pixel core [3.3V].
38 P_DATA <0> Input Digital input. Data parallel interface (LSB).
39 P_DATA <1> Input Digital input. Data parallel interfac e.
40 P_DATA <2> Input Digital input. Data parallel interfac e.
41 P_DATA <3> Input Digital input. Data parallel interfac e.
42 P_DATA <4> Input Digital input. Data parallel interfac e.
43 P_DATA <5> Input Digital input. Data parallel interfac e.
44 P_DATA <6> Input Digital input. Data parallel interfac e.
45 P_DATA <7> Input Digital input. Data parallel interfac e.
46 SI2_ADDR<0> Input Digital Input. Connect to GNDD.
47 SI2_ADDR<1> Input Digital Input. Connect to GNDD.
48 SI2_ADDR<2> Input Digital Input. Connect to GNDD.
49 SI2_ADDR<3> Input Digital Input. Connect to GNDD.
50 SI2_ADDR<4> Input Digital Input. Connect to GNDD.
51 GNDAB Supply Analog supply voltage. Anti-blooming ground.
52 VDDR_RIGHT Supply Analog supply voltage. V a riable reset voltage (multiple slope operation). Decouple with 1
μ
F
to GNDA.
53 ADC_VLOW Input Analog reference input. ADC low reference voltage.Default: Connect to GNDA with
R = 1200
Ω
and decouple with C = 100 nF to GNDA.
54 ADC_GNDA Ground An alog ground. ADC analog ground .
55 ADC_VDDA Supply Analog supply voltage. ADC analog supply voltage [3.3V].
56 ADC_GNDD Ground Digital ground. ADC digital ground.
57 ADC_VDDD Supply Digital supply voltage. ADC digital supply voltage [3.3V].
58 ADC_CLOCK Input Digital input. ADC clock (40 MHz).
59 ADC_OUT<9> Output Digital output. ADC data output (MSB).
60 ADC_OUT<8> Output Digital output. ADC data output.
61 ADC_OUT<7> Output Digital output. ADC data output.
62 ADC_OUT<6> Output Digital output. ADC data output.
63 ADC_OUT<5> Output Digital output. ADC data output.
64 ADC_OUT<4> Output Digital output. ADC data output.
Table 19. Pin List
[3, 4, 5]
(continued)
Pin Pin Name Pin Type Pin Description
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Document #: 38-05710 Rev. *F Page 25 of 41
65 ADC_OUT<3> Output Digital output. ADC data output.
66 ADC_OUT<2> Output Digital output. ADC data output.
67 ADC_OUT<1> Output Digital output. ADC data output.
68 ADC_OUT<0> Output Digital output. ADC data output (LSB).
69 ADC_IN Input Analog input. ADC analog input.
70 ADC_CMD Input Analog input. Biasing of the input stage of the ADC. Connect to ADC_VDDA with R = 50 k
Ω
and decouple with C = 100 nF to ADC_GNDA.
71 ADC_VDDD Supply Digital supply voltage. ADC digital supply voltage [3.3V].
72 ADC_GNDA Ground An alog ground. ADC analog ground .
73 ADC_GNDD Ground Digital ground. ADC digital ground.
74 ADC_VDDA Supply Analog supply voltage. ADC analog supply voltage [3.3V].
75 ADC_VHIGH Input Analog refere nce input. ADC high reference volt age.Default: Connect to VDDA with
R=360
Ω
and decouple with C = 100 nF to GNDA.
76 VDDR_LEFT Supply Analog supply voltage. High reset level [4.5V].
77 VDDH Su ppl y A n alog supply voltage. High suppl y voltage for HOLD switches in the image co re [4.5V]
78 P_DATA <15> Input Digital input. Data parallel interface (MSB).
79 P_DATA <14 > Input Digital input. Data parallel interface.
80 P_DATA <13 > Input Digital input. Data parallel interface.
81 P_DATA <12 > Input Digital input. Data parallel interface.
82 P_DATA <11> Input Digital input. Data parallel interface.
83 P_DATA <10 > Input Digital input. Data parallel interface.
84 P_DATA <9> Input Digital input. Data parallel interfac e.
Table 19. Pin List
[3, 4, 5]
(continued)
Pin Pin Name Pin Type Pin Description
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IBIS5-B-1300 CYII5FM1300AB
Document #: 38-05710 Rev. *F Page 26 of 41
Specifications
General Specifications. Electro-Optical Specifications
Table 20. General Specifications
Parameter Specification Remarks
Pixel architecture 4T-pixel High fill fa ctor square
pixels (based on the high
fill factor active pixel
sensor technol ogy of
Cypress). Patents
pending.
Pixel size 6.7
μ
m x 6.7
μ
m The resolution and pixel
size results in a 2/3"
optical form at .
Resolution 1280 x 1024
Pixel rate 40 MHz Using a 40 MHz system
clock.
Shutter type • Electronic
rolling shutter
• Snapshot
shutter
• Continuous imaging.
• Triggered global
shutter with
integration and
readout separate in
time.
Full frame rate 27 frames/second Increases with ROI read
out and/or sub sampling.
Table 21. Electro-Optical Specifications
Parameter Specification Remarks
FPN (local) <0.20% RMS % of saturation
signal.
PRNU (local) <10% Peak-to-peak of signal
level.
Conversion gain 17.6 µV/electron @ output (measured).
Output signal
amplitude 1V At nominal conditions.
Saturation charge 62500 e-
Sensitivity (peak) 715V.m2/W.s
8.40 V/lux.s @ 650 nm
(85 lux = 1 W/m2).
Sensitivity (visible) 572 V.m2/W.s
3.51 V/lux.s 400-700 nm
(163 lux = 1 W/m2).
Peak QE * FF Peak
Spectral Resp. 30%0.16 A/W Average QE*FF = 22%
(visible range).
Average SR*FF = 0.1
A/W (visible range).
See spectral response
curve.
Fill factor 40% Light sensitive part of
pixel (measured).
Dark current 7.22 mV/s
410e-/s Typical value of average
dark current of the whole
pixel array (@ 21 °C).
Dark Signal Non
Uniformity 7 mV/s
400 e-/s Dark current RMS value
(@ 21 °C).
Temporal noise 40 RMS e- Measured at digital
output (in the dark).
S/N Ratio 1563:1 (64 dB) Measured at digital
output (in the dark).
Spectral sensitivity
range 400 - 1000 nm
Optical cross talk 16% To the first neighboring
pixel.
Parasitic Sensitivity 3% Averaged over spectrum
Power dissipation 175 mWatt Typical (including ADCs).
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Document #: 38-05710 Rev. *F Page 27 of 41
Spectral Response Curve
Figure 27 shows the spectral response characteristic for the IBIS5-B-1300 (CYII5SM1300AB) and the IBIS-5-BE-1300
(CYII5FM1300AB). The curve is measured direct ly on the pixels. It includes effects of non-sensitive areas in the pixel, for example,
interconnection lines. The sensor is light sensitive between 400 and 1000 nm. The peak QE * FF is 30%, approximately around 650
nm. In view of a fill factor of 40%, the QE is thus close to 75% between 500 and 700 nm. The IBIS5-BE-1300 has superior response
in the NIR region (700-900 nm). For more information about the IBIS5-B-1300, refer to IBIS5-BE-1300 (CYII5FM1300AB) on page 28.
Figure 27. Spectral response curve
QE 10%
QE 20%
QE 30%
QE 40%
0
0.025
0.05
0.075
0.1
0.125
0.15
0.175
0.2
0.225
400 500 600 700 800 900 1000
W ave l enght [nm]
S p ec res [A/ W]
CYII5SM1300AB
CYII5FM1300AB
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Document #: 38-05710 Rev. *F Page 28 of 41
Electro-voltaic Response Curve
Figure 28 shows the pixel response curve in linear response mode. This cu rve is the re lation b etween the ele ctrons de tected i n the
pixel and the output signal. The resulting voltage-electron curve is independent of any parameters (integration time, and others). The
voltage to electrons conversion gain is 17.6 µV/electron.
IBIS5-BE-1300 (CYII5FM1300AB)
The IBIS5-BE-1300 is processed on a thicker epitaxial Si layer featuring a superb sensitivity in the NIR (Near Infra Red) wavelengths
(700–900 nm). The spec tral response curves of the two IBIS5-B-130 0 image sens ors are shown in Figure 27 on page 27. As many
machine vision applications use light sources in the NIR, the IBIS5-BE-1300 sensor has a significant sensitivity advantage in the NIR.
A drawback of the thicker epitaxial layer is a slight performance decrease in MTF (Modular Transfer Function or electrical pixel to pixel
cross-talk) as indicated in the Table 22.
The resulting image sharpness is hardly affected by this decreased MTF value.
Both IBIS5-B-1300 versions are fully pin compatible and have identical ti ming and biasing
Table 22. MTF comparison
Direction Wavelength IBIS5-B-1300 IBIS5-BE-1300
Horizontal 600 0.58 0.37
Horizontal 700 0.18
Horizontal 800 0.16
Horizontal 900 0.07
Vertical 600 0.53 0.26
Vertical 700 0.16
Vertical 800 0.13
Vertical 900 0.11
0
0,2
0,4
0,6
0,8
1
1,2
0 10000 20000 30000 40000 50000 60000 70000 80000
# electrons
O utput swing [V]
Figure 28. Electro-Voltaic Response Curve
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Document #: 38-05710 Rev. *F Page 29 of 41
Features and General Specifications
Electrical Specifications
Absolute Maximum Ratings
VDD = VDDD = VDDA (VDDD is supply to digital circuit, VDDA to analog circuit).
Stresses beyo nd those liste d under the section Absolute Maximum Ratings can cause p ermanen t d amage to the device. Th ese are
stress ratings only and functional operation of the device at these or any other conditions beyond those ind icated in the operational
sections are not implied. Exposure to absolute maximum rating conditions for exten ded periods can affect device reliability.
Table 23. Features and General Specifications
Feature Specification/Description
Electronic shutter types 1. Rolling curtain shutter.
2. Synchronous (snapshot) shutter.
Windowing (ROI) Implemented as scanning of lines/columns from an uploaded position.
Sub-sampling modes: 1:2 sub-sampling.
Sub-sampling patterns:
XXOOXXOO (for Bayer pattern color filter)
OOXXOOXX (for Bayer pattern color filter)
XOXOXOXOOXOXOXOX
Identical sub-sample patterns in X- and Y-di rection.
Extended dynamic range In rolling shutter: Normal (1) or double (2) slope.
In Synchronous shutter: 1, 2, 3 or 4 slopes.
Digital output 10 bit ADC @ 40 MSamples/s.
Programmable gain range x1 to x12, in 16 steps of approx. 1.5 dB using 4-bit programming.
Programmable offset 128 steps (7 bit).
Supply voltage VDD Image core supp ly: Range from 3.0V to 4.5V
Analog supply: Nominal 3.3V
Digital: Nominal 3.3V
Logic levels 3.3 V (Digital supply).
Operational temperature range –30°C to 65°C, with degradation of dark current.
Die size (with scribe lines) 10.1 mm by 9.3 mm (x by y).
Package 84 pins LCC.
Table 24. Absolute Maximum Ratings
Parameter Description Value Unit
VDD DC supply voltage –0.5 to 4.5 V
V
IN
DC input voltage –0.5 to 3.8 V
V
OUT
DC output voltage –0.5 to 3.8 V
I
IO
DC current drain per pin; any single input or output. ± 50 mA
T
L
Lead temperature (5 seconds soldering). 350 °C
T
ST
Storag e temperature –30 to +85 °C
H Humidity (relative) 85% at 85°C
ESD ESD susceptibility 2000 V
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Document #: 38-05710 Rev. *F Page 30 of 41
Recommended Operating Conditions
All parameters are characterized for DC conditions after thermal equilibrium is established.
Always tie unused inputs to an appropriate logic level, for example, either VDD or GND.
This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. However, take normal
precautions to avoid application of any voltages higher than the maximum rated voltages to this high imp eda nce circuit.
DC Electrical Characteristics
Table 25. Recommended Operating Conditions
Parameter Description Typical
Currents Peak
Currents Min Typ Max Unit
VDDH Voltage on HOLD switches. 0.047 mA 100 mA +3.3 +4.5 +4.5 V
VDDR_LEFT Highest reset voltage. 0.050 mA 100 mA +3.3 +4.5 +4.5 V
VDDC Pixel core voltage. 0.052 mA 100 mA +2.5 +3.0 +3.3 V
VDDA Analog supply voltage of the image core. 19.265 mA N/A +3.0 +3.3 +3.6 V
VDDD Digital supply voltage of the image core. 5.265 mA N/A +3.0 +3.3 +3.6 V
IDDA_ADC Analog supply of the ADC 34.5 mA N/A N/A N/A N/A mA
IDDD_ADC Digital Supply o fthe ADC 10.5 mA N/A N/A N/A N/A mA
T
A
Commercial operating temperature. N/A N/A 0 30 60 °C
Table 26. DC Electrical Characteristics
Parameter Characteristic Condition Min Max Unit
V
IH
Input high voltage 2.1 V
V
IL
Input low voltage 0.6 V
I
IN
Input leakage current V
IN
= VDD or GND –10 +10 µA
V
OH
Output high voltage VDD = min; I
OH
= –100 uA 2.2 V
V
OL
Output low voltage VDD = min; I
OH
= 100 uA 0.5 V
I
DD
Maximum operating current System clock <= 40 MHz 40 60 mA
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Pad position and Packaging
Bare Die
The IBIS5-B-1300 image sensor has 84 pins, 21 pins on every edge. The die size from pad-edge to pad-edge (without scribe-line) is:
10156.5 µm (x) by 9297.25 µm (y). Scribe lines take about 100 to 150 µm extra on each side. Pin 1 is located in the middle of the left
side, indicated by a ‘1’ on the layout. A logo and some identification tags are on the top right of the die.
Identification Test structure
Figure 29. IBIS5-B-1300 Bare Die Dimensions (All dimen sions i n µm)
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IBIS5-B-1300 in 84-pin LCC Package
Technical Draw ing of 84-pin LCC Package (spec 001-05461-**)
Figure 30. Top View of the 84-Pin LCC Package (all dimensions in mm)
Figure 31. Side View of the 84-pin LCC Package (all dimensions in mm
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Table 27. Side View Dimensio ns
Dimension Description (Inch) (mm)
Min Typ Max Min Typ Max
A Glass (thickness) - mono 0.020 0.022 0.024 0.500 0.550 0.600
B Cavity (depth) 0.060 0.069 0.078 1.520 1.750 1.980
C Die - Si (thickness) - mono 0.029 0.740
D Bottom layer (thickness) 0.020 0.500
E Die attach-bondline (thickness) 0.001 0.002 0.004 0.030 0 .060 0.090
F Glass attach-bondline (thickness) 0.001 0.003 0.004 0.030 0.070 0.110
G Imager to lid-outer surface 0.062 1.570
H Imager to lid-inner surface 0.037 0.950
J Imager to seating plane of package 0.050 0.051 0.052 1 .2 70 1.300 1.330
Figure 32. Side View Dimensions
P
in 1
Figure 33. Bottom View of the 84-pin LCC Package (all dimensions in mm)
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Cover Glass
A D263 glass lid (which has a refraction index of 1.52) is used as a protection glass lid on top of all IBIS5-B-1300 sensors. Figure 36
shows the transmission characteristics of the D263 glass.
0
10
20
30
40
50
60
70
80
90
100
400 500 600 700 800 900
Waveleng th [nm]
Transmission [%]
Figure 36. Transmission Cha racteristics of the D263 Glass
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Handling Precautions
Handling and Soldering Conditions
Take special care when soldering image sensors with color filter
arrays (RGB color fil ters) onto a circuit board since color fil ters
are sensitive to high temperatures. Prolonged heating at
elevated temperatures can result in deterioration of the perfor-
mance of the sensor . The following recommendations are made
to ensure that sensor performance is not compromised during
end-users' assembly processes. For proper handling and
storage conditions, refer to the Cypress application note
AN52561 at www.cypress.com.
Board Assembly
Place the device onto boards in accordance with strict ESD
controls for Class 0, JESD22 Human Body Model, and Class A,
JESD22 Machine Model devices. Assembly operators must
always wear all designated and approved grounding equipment;
use grounded wrist straps at ESD protected workstations
including the ionized blowers. Use only ESD prote c ted tools.
Manual Soldering
Observe the following conditions when using a soldering iron:
Use a soldering iron with temperature control at the tip. The
soldering iron tip temperature must not exceed 350°C. Make
certain that the soldering period for each pin is less than five
seconds.
Reflow Soldering
Figure 37 shows the maximum recommended thermal profile for
a reflow soldering system. If the temperature/time profile
exceeds these recommendations, damage to the image sensor
can occur. See Figure 37 for more details.
X-ray inspection
X-ray inspection to check the solder leads of th e image sensor
is not recommended because the high energetic radiation can
permanently damage the devices or cause image artefacts.
Limited Warranty
Cypress Image Sensor Business Unit warrants that the image
sensor products to be delivered hereunder if properly used and
serviced, will conform to Seller's published specifications and will
be free from defects in material and workmanship for one (1)
year following the date of shi pment. If a de fect were to manifest
itself within 1 (one) year period from the sale date, Cypress will
either replace the product or give credit for the product.
Return Material Authorization (RMA)
Cypress packages all of its image sensor products in a clean
room environment under strict handling procedures and ships all
image sensor products in ESD-safe shipping containers.
Products returned to Cypress for failure analysis should be
handled under these same conditions and packed in its original
packing materials, or the customer may be liable for the product.
Figure 37. Reflow Sold ering Temperature Profile
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RoHS (Pb-free) Compliance
This paragraph reports the use of hazardous chemical
substances as required by the RoHS Directive (excluding
packing material).
Information on Pb-Free Soldering:
IBIS5-B-1300-M2 (serial numbers beyond 3694): the product
was tested successfully for Pb-free soldering processes, using a
reflow temperature profile with maximum 260°C, minimum 40s
at 255°C and minimum 90s at 217°C.
Note ‘Intentional conten t’ is de fined as an y material deman ding
special attention that is allowed into the product as follows:
1. A chemical composition is added into the inquired product
intentionally in order to produce an d maintain the required
performance and function of the product.
2. A chemical composition which is used inte ntionally in the
manufacturing process, that is allowed into the product.
The following case is not treated as ‘intention al content’:
1. The above material is contained as an impurity into raw ma-
terials or parts of the intended product. The impurity is defined
as a substance that cannot be removed industrially, or it is
produced using a process such as chemical composing or
reaction, and it cannot be removed tech nical ly.
T able 28. The Chemical Substances and Information About
Any Intentio nal Content
Chemical
Substance Intentional
content? Whe r e i s the intentional
content contained?
Lead NO -
Cadmium NO -
Mercury NO -
Hexavalent
Chromium NO -
PBB
(Polybrominated
biphenyls)
NO -
PBDE
(Polybrominated
diphenyl ethers)
NO -
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IBIS5-B-1300 CYII5FM1300AB
Document #: 38-05710 Rev. *F Page 39 of 41
Appendix A: IBIS5 Demo Kit
For evaluating purposes an IBIS5 de mo kit is available.
The kit consists of a high speed digital board (mother board)
along with a sensor specific rider card (analog board). The PCBs
are cased in an e asy to han dle plasti c casing a nd supp lied with
the power supply, stand and USB cables.
The Cypress Video Capture software (provided in CD with
reference schematics) is compatible with Windows-XP operating
system and allows the user to grab live images from the sensor,
store the images in different formats for analysis and test
different functional modes of the sensor
Figure 38. The IBIS5 Demo Kit
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IBIS5-B-1300 CYII5FM1300AB
Document #: 38-05710 Rev. *F Page 40 of 41
Appendix B: IBIS5-1300 Revision Overview
Notes
6. Rolling shutter mode (see also paragraph ).
Table 29. IBIS5-1300 Revision Differences
Parameter IBIS5-1300 IBIS5-A-1300 IBIS5-AE-1300 IBIS5-B-1300
Status Obsole te On Prune Cycle On Prune Cycle Producti on
QE * FF (peak) 0.13 A/W
(@ 650 nm) 0.16 A/W
(@ 650 nm) 0.21 A/W
(@ 760 nm) 0.16 A/W
(@ 650 nm)
Full well charge 120.000 e- 6 2.500 e- 62.500 e- 62.500 e-
Output signal swing 1V (unity gain)
1.8V (max.) 1.1V (unity gain)
1.8V (max) 1.1V (unity gain)
1.8V (max) 1.1V (unity gain)
1.8V (max)
Conversion gain 12
μ
V/e– 17.6
μ
V/e– 17.6
μ
V/e– 17.6
μ
V/e–
Temporal noise 85 e– 40 e– 40 e– 40 e–
S/N ratio 1412:1 / 63 dB 1563:1 / 64 dB 1563:1 / 64 dB 1563:1 / 64 dB
FPN 0.34 (% of fw) 0.15 (% of fw) 0.15 (% of fw) 0.15 (% of fw)
PRNU (at Qsat/2) < 10% (p-p) < 10% (p-p) < 10% (p-p) < 10% (p-p)
Dark current (average) 66 mV/s 7.22 mV/s 7.22 mV/s 7.22 mV/s
Pixel output rate 40 MHz 40 MHz 40 MHz 40 MHz
Frame rate 27.5 fps
[6]
27.5 fps
[6]
27.5 fps
[6]
27.5 fps
[6]
Interface Serial 3-wire
Parallel Serial 3-wire
Parallel Serial 3-wire
Parallel Serial 3-wire
Parallel
Extended dynamic range Double/multiple slope Double/multiple slope Double/multiple slope Do uble /mul tiple slope
Timing See Timing Diagrams
on page 18 Identical Identical Identical
Biasing: DEC_CMD
DAC_VHIGH
DAC_VLOW
AMP_CMD
COL_CMD
PC_CMD
ADC_CMD
ADC_VHIGH
ADC_VLOW
50 k
Ω
5 k
Ω
10 k
Ω
50 k
Ω
50 k
Ω
25 k
Ω
50 k
Ω
130
Ω
240
Ω
50 k
Ω
0
Ω
0
Ω
50 k
Ω
50 k
Ω
25 k
Ω
50 k
Ω
90
Ω
360
Ω
50 k
Ω
0
Ω
0
Ω
50 k
Ω
50 k
Ω
25 k
Ω
50 k
Ω
90
Ω
360
Ω
50 k
Ω
0
Ω
0
Ω
50 k
Ω
50 k
Ω
25 k
Ω
50 k
Ω
360
Ω
1200
Ω
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Document #: 38-05710 Rev. *F Revised March 29, 2010 Page 41 of 41
All products and company names mentioned in this document may be the trademarks o f t heir respect i ve holders.
IBIS5-B-1300 CYII5FM1300AB
© Cypress Semicondu ctor Corpor ation, 2005-201 0. The informati on cont ained herein is subject to change witho ut notice. Cypr ess Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products a re not war ran ted no r inte nd ed to be us ed fo r
medical, life supp or t, l if e savi n g, cr it ical control or safety ap pl i cations, unless pur suan t to an express written ag re em en t w ith Cypress. Furthermor e, Cyp re ss does not author i ze i t s pr o ducts for use as
critical components in life-support systems where a malfunction or failur e may reasonably be expected to result in significant injury to the user. The inclusion of Cyp ress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and interna tional trea ty provisi ons. Cyp ress he reby gra nt s to l icense e a per sonal , non-excl usive , no n-tran sferab le lic ense to cop y, use, modify, create derivative wor ks of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of lice nsee product to be used on ly in conjunction wi th a Cypress
integrated circui t as specified in the applicab le agreement. Any r eproduction, m odification, transl ation, compilatio n, or represent ation of this S ource Code except a s specified abo ve is prohibit ed without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTA BILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liabil ity ar ising ou t of the app licati on or us e of an y product or circ uit de scrib ed herei n. Cy press does n ot auth orize it s product s for use a s critical componen ts in life-suppo rt systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document History Page
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress offers standard and customized CMOS image sensors for consumer as well as industrial and professional applications.
Consumer applications include solutions for fast growing high speed machine vision, motion monitoring, medi cal imaging, intelligent
traff ic systems, security, and barcode applications. Cypress's customized CMOS image sensors are charac terized by very high pixel
counts, large area, very high frame rates, large dynamic range, and high sensitivity.
Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives, and distributors. For more
information on Image sensors, please contact imagesensors@cypress.com.
Document Title: IBIS5-B-1300 CYII5FM1300AB
1.3 MP CMOS Image Sensor
Document Number: 38-05710
Rev. ECN No. Orig. of
Change Submission
Date Description of Change
** 310213 FVK See ECN New Data Sheet
*A 649064 FPW See ECN Ordering information update and ne w layout.
Implemented the new template. Moved figure captions to the top of the
figures and moved notes to the bottom of the page per new template.
V erified all cross-referencing. Moved the specifications towards the back.
Corrected one variable on the Master pages. Sp elle d checked.
*B 1162847 FPW/ARI See ECN BGA package information removed. Implemented new template. Edited for
template compliance.
*C 1417584 FPW See ECN Die placement drawing up date
*D 2765859 NVEA 09/18/09 Updated Ordering Information table
*E 2786518 SHEA 10/14/09 Minor ECN to correct copyright year
*F 2903130 NVEA 04/01/10 Removed reference to I2C, IBIS5-A. Updated Figure 23, Added dynamic
currents to Tab le 26. Upda ted Appendix A. Added hand ling and limited
warranty statement.
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