PF48F3000P0ZTQ0 - Intel - Product.Network

Order Number: 306666, Revision: 001

April 2005

Intel St r ataF las h® Embedded Memory

(P30)

1-Gbit P30 Family

Datasheet

Product Features

The Intel StrataFlash® Embedded Memory (P30) product is the latest generation of Intel

StrataFlash® memory devices. Offered in 64-Mbit up through 1-Gbit densities, the P30 device

brings reliable, two-bit-per-cell storage technology to the embedded flash market segment.

Benefits include more density in less space, high-speed interface, lowest cost-per-bit NOR

device, and support for code and data storage. Features include high-performance synchronous-

burst read mode, fast asynchronous access times, low power, flexible security options, and three

industry standard package choices.

The P30 product family is manufactured using Intel® 130 nm ETOX™ VIII process technology.

■High performance

— 85/88 ns initial access

— 40 MHz with zero wait states, 20 ns clock-to-

data outp ut synchronous-burst read mode

— 25 ns asyn chronous-page read mode

— 4-, 8-, 16- , an d continuous-word burst mo de

— Buffered En hanced Factory Programm ing

(BEFP ) at 5 µs/by te (Typ)

— 1.8 V buffered programming at 7 µs/byte (Typ)

■Architecture

— Multi- Level Cell Techn ology: High est Density

at Lowes t Cost

— Asymm etrically-blocked archit ecture

— Four 32 -KByte parameter block s: top or

bo ttom confi guratio n

— 128-KByte main blocks

■Voltage and Power

—V

CC (c ore) voltage: 1.7 V – 2.0 V

—V

CCQ (I/O) voltage: 1. 7 V – 3.6 V

— Standby cur rent: 55 µA (Typ) for 256-Mbit

— 4-Word sy nchronous read current:

13 mA (Typ) at 40 MHz

■Quality and Reliability

— Operat ing temperature: –40 °C to +85 °C

• 1-Gbit in SCSP is –30 °C to +85 °C

— Minimum 100,000 erase cycles per block

— ETOX™ VI II process technology (130 nm)

■Security

— One-Time Programmable Registers:

• 64 unique factory device identifier bits

• 64 user-programmable OTP bits

• Additional 2048 user-programmable OTP bits

— S electable OTP Space in Main Array:

• 4x32KB parameter blocks + 3x128KB main

bloc ks (top or bottom configurati on)

— A bsolute write protection: VPP = VSS

— P ower-transition erase /program lockout

— I ndividual zero-latency blo ck locking

— Individual block lock-down

■Software

— 2 0 µs (Typ) program suspend

— 2 0 µs (Typ) erase susp end

—Intel

® Flash D ata Integrator optim ized

— B asic Command Set and Extended Co mmand

Set co mpatible

— C ommon Flash Interface cap able

■Dens ity and Packaging

— 6 4/128/256-Mbit densities in 56 -Lead TSOP

package

— 6 4/128/256/512-Mbit den sities in 64-Ball

Intel® Easy BGA package

— 6 4/128/256/512-Mbit and 1-Gbit densities in

Intel® QUAD+ SCS P

— 1 6-bit wide data bus

April 2005 Intel StrataFlash® Embedded Memory (P30) Datasheet

2 Order Number: 306666, Revision: 001

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY

ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN

INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS

ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCL UDING LIABILITY OR WARRANTIES

RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER

INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

This document contains information on products in the design phase of development. The information here is subject to change without notice. Do not

finalize a design with this information.

S t rat aFlash® Embedded Memory (P30) Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing

your product order.

Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-

548-4725 or by visiting Intel's website at http://www.intel.com.

* Other names and brands may be claimed as the property of others.

1-Gbit P30 Family

Datasheet Intel StrataFlash® Embedded Memory (P30) April 2005

Order Number: 306666, Revision: 001 3

Contents

1.0 Introduction ...............................................................................................................................7

1.1 Nomenclature .......................................................................................................................7

1.2 Acronyms..............................................................................................................................7

1.3 Conventions..........................................................................................................................8

2.0 Functional Overview..............................................................................................................9

3.0 Package Information............................................................................................................10

3.1 56-Lead TSOP Package.....................................................................................................10

3.2 64-Ball Easy BGA Package................................................................................................12

3.3 QUAD+ SCSP Packages....................................................................................................13

4.0 Ballout and Signal Descriptions......................................................................................17

4.1 Signal Ballout......................................................................................................................17

4.2 Signal Descriptions.............................................................................................................20

4.3 SCSP Configurations............... ........... ........................................... .......... ........... ........... .....22

4.4 Memory Maps.....................................................................................................................24

5.0 Maximum Ratings and Operat ing Cond itions ...........................................................29

5.1 Absolute Maximum Ratings................................................................................................29

5.2 Operating Conditions..........................................................................................................30

6.0 Electrical Specifications.....................................................................................................31

6.1 DC Current Characteristics.................................................................................................31

6.2 DC Voltage Characteristics.................................................................................................32

7.0 AC Characteristics................................................................................................................33

7.1 AC Test Conditions.................. ........... ........... .....................................................................33

7.2 Capacitance........................................................................................................................34

7.3 AC Read Specifications. .......... ...........................................................................................35

7.4 AC Write Specifications........... ........... ........... .....................................................................41

7.5 Program and Erase Characteristics....................................................................................45

8.0 Power and Reset Specifications .....................................................................................46

8.1 Power Up and Down...........................................................................................................46

8.2 Reset Specifications...........................................................................................................46

8.3 Power Supply Decoupling...................................................................................................47

9.0 Device Operations.................................................................................................................48

9.1 Bus Operations...................................................................................................................48

9.1.1 Reads ....................................................................................................................48

9.1.2 Writes.....................................................................................................................49

9.1.3 Output Disable.......................................................................................................49

9.1.4 Standby..................................................................................................................49

9.1.5 Reset .....................................................................................................................49

9.2 Device Commands .............................................................................................................50

9.3 Command Definitions .........................................................................................................51

1-Gbit P30 Family

April 2005 Intel StrataFlash® Embedded Memory (P30) Datasheet

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10.0 Read Operations....................................................................................................................53

10.1 Asynchronous Page-Mode Read........................................................................................53

10.2 Synchronous Burst-Mode Read..........................................................................................53

10.3 Read Configuration Register ...... ........................................... ........... .......... ........................54

10.3.1 Read Mode.................... ........... ........... ..................................................................55

10.3.2 Latency Count........................................................................................................55

10.3.3 WAIT Polarity.........................................................................................................57

10.3.4 Data Hold...............................................................................................................58

10.3.5 WAIT Delay............................................................................................................59

10.3.6 Burst Sequence.....................................................................................................59

10.3.7 Clock Edge ............................................................................................................59

10.3.8 Burst Wrap.............................................................................................................59

10.3.9 Burst Length ..........................................................................................................60

11.0 Programming Operations ..................................................................................................61

11.1 Word Programming.............................................................................................................61

11.1.1 Factory Word Programming...................................................................................62

11.2 Buffered Programming........................................................................................................62

11.3 Buffered Enhanced Factory Programming .........................................................................63

11.3.1 BEFP Requirements and Considerations..............................................................64

11.3.2 BEFP Setup Phase................................................................................................64

11.3.3 BEFP Program/Verify Phase.................................................................................64

11.3.4 BEFP Exit Phase...................................................................................................65

11.4 Program Suspend.................................................................. ........... .......... ........................65

11.5 Program Resume........................ ..................................................................................... ...66

11.6 Program Protection................................ ........... .......... ........................................................66

12.0 Erase Operations...................................................................................................................67

12.1 Block Erase.........................................................................................................................67

12.2 Erase Suspend...................................................................................................................67

12.3 Erase Resume....................................................................................................................68

12.4 Erase Protection.................................................................................................................68

13.0 Security Modes.......................................................................................................................69

13.1 Block Locking......................................................................................................................69

13.1.1 Lock Block .............................................................................................................69

13.1.2 Unlock Block..........................................................................................................69

13.1.3 Lock-Down Block...................................................................................................69

13.1.4 Block Lock Status..................................................................................................70

13.1.5 Block Locking During Suspend..............................................................................70

13.2 Selectable One-Time Programmable Blocks......................................................................71

13.3 Protection Registers ......... ..................................................................................... .............72

13.3.1 Reading the Protection Registers..........................................................................73

13.3.2 Programming the Protection Registers..................................................................73

13.3.3 Locking the Protection Registers...........................................................................74

14.0 Special Read States .............................................................................................................75

14.1 Read Status Register.................. ........... .............................................................................75

14.1.1 Clear Status Register.............................................................................................76

14.2 Read Device Identifier ...... .......... ........... .............................................................................76

1-Gbit P30 Family

Datasheet Intel StrataFlash® Embedded Memory (P30) April 2005

Order Number: 306666, Revision: 001 5

14.3 CFI Query...........................................................................................................................77

Appendix A Write State Machine..........................................................................................78

Appendix B Flowcharts............................................................................................................85

Appendix C Common Fl ash Interface ................................................................................93

Appendix D Additional Information...................................................................................100

Appendix E Ordering Information for Discrete Products ........................................101

Appendix F Ordering Information for SCSP Products..............................................102

1-Gbit P30 Family

April 2005 Intel StrataFlash® Embedded Memory (P30) Datasheet

6 Order Number: 306666, Revision: 001

Revision History

Revision Date Revision Desc ription

April 2005 -001 Initial Release

1-Gbit P30 Family

Datasheet Intel StrataFlash® Embedded Memory (P30) April 2005

Order Number: 306666, Revision: 001 7

1.0 Introduction

This document provides information about the Intel St rataFlash® Embedded Memory (P30) device

and describes its features, operation, and specifications.

1.1 Nomenclature

1.2 Acronyms

1.8 V : VCC (core) voltage range of 1.7 V – 2.0 V

3.0 V : VCCQ (I/O) voltage range of 1.7 V – 3.6 V

9.0 V : VPP voltage range of 8.5 V – 9.5 V

Block : A group of bits, bytes,1-Gbit P30 Family or words within the

flash memory array that erase simultaneously when the Erase

command is issued to the device. The 1-Gbit P30 Family has

two block sizes: 32-KByte and 128-KByte.

Main block : An array block that is usually used to store code and/or data.

Main blocks are larger than parameter blocks.

Parameter block : An array block that is usually used to store frequently changing

data or small system parameters that traditionally would be

stored in EEPROM.

Top parameter device : A device with its parameter blocks located at the highest

physical address of its memory map.

Bottom parameter device : A device with its parameter blocks located at the lowest

physical address of its memory map.

BEFP : Buffer Enhanced Factory Programming

CUI : Command User Interface

MLC : Multi-Level Cell

OTP : One-Time Programmable

PLR : Protection Lock Register

PR : Protection Register

RCR : Read Configuration Register

1-Gbit P30 Family

April 2005 Intel StrataFlash® Embedded Memory (P30) Datasheet

8 Order Number: 306666, Revision: 001

1.3 Conventions

RFU : Reserved for Future Use

SR : Status Register

WSM : Write State Machine

VCC : Signal or voltage connection

VCC :Signal or voltage level

0x : Hexadecima l number prefix

0b : Binary number prefix

SR[4] : Denotes an individual register bit.

A[15:0] : Denotes a group of similarly named signals, such as address

or data bus.

A5 : Denotes one element of a signal group membership, such as

an individual address bit.

Bit : Binary unit

Byte : Eight bits

Word : Two bytes, or sixteen bits

Kbit : 1024 bits

KByte : 1024 bytes

KWord : 1024 words

Mbit : 1,048,576 bits

MByte : 1,048,576 bytes

MWord : 1,048,576 words

1-Gbit P30 Family

Datasheet Intel StrataFlash® Embedded Memory (P30) April 2005

Order Number: 306666, Revision: 001 9

2.0 Functional Overview

This section provides an overview of the features and capabilities of the 1-Gbit P30 Family device.

The P30 family provides density upgrades from 64-Mbit through 1-Gbit. This family of devices

provides high performance at low voltage on a 16-bit data bus. Individually erasable memory

blocks are sized for optimum code and data storage.

Upon initial power up or return from reset, the device defaults to asynchronous page-mode read.

Configuring the Read Configuration Register enables synchronous burst-mode reads. In

synchronous burst mode, output data is synchronized with a user-supplied clock signal. A WAIT

signal provides an easy CPU-to-flash memory synchronization.

In addition to the enhanced architecture and interface, the device incorporates technology that

enables fast factory program and erase operations. Designed for low-voltage systems, the 1-Gbit

P30 Family supports read operations with VCC at 1.8 V, and erase and program operations with

VPP at 1.8 V or 9.0 V. Buffered Enhanced Factory Programming (BEFP) provides the fastest flash

array programming performance with VPP at 9.0 V, which increases factory throughput. With VPP

at 1.8 V, VCC and VPP can be tied together for a simple, ultra low power design. In addition to

voltage flexibility, a dedicated VPP connection provides complete data protection when VPP ≤

VPPLK.

A Command User Interface (CUI) is the interface between the system processor and all internal

operations of the device. An internal Write State Machine (WSM) automatically executes the

algorithms and timings necessary for block erase and program. A Status Register indicates erase or

program completion and any errors that may have occurred.

An industry-standard command sequence invokes program and erase automation. Each erase

operation erases one block. The Erase Suspend feature allows system software to pause an erase

cycle to read or program data in another block. Program Suspend allows system software to pause

programming to read other locations. Data is programmed in word increments (16 bits).

The 1-Gbit P30 Family’s protection register allows unique flash device identification that can be

used to increase system security. The individual Block Lock feature provides zero-latency block

locking and unlocking. In addition, the P30 device also has four pre-defined spaces in the main

array that can be configured as One-Time Programmable (OTP).

1-Gbit P30 Family

April 2005 Intel StrataFlash® Embedded Memory (P30) Datasheet

10 Order Number: 306666, Revision: 001

3.0 Package Information

3.1 56-Lead TSOP Package

Figure 1. TSOP Mechanical Specifications

Detail A

Pin 1

Detail B

See Detail A

See Detail B

Seating

Plane

See Note 2

[231369-90]

See Notes 1 and 3

Table 1. TSOP Package Dimensions (Sheet 1 of 2)

Produc t Informat io n Sym Millimeters Inches

Min Nom Max Min Nom Max

Package Height A - - 1.200 - - 0.047

Standoff A10.050 - - 0.002 - -

Package Body Thickness A20.965 0.995 1.025 0.038 0.039 0.040

Lead Width b 0.100 0.150 0.200 0.004 0.006 0.008

Lead Thickness c 0.100 0.150 0.200 0.004 0.006 0.008

Package Body Length D118.200 18.400 18.600 0.717 0.724 0.732

Package Body Width E 13.800 14.000 14.200 0.543 0.551 0.559

Lead Pitch e - 0.500 - - 0.0197 -

1-Gbit P30 Family

Datasheet Intel StrataFlash® Embedded Memory (P30) April 2005

Order Number: 306666, Revision: 001 11

Terminal Dimension D 19.800 20.00 20.200 0.780 0.787 0.795

Lead Tip Lengt h L 0.500 0.600 0.700 0.020 0.024 0.028

Lead Count N - 56 - - 56 -

Lead Tip Angle ∅0° 3° 5° 0° 3° 5°

Seating Plane Coplanarity Y - - 0.100 - - 0.004

Lead to Package Offset Z 0. 150 0.250 0. 350 0. 006 0. 010 0.014

Table 1. TSOP Package Dimensions (Sheet 2 of 2)

Product Infor m at ion Sym Millimeters Inches

Min Nom Max Min Nom Max

1-Gbit P30 Family

April 2005 Intel StrataFlash® Embedded Memory (P30) Datasheet

12 Order Number: 306666, Revision: 001

3.2 64-Ball Easy BGA Package

Note: Daisy Chain Evaluati on Unit information is at I ntel® Fla s h Memory Packagin g Technolog y http://developer.intel.com/

design/flash/packtech.

Figure 2. Easy BGA Mechanical Specifications

Table 2. Easy BGA Package Dimensions

Produc t Inf or ma tion Symbol Millimeters Inches Notes

Min Nom Max Min Nom Max

Package Height (64/128/256-Mbit) A - - 1.200 - - 0.0472

Package Height (512-Mbit) A - - 1.300 - - 0.0512

Ball Height (64/128/256-Mbit) A1 0.250 - - 0.0098 - -

Ball Height (512-Mbit) A1 0.240 - - 0.0094 - -

Package Body Thickness (64/128/256-Mbit) A2 - 0.780 - - 0.0307 -

Package Body Thickness (512-Mbit) A2 - 0.910 - - 0.0358 -

Ball (Lead) Width b 0.330 0.430 0.530 0.0130 0.0169 0.0209

Package Body Width D 9.900 10.000 10.100 0.3898 0.3937 0.3976 1

Package Body Length E 12.900 13.000 13.100 0.5079 0.5118 0.5157 1

Pitch [e] - 1.000 - - 0.0394 -

Ball (Lead) Count N - 64 - - 64 -

Seating Plane Coplanarity Y - - 0.100 - - 0.0039

Corner to Ball A1 Distance Along D S1 1.400 1.500 1.600 0.0551 0.0591 0.0630 1

Corner to Ball A1 Distance Along E S2 2.900 3.000 3.100 0.1142 0.1181 0.1220 1

Seating

Plane

To p V i ew - B all si de down Bottom View - Ball Side Up

Ball A1

Corner

Not e: Drawing not to scal e

87654321

Ball A1

Corner

1-Gbit P30 Family

Datasheet Intel StrataFlash® Embedded Memory (P30) April 2005

Order Number: 306666, Revision: 001 13

3.3 QUAD+ SCSP Packages

Figure 3. 64/128-Mbit, 88-ball (80 active) QUAD+ SCSP Specifications (8x10x1.2 mm)

Millimeters Inches

Dimensions Symbol Min Nom Max Min Nom Max

Package Height A - - 1.200 - - 0.0472

Ball Height A

0.200 - - 0.0079 - -

Packa ge Body Thickness A

- 0.860 - - 0.0339 -

Ball (L ead) Width b 0.325 0.375 0.425 0.0128 0.0148 0.0167

Package Body Width D 9.900 10 .000 10.100 0.3898 0.3937 0.3976

Package Body Length E 7.900 8.000 8.100 0.3110 0.3150 0.3189

Pitch e - 0.800 - - 0.0315 -

B all (Lead) Count N - 88 - - 88 -

Seating Plane Coplanarity Y - - 0.100 - - 0.0039

Cor ner t o Ball A1 Dista nc e Along E S

1.100 1.200 1.300 0.0433 0.0472 0.0512

Cor ner t o Ball A1 Dista nc e Along D S

0.500 0.600 0.700 0.0197 0.0236 0.0276

T op View - Ball

Down Botto m View - Ball U p

D raw ing not to s cale.

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A1 Index

Mark

1-Gbit P30 Family

April 2005 Intel StrataFlash® Embedded Memory (P30) Datasheet

14 Order Number: 306666, Revision: 001

Figure 4. 256-Mbit, 88-ball (80 ac tive) QUAD+ SCSP Specifications (8x11x1.0 mm)

Millimeters Inches

Dimensions Symbol Min Nom Max Min Nom Max

Package Height A - - 1.0 00 - - 0.0 394

Ball Height A1 0.117 - - 0.0046 - -

Package Body Thickness A2 - 0.740 - - 0.0291 -

Ball (Lead) Width b 0.300 0.350 0.400 0.0118 0.0138 0.0157

Package Body Length D 10.900 11.00 11.100 0.4291 0.4331 0.4370

Package Body Width E 7.900 8.00 8.100 0.3110 0.3150 0.3189

Pitch e - 0.80 - - 0.0 31 5 -

Ball (Lead) Count N - 88 - - 88 -

Seati ng Plane Coplanarity Y - - 0.100 - - 0.0 039

Corner to B all A1 Di stance Along E S1 1.10 0 1.200 1.30 0 0.0 43 3 0 .0 47 2 0.0512

Corner to B all A1 Di stance Along D S2 1.000 1.100 1.20 0 0.0 39 4 0 .0 43 3 0.0472

Top View - Ball Dow n Bot tom View - Ball Up

Draw in g not t o s c ale.

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A1 Index

Mark

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Note: Dimensions A1, A2, and b are preliminary

1-Gbit P30 Family

Datasheet Intel StrataFlash® Embedded Memory (P30) April 2005

Order Number: 306666, Revision: 001 15

Figure 5. 512-Mbit, 88-ball (80 active) QUAD+ SCSP Specifications (8x11x1.2 mm)

Millimeters Inches

Dimensions Symbol Min Nom Max Min Nom Max

Package Height A - - 1.200 - - 0.0472

B all Height A1 0.200 - - 0.0079 - -

Package Body Thickness A2 - 0.860 - - 0.0339 -

B all (Lead) Width b 0.32 5 0.375 0.425 0.0128 0.0148 0.0167

Package Body Length D 10.900 1 1.000 11.100 0.4291 0.4331 0.4370

Package Body Width E 7.900 8.000 8.100 0.3110 0.3150 0.3189

Pitch e - 0.80 0 - - 0.031 5 -

Ball (Lea d) Count N - 8 8 - - 8 8 -

Seati ng Plane Coplanarity Y - - 0.100 - - 0.0039

Cor n e r to Ball A1 Distanc e Along E S 1 1.100 1 .200 1. 30 0 0. 0433 0. 04 72 0. 05 12

Cor n e r to Ball A1 Distanc e Along D S 2 1.000 1 .100 1. 20 0 0. 0394 0. 04 33 0. 04 72

T op View - Ball Down Bottom View - Ball Up

D raw ing not t o s c ale .

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A1 Index

Mark

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1-Gbit P30 Family

April 2005 Intel StrataFlash® Embedded Memory (P30) Datasheet

16 Order Number: 306666, Revision: 001

Figure 6. 1- Gbit, 88-ball (80 active) QUAD+ SCSP Specifications (11x11x1.4 mm)

Millimeters Inches

Dimensions Symbol Min Nom Max Min Nom Max

Package Height A - - 1.400 - - 0.0551

Ball Height A1 0.200 - - 0.0079 - -

Package Body Thickness A2 - 1.070 - - 0.0421 -

Ball (Lead) Width b 0.325 0.375 0.425 0.0128 0.0148 0.0167

Package Body Length D 10.900 11.000 11.100 0.4291 0.4331 0.4370

Package Body Width E 10.900 11.000 11.100 0.4291 0.4331 0.4370

Pitch e - 0.800 - - 0.0315 -

Ball (Lead) Count N - 88 - - 88 -

Seating Plane Coplanarity Y - - 0.100 - - 0.0039

Corner to Ball A1 Distance Along E S1 2.600 2.700 2.800 0.1024 0.1063 0.1102

Corner to Ball A1 Distance Along D S2 1.000 1.100 1.200 0.0394 0.0433 0.0472

Top View - Ball Dow n Botto m View - Ba ll U p

Drawing not to scale.

2345678

A1 Index

Mark 12345678

1-Gbit P30 Family

Datasheet Intel StrataFlash® Embedded Memory (P30) April 2005

Order Number: 306666, Revision: 001 17

4.0 Ballout and Signal Descriptions

4.1 Signal Ballout

Notes:

1. A1 is the least significant address bit.

2. A23 is valid for 128-Mbit densities and above; otherwise, it is a no connect (NC).

3. A24 is valid for 256-Mbit densities and above; otherwise, it is a no connect (NC).

Figure 7. 56-Lead TSOP Pinout (64/128/256-Mbit)

Int el StrataFlash®

Embedded Memory (P30)

56-Lead TSOP Pinout

14 mm x 20 mm

Top View

A14

A13

A12

A10

A11

A23

A21

VSS

A22

VCC

WP#

A20

WE#

A19

A18

RFU

VSS

A24

WAIT

DQ15

DQ7

A17

DQ14

DQ13

DQ5

DQ6

DQ12

ADV#

CLK

DQ4

RST#

A16

DQ3

VPP

DQ10

VCCQ

DQ9

DQ2

DQ1

DQ0

VCC

DQ8

OE#

CE#

VSS

A15

DQ11

1-Gbit P30 Family

April 2005 Intel StrataFlash® Embedded Memory (P30) Datasheet

18 Order Number: 306666, Revision: 001

Notes:

1. A1 is the least significant address bit.

2. A23 is valid for 128-Mbit densities and above ; otherwise, it is a no connect (NC).

3. A24 is valid for 256-Mbit densities and above ; otherwise, it is a no connect (NC).

4. A25 is valid for 512-Mbi t densities; otherwise, it is a no connect (NC) .

Figure 8. 64-Ball Easy BGA Ballout (64/128/256/512-Mbit)

234567

Easy BGA

Top Vie w - Bal l side down Easy BGA

Botto m Vi ew- Ball side up

8234

A2 VSS A9 A14CE# A19 RFUA25

RFU VSS VCC DQ13VSS DQ7 A24VSS

A3 A7 A10 A15A12 A20 A21WP#

A4 A5 A11 VCCQRST# A16 A17VCCQ

RFUDQ8 DQ1 DQ9 DQ4DQ3 DQ15CLK

RFU OE#DQ0 DQ10 DQ12DQ11 WAITADV#

WE#A23 RFU DQ2 DQ5VCCQ DQ14DQ6

A1 A6 A8 A13VPP A18 A22VCC

A23

A4A5A11VCCQ RST#A16A17 VCCQ

A1A6A8A13 VPPA18A22 VCC

A3A7A10A15 A12A20A21 WP#

RFU DQ8DQ1DQ9DQ4 DQ3DQ15 CLK

RFUOE# DQ0DQ10DQ12 DQ11WAIT ADV#

WE# RFUDQ2DQ5 VCCQDQ14 DQ6

A2VSSA9A14 CE#A19RFU A25

RFUVSSVCCDQ13 VSSDQ7A24 VSS

1-Gbit P30 Family

Datasheet Intel StrataFlash® Embedded Memory (P30) April 2005

Order Number: 306666, Revision: 001 19

Figure 9. 88-Ball (80-Active Ball) QUAD+ SCSP Ballout

Pin 1 12345678

ADU DU Depop Depop Depop Depop DU DU A

BA4 A18 A19 VSS VCC VCC A21 A11 B

CA5 RFUA23VSSRFUCLKA22A12 C

DA3 A17 A24 VPP RFU RFU A9 A13 D

EA2 A7 RFU WP# ADV# A20 A10 A15 E

FA1 A6 RFU RST# WE# A8 A14 A16 F

GA0 DQ8 DQ2 DQ10 DQ5 DQ13 WAIT F2-CE# G

HRFU DQ0 DQ1 DQ3 DQ12 DQ14 DQ7 F2-OE# H

JRFU F1-OE# DQ9 DQ11 DQ4 DQ6 DQ15 VCCQ J

KF1-CE# RFU RFU RFU RFU VCC VCCQ RFU K

LVSS VSS VCCQ VCC VSS VSS VSS VSS L

MDU DU Depop Depop Depop Depop DU DU M

12345678

1-Gbit P30 Family

April 2005 Intel StrataFlash® Embedded Memory (P30) Datasheet

20 Order Number: 306666, Revision: 001

4.2 Signal Descriptions

This section has signal descriptions for the various P30 packages.

Table 3. T SOP and Easy BGA Signal Descriptions (Sheet 1 of 2)

Symbol Typ e Nam e an d Fu nc tio n

A[MAX:1] Input ADDRESS INPUTS: D evice address inputs. 64-Mbit: A[22:1]; 128-Mbit: A[23:1]; 256-Mbit: A[24:1];

512 -M bi t: A[ 25 :1 ].

See Table 5 on page 22 and Figure 10 on page 23 for 512-Mbit addressing.

DQ[15:0] Input/

Output

DATA INPUT/O UTPUTS : Input s data and commands during write cycles; outputs data during

memory, Status Register, Protection Register, and Read Configuration Register read s. Data balls

float when t he CE# or OE# ar e deasserted. Data is internally latched during writes.

ADV# Input

ADDRESS VALID: Active low input. Dur ing synchronous read operations, ad dresses are latched on

the rising edge of ADV #, or on the next valid CLK edge with ADV# low, whichever occurs firs t.

In asynchronous mode, the addr ess is latched when ADV# going high or continuou sly flows through

if ADV # is he ld low.

WARNING: Designs not using ADV# must tie it to VSS to allow addresses to flow through.

CE# Input

FLASH CHIP ENABL E: Act ive low input. CE# low sel ects the associated flash memory die. When

asser ted, flash internal control logic, input buffer s , decoders, and sense amplifiers are act ive. When

deasserted, the associated flash die is deselecte d, power is reduced to standby lev els, data and

WAIT outputs are placed in high-Z state.

WARNING: All chip enables must be high when device is not in use.

CLK Input

CLOCK: Synchronizes the device with the sys tem’s bus frequency in synchronous-read mode.

During synchronous read operations, addresses are latched on the rising edge of ADV#, or on the

next valid CLK edge with ADV# low, whichever occurs first.

WARNING: Designs not using CLK for synchronous read mode must tie it to VCCQ or VSS.

OE# Input OUTPUT ENABLE: Active low input. OE# low enables the device’s output data buffers during read

cycles. OE# high plac es the data outputs and WAIT in High-Z.

RST# Input RESET: Active low input. RST# resets internal automation and inhibits write operations. This

pro v ides data protection during pow er transitions. RS T# high enables normal operation. Exit from

reset places the device in asynchronous read array mode.

WAIT Output

WAIT: Indicates data valid in synchr onous array or non-array burst reads. Read Configuration

VOH when CE# and OE# are VIL. WAIT is hi gh-Z if CE# or OE# i s VIH.

• In synchronous array or no n-array read modes, W AIT indicates invalid data when asser ted and

valid data when deasserted.

• I n as y n chro no u s pag e mo de , an d all write mod e s, WAIT is dea s se rt e d .

WE# Input WRITE ENABLE: Active low input. WE# controls writes to the device. Address and data are lat c hed

on the risi ng edge o f WE#.

WP# Input WRI TE PROTECT: Active low input. WP# low ena bles the lock-down mechanism. Blocks in lock-

down cannot be unlocked with the Unlock command. WP# high overrides the lock-down function

enabling blocks to be erased or programmed using software commands.

VPP Power/

Input

Erase and Program Powe r: A valid voltage on thi s pin allows erasing or programming. Memory

contents cannot be alter ed when VPP ≤ VPPLK. Block erase and progra m at invalid VPP voltages

should not be attempted.

Set VPP = VCC for in- syst em pr og ram a nd erase op er ati ons. To a ccom moda te r esi stor o r di ode dro p s

from t he syste m supply, the VIH level of VPP c an be as lo w as VPPL min. VPP must rema in abov e VPPL

min t o perform in-system flash modification. VP P may be 0 V during read operations.

VPPH can be applied to main blocks for 1000 cycles maximum and t o parameter blocks for 2500

cycles. VPP can be connected to 9 V for a c umulative total no t to exceed 80 hours. Extended use of

this pin at 9 V may reduce block cycl ing capability.

VCC Power Device Core Power Supply: Core (logic) source voltage. Writes to the flash array are inhibited when

VCC ≤ VLKO. Operations at invalid VCC voltages should not be attempted.

1-Gbit P30 Family

Datasheet Intel StrataFlash® Embedded Memory (P30) April 2005

Order Number: 306666, Revision: 001 21

VCCQ Power Output Power Supply: Output-driver source voltage.

VSS Power Ground: Connec t to system ground. Do not float any VS S connect ion.

RFU — Reser ved for Future Use: Reser ved by Inte l for fu tur e devic e functi onali ty and enhanc ement. These

should be treated in the same way as a Do Not Use (DU) signal .

DU — Do Not Use: Do not connect to any other signal, or power su pply; must be left floating.

NC — No Connect: No internal connecti on; can be driven or floated.

Table 3. TSOP and Easy BGA Signal Descriptions (Sheet 2 of 2)

Symbol Type Name and Function

Table 4. QU AD+ SCSP Signal Descriptions (Sheet 1 of 2)

Symbol Type Name and Function

A[MAX:0] Input

ADDRES S INPU TS: Devi ce address inputs. 64-Mbit: A[21:0]; 128-Mbit: A[22:0]; 256-Mbit: A[23:0];

512-Mbit: A[24:0].

See Ta bl e 6 on pag e 22 , Fi gure 11 on page 23, and Figure 12 on page 23 for 512-Mbit and 1-Gbit

addressing.

DQ[15:0] Input/

Output

DATA INPUT/OUTPUTS: Inputs da ta an d c om m a nd s dur ing writ e cy c le s ; ou tp uts data during

memory, Status Register, Protection Register, and Read Configuration Register reads. Data balls

float when the CE# or OE# are deasserted. Data is internally latched dur ing writes.

ADV# Input

ADDRESS VALID: Active low input. Dur ing synchronous read oper ations, addresses are latched on

the r ising edge of ADV#, or on the next valid CLK edge with ADV# low, whichever occurs first.

In asynchronous mode, the address is latched when ADV# going high or continuously flows through

if ADV# is held low.

WARNING: Designs not using ADV# must tie it to VSS to allow addresses to flow through.

F1-CE#

F2-CE# Input

FLASH CHIP ENABLE: Active low input. CE# low se lects the associated flash memory die. When

asser ted, flash int ernal co ntrol logic, input buffers, d ecoders, and sense amplifiers are acti ve. When

deasserted, the assoc iated flash die is desel ected, power is reduced to standby levels, data and

WAIT out p uts are placed in hig h-Z state.

See Ta bl e 6 on pag e 22 for CE# assignment definitions.

WARNING: All chip enables must be high when device is not in use.

CLK Input

CLOCK: Synchronizes the device with the system’s bus frequency in synchronous-read mode.

During synchronous read operations, addresses are latched on the rising edge of ADV#, or on the

next valid CLK edge with ADV# low, whichever occurs first.

WARNING: Designs not using CLK for synchronous read mode must tie it to VCCQ or VSS.

F1-OE#

F2-OE# Input OUTPUT ENABLE: Active low input. OE# low enables the device’ s out put data buffers during read

cycles. OE# high places the data outputs and WAIT in H igh-Z.

F1-OE # and F2-OE# should be tied together for all densities.

RST# Input RESET: Act ive low input. RST# resets internal automation and inhi bits write operations. This

provi des data protecti on during power transitions. RS T# high enables normal operation. Exit from

reset places the device in asynch ronous read arra y mode.

WAIT Output

WAIT: Indicate s data valid in synchronous array or non-array burst reads. Read Confi guration

VOH whe n CE # and OE# are VIL. WAIT is hi gh - Z if CE # or O E# is VIH.

• In syn chronous array or non-array read modes, WAIT indicates invalid data when asserted and

valid data when deasserted.

• In asynchronous page mode, and all write modes, W AIT is deasserted.

WE# Input WRITE ENABLE: Active low input. WE# cont rols writes to the device. Addr ess and data are la tched

on the rising edge of WE# .

1-Gbit P30 Family

April 2005 Intel StrataFlash® Embedded Memory (P30) Datasheet

22 Order Number: 306666, Revision: 001

4.3 SCSP Configurations

WP# Input WRI TE PROTECT: Active low input. WP# low ena bles the lock-down mechanism. Blocks in lock-

down cannot be unlocked with the Unlock command. WP# high overrides the lock-down function

enabling blocks to be erased or programmed using software commands.

VPP Power/

lnput

Erase and Program Powe r: A valid voltage on thi s pin allows erasing or programming. Memory

contents cannot be alter ed when VPP ≤ VPPLK. Block erase and progra m at invalid VPP voltages

should not be attempted.

Set VPP = VCC for in- syst em pr og ram a nd erase op er ati ons. To a ccom moda te r esi stor o r di ode dro p s

from t he syste m supply, the VIH level of VPP c an be as lo w as VPPL min. VPP must rema in abov e VPPL

min t o perform in-system flash modification. VP P may be 0 V during read operations.

VPPH can be applied to main blocks for 1000 cycles maximum and t o parameter blocks for 2500

cycles. VPP can be connected to 9 V for a c umulative total no t to exceed 80 hours. Extended use of

this pin at 9 V may reduce block cycl ing capability.

VCC Power Device Core Power Supply: Core (logic) source voltage. Writes to the flash array are inhibited when

VCC ≤ VLKO. Operations at invalid VCC voltages should not be attempted.

VCCQ Power Output Power Supply: Output- driver source voltage.

VSS Power Ground: Connect to system ground. Do not float any VSS connecti on.

RFU — Reserved for Future Use: Reserved by Intel for fut ure device fun ctio nality a nd enha ncement . The se

should be treated in the s ame way as a Do Not Use (DU) signal.

DU — Do Not Use: Do not connect to any other signal, or power supply; must be left floating.

NC — No Connect: No internal connection; can be driven or floated.

Table 4. QUAD+ SCSP Signal Descriptions (Sheet 2 of 2)

Symbol Typ e Nam e an d Fu nc tio n

Table 5. Stacked Easy BGA Chip Select Logic

Stack Combination Selected Flash

Die #1 Selected Flash

Di e #2

1-die F1-CE# -

2-die F1-CE# + A2 5 (VIL) F1-CE# + A25 (VIH)

Tab le 6. QUAD+ SCSP Chip Select Logic

Stack

Combination Selected Flash

Die #1 Sel ected Fl ash

Die #2 Selected Flash

Die #3 Selected Flash

Die #4

1-die F1-CE# - - -

2-d ie F1- CE# + A24 (VIL) F1-CE# + A24 (VIH)- -

4-d ie F1- CE# + A24 (VIL) F1-CE# + A24 (VIH) F2-CE# + A24 (VIL) F2-CE# + A 24 (VIH)

1-Gbit P30 Family

Datasheet Intel StrataFlash® Embedded Memory (P30) April 2005

Order Number: 306666, Revision: 001 23

Figure 10. 512-Mbit Easy BGA Device Block Diagram

Figure 11. 512-Mbit QUAD+ SCSP Device Block Diagram

Figure 12. 1-Gbit QUAD+ SCSP Device Block Diagram

Flash Die #1

(256-Mbit)

Flash Die #2

(256-Mbit)

WP#

CLK

F1-CE#

ADV#

OE#

WAIT

WE#

RST#

VCC

VPP

DQ[15:0]

A[MAX:1]

VCCQ

VSS

Easy BGA 2-Die (512-Mbit) Device Configuration

Flash Die #1

(256-Mbit)

Flash Die #2

(256-Mbit)

WP#

CLK

F1-CE#

ADV#

OE#

WAIT

WE#

RST#

VCC

VPP

DQ[15:0]A[MAX:0]

VCCQ

VSS

QUAD+ 2-Die (512-Mbit ) Device Configuration

Flash Die #1

(256-Mbit) Flash Die #3

(256-Mbit)

Flash Die #2

(256-Mbit) Flash Die #4

(256-Mbit)

WP#

CLK

F1-CE#

ADV#

OE#

F2-CE#

WAIT

WE#

RST#

VCC

VPP

DQ[15:0]A[MAX:0]

VCCQ

VSS

QUAD+ 4-Die (1-Gbit) Device Configuration

1-Gbit P30 Family

April 2005 Intel StrataFlash® Embedded Memory (P30) Datasheet

24 Order Number: 306666, Revision: 001

4.4 Memory Maps

Table 7 through Table 10 show the P30 memory maps. See Section 11.0, “Programming

Operations” on page 61 for Programming Region information.

Table 7. Discrete Top Parameter Memory Maps (all packages)

Programming

Region # Size

(KB) Blk 256-Mbit Blk 128-Mbit Programming

Region # Size

(KB) Blk 64-Mbit

32 258 FFC000 - FFFFFF 130 7FC000 - 7FFFFF

32 66 3FC0 00 - 3 FFFFF

...

32 255 FF0000 - FF3FFF 127 7F0000 - FF3FFF 32 63 3F0000 - 3F3FFF

128 254 FE0000 - FE FFFF 126 7E0000 - 7EFFFF 128 62 3E0000 - 3EFFFF

...

128 240 F00000 - F0FFFF 120 780000 - 78FFFF 128 56 380000 - 38FFFF

128 239 EF0000 - EFFFFF 119 770000 - 77FFFF

128 55 370000 - 37FFFF

...

128 224 E00000 - E0FFFF 112 700000 - 70FFFF 128 48 300000 - 30FFFF

128 223 DF0000 - DFFFFF 111 6F0000 - 6FFFFF

128 47 2F0000 - 2FFFFF

...

128 208 D00000 - D0FFFF 104 680000 - 68FFFF 128 40 280000 - 28FFFF

128 207 CF0000 - CFFFFF 103 670000 - 67FFFF

128 39 270000 - 27FFFF

...

128 192 C00000 - C0FFFF 96 600000 - 60FFFF 128 32 200000 - 20FFFF

128 191 BF0000 - BFFFFF 95 5F0000 - 5FFFFF

128 31 1F0000 - 1FFFFF

...

128 176 B00000 - B0FFFF 88 580000 - 58FFFF 128 24 180000 - 18FFFF

128 175 AF0000 - AFFFFF 87 570000 - 57FFFF

128 23 170000 - 17FFFF

...

128 160 A0000 - A0FFFF 80 500000 - 50FFFF 128 16 100000 - 10FFFF

128 159 9F0000 - 9FFFFF 79 4F0000 - 4FFFFF

128 15 0F0000 - 0FFFFF

...

128 144 900000 - 90FFFF 72 480000 - 48FFFF 128 8 080000 - 08FFFF

128 143 8F0000 - 8FFFFF 71 470000 - 47FFFF

128 7 070000 - 07FFFF

...

128 128 800000 - 80FFFF 64 400000 - 40FFFF 128 0 000000 - 00FFFF

128 127 7F0000 - 7FFFFF 63 3F0000 - 3FFFFF

...

128 112 700000 - 70FFFF 56 380000 - 38FFFF

1-Gbit P30 Family

Datasheet Intel StrataFlash® Embedded Memory (P30) April 2005

Order Number: 306666, Revision: 001 25

128 111 6F0000 - 6FFFFF 55 370000 - 37FFFF

...

128 96 600000 - 60FFFF 48 300000 - 30FFFF

128 95 5F0000 - 5FFFFF 47 2F0000 - 2FFFFF

...

128 80 500000 - 50FFFF 39 280000 - 28FFFF

128 79 4F0000 - 4FFFFF 38 270000 - 27FFFF

...

128 64 400000 - 40FFFF 32 200000 - 20FFFF

128 63 3F0000 - 3FFFFF 31 1F0000 - 1FFFFF

...

128 48 300000 - 30FFFF 24 180000 - 18FFFF

128 47 2F0000 - 2FFFFF 23 170000 - 17FFFF

...

128 32 200000 - 20FFFF 16 100000 - 10FFFF

128 31 1F0000 - 1FFFFF 15 0F0000 - 0FFFFF

...

128 16 100000 - 10FFFF 8 080000 - 08FFFF

128 15 0F0000 - 0FFFFF 7 070000 - 07FFFF

...

128 0 000000 - 00FFFF 0 000000 - 00FFFF

Table 7. Discrete Top Parameter Memory Maps (all packages)

Programming

Region # Size

(KB) Blk 256-Mbit Blk 128-Mbit Programming

R egion # Size

(KB) Blk 64-Mbit

Table 8. Discrete Bottom Parameter Memory Maps (all packages)

Programming

Region Size

(KB) Blk 256-Mbit Blk 128-Mbit Programming

Region Size

(KB) Blk 64-Mbit

128 258 FF0000 - FFFFFF 130 7F0000 - 7FFFFF

128 62 3F0000 - 3FFFFF

...

128 243 F00000 - F0FFFF 123 780000 - 78FFFF 128 56 380000 - 38FFFF

128 242 EF0000 - EFFFFF 122 770000 - 77FFFF

128 55 370000 - 37FFFF

...

128 227 E00000 - E0FFFF 115 700000 - 70FFFF 128 48 300000 - 30FFFF

128 226 DF0000 - DFFFFF 114 6F0000 - 6FFFFF

128 47 2F0000 - 2FFFFF

...

128 211 D00000 - D0FFFF 107 680000 - 68FFFF 128 40 280000 - 28FFFF

1-Gbit P30 Family

April 2005 Intel StrataFlash® Embedded Memory (P30) Datasheet

26 Order Number: 306666, Revision: 001

128 210 CF0000 - CFFFFF 106 670000 - 67FFFF

128 39 270000 - 27FFFF

...

128 195 C00000 - C0FFFF 99 600000 - 60FFFF 128 32 200000 - 20FFFF

128 194 BF0000 - BFFFFF 98 5F0000 - 5FFFFF

128 31 1F0000 - 1FFFFF

...

128 179 B00000 - B0FFFF 91 580000 - 58FFFF 128 24 180000 - 18FFFF

128 178 AF0000 - AFFFFF 90 570000 - 57FFFF

128 23 170000 - 17FFFF

...

128 163 A0000 - A0FFFF 83 500000 - 50FFFF 128 16 100000 - 10FFFF

128 162 9F0000 - 9FFFFF 82 4F0000 - 4FFFFF

128 15 0F0000 - 0FFFFF

...

128 147 900000 - 90FFFF 75 480000 - 48FFFF 128 8 080000 - 08FFFF

128 146 8F0000 - 8FFFFF 74 470000 - 47FFFF

128 10 070000 - 07FFFF

...

128 131 800000 - 80FFFF 67 400000 - 40FFFF 128 4 010000 - 01FFFF

128 130 7F0000 - 7FFFFF 66 3F0000 - 3FFFFF 32 3 00C000 - 00FFFF

...

128 115 700000 - 70FFFF 59 380000 - 38FFFF 32 0 000000 - 003FFF

128 114 6F0000 - 6FFFFF 58 370000 - 37FFFF

...

128 99 600000 - 60FFFF 51 300000 - 30FFFF

128 98 5F0000 - 5FFFFF 50 2F0000 - 2FFFFF

...

128 83 500000 - 50FFFF 43 280000 - 28FFFF

128 82 4F0000 - 4FFFFF 42 270000 - 27FFF F

...

128 67 400000 - 40FFFF 35 200000 - 20FFFF

128 66 3F0000 - 3FFFFF 34 1F0000 - 1FFFFF

...

128 51 300000 - 30FFFF 27 180000 - 18FFFF

128 50 2F0000 - 2FFFFF 26 170000 - 17FFF F

...

128 35 200000 - 20FFFF 19 100000 - 10FFFF

128 34 1F0000 - 1FFFFF 18 0F0000 - 0FFFFF

...

128 19 100000 - 10FFFF 11 080000 - 08FFFF

Table 8. Discrete Bottom Parameter Memory Maps (all packages)

Programming

Region Size

(KB) Blk 256-Mbit Blk 128-Mbit Programming

Region Size

(KB) Blk 64-Mbit

1-Gbit P30 Family

Datasheet Intel StrataFlash® Embedded Memory (P30) April 2005

Order Number: 306666, Revision: 001 27

128 18 0F0000 - 0FFFFF 10 070000 - 07FFFF

...

128 4 010000 - 01FFFF 4 010000 - 01FFFF

32 3 00C000 - 00FFFF 3 00C000 - 00FFFF

...

32 0 000000 - 03FFFF 0 000000 - 00FFFF

Table 8. Discrete Bottom Parameter Memory Maps (all packages)

Programming

Region Size

(KB) Blk 256-Mbit Blk 128-Mbit Programming

Region Size

(KB) Blk 64-Mbit

Table 9. 512-Mbit Memory Map (Easy BGA and QUAD+ SCSP)

Flash Die # Die Stack Config. S ize (KB) 512-Mbit Flash (2x256- Mbit w/ 1 CE )

Blk Address Range

2Flash Die #2

(Top Parameter)

32 258 FFC000 - FFFFFF

...

32 255 FF0000 - FF3FF F

128 254 FE0000 - FEFFFF

...

128 0 000000 - 00FFFF

1Flash Die #1 (Bottom

Parameter)

128 258 FF0000 - FFFFFF

...

128 4 010000 - 01FFFF

32 3 00C000 - 00FFFF

...

32 0 000000 - 003FFF

Note: R efer to 256-Mbit Memory Map (Table 7 and Table 8) for Programming Region Inf ormation.

1-Gbit P30 Family

April 2005 Intel StrataFlash® Embedded Memory (P30) Datasheet

28 Order Number: 306666, Revision: 001

Tab le 10. 1-Gbit Memory Map ( QUAD+ SCSP o nly)

Flash Die # Die Stack Config. Si ze (KB) 1-Gbit Flash (4x256-Mbit w/ 2CE)

Blk Address Range

4Flash Die #4

(To p Para mete r)

32 258 FFC000 - FFFFFF

...

32 255 FF0000 - FF3FFF

128 254 FE0000 - FEFFFF

...

128 0 000000 - 00FFFF

3Flash Die #3

(Botto m Pa ram ete r)

128 258 FF0000 - FFFFFF

...

128 5 020000 - 02FFFF

32 3 00C000 - 00FFFF

...

32 0 000000 - 003FFF

2Flash Die #2

(To p Para mete r)

32 258 FFC000 - FFFFFF

...

32 255 FF0000 - FF3FFF

128 254 FE0000 - FEFFFF

...

128 0 000000 - 00FFFF

1Flash Die #1

(Botto m Pa ram ete r)

128 258 FF0000 - FFFFFF

...

128 4 010000 - 01FFFF

32 3 00C000 - 00FFFF

...

32 0 000000 - 003FFF

Note: Refer t o 256-Mbit Memory M ap (Table 7 and Table 8) for Program m ing Regi on Inform ati on.

1-Gbit P30 Family

Datasheet Intel StrataFlash® Embedded Memory (P30) April 2005

Order Number: 306666, Revision: 001 29

5.0 Maximum Ratings and Operating Conditions

5.1 Absolute Maximum Ratings

Warning: Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage.

These are stress ratings only.

Paramete r Maximu m Ra tin g Note s

Tem p erat ure und er bi as –4 0 °C to +85 °C 1

Storage tempera ture –65 °C to +125 °C

Voltage on any signal (except VCC, VPP) –0.5 V to +4.1 V 2

VPP voltage –0.2 V to +10 V 2,3,4

VCC voltage –0.2 V to +2.5 V 2

VCCQ voltage –0.2 V to +4.1 V 2

Output short circuit current 100 mA 5

Notes:

1. Temperature f or 1-Gbit SCSP is –30 °C to +85 °C .

2. Voltages shown are specifie d with respect to VSS. Minimum DC voltage is –0.5 V on input/output

signal s an d –0.2 V on VCC, VCCQ, and VPP. During transitions, this level may undershoot to –2.0 V for

periods < 20 ns. Maximum DC voltage on VCC is VCC + 0.5 V, whic h, duri ng trans itions, may

overs hoo t to VCC + 2.0 V for periods < 20 ns. Maximum DC vo ltage on input/ output signals and VCCQ

is VCCQ + 0.5 V, which, dur ing transitions, may overshoot to VCCQ + 2.0 V for periods < 20 ns.

3. Maximum DC voltage on VPP may overshoot to +11.5 V for periods < 20 ns.

4. Program/er ase voltage is typ ically 1.7 V – 2.0 V. 9.0 V can be applied for 80 hours maximum total, to

any blocks for 1000 cycles maximum. 9.0 V program/erase voltage may reduce block cycling

capability.

5. Output shorted for no more than one second. No more than one output shorted at a time.

1-Gbit P30 Family

April 2005 Intel StrataFlash® Embedded Memory (P30) Datasheet

30 Order Number: 306666, Revision: 001

5.2 Operating Conditions

Note: Operation beyond the “Operating Conditions” is not recommended and extended exposure beyond

the “Operating Conditions” may affect device reliability.

Table 11. Operating Conditions

Symbol Parameter Min Max Units Notes

TCOp er ating Tempera tu re – 40 + 85 °C 1, 2

VCC VCC Supply Voltage 1.7 2.0

VCCQ I/O Supply Voltage CMOS in pu ts 1.7 3.6

TTL in pu ts 2.4 3 .6

VPPL VPP Voltage Supply (Logic Level) 0.9 3.6

VPPH Factory word programming VPP 8.5 9.5

tPPH Maximum VPP Hours VPP = VPPH -80Hours

Block

Erase

Cycles

Main and Parameter Blocks VPP = VCC 100,000 -

CyclesMain Blocks VPP = VPPH -1000

Parameter Blocks VPP = VPPH -2500

NOTES:

1. TC = Case Temp erature

2. Temperature for 1-Gbit SC SP is –30 °C to +85 °C.

3. In typical operation, the VPP program voltage is VPPL. VPP can be connected to 8.5 V – 9.5 V for 80

hours.

1-Gbit P30 Family

Datasheet Intel StrataFlash® Embedded Memory (P30) April 2005

Order Number: 306666, Revision: 001 31

6.0 Electrical Specifications

6.1 DC Current Characteristi c s

Table 12. DC Current Characteristics (Sheet 1 of 2)

Sym Parameter

CMOS

Inputs

(VCCQ =

1.7 V - 3.6 V)

TTL Inputs

(VCCQ =

2.4 V - 3.6 V) Unit Test Conditions Notes

Typ Max Typ Max

ILI Input Load Current - ±1 - ±2 µA VCC = VCCMax

VCCQ = V CCQMax

VIN = VCCQ or VSS 1

ILO Output

Leakage

Current DQ [1 5 :0] , WAIT - ± 1 - ±10 µA VCC = VCCMax

VCCQ = V CCQMax

VIN = VCCQ or VSS

ICCS,

ICCD

VCC Standby,

Power Down

64-Mbit20352035

µA

VCC = VCCMax

VCCQ = V CCQMax

CE# = VCCQ

RST# = VCCQ (for ICCS)

RST# = VSS (for ICCD)

WP# = VIH

1,2

128-Mbit 30 75 30 75

256-Mbit 55 115 55 200

512-Mbit 110 230 110 400

1-Gbit 220 460 220 800

ICCR

Average

VCC

Read

Current

Asynchronous Single-

Word f = 5 MHz (1 CLK) 14 16 14 16 mA 1-Word

Read

VCC = VCCMax

CE# = VIL

OE# = VIH

Inputs: VIL or VIH

Pag e-Mode Read

f = 13 MHz (5 CLK) 910910mA

4-Wor d

Read

Synchronous Burst

f = 40 MHz

13 17 n/a n/a mA BL = 4W

15 19 n/a n/a mA BL = 8W

17 21 n/a n/a mA BL = 16W

21 26 n/a n/a mA BL = Cont.

ICCW,

ICCE

VCC Program Current,

VCC Erase Current

36 51 36 51 mA VPP = VPPL, pgm/ers in progress 1,3,4,7

26 33 26 33 VPP = VPPH, pgm/ers in progress 1,3,5,7

ICCWS,

ICCES

VCC Program

Suspend Current,

VCC Erase

Suspend Current

64-Mbit20352035

µA CE# = VCCQ; suspend in

progress 1,3,6

128-Mbit 30 75 30 75

256-Mbit 55 115 55 200

512-Mbit 110 230 110 400

1-Gbit 220 460 220 800

IPPS,

IPPWS,

IPPES

VPP Standby Current,

VPP Program Suspend Current,

VPP Erase Suspen d Current 0.2 5 0.2 5 µA VPP = VPPL, suspend in progress 1,3

IPPR VPP Read 2 15 2 15 µA VPP ≤ VCC 1,3

1-Gbit P30 Family

April 2005 Intel StrataFlash® Embedded Memory (P30) Datasheet

32 Order Number: 306666, Revision: 001

6.2 DC Voltage Characteristics

IPPW VPP Program Current 0.05 0.10 0.05 0.10 mA VPP = VPPL, program in progress

822822 V

PP = VPPH, program in progress

IPPE VPP Erase Current 0.05 0.10 0.05 0.10 mA VPP = VPPL, erase in progress

822822 V

PP = VPPH, erase in progress

Notes:

1. All currents are RMS unless noted. Typical values at typical VCC, TC = +25 °C.

2. ICCS is the average current measured over any 5 ms time interval 5 µs af ter CE# is deasse rted.

3. Sampled, not 100% tested.

4. VCC read + program current is the sum of VCC read and VCC program curr ents.

5. VCC read + erase current is the sum of VCC read and VCC erase currents.

6. ICCES is specified wit h the device deselected. If devic e is read while in er ase suspe nd, curr ent is I CCES plus ICCR.

7. ICCW, ICCE measur ed over typical or max times specified in Section 7.5, “Program and Erase Characteristics” on

page 45.

Table 13. DC Voltage Characteristics

Sym Parameter

CMOS Inputs

(VCCQ = 1.7 V - 3.6 V) TTL Inputs (1)

(VCCQ = 2.4 V - 3.6 V) Unit Test Condition No tes

Min Max Min Max

VIL Input Low Voltage 0 0.4 0 0.6 V 2

VIH Input High Voltage V CCQ – 0.4 VCCQ 2.0 VCCQ V

VOL Output Low Voltage - 0.1 - 0.1 V VCC = VCCMin

VCCQ = VCCQMin

IOL = 100 µA

VOH Output High Voltage VCCQ – 0.1 - VCCQ – 0. 1 - V VCC = V CCMin

VCCQ = VCCQMin

IOH = –100 µA

VPPLK VPP Lock-Out Volta ge - 0.4 - 0.4 V 3

VLKO VCC Lock Vo lta ge 1 .0 - 1 .0 - V

VLKOQ VCCQ Lock Volta ge 0.9 - 0 .9 - V

NOTES:

1. Synchr onous read mode is not supported with TTL inputs.

2. VIL can undershoot to –0.4 V and VIH can overshoot to VCCQ+ 0.4 V for duratio ns of 20 ns or less.

3. VPP ≤ VPPLK inhibit s erase and program operations. Do not use VPPL and VPPH outside their valid ranges.

Table 12. DC Current Characteristics (Sheet 2 of 2)

Sym Parameter

CMOS

Inputs

(VCCQ =

1.7 V - 3.6 V)

TTL Inputs

(VCCQ =

2.4 V - 3.6 V) Unit Test Conditions Notes

Typ Max Typ Max

1-Gbit P30 Family

Datasheet Intel StrataFlash® Embedded Memory (P30) April 2005

Order Number: 306666, Revision: 001 33

7.0 AC Characteristics

7.1 AC Test Conditions

Note: AC test input s are dri v en at VCCQ for Logic "1" and 0.0 V for Logic "0." Input/outp ut timing begin s/ends

at VCCQ/2. Input rise and fall times (10% to 90%) < 5 ns. Worst case spee d occurs at VCC = VCCMin.

NOTES:

1. See the following table for component values.

2. Test configuration component value for worst case spee d conditions.

3. CL includes jig capacitance

Figure 13. AC Input /Output Reference Waveform

Input V

CCQ

/2 V

CCQ

/ 2 Output

CCQ

Test Points

Figure 14. Transient Equivalent Testing Load Circuit

Device

Un de r T est Out

Table 14. Test configuration compone nt v alue for wors t case speed conditions

Test Configurati on CL (pF)

VCCQMin St andard Test 30

Figure 15. Clock Input AC Waveform

CLK [C]

R203R202

R201

1-Gbit P30 Family

April 2005 Intel StrataFlash® Embedded Memory (P30) Datasheet

34 Order Number: 306666, Revision: 001

7.2 Capacitance

Table 15. Capacitance

Symbol Parameter Signals Min Typ Max Unit Condition Note

CIN Input Capacitance

Address, Data,

CE#, WE#, OE#,

RST#, CLK,

ADV#, WP#

26 7 pF

Typ temp = 25 °C,

Max temp = 85 °C,

VCC = VCCQ = (0 V - 1.9 5 V),

Discrete silicon die

1,2,3

COUT Output Capacitance Data, WAIT 2 4 5 pF

NOTES:

1. Capaci tance values are for a single di e; for 2-die and 4-die stacks multiple the above values by the number of die in t he

stack.

2. Sampled, not 100% tested.

3. S il ic o n di e capaci ta n c e on ly, add 1 pF fo r dis c rete pack a ges.

1-Gbit P30 Family

Datasheet Intel StrataFlash® Embedded Memory (P30) April 2005

Order Number: 306666, Revision: 001 35

7.3 AC Read Specifications

Table 16. AC Read Sp ecifications for 64/128-Mbit Densities (Sheet 1 of 2)

Num Symbol Parameter Min Max Unit Notes

Asynchronou s Spec ifications

R1 tAVAV Read cycle time 85 - ns

R2 tAVQV Addres s to output valid - 8 5 ns

R3 tELQV CE# low to output valid - 85 ns

R4 tGLQV OE# low to output valid - 25 ns 1,2

R5 tPHQV RST# high to output valid - 150 ns 1

R6 tELQX CE# low to output in low-Z 0 - ns 1,3

R7 tGLQX OE# low to output in low-Z 0 - ns 1,2,3

R8 tEHQZ CE# high to output in high-Z - 24 ns

1,3R9 tGHQZ OE# high to output in high-Z - 24 ns

R10 tOH Output hold from first occurring address, CE#, or OE# change 0 - ns

R11 tEHEL CE# pulse width high 20 - ns 1

R12 tELTV CE# l o w to WAIT val i d - 17 ns

R13 tEHTZ CE# high to WAIT high-Z - 20 ns 1,3

R15 tGLTV OE# l o w to WAIT va l i d - 17 n s 1

R16 tGLTX OE# low to WAIT in low-Z 0 - ns 1,3

R17 tGHTZ OE# high to W AIT in high-Z - 20 ns

Latching Specifications

R101 tAVVH Address setup to ADV# high 10 - ns

R102 tELVH CE# low to ADV# high 10 - ns

R103 tVLQV ADV# low to output valid - 85 ns

R104 tVLVH ADV# pulse width low 10 - ns

R105 tVHVL ADV# pulse width high 10 - ns

R106 tVHAX Address hold from ADV# high 9 - ns 1,4

R108 tAPA Page address access - 25 ns 1

R111 tphvh RST# high to ADV# high 30 - ns

Cloc k Sp ec ifications

R200 fCLK CLK frequency - 40 MHz

1,3,6

R201 tCLK CLK period 25 - ns

R202 tCH/CL CLK high/low time 5 - ns

R203 tFCLK/RCLK CLK fa l l /rise ti me - 3 ns

Synchronou s Specifications

R301 tAVCH/L Address setup to CLK 9 - ns

R302 tVLCH/L ADV# low setup to CLK 9 - ns

R303 tELCH/L CE# l o w se tup to CLK 9 - ns

R304 tCHQV / tCLQV CLK to output valid - 20 ns

1-Gbit P30 Family

April 2005 Intel StrataFlash® Embedded Memory (P30) Datasheet

36 Order Number: 306666, Revision: 001

R305 tCHQX Output hold from CLK 3 - ns 1,5

R306 tCHAX Address hold from CLK 10 - ns 1,4,5

R307 tCHTV CL K to WAIT va lid - 20 ns 1,5

R311 tCHVL CLK Valid to ADV# Setup 3 - ns 1

R312 tCHTX WAIT Hold from CLK 3 - ns 1,5

NOTES:

1. See Fi gur e 13, “AC Input/ Out pu t Ref er enc e W ave fo rm” on page 33 for timing measurements and max allowable input

slew rate.

2. OE# may be del ayed by up to tELQV – tGLQV after CE#’s falling edge without impact to tELQV.

3. Sampled, not 100% tested.

4. Address hold in synchronous burst mode is tCHAX or tVHAX, whichever timing specification is satisfied first.

5. Applies only to subsequent synchronous re ads.

6. See your local Intel repr esentative for designs requiring higher than 40 MHz sy nchronous operation.

Table 16. AC Read Specifications for 64/128-Mbit Densities (Sheet 2 of 2)

Num Symbol Parameter Min Max Unit Notes

Table 17. AC Read Specifications for 256/512-Mbit and 1-Gbit Densities (Sheet 1 of 2)

Num Symbol Parameter Speed Min Max Unit Notes

Asynchronous Specifications

R1 tAVAV Read cycle time Vcc = 1.8 V – 2.0 V 85 - ns

Vcc = 1.7 V – 2.0 V 88 -

R2 tAVQV Address to output valid Vcc = 1.8 V – 2.0 V -85

Vcc = 1.7 V – 2.0 V -88

R3 tELQV CE# low to output valid Vcc = 1.8 V – 2.0 V -85

Vcc = 1.7 V – 2.0 V -88

R4 tGLQV OE# low to output valid - 25 ns 1,2

R5 tPHQV RST# high to output valid - 150 ns 1

R6 tELQX CE# low to output in low-Z 0 - ns 1,3

R7 tGLQX OE# low to output in low-Z 0 - ns 1,2,3

R8 tEHQZ CE# high to output in high-Z - 24 ns

1,3R9 tGHQZ OE # high to output in high-Z - 24 ns

R10 tOH Output hold from first occurring address, CE#, or OE# change 0 - ns

R11 tEHEL CE# pulse width high 20 - ns 1

R12 tELTV C E # l o w to WAIT va l i d - 17 n s

R13 tEHTZ CE# high to WAIT high-Z - 20 ns 1,3

R15 tGLTV OE# low to WAIT va li d - 17 ns 1

R16 tGLTX OE# low to WAIT in low-Z 0 - ns 1,3

R17 tGHTZ OE# high to WAIT in high-Z - 20 ns

Latching Specifications

1-Gbit P30 Family

Datasheet Intel StrataFlash® Embedded Memory (P30) April 2005

Order Number: 306666, Revision: 001 37

R101 tAVVH Address setup to ADV# high 10 - ns

R102 tELVH CE# low to ADV# high 10 - ns

R103 tVLQV ADV# low to output valid Vcc = 1.8 V – 2.0 V -85

Vcc = 1.7 V – 2.0 V -88

R104 tVLVH ADV# pulse width low 10 - ns

R105 tVHVL ADV# pulse width high 10 - ns

R106 tVHAX Address hold from ADV# high 9 - ns 1,4

R108 tAPA Page address access - 25 ns 1

R111 tphvh RST# high to ADV# high 30 - ns

Cloc k Sp ec ifications

R200 fCLK CLK frequency - 40 MHz

1,3,6

R201 tCLK CLK period 25 - ns

R202 tCH/CL CLK high/low time 5 - ns

R203 tFCLK/RCLK CLK fa l l /rise ti me - 3 ns

Synchronou s Specifications

R301 tAVCH/L Address setup to CLK 9 - ns

R302 tVLCH/L ADV# low setup to CLK 9 - ns

R303 tELCH/L CE# l o w se tup to CLK 9 - ns

R304 tCHQV / tCLQV CLK to output valid - 20 ns

R305 tCHQX Out put hold from CLK 3 - ns 1,5

R306 tCHAX Address hold from CLK 10 - ns 1,4,5

R307 tCHTV CLK to WAIT va l i d - 2 0 ns 1 ,5

R311 tCHVL CLK Valid to ADV# Setup 3 - ns 1

R312 tCHTX WAIT Hold from CLK 3 - ns 1,5

NOTES:

1. See Figure 13, “AC Input/Output Reference Waveform” on page 33 for timing measurements and max allowable i nput

slew rate.

2. OE# ma y be delayed by up to tELQV – tGLQV after CE#’s falling edge without impact to tELQV.

3. Sampled, not 100% tested.

4. Address hold in synchronous bur st mode is tCHAX or tVHAX, whichever timing specification is satisfied first.

5. Applies only to subsequent synchronous reads.

6. See your local Intel repres entative for designs requiring higher than 40 MHz synchr onous operation.

Table 17. AC Read Specifications for 256/512-Mbit and 1-Gbit Densities (Sheet 2 of 2)

Num Symbol Parameter Speed Min Max Unit Notes

1-Gbit P30 Family

April 2005 Intel StrataFlash® Embedded Memory (P30) Datasheet

38 Order Number: 306666, Revision: 001

Note: W AIT shown deasserted during asynchronous read mode (RCR[10]=0, Wait asserted low).

Figure 16. Asynchronous Single-Word Read (ADV# Low)

R17R15

R9R4

R8R3

R2 R1

ddre ss [A]

ADV#

CE # [ E}

OE# [G]

WAIT [T]

Data [D/Q]

RST# [P ]

Figure 17. Asynchronous Sin gle-Word Rea d (ADV# Latch)

R10

R17R15

R9R4

R8R3

R106

R101

R105R105

R2 R1

ddress [A]

A[1:0][A]

ADV#

CE# [E}

OE# [G]

WAIT [T]

Data [D/Q]

1-Gbit P30 Family

Datasheet Intel StrataFlash® Embedded Memory (P30) April 2005

Order Number: 306666, Revision: 001 39

Note: WAIT shown deasserted during asynchronous read mode (RCR[10]=0, Wait asserted low).

1. WAIT is dri ven pe r O E# a ssert io n duri ng sync hr onous ar ray or n on-a r ray r ea d, a nd can be conf igu red to

assert eith er during or one data cycle befor e valid data.

2. This diagram illustrates the case in which an n-word burst is initiated to the flash memory array and it is

terminated by CE# deassertion after the first word in the burst.

Figure 18. Asynchronous Page-Mode Read Timing

R108 R9R7

R17R15

R10R4

R8R3

R106

R101

R105R105

R1R1

[M ax:2 ] [A ]

A[1:0]

ADV#

CE# [E]

OE# [G]

WAIT [T]

DATA [ D/Q]

Figure 19. Synchronous Single-Word Array or Non-array Read Timing

R312

R305R304

R17R307R15

R9R7

R303

R102 R3

R104

R106R101

R104

R105R105

R306R301

CL K [C]

ddress [A]

ADV# [V]

CE # [E]

OE# [G]

WAIT [T]

Data [D/Q]

1-Gbit P30 Family

April 2005 Intel StrataFlash® Embedded Memory (P30) Datasheet

40 Order Number: 306666, Revision: 001

Notes:

1. WAI T i s dr iv en per OE# ass erti on du rin g sy nch rono us a rr ay o r no n- arr ay r ead , and ca n b e conf igur e d to

assert either during or one data cycle before valid data.

2. At the end of Word Line; the delay incurr ed when a burst access crosses a 16-word boundary and the

starting address is not 4-word boundary aligned.

Figure 20. Contin uous Burst Read, showing an Output Delay Timing

R305R305R305R305

R304

R312R307R15

R303

R102 R3

R106

R105R105

R101 R2

R304R304R304R306

R302

R301

CL K [ C]

ddr ess [A]

ADV# [V]

CE# [E]

OE# [G]

WAIT [T]

Data [D/Q ]

1-Gbit P30 Family

Datasheet Intel StrataFlash® Embedded Memory (P30) April 2005

Order Number: 306666, Revision: 001 41

Note: WAIT is driven per OE# assertion during synchronous array or non-array read. WAIT asserted du ring

initial latency and deasse rted during valid data (RCR[10] = 0, Wait asserted low).

7.4 AC Write Specifications

Figure 21. Synchronous Bu rst -Mode Four-Word Read Timing

Q0 Q1 Q2 Q3

R307

R10

R304

R305R304

R17R15

R303

R106

R102

R105R105

R101 R2

R306

R302

R301

CLK [C]

ddress [A]

ADV # [V]

CE# [E]

OE# [G]

WAIT [T]

Da ta [D/Q]

Table 18. AC Write Specifications (Sheet 1 of 2)

Num Symbol Parameter Min Max Units Notes

W1 tPHWL RST# high reco very to WE # low 150 - ns 1,2,3

W2 tELWL CE# s etup to WE# low 0 - ns 1,2,3

W3 tWLWH WE# write pulse width low 50 - ns 1,2,4

W4 tDVWH Data setup to WE# high 50 - ns

1,2

W5 tAVWH Address setup to WE# high 50 - ns

W6 tWHEH CE # ho ld fr o m WE # hi g h 0 - n s

W7 tWHDX Data ho ld from WE # hi gh 0 - ns

W8 tWHAX Address hold fr om WE# high 0 - ns

W9 tWHWL WE# pulse width high 20 - ns 1,2,5

W10 tVPWH V

PP setup to WE# high 200 - ns 1,2,3,7

W11 tQVVL VPP hold from Status read 0 - ns

W12 tQVBL WP# hold from Status read 0 - ns 1,2,3,7

W13 tBHWH WP# setup to WE# high 200 - ns

1-Gbit P30 Family

April 2005 Intel StrataFlash® Embedded Memory (P30) Datasheet

42 Order Number: 306666, Revision: 001

W14 tWHGL WE# high to O E# low 0 - ns 1,2 ,9

W16 tWHQV WE# high t o rea d val id tAVQV + 35 - ns 1,2,3,6,1

Writ e to A sy n ch r on ous Re ad Specification s

W18 tWHAV WE# hi gh to Ad dre ss val id 0 - ns 1,2 ,3 ,6 ,8

Write to Synchronous Read Specifications

W19 tWHCH/L WE# hi gh to C lo c k va l id 19 - ns 1,2,3,6,1

W20 tWHVH WE# high to AD V # high 19 - ns

Write Specifications with Clock Active

W21 tVHWL ADV# high to WE# low - 20 ns 1,2,3,11

W22 tCHWL Clock hi gh to WE # lo w - 20 ns

Notes:

1. Write timin g characteristics dur ing erase suspend are the same as write-only operations.

2. A write operation can be terminated with either CE# or WE#.

3. Sampled, not 100% tested.

4. Write pulse width low (tWLWH or tELEH) is def ined from CE# or WE # low (whichever occurs last) to

CE# or WE# high (whichever occurs first). Hence, tWLWH = tELEH = tWLEH = tELWH.

5. Write pulse width high (tWHWL or tEHEL) is def ined from CE# or WE# high (whichever occurs first) to

CE# or WE# low (whichever occurs last). Hence, tWHWL = tEHEL = tWHEL = tEHWL).

6. tWHVH or tWHCH/L must be met when transitioning from a write cycle to a synchronous burst read.

7. VPP and WP# should be at a valid level unt il erase or progr am success is determined.

8. This specifi cation is only applicable when transitioning from a writ e cycle to an asynchronous read.

See spec W19 and W20 for synchronous read.

9. When doi ng a Read Status oper ati on f ol lo wing any com mand that al t ers the Sta tus Regi st er, W14 is

20 ns.

10. Add 10 ns if the write operations results in a RCR or block lock status change, for the subse quent

read operation to reflect this change.

11. Thes e specs ar e requ ir ed only wh en t he devic e is in a synch r ono us mode and cloc k is act i ve duri ng

address setup phase.

Table 18. AC Write Specifications (Sheet 2 of 2)

Num Symbol Parameter Min Max Units Notes

Figu re 22. Write-to-Write Timin g

W7W4W7W4

W3W9 W3W9W3W3

W6W2W6W2

W8W8 W5W5

ddress [A]

CE# [ E}

WE# [W]

OE# [G]

Da ta [D/Q]

RS T# [P ]

1-Gbit P30 Family

Datasheet Intel StrataFlash® Embedded Memory (P30) April 2005

Order Number: 306666, Revision: 001 43

Note: WAIT deasserted during asyn chronous read and during write. WAIT High-Z duri ng write per OE#

deasserted.

Figure 23. Asynchronous Read-to-Write Timing

Q D

W4R10

R17R15

W6W3W3W2

R9R4

R8R3

W8W5

R2 R1

ddress [A]

CE# [ E }

OE# [G]

WE# [W]

WAIT [T]

Data [D/Q]

RST# [P]

Figure 24. Write-to-Asy nchronous Read Timing

D Q

R9 R8

W7W4

R17R15

W14

W18W3W3

R10W6W2

R1R1W8W5

ddress [A]

ADV# [V ]

CE# [ E}

WE# [ W]

OE# [G]

WAIT [T ]

Da ta [D/Q ]

RST# [P]

1-Gbit P30 Family

April 2005 Intel StrataFlash® Embedded Memory (P30) Datasheet

44 Order Number: 306666, Revision: 001

Note: WAIT shown deasserted and High-Z per OE# deassertion during write operation (RCR[10]=0, Wait asserted low). Clock is

ignored during wri te opera tion.

Note: WAIT shown deasserted and High-Z per OE# deassertion during write operation (RCR[10]=0, Wait asserted low).

Figure 25. Synchron ous Read-to-Write Timing

Figure 26. Write -to-Synchronous Re ad Timing

Lat ency C ount

Q D D

W7R305

R304

R312R307R16

W15

W22

W21

W8 W9W3

W22 W21

W3W2

R11R13

R11

R303

R104R104

R106

R102

R105R105

W18

R101 R2

R306

R302

R301

CLK [C]

ddress [A]

AD V# [ V]

CE# [E]

OE# [ G]

WE#

WAIT [T]

Data [D/Q]

D Q Q

R304

R305R304

R307R15

W20

W19

W18

W3W3

R11 R303

R11

R104 R106

R104

R306W8W5

R302 R301 R2

CLK

ddress [A]

ADV#

CE# [E}

WE# [W]

OE# [G]

WAIT [T]

Data [D/Q]

RST# [P]

1-Gbit P30 Family

Datasheet Intel StrataFlash® Embedded Memory (P30) April 2005

Order Number: 306666, Revision: 001 45

7.5 Program and Erase Characteristics

Num Symbol Parameter VPPL VPPH Units Notes

Min Typ Max Min Typ Max

Conventional Word Pr ogramming

W200 tPROG/W Program

Time Single word - 90 200 - 85 190 µs 1

Single cell - 30 60 - 30 60

Buffered Programming

W200 tPROG/W Program

Time Single word - 90 200 - 85 190 µs 1

W251 tBUFF 32 -word buffer - 440 880 - 340 680

Buffered Enhanced Fact ory Programming

W451 tBEFP/W Program Single word n/a n/a n/a - 10 - µs 1,2

W452 tBEFP/

Setup BEFP Se tu p n/a n/a n /a 5 - - 1

Erasing and Suspending

W500 tERS/PB Erase Time 32-KByte Parameter - 0.4 2.5 - 0.4 2.5 s1

W501 tERS/MB 128-KByte Main - 1.2 4.0 - 1.0 4.0

W600 tSUSP/P Suspend

Latency Program suspend - 20 25 - 20 25 µs

W601 tSUSP/E Era s e s us p end - 20 2 5 - 20 2 5

Notes:

1. Typical values measured at TC = +25 °C and nomi nal voltages. Performance number s are valid for all

speed versions. Excludes system overhead. Sampled, but not 100% tested.

2. Averaged over entire device.

1-Gbit P30 Family

April 2005 Intel StrataFlash® Embedded Memory (P30) Datasheet

46 Order Number: 306666, Revision: 001

8.0 Power and Reset Specifications

8.1 Power Up and Down

Power supply sequencing is not required if VCC, VCCQ, and VPP are connected together; If

VCCQ and/or VPP are not connected to the VCC supply, then VCC should attain VCCMIN before

applying VCCQ and VPP. Device inputs should not be driven before supply voltage equals VCCMIN.

Power supply transitions should only occur when RST# is low. This protects the device from

accidental programming or erasure during power transitions.

8.2 Reset Specifications

Asserting RST# during a system reset is important with automated program/erase devices because

systems typically expect to read from flash memory when coming out of reset. If a CPU reset

occurs without a flash memory reset, proper CPU initialization may not occur. This is because the

flash memory may be providing status information, instead of array data as expected. Connect

RST# to the same active low reset signal used for CPU initialization.

Also, because the device is disabled when RST# is asserted, it ignores its control inputs during

power-up/down. Invalid bus conditions are masked, providing a level of memory protection.

Num Symbol Parameter Min Max Unit Notes

P1 tPLPH RST# pulse width low 100 - ns 1,2,3,4

P2 tPLRH RS T# low to device r eset during erase - 25 µs 1,3,4,7

RST# low to device reset during program - 25 1,3,4,7

P3 tVCCPH VCC Power valid to RST# de-assertion (high) 60 - 1,4,5,6

Notes:

1. The se specifications are valid for all devi ce versions (packages and speeds).

2. The device may reset if tPLPH is < tPLPH MIN, but this is not guaranteed.

3. Not applicable if RST# is tied to Vcc.

4. Sampled, but not 100% tested.

5. If RST# is tied to the VCC supply, device will not be ready until tVCCPH after VCC ≥ VCCMIN.

6. If RST# is tied to any supply/signal with VCCQ voltage levels, the RST# input voltage must not exceed

VCC until VCC ≥ VCCMIN.

7. Reset complet es within tPLPH if R ST# is asserted while no erase or program ope ration is executing.

1-Gbit P30 Family

Datasheet Intel StrataFlash® Embedded Memory (P30) April 2005

Order Number: 306666, Revision: 001 47

8.3 Power Supply Decoupling

Flash memory devices require careful power supply de-coupling. Three basic power supply current

considerations are: 1) standby current levels; 2) active current levels; and 3) transient peaks

produced when CE# and OE# are asserted and deasserted.

When the device is accessed, many internal conditions change. Circuits within the device enable

charge-pumps, and internal logic states change at high speed. All of these internal activities

produce transient signals. Transient current magnitudes depend on the device outputs’ capacitive

and inductive loading. Two-line control and correct de-coupling capacitor selection suppress

transient voltage peaks.

Because Intel® Multi-Level Cell (MLC) flash memory devices draw their power from VCC, VPP,

and VCCQ, each power connection should have a 0.1 µF ceramic capacitor to ground. High-

frequency, inherently low-inductance capacitors should be placed as close as possible to package

leads.

Additionally, for every eight devices used in the system, a 4.7 µF electrolytic capacitor should be

placed between power and ground close to the devices. The bulk capacitor is meant to overcome

voltage droop caused by PCB trace inductance.

Figure 27. Reset Operation Waveforms

(

A) Reset during

read mode

(B) Reset during

program or block e rase

≤

program or block e rase

≥

RST# [P]

Abort

Complete

Abort

Complete

(D) VCC Power-up to

RST# high

P1 R5

P2 R5

1-Gbit P30 Family

April 2005 Intel StrataFlash® Embedded Memory (P30) Datasheet

48 Order Number: 306666, Revision: 001

9.0 Device Operations

This section provides an overview of device operations. The system CPU provides control of all in-

system read, write, and erase operations of the device via the system bus. The on-chip Write State

Machine (WSM) manages all block-erase and word-program algorithms.

Device commands are written to the Command User Interface (CUI) to control all flash memory

device operations. The CUI does not occupy an addressable memory location; it is the mechanism

through which the flash device is controlled.

9.1 Bus Operations

CE# low and RST# high enable device read operations. The device internally decodes upper

address inputs to determine the accessed block. ADV# low opens the internal address latches. OE#

low activates the outputs and gates selected data onto the I/O bus.

In asynchronous mode, the address is latched when ADV# goes high or continuously flows through

if ADV# is held low. In synchronous mode, the address is latched by the first of either the rising

ADV# edge or the next valid CLK edge with ADV# low (WE# and RST# must be VIH; CE# must

be VIL).

Bus cycles to/from the P30 device conform to standard microprocessor bus operations. Table 19

summarizes the bus operations and the logic levels that must be applied to the de vice control signal

inputs.

9.1.1 Reads

To perform a read operation, RST# and WE# must be deasserted while CE# and OE# are asserted.

CE# is the device-select control. When asserted, it enables the flash memory device. OE# is the

data-output control. When asserted, the addressed flash memory data is driven onto the I/O bus.

See Section 10.0, “Read Operations” on page 53 for details on the available read modes, and see

Section 14.0, “Special Read States” on page 75 for details regarding the available read states.

Tab le 19. Bus Operations Summary

Bus Operation RST# CLK ADV# CE# OE# WE# WAIT DQ[15:0] Notes

Read Asynchronous VIH X L L L H Deasserted Output

Synchronous VIH Running L L L H Driven Output

Write VIH X L L H L High-Z Input 1

Output Disable VIH X X L H H High-Z High-Z 2

Standby VIH X X H X X High-Z High-Z 2

Reset VIL X X X X X High-Z High-Z 2,3

Notes:

1. Refer to the Table 20, “C ommand Bus Cycles” on page 50 for valid DQ[15:0] during a write operation.

2. X = Don’t Care (H or L).

3. RST# must be at VSS ± 0.2 V to meet the maximum spec ified power-down current.

1-Gbit P30 Family

Datasheet Intel StrataFlash® Embedded Memory (P30) April 2005

Order Number: 306666, Revision: 001 49

9.1.2 Writes

To perform a write operation, both CE# and WE# are asserted while RST# and OE# are deasserted.

During a write operation, address and data are latched on the rising edge of WE# or CE#,

whichever occurs first. Table 20, “Command Bus Cycles” on page 50 shows the bus cycle

sequence for each of the supported device commands, while Table 21, “Command Codes and

Definitions” on page 51 describes each command. See Section 7.0, “AC Characteristics” on

page 33 for signal-timing details.

Note: W rite operations with invalid VCC and/or VPP voltages can produce spurious results and should not

be attempted.

9.1.3 Output Disable

When OE# is deasserted, device outputs DQ[15:0] are disabled and placed in a high-impedance

(High-Z) state, WAIT is also placed in High-Z.

9.1.4 Standby

When CE# is deasserted the device is deselected and placed in standby, substantially reducing

power consumption. In standby, the data outputs are placed in High-Z, independent of the level

placed on OE#. Standby current, ICCS, is the average current measured over any 5 ms time interval,

5 µs after CE# is deasserted. During standby, average current is measured over the same time

interval 5 µs after CE# is deasserted.

When the device is deselected (while CE# is deasserted) during a program or erase operation, it

continues to consume active power until the program or erase operation is completed.

9.1.5 Reset

As with any automated device, it is important to assert RST# when the system is reset. When the

system comes out of reset, the system processor attempts to read from the flash memory if it is the

system boot device. If a CPU reset occurs with no flash memory reset, improper CPU initialization

may occur because the flash memory may be providing status information rather than array data.

Flash memory devices from Intel allow proper CPU initialization following a system reset through

the use of the RST# input. RST# should be controlled by the same low-true reset signal that resets

the system CPU.

After initial power-up or reset, the device defaults to asynchronous Read Array, and the Status

drivers in High-Z. When RST# is asserted, the device shuts down the operation in progress, a

process which takes a minimum amount of time to complete. When RST# has been deasserted, the

device is reset to asynchronous Read Array state.

Note: If RST# is asserted during a program or erase operation, the operation is terminated and the

memory contents at the aborted location (for a program) or block (for an erase) are no longer valid,

because the data may have been only partially written or erased.

When returning from a reset (RST# deasserted), a minimum wait is required before the initial read

access outputs valid data. Also, a minimum delay is required after a reset before a write cycle can

be initiated. After this wake-up interval passes, normal operation is restored. See Section 7.0, “AC

Characteristics” on page 33 for details about signal-timing.

1-Gbit P30 Family

April 2005 Intel StrataFlash® Embedded Memory (P30) Datasheet

50 Order Number: 306666, Revision: 001

9.2 Device Commands

Device operations are initiated by writing specific device commands to the Command User

Interface (CUI). See Tabl e 20, “C om m a nd B u s Cycles ” on p a g e 50. Several commands are used to

modify array data including Word Program and Block Erase commands. Writing either command

to the CUI initiates a sequence of internally-timed functions that culminate in the completion of the

requested task. However, the operation can be aborted by either asserting RST# or by issuing an

appropriate suspend command.

Table 20. Command Bus Cycles (Sheet 1 of 2)

Mode Command Bus

Cycles

First Bus Cycle Second Bus Cycle

Oper Addr(1) Data(2) Oper Addr(1) Data(2)

Read

Read Array 1 Write DBA 0xFF - - -

Read Device Identifier ≥ 2 Write DBA 0x90 Read DBA + IA ID

CFI Query ≥ 2 Write DBA 0x98 Read DBA + QA QD

Read Status Register 2 Write DBA 0x70 Read DBA SRD

Clear Stat u s Re gist er 1 Write DB A 0x 50 - - -

Program

Word Program 2 Write WA 0x40/

0x10 Write WA WD

Buffered Program(3) > 2 Write WA 0xE8 Write WA N - 1

Buffered Enhanced Factory

Program (BEFP)(4) > 2 Write WA 0x80 Write WA 0xD0

Erase Block Er ase 2 Write BA 0x20 Write BA 0xD0

Suspend Program/Erase Suspend 1 Write DBA 0xB0 - - -

Program/Erase Resume 1 Write DBA 0xD0 - - -

Block

Locking/

Unlocking

Lock Block 2 Write BA 0x60 Write BA 0x01

Unlock B lock 2 Write BA 0x60 Write BA 0xD0

Lock-dow n Block 2 Write BA 0x60 Write BA 0x2F

1-Gbit P30 Family

Datasheet Intel StrataFlash® Embedded Memory (P30) April 2005

Order Number: 306666, Revision: 001 51

9.3 Command Definitions

Valid device command codes and descriptions are shown in Table 21.

Protection Program Protection Register 2 Write PRA 0xC0 Write PRA PD

Pro gr am Lo c k R e gi ster 2 Wri te LRA 0xC0 W rite LRA LRD

Configuration Program Read Configuration

Notes:

1. First command cycle address should be the same as the operat ion’s tar get address.

DBA = Device Base Address (NOTE: needed for 2 or more die stacks)

IA = Identificati on code address offset.

QA = CFI Query address offset.

WA = Word address of memory location to be written.

BA = Address within the block.

PRA = Protection Register address.

LRA = Lock R egister address.

RCD = Read Configuration Register data on A[15:0].

2. ID = Identifier dat a.

QD = Qu er y da ta on DQ[ 15 :0 ].

SRD = Status Register data.

WD = Word data.

N = Wo rd count of data to be loaded into the write buffer.

PD = Protection Register data.

LRD = Lock Register data.

3. The secon d cy cle of t he Buffered Pr ogr am Comma nd i s t he word co unt of the data to be l oaded i nt o the w rit e bu ff er. Th is

is followed by up to 32 words of data.Th en the conf irm command (0xD0) is issued, trigge ring the array programming

operation.

4. The conf irm command (0xD0) is foll owed by the buffer data.

Table 20. Command Bus Cycles (Sheet 2 of 2)

Mode Command Bus

Cycles

Fir s t Bu s Cy cle Secon d B us C yc le

Oper Addr(1) Data(2) Oper Addr(1) Data(2)

Table 21. Command Codes and Definit i ons (Sheet 1 of 2)

Mode Code Device Mode Description

Read

0xFF Read Array Places the device in Read Arra y mode. Ar ray dat a is output on DQ[15:0].

0x70 Read Status Register Pla ces the device in Read Status Regis ter mode. The device enters this mode

after a program or erase command is iss ued. Status Register data is output on

DQ[7:0].

0x90 Read Device ID

or Configuration

Places device in Read Device Identifier mode. Subsequent reads output

manufactu rer/device codes, Configuration Register data, Block Lock status , or

Protection Register data on DQ[15:0].

0x98 Read Query Places the device in Read Quer y m ode. Subsequent reads output Common

Flash Interface information on DQ[7:0].

0x50 Clear Status Register The WSM can only set Stat us Register error bits. The Clear Status Register

command is used to clear the SR error bits.

Write 0x40 Word Program Setup

First cycle of a 2-cycle programming comman d; prepares the CUI for a write

oper ation. On the next writ e cycle, the address and data are latched and the

WSM executes the progr amming algorithm at the addressed location. During

pro gram operations, the device responds on ly to Read Status Re gister and

Program Sus pend commands. CE# or OE# must be toggl ed to update the

S t atus Reg ister in asynchr onou s read. CE# or ADV# must be toggle d to upda te

the Status Register Data for synchronous Non-array reads. The Read Array

command must be issued to re ad array data af ter programming has finished.

1-Gbit P30 Family

April 2005 Intel StrataFlash® Embedded Memory (P30) Datasheet

52 Order Number: 306666, Revision: 001

Write

0x10 Altern ate Word

Program Se tup Equivalent to the Word Program Setup command, 0x40.

0xE8 Buffered Pr ogram T hi s com m a nd lo ads a vari a ble num b er of wo rd s up t o th e bu ffer s iz e of 32

wor d s ont o th e progr am buffer.

0xD0 Buffered Program

Confirm

The confirm command is Issu ed after the data streaming for writing into the

buffer is done. This instruct s the WSM to perform the Buffered Program

algor ithm, writing the data from the buff er to the flash memory array.

0x80 BEF P Se tu p

First cycle of a 2-cycle comma nd; initiates Buffered Enhanced Factory

Program mode (BEFP). The CUI then waits for the BEFP Confirm command,

0xD0, that initiates the BEFP algorithm. All other commands are ignored when

BEFP mode begins.

0xD0 BEFP Co nfirm If the prev ious c omman d w as BE FP Se tup ( 0x8 0), t he CUI la tch es t he add ress

and data, and prepares the device for BEFP mode.

Erase

0x20 Block Erase Setup

Firs t cycle of a 2-cycle command; prepar es the CUI for a block-erase

operation. The WSM performs the erase algorithm on the block addressed by

the Erase Confirm command. If the next command is not the Erase Confirm

(0xD0) command, the CUI sets Status Register bits SR[ 4] and SR [5], and

places the device in read status register mode.

0xD0 Block Erase Confirm

If the first command was Block Erase Setup (0x20), the CUI latches the

address and data, and the WSM erases the addressed block. During block-

eras e operations, the device respon ds only to Read Status Register and Erase

Suspend commands. CE# or OE# must be toggled to update the Status

Status Register Data for synchronous Non-array reads

Suspend 0xB0 Program or Er a s e

Suspend

This command issued to any device address initiates a suspend of the

currently-executing program or block era s e operation. The Status Register

indicates successful suspend operation by setting either SR[2] (program

suspended) or SR[6] (erase suspended), along with SR[7] (ready). The Write

S ta te Machi ne remains in the suspen d mode regardle ss of cont rol signa l sta tes

(except for RST# asserted).

0xD0 Suspend Resume This command issu ed t o any devi ce add ress r esu mes the su spen ded progr am

or block-erase operation.

Bloc k Lockin g/

Unlocking

0x60 Lock Block Setup

First cycl e o f a 2- cyc le comma nd; pre p ar es the CUI f or block lo ck co nf igur atio n

changes. If the ne xt command is not Block Lock (0x01), Block Unlock (0xD0),

or Block Lock -Do wn (0 x2F) , the C UI se t s Stat us Regi ster bi ts S R[4] an d SR[5] ,

indicating a command sequence error.

0x01 Lock Block If the previous command was Bloc k Lock Setup ( 0x60), the addressed block is

locked.

0xD0 Unlock Block If the previous command was Block Lock Setup (0x60), the addressed block is

unlocked. If the addressed block is in a lock-down st ate, the operation has no

effect.

0x2F Lock-Down Block If the previous command was Bloc k Lock Setup (0x60), the addressed block is

locked down.

Protection 0xC0 Program Protection

First cy cle of a 2 -cycl e comma nd; pr ep are s t he d evi ce for a Prot ect ion Re giste r

or Loc k Registe r program operation. The second cycle latches the regist er

addr ess and data, and starts the programming algorithm

Configuration

0x60 Read Configuration

Firs t cycle of a 2-cycle command; prepar es the CUI for device read

configuration. If the Set Read Configuration Register command (0x03) is not

the next command, the CUI sets S tatus Register bits SR[4] and SR[5],

indicating a command sequence error.

0x03 Read Configuration

If the previous command was Read Configuration Register Setup (0x60), the

CUI l atc hes t he add ress and w rit es A[15 :0 ] to th e Re ad Co nf ig urat io n Reg is te r.

Following a C onfigur e Read Configuration Register command, subseq uent

read operations access array data.

Table 21. Command Codes and Definitions (Sheet 2 of 2)

Mode Code Device Mode Descriptio n

1-Gbit P30 Family

Datasheet Intel StrataFlash® Embedded Memory (P30) April 2005

Order Number: 306666, Revision: 001 53

10.0 Read Operations

The device supports two read modes: asynchronous page mode and synchronous burst mode.

Asynchronous page mode is the default read mode after device power-up or a reset. The Read

Configuration Register must be configured to enable synchronous burst reads of the flash memory

array (see Section 10.3, “Read Configuration Register” on page 54).

The device can be in any of four read states: Read Array, Read Identifier, Read Status or Read

Query. Upon power-up, or after a reset, the device defaults to Read Array. To change the read state,

the appropriate read command must be written to the device (see Section 9.2, “Device Commands”

on page 50). See Section 14.0, “Special Read States” on page 75 for details regarding Read Status,

Read ID, and CFI Query modes.

The following sections describe read-mode operations in detail.

10.1 Asynchronous Page-Mode Read

Following a device power-up or reset, asynchronous page mode is the default read mode and the

device is set to Read Array. However, to perform array reads after any other device operation (e.g.

write operation), the Read Array command must be issued in order to read from the flash memory

array.

Note: Asynchronous page-mode reads can only be performed when Read Configuration Register bit

RCR[15] is set ( see Section 10.3, “Read Configuration Register” on page 54).

To perform an asynchronous page-mode read, an address is driven onto the Address bus, and CE#

and ADV# are asserted. WE# and RST# must already have been deasserted. WAIT is deasserted

during asynchronous page mode. ADV# can be driven high to latch the address, or it must be held

low throughout the read cycle. CLK is not used for asynchronous page-mode reads, and is ignored.

If only asynchronous reads are to be performed, CLK should be tied to a valid VIH level, WAIT

signal can be floated and ADV# must be tied to ground. Array data is driven onto DQ[15:0] after

an initial access time tAVQV delay. (see Section 7.0, “AC Characteristics” on page 33).

In asynchronous page mode, four data words are “sensed” simultaneously from the flash memory

array and loaded into an internal page buffer. The buffer word corresponding to the initial address

on the Address bus is driven onto DQ[15:0] after the initial access delay. The lowest two address

bits determine which word of the 4-word page is output from the data buffer at any given time.

10.2 Synchronous Burst-Mode Read

To perform a synchronous burst- read, an initial address is driven onto the Address bus, and CE#

and ADV# are asserted. WE# and RST# must already have been deasserted. ADV# is a sserted, and

then deasserted to latch the address. Alternately, ADV# can remain asserted throughout the burst

access, in which case the address is latched on the next valid CLK edge while ADV# is asserted.

During synchronous array and non-array read modes, the first word is output from the data buffer

on the next valid CLK edge after the initial access latency delay (see Section 10.3.2, “Latency

Count” on page 55). Subsequent data is output on valid CLK edges following a minimum delay.

1-Gbit P30 Family

April 2005 Intel StrataFlash® Embedded Memory (P30) Datasheet

54 Order Number: 306666, Revision: 001

However, for a synchronous non-array read, the same word of data will be output on successive

clock edges until the burst length requirements are satisfied. Refer to the following waveforms for

more detailed information:

•Figure 19, “Synchronous Single-Word Array or Non-array Read Timing” on page 39

•Figure 20, “Continuous Burst Read, showing an Output Delay Timing” on page 40

•Figure 21, “Synchronous Burst-Mode Four-Word Read Timing” on page 41

10.3 Read Configuration Register

The Read Configuration Register (RCR) is used to select the read mode (synchronous or

asynchronous), and it defines the synchronous burst characteristics of the device. To modify RCR

settings, use the Configure Read Configuration Register command (see Section 9.2, “Device

Commands” on page 50).

RCR contents can be examined using the Read Device Identifier command, and then reading from

offset 0x05 (see Section 14.2, “Read Device Identifier” on page 76).

The RCR is shown in Table 22. The following sections describe each RCR bit.

Table 22. Read Configuration Register Description (Sheet 1 of 2)

Read Configura tion Regist er (RCR)

Read

Mode RES Latency Count WAIT

Polarity Data

Hold WAIT

Delay Burst

Seq CLK

Edge RES RES Burst

Wrap Burst Length

RM RLC[2:0] WP DH WD BS CE R R BW BL[2:0]

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit Name Description

15 Read Mode (RM) 0 = Synchronous bu rst-mode read

1 = Asynchronous page- mode read (default)

14 Reserved (R) Reserved bits should be cleared (0)

13:11 Latency Count (LC[2:0]) 010 =Code 2

011 =Code 3

100 =Code 4

101 =Code 5

110 =Code 6

111 =Code 7 (default)

(Other bit settings are reserved)

10 Wait Polarity (WP) 0 =WAIT signal is active low

1 =WAIT signal is ac ti v e hi gh (d e fa ul t)

9 Data Hold (DH) 0 =Data held for a 1-clock data cycle

1 =Data hel d for a 2- clock data cycle (default)

8 Wait Delay (WD) 0 =WAIT deasserted with valid data

1 =WAIT deasserted one data cycle before valid data (default)

7 Burs t Se qu ence (BS ) 0 =Res er v e d

1 =Linear (default)

6 Clock Edge (CE) 0 = Falling edge

1 = Rising edge (default)

5:4 Reserved (R) Reserved bits should be cleared (0)

1-Gbit P30 Family

Datasheet Intel StrataFlash® Embedded Memory (P30) April 2005

Order Number: 306666, Revision: 001 55

10.3.1 Read Mode

The Read Mode (RM) bit selects synchronous burst-mode or asynchronous page-mode operation

for the device. When the RM bit is set, asynchronous page mode is selected (default). When RM is

cleared, synchronous burst mode is selected.

10.3.2 Latency Count

The Latency Count bits, LC[2:0], tell the device how many clock cycles must elapse from the

rising edge of ADV# (or from the first valid clock edge after ADV# is asserted) until the first data

word is to be driven onto DQ[15:0]. The input clock frequency is used to determine this value.

Figure 28 shows the data output latency for the different settings of LC[2:0].

Synchronous burst with a Latency Count setting of Code 4 will result in zero WAIT state; however ,

a Latency Count setting of Code 5 will cause 1 WAIT state (Code 6 will cause 2 WAIT states, and

Code 7 will cause 3 WAIT states) after every four words, regardless of whether a 16-word

boundary is crossed. If RCR[9] (Data Hold) bit is set (data hold of two clocks) this WAIT condition

will not occur because enough clocks elapse during each burst cycle to eliminate subsequent WAIT

states.

Refer to Table 23, “LC and Frequency Support” on page 56 for Latency Code Settings.

3 Burs t Wrap (BW) 0 =Wrap; Burst accesses wrap within burs t length set by BL[2:0]

1 =No Wrap; Burs t accesses do not wrap within burs t lengt h (defaul t)

2:0 Burst Length (BL[2:0] ) 001 =4-word burst

010 =8-word burst

011 =16-word burst

111 =Continuous-word burst (default)

(Other bit settings are reserved)

Note: Latency C ode 2, Dat a Hold for a 2-cl ock d ata cycl e ( DH = 1 ) WAIT must be deass er t ed wit h val id d at a (W D =

0). Latency Code 2, Data Hold for a 2- cock data cycle (DH=1) WAIT deasserted one data cycle before valid

data (WD = 1) combination is not s upported.

Table 22. Read Configuration Register Description (Sheet 2 of 2)

1-Gbit P30 Family

April 2005 Intel StrataFlash® Embedded Memory (P30) Datasheet

56 Order Number: 306666, Revision: 001

See Figure 29, “Example Latency Count Setting using Code 3.

Figure 28. First-Acce ss Latency Count

Code 1

(Reserved

Code 6

Code 5

Code 4

Code 3

Code 2

Code 0 (R eserved)

Code 7

Valid

Address

Valid

Output Valid

Output

Valid

Output Valid

Output

Valid

Output Valid

Output

Valid

Output Valid

Output

Valid

Output Valid

Output

Valid

Output Valid

Output

Valid

Output Valid

Output

Valid

Output

Address [A]

ADV# [V]

DQ15-0 [D/Q]

CLK [C]

DQ15-0 [D/Q]

Table 23. LC and Frequency Support

Latency Count Settings Frequency Support (MHz)

2≤ 27

3≤ 40

1-Gbit P30 Family

Datasheet Intel StrataFlash® Embedded Memory (P30) April 2005

Order Number: 306666, Revision: 001 57

10.3.3 WAIT Polarity

The WAIT Polarity bit (WP), RCR[10] determines the asserted level (VOH or VOL) of WAIT.

When WP is set, WAIT is asserted high (default). When WP is cleared, WAIT is asserted low.

WAIT changes state on valid clock edges during active bus cycles (CE# asserted, OE# asserted,

RST# deasserted).

10.3.3.1 WAIT Signa l Function

The WAIT signal indicates data valid when the device is operating in synchronous mode

(RCR[15]=0). The WAIT signal is only “deasserted” when data is valid on the bus.

When the device is operating in synchronous non-array read mode, such as read status, read ID, or

read query. The WAIT signal is also “deasserted” when data is valid on the bus.

WAIT behavior during synchronous non-array reads at the end of word line works correctly only

on the first data access.

When the device is operating in asynchronous page mode, asynchronous single word read mode,

and all write operations, WAIT is set to a deasserted state as determined by RCR[10]. See Figure

17, “Asynchronous Single-Word Read (ADV# Latch)” on page 38, and Figure 18, “Asynchronous

Page-Mode Read Timing” on page 39.

Figure 29. Example Latency Count Setting using Code 3

CLK

CE#

ADV#

A[MAX:0]

D[15:0]

tData

Code 3

Address

Data

012

R103

High-Z

1-Gbit P30 Family

April 2005 Intel StrataFlash® Embedded Memory (P30) Datasheet

58 Order Number: 306666, Revision: 001

10.3.4 Dat a Hold

For burst read operations, the Data Hold (DH) bit determines whether the data output remains valid

on DQ[15:0] for one or two clock cycles. This period of time is called the “dat a cycle ”. When DH

is set, output data is held for two clocks (default). When DH is cleared, output data is held for one

clock (see Figure 30). The processor’s data setup time and the flash memory’s clock-to-data output

delay should be considered when determining whether to hold output data for one or two clocks. A

method for determining the Data Hold configuration is shown below:

To set the device at one clock data hold for subsequent reads, the following condition must be

satisfied:tCHQV (ns) + tDATA (ns) ≤ One CLK Period (ns)

tDATA = Data set up to Clock (defined by CPU)

For example, with a clock frequency of 40 MHz, the clock period is 25 ns. Assuming

tCHQV = 20 ns and tDATA = 4 ns. Applying these values to the formula above:

20 ns + 4 ns ≤ 25 ns

The equation is satisfied and data will be available at every clock period with data hold setting at

one clock. If tCHQV (ns) + tDATA (ns) > One CLK Period (ns), data hold setting of 2 clock periods

must be used.

Table 24. WAIT Functionality Table

Condition WAIT Notes

CE# = ‘1’, OE# = ‘X’ or CE# = ‘0’, OE# = ‘1’ High -Z 1

CE# =’0’, OE# = ‘0’ Active 1

Synchronous Array R eads Active 1

Synchronous Non-Array Re ads Active 1

All Async hr onous Reads Deasserted 1

All Wr ites High- Z 1,2

Notes:

1. Active: WAIT is asserted until data becomes vali d, then deasserts

2. When OE# = VIH during writes, WAIT = High- Z

Figure 30. Data Hold Timing

Valid

Output

Valid

Output

Valid

Output Valid

Output

CLK [C]

D[15:0] [Q]

2 CLK

Data Hold

1 CLK

Data Hold

1-Gbit P30 Family

Datasheet Intel StrataFlash® Embedded Memory (P30) April 2005

Order Number: 306666, Revision: 001 59

10.3.5 WAIT Delay

The WAIT Delay (WD) bit controls the WAIT assertion-delay behavior during synchronous burst

reads. WAIT can be asserted either during or one data cycle before valid data is output on

DQ[15:0]. When WD is set, WAIT is deasserted one data cycle before valid data (default). When

WD is cleared, WAIT is deasserted during valid data.

10.3.6 Burst Sequence

The Burst Sequence (BS) bit selects linear-burst sequence (default). Only linear-burst sequence is

supported. Table 25 shows the synchronous burst sequence for all burst lengths, as well as the

effect of the Burst Wrap (BW) setting.

10.3.7 Clock Edge

The Clock Edge (CE) bit selects either a rising (default) or falling clock edge for CLK. This clock

edge is used at the start of a burst cycle, to output synchronous data, and to assert/deassert WAIT.

10.3.8 Burst Wrap

The Burst Wrap (BW) bit determines whether 4-word, 8-word, or 16-word burst length accesses

wrap within the selected word-length boundaries or cross word-length boundaries. When BW is

set, burst wrapping does not occur (default). When BW is cleared, burst wrapping occurs.

When performing synchronous burst reads with BW set (no wrap), an output delay may occur

when the burst sequence crosses its first device-row (16-word) boundary. If the burst sequence’s

start address is 4-word aligned, then no delay occurs. If the start address is at the end of a 4-word

Table 25. Burst Se quence Word Ordering

Start

Addr.

(DEC) Burst Wra p

(RCR[3])

Burst Addressing Sequence (DEC)

4-Word Burst

(BL[2:0] = 0b001) 8-Word Burst

(BL[2:0] = 0b010) 16-Word Burst

(BL[2:0] = 0b011) Contin uous Burst

(BL[2:0] = 0b111)

0 0 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-4…14-15 0-1-2-3-4-5-6-…

1 0 1-2-3-0 1-2-3-4-5-6-7-0 1-2-3-4-5…15-0 1-2-3-4-5-6-7-…

2 0 2-3-0-1 2-3-4-5-6-7-0-1 2-3-4-5-6…15-0-1 2-3-4-5-6-7-8-…

3 0 3-0-1-2 3-4-5-6-7-0-1-2 3-4-5-6-7…15-0-1-2 3-4-5-6-7-8-9-…

40 4-5-6-7-0-1-2-3 4-5-6-7-8…15-0-1-2-3 4-5-6-7-8-9-10…

50 5-6-7-0-1-2-3-4 5-6-7-8-9…15-0-1-2-3-4 5-6-7-8-9-10-11…

60 6-7-0-1-2-3-4-5 6-7-8-9-10…15-0-1-2-3-4-5 6-7-8-9-10-11-12-…

70 7-0-1-2-3-4-5-6 7-8-9-10…15-0-1-2-3-4-5-6 7-8-9-10-11-12-13…

…

14 0 14-15-0-1-2…12-13 14-15-16-17-18-19-20-…

15 0 15-0-1-2-3…13-14 15-16-17-18-19-20-21-…

…

0 1 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-4…14-15 0-1-2-3-4-5-6-…

1 1 1-2-3-4 1-2-3-4-5-6-7-8 1-2-3-4-5…15-16 1-2-3-4-5-6-7-…

2 1 2-3-4-5 2-3-4-5-6-7-8-9 2-3-4-5-6…16-17 2-3-4-5-6-7-8-…

3 1 3-4-5-6 3-4-5-6-7-8-9-10 3-4-5-6-7…17-18 3-4-5-6-7-8-9-…

41 4-5-6-7-8-9-10-11 4-5-6-7-8…18-19 4-5-6-7-8-9-10…

51 5-6-7-8-9-10-11-12 5-6-7-8-9…19-20 5-6-7-8-9-10-11…

61 6-7-8-9-10-11-12-13 6-7-8-9-10…20-21 6-7-8-9-10-11-12-…

71 7-8-9-10-11-12-13-14 7-8-9-10-11…21-22 7-8-9-10-11-12-13…

…

14 1 14-15-16-17-18…28-29 14-15-16-17-18-19-20-…

15 1 15-16-17-18-19…29-30 15-16-17-18-19-20-21-…

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boundary, the worst case output delay is one clock cycle less than the first access Latency Count.

This delay can take place only once, and doesn’t occur if the burst sequence does not cross a

device-row boundary. WAIT informs the system of this delay when it occurs.

10.3.9 Burst Length

The Burst Length bit (BL[2:0]) selects the linear burst length for all synchronous burst reads of the

flash memory array. The burst lengths are 4-word, 8-word, 16-word, and continuous word.

Continuous-burst accesses are linear only, and do not wrap within any word length boundaries (see

Table 25, “Burst Sequence Word Ordering” on page 59). When a burst cycle begins, the device

outputs synchronous burst data until it reaches the end of the “burstable” address space.

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11.0 Programming Operations

The device supports three programming methods: Word Programming (40h/10h), Buffered

Programming (E8h, D0h), and Buffered Enhanced Factory Programming (80h, D0h). See Section

9.0, “Device Operations” on page 48 for details on the various programming commands issued to

the device. The following sections describe device programming in detail.

Successful programming requires the addressed block to be unlocked. If the block is locked down,

WP# must be deasserted and the block must be unlocked before attempting to program the block.

Attempting to program a locked block causes a program error (SR[4] and SR[1] set) and

termination of the operation. See Section 13.0, “Security Modes” on page 69 for details on locking

and unlocking blocks.

The Intel StrataFlash® Embedded Memory (P30) is segmented into multiple Programming

Regions. Programming Regions are made up of 8 or 16 blocks depending on the density. The 64-

and 128-Mbit devices have 8 blocks per Programming Region, while the 256-Mbit has 16 blocks in

each Programming Region (see Table 26). See Section 4.4, “Memory Maps” on page 24 for

address ranges of each Programming Region per density.

Execute in Place (XIP) is defined as the ability to execute code directly from the flash memory.

XIP applications must partition the memory such that code and data are in separate programming

regions (see Table 26, “Programming Regions per Device” on page 61). Each Programming

Region should contain only code or data, and not both. The following terms define the difference

between code and data. System designs must use these definitions when partitioning their code and

data for the P30 device.

11.1 Word Programming

Word programming operations are initiated by writing the Word Program Setup command to the

device (see Section 9.0, “Device Operations” on page 48). This is followed by a second write to the

device with the address and data to be programmed. The device outputs Status Register data when

read. See Figure 40, “Word Program Flowchart” on page 85. V PP must be above VPPLK, and within

the specified VPPL min/max values (nominally 1.8 V).

Table 26. Programming Regions per Device

Device Density Number of blocks per

Programming Region Numb er of Pr og ra mm ing

Regi ons per De v ic e

64-Mbit 8 bloc ks 8

128 - M bit 8 blocks 16

256-M bit 16 b locks 16

512-M bit 16 b locks 32

1-Gb it 16 blocks 64

Code : Execution code ran out of the flash device on a continuous basis in the system.

Data : Information periodically programmed into the flash device and read back (e.g.

execution code shadowed and executed in RAM, pictures, log files, etc.).

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During programming, the Write State Machine (WSM) executes a sequence of internally-timed

events that program the desired data bits at the addressed location, and verifies that the bits are

sufficiently programmed. Programming the flash memory array changes “ones” to “zeros”.

Memory array bits that are zeros can be changed to ones only by erasing the block (see Section

12.0, “Erase Operations” on page 67).

The Status Register can be examined for programming progress and errors by reading at any

address. The device remains in the Read Status Register state until another command is written to

the device.

Status Register bit SR[7] indicates the programming status while the sequence executes.

Commands that can be issued to the device during programming are Program Suspend, Read Status

When programming has finished, Status Register bit SR[4] (when set) indicates a programming

failure. If SR[3] is set, the WSM could not perform the word programming operation because VPP

was outside of its acceptable limits. If SR[1] is set, the word programming operation attempted to

program a locked block, causing the operation to abort.

Before issuing a new command, the Status Register contents should be examined and then cleared

using the Clear Status Register command. Any valid command can follow, when word

programming has completed.

11.1.1 Factory Word Programming

Factory word programming is similar to word programming in that it uses the same commands and

programming algorithms. However, factory word programming enhances the programming

performance with VPP = VPPH. This can enable faster programming times during OEM

manufacturing processes. Factory word programming is not i ntended for e xtended use. See Sec tion

5.2, “Operating Conditions” on page 30 for limitations when VPP = VPPH.

Note: When VPP = VPPL, the device draws programming current from the VCC supply. If VPP is driven

by a logic signal, VPPL must remain above VPPL MIN to program the device. When VPP = VPPH,

the device draws programming current from the VPP supply. Figure 31, “Example VPP Supply

Connections” on page 66 shows examples of device power supply configurations.

11.2 Buffered Programming

The device features a 32-word buffer to enable optimum programming performance. For Buffered

Programming, data is first written to an on-chip write buffer. Then the buffer data is programmed

into the flash memory array in buffer-size increments. This can improve system programming

performance significantly over non-buffered programming.

When the Buffered Programming Setup command is issued (see Section 9.2, “Device Commands”

on page 50), Status Register information is updated and reflects the availability of the buffer. SR[7]

indicates buffer availability: if set, the buffer is available; if cleared, the buffer is not available. To

retry, issue the Buffered Programming Setup command again, and re-check SR[7]. When SR[7] is

set, the buffer is ready for loading. (see Figure 42, “Buffer Program Flowchart” on page 87).

On the next write, a word count is written to the device at the buffer address. This tells the device

how many data words will be written to the buffer, up to the maximum size of the buffer.

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On the next write, a device start address is given along with the first data to be written to the flash

memory array. Subsequent writes provide additional device addresses and data. All data addresses

must lie within the start address plus the word count. Optimum programming performance and

lower power usage are obtained by aligning the starting address at the beginning of a 32-word

boundary (A[4:0] = 0x00). Crossing a 32-word boundary during programming will double the total

programming time.

After the last data is written to the buffer, the Buffered Programming Confirm command must be

issued to the original block address. The WSM begins to program buffer contents to the flash

memory array . I f a command other than the Buffered Programming Confirm command is written to

the device, a command sequence error occurs and Status Register bits SR[7,5,4] are set. If an error

occurs while writing to the array, the device stops programming, and Status Register bits SR[7,4]

are set, indicating a programming failure.

When Buffered Programming has completed, additional buffer writes can be initiated by issuing

another Buffered Programming Setup command and repeating the buffered program sequence.

Buffered programming may be performed with VPP = VPPL or VPPH (see Section 5.2, “Operating

Conditions” on page 30 for limitations when operating the device with VPP = VPPH).

If an attempt is made to program past an erase-block boundary using the Buffered Program

command, the device aborts the operation. This generates a command sequence error, and Status

If Buffered programming is attempted while VPP is below VPPLK, Status Register bits SR[4,3] are

set. If any errors are detected that have set Status Register bits, the Status Register should be

cleared using the Clear Status Register command.

11.3 Buffered Enhanced Factory Programming

Buffered Enhanced Factory Programing (BEFP) speeds up Multi-Level Cell (MLC) flash

programming. The enhanced programming algorithm used in BEFP eliminates traditional

programming elements that drive up overhead in device programmer systems.

BEFP consists of three phases: Setup, Program/Verify, and Exit (see Figure 43, “BEFP Flowchart”

on page 88). It uses a write buffer to spread MLC program performance across 32 data words.

Verification occurs in the same phase as programming to accurately program the flash memory cell

to the correct bit state.

A single two-cycle command sequence programs the entire block of data. This enhancement

eliminates three write cycles per buffer: two commands and the word count for each set of 32 data

words. Host programmer bus cycles fill the device’ s write buf fer followed by a status check. SR[0]

indicates when data from the buffer has been programmed into sequential flash memory array

locations.

Following the buffer-to-flash array programming sequence, the Write State Machine (WSM)

increments internal addressing to automatically select the next 32-word array boundary. This

aspect of BEFP saves host programming equipment the address-bus setup overhead.

With adequate continuity testing, programming equipment can rely on the WSM’s internal

verification to ensure that the device has programmed properly. This eliminates the external post-

program verific ation and its associated overhead.

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11.3.1 BEFP Requirements and Considerations

BEFP requirements:

•Case temperature: TC = 25 °C ± 5 °C

•VCC within specified operating range

•VPP driven to VPPH

•Target block unlocked before issuing the BEFP Setup and Confirm commands

•The first-word address (WA0) for the block to be programmed must be held constant from the

setup phase through all data streaming into the target block, until transition to the exit phase is

desired

•WA0 must align with the start of an array buffer boundary1

BEFP considerations:

•For optimum performance, cycling must be limited below 100 erase cycles per block2

•BEFP programs one block at a time; all buffer data must fall within a single block3

•BEFP cannot be suspended

•Programming to the flash memory array can occur only when the buffer is full4

NOTES:

1. Word buffer boundaries in the arr ay are deter m ined by A[4: 0] (0x00 through 0x1F ). The alignment start

point is A[4:0] = 0x00.

2. Some degradation in per formanc e m ay occur if this l imit is exceeded, but th e internal alg orithm

continues to work properly.

3. If the internal address co unt er increments beyond the block's maximum addre ss, addr essing wraps

around to the be ginning of the block.

4. If the number of words is less than 32 , rem aining locations m ust be filled with 0xFFFF.

11.3.2 BEFP Setup Phase

After receiving the BEFP Setup and Confirm command sequence, Status Register bit SR[7]

(Ready) is cleared, indicating that the WSM is busy with BEFP algorithm startup. A delay before

checking SR[7] is required to allow the WSM enough time to perform all of its setups and checks

(Block-Lock status, VPP level, etc.). If an error is detected, SR[4] is set and BEFP operation

terminates. If the block was found to be locked, SR[1] is also set. SR[3] is set if the error occurred

due to an incorrect VPP level.

Note: Reading from the device after the BEFP Setup and Confirm command sequence outputs Status

loaded into the buffer.

11.3.3 BEFP Program/Verify Phase

After the BEFP Setup Phase has completed, the host programming system must check SR[7,0] to

determine the availability of the write buffer for data streaming. SR[7] cleared indicates the device

is busy and the BEFP program/verify phase is activated. SR[0] indicates the write buffer is

available.

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Two basic sequences repeat in this phase: loading of the write buffer, followed by buffer data

programming to the array. For BEFP, the count value for buffer loading is always the maximum

buffer size of 32 words. During the buffer-loading sequence, data is stored to sequential buffer

locations starting at address 0x00. Programming of the buffer contents to the flash memory array

starts as soon as the buffer is full. If the number of words is less than 32, the remaining buffer

locations must be filled with 0xFFFF.

Caution: The buffer must be completely filled for programming to occur. Supplying an addr ess outside of t he

current block's range during a buffer-fill sequence causes the algorithm to exit immediately. Any

data previously loaded into the buffer during the fill cycle is not programmed into the array.

The starting address for data entry must be buffer size aligned, if not the BEFP algorithm will be

aborted and the program fails and (SR[4]) flag will be set.

Data words from the write buffer are directed to sequential memory locations in the flash memory

array; programming continues from where the previous buffer sequence ended. The host

programming system must poll SR[0] to determine when the buffer program sequence completes.

SR[0] cleared indicates that all buffer data has been transferred to the flash array; SR[0] set

indicates that the buffer is not available yet for the next fill cycle. The host system may check full

status for errors at any time, but it is only necessary on a block basis after BEFP exit. After the

buffer fill cycle, no write cycles should be issued to the device until SR[0] = 0 and the device is

ready for the next buffer fill.

Note: Any spurious writes are ignored after a buffer fill operation and when internal program is

proceeding.

The host programming system continues the BEFP algorithm by providing the next group of data

words to be written to the buffer. Alternatively, it can terminate this phase by changing the block

address to one outside of the current block’s range.

The Program/Verify phase concludes when the programmer writes to a different block address;

data supplied must be 0xFFFF. Upon Program/Verify phase completion, the device enters the

BEFP Exit phase.

11.3.4 BEFP Exit Phase

When SR[7] is set, the device has returned to normal operating conditions. A full status check

should be performed at this time to ensure the entire block programmed successfully . When exiting

the BEFP algorithm with a block address change, the read mode will not change. After BEFP exit,

any valid command can be issued to the device.

11.4 Program Suspend

Issuing the Program Suspend command while programming suspends the programming operation.

This allows data to be accessed from the device other than the one being programmed. The

Program Suspend command can be issued to any device address. A program operation can be

suspended to perform reads only . Additionally, a program operation that is running during an erase

suspend can be suspended to perform a read operation (see Figure 41, “Program Suspend/Resume

Flowchart” on page 86).

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When a programming operation is executing, issuing the Program Suspend command requests the

WSM to suspend the programming algorithm at predetermined points. The device continues to

output Status Register data after the Program Suspend command is issued. Programming is

suspended when Status Register bits SR[7,2] are set. Suspend latency is specified in Section 7.5,

“Program and Erase Characteristics” on page 45.

To read data from the device, the Read Array command must be issued. Read Array, Read Status

program suspend.

During a program suspend, deasserting CE# places the device in standby, reducing active current.

VPP must remain at its programming level, and WP# must remain unchanged while in program

suspend. If RST# is asserted, the device is reset.

11.5 Program Resume

The Resume command instructs the device to continue programming, and automatically clears

Status Register bits SR[7,2]. This command can be written to any address. If error bits are set, the

S tatus Register should be cleared before issuing the next instruction. RST# must remain deasserted

(see Figure 41, “Program Suspend/Resume Flowchart” on page 86).

11.6 Program Protection

When VPP = VIL, absolute hardware write protection is provided for all device blocks. If VPP is at

or below VPPLK, programming operations halt and SR[3] is set indicating a VPP-level error. Block

lock registers are not affected by the voltage level on VPP; they may still be programmed and read,

even if VPP is less than VPPLK.

Figure 31. Example VPP Supply Connections

• Factory Program m ing with VPP = VPPH

• Complete write/Erase Pr otect ion w hen VPP ≤ VPPLK

VCC

VPP

VCC

VPP

• Low Voltage and Factory Programming

• Low-volt age Programm ing only

• Logic Control of Device Protection

VCC

VPP

• Low Voltage P rogr am m ing Only

• Full Device Protection Unavailable

VCC

VPP

≤ 10K Ω

VPP

VCC VCC

PROT #

VCC

VPP=VPPH

VCC

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12.0 Erase Operations

Flash erasing is performed on a block basis. An entire block is erased each time an erase command

sequence is issued, and only one block is erased at a time. When a block is erased, all bits within

that block read as logical ones. The following sections describe block erase operations in detail.

12.1 Block Erase

Block erase operations are initiated by writing the Block Erase Setup command to the address of

the block to be erased (see Section 9.2, “Device Commands” on page 50). Next, the Block Erase

Confirm command is written to the address of the block to be erased. If the device is placed in

standby (CE# deasserted) during an erase operation, the device completes the erase operation

before entering standby.VPP must be above VPPLK and the block must be unlocked (see Figure 44,

“Block Erase Flowchart” on page 89).

During a block erase, the Write State Machine (WSM) executes a sequence of internally-timed

events that conditions, erases, and verifies all bits within the block. Erasing the flash memory array

changes “zeros” to “ones”. Memory array bits that are ones can be changed to zeros only by

programming the block (see Section 11.0, “Programming Operations” on page 61).

The Status Register can be examined for block erase progress and errors by reading any address.

The device remains in the Read Status Register state until another command is written. SR[0]

indicates whether the addressed block is erasing. Status Register bit SR[7] is set upon erase

completion.

Status Register bit SR[7] indicates block erase status while the sequence executes. When the erase

operation has finished, Status Register bit SR[5] indicates an erase failure if set. SR[3] set would

indicate that the WSM could not perform the erase operation because VPP was outside of its

acceptable limits. SR[1] set indicates that the erase operation attempted to erase a locked block,

causing the operation to abort.

Before issuing a new command, the Status Register contents should be examined and then cleared

using the Clear Status Register command. Any valid command can follow once the block erase

operation has completed.

12.2 Erase Suspend

Issuing the Erase Suspend command while erasing suspends the block erase operation. This allows

data to be accessed from memory locations other than the one being erased. The Erase Suspend

command can be issued to any device address. A block erase operation can be suspended to

perform a word or buffer program operation, or a read operation within any block except the block

that is erase suspended (see Figure 41, “Program Suspend/Resume Flowchart” on page 86).

When a block erase operation is executing, issuing the Erase Suspend command requests the WSM

to suspend the erase algorithm at predetermined points. The device continues to output Status

Characteristics” on page 45.

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To read data from the device (other than an erase-suspended block), the Read Array command must

be issued. During Erase Suspend, a Program command can be issued to any block other than the

erase-suspended block. Block erase cannot resume until program operations initiated during erase

susp end co mplete . Read Array, Read S tat us Regi ste r , Read Device Iden tifi er , CFI Query, and Er ase

Resume are valid commands during Erase Suspend. Additionally, Clear Status Register, Program,

Program Suspend, Block Lock, Block Unlock, and Block Lock-Down are valid commands during

Erase Suspend.

During an erase suspend, deasserting CE# places the device in standby, reducing active current.

VPP must remain at a valid level, and WP# must remain unchanged while in erase suspend. If

RST# is asserted, the device is reset.

12.3 Erase Resume

The Erase Resume command instructs the device to continue erasing, and automatically clears

status register bits SR[7,6]. This command can be written to any address. If status register error bits

are set, the Status Register should be cleared before issuing the next instruction. RST# must remain

deasserted (see Figure 41, “Program Suspend/Resume Flowchart” on page 86).

12.4 Erase Protection

When VPP = VIL, absolute hardware erase protection is provided for all device blocks. If VPP is

below VPPLK, erase operations halt and SR[3] is set indicating a VPP-level error.

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13.0 Security Modes

The device features security modes used to protect the information stored in the flash memory

array. The following sections describe each security mode in detail.

13.1 Block Locking

Individual instant block locking is used to protect user code and/or data within the flash memory

array. All blocks power up in a locked state to protect array data from being altered during power

transitions. Any block can be locked or unlocked with no latency. Locked blocks cannot be

programmed or erased; they can only be read.

Software-controlled security is implemented using the Block Lock and Block Unlock commands.

Hardware-controlled security can be implemented using the Block Lock-Down command along

with asserting WP#. Also, VPP data security can be used to inhibit program and erase operations

(see Section 11.6, “Program Protection” on page 66 and Section 12.4, “Erase Protection” on

page 68).

The P30 device also offers four pre-defined areas in the main array that can be configured as One-

Time Programmable (OTP) for the highest level of security. These include the four 32 KB

parameter blocks together as one and the three adjacent 128 KB main blocks. This is available for

top or bottom parameter devices.

13.1.1 Lock Block

To lock a block, issue the Lock Block Setup command. The next command must be the Lock Block

command issued to the desired block’s address (see Section 9.2, “Device Commands” on page 50

and Figure 46, “Block Lock Operations Flowchart” on page 91). If the Set Read Configuration

instead.

Block lock and unlock operations are not affected by the voltage level on VPP. The block lock bits

may be modified and/or read even if VPP is at or below VPPLK.

13.1.2 Unlock Block

The Unlock Block command is used to unlock blocks (see Section 9.2, “Device Commands” on

page 50). Unlocked blocks can be read, programmed, and erased. Unlocked blocks return to a

locked state when the device is reset or powered down. If a block is in a lock-down state, WP#

must be deasserted before it can be unlocked (see Figure 32, “Block Locking State Diagram” on

page 70).

13.1.3 Lock-Down Block

A locked or unlocked block can be locked-down by writing the Lock-Down Block command

sequence (see Section 9.2, “Device Commands” on page 50). Blocks in a lock-down state cannot

be programmed or erased; they can only be read. However , unlike locked blocks, their locked state

cannot be changed by software commands alone. A locked-down block can only be unlocked by

issuing the Unlock Block command with WP# deasserted. To return an unlocked block to locked-

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down state, a Lock-Down command must be issued prior to changing WP# to VIL. Locked-down

blocks revert to the locked state upon reset or power up the device (see Figure 32, “Block Locking

State Diagram” on page 70).

13.1.4 Block Lock Status

The Read Device Identifier command is used to determine a block’s lock status (see Section 14.2,

“Read Device Identifier” on page 76). Data bits DQ[1:0] display the addressed block’s lock status;

DQ0 is the addressed block’s lock bit, while DQ1 is the addressed block’s lock-down bit.

13.1.5 Block Locking During Suspend

Block lock and unlock changes can be performed during an erase suspend. To change block

locking during an erase operation, first issue the Erase Suspend command. Monitor the Status

another command.

Next, write the desired lock command sequence to a block, which changes the lock state of that

block. After completing block lock or unlock operations, resume the erase operation using the

Erase Resume command.

Note: A Lock Block Setup command followed by any command other than Lock Block, Unlock Block,

or Lock-Down Block produces a command sequence error and set Status Register bits SR[4] and

Figure 32. Block Locking State Diagram

[X00]

[X01]

Power-Up/Reset

Unlocked

Locked

[011]

[111] [110]

Locked-

Down4,5

Software

Locked

[011]

Hard w are

Locked5

Unlocked

W P # Hardware Con trol

Note s : 1. [a , b ,c] re p r e s en ts [ WP# , DQ 1 , DQ 0]. X = Do n’t Ca re .

2. DQ1 indicates Block Lock-D own status. DQ 1 = ‘0’, Lock-D own has not been issued

to this block. DQ 1 = ‘1’, Lock-Dow n has been issued to this block.

3. DQ0 indicates block lock status . DQ0 = ‘0’, block is un locked. D Q0 = ‘1’, block is

locke d.

4. Locked-down = Hardware + Software locked.

5. [011] states should be tracked by system softw are to determine difference between

Ha rdware Locked and Lo cked -D ow n states.

Software Block Lock (0x60/0x01) or Software B lock Unlock (0x60/0xD0)

Software Block Lock-Dow n (0x60 /0x2F)

W P# hardware control

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SR[5]. If a command sequence error occurs during an erase suspend, SR[4] and SR[5] remains set,

even after the erase operation is resumed. Unless the Status Register is cleared using the Clear

Status Register command before resuming the erase operation, possible erase errors may be

masked by the command sequence error.

If a block is locked or locked-down during an erase suspend of the same block, the lock status bits

change immediately. However, the erase operation completes when it is resumed. Block lock

operations cannot occur during a program suspend. See Appendix A, “Write State Machine” on

page 78, which shows valid commands during an erase suspend.

13.2 Selectable One-Time Programmable Blocks

Any of four pre-defined areas from the main array (the four 32 KB parameter blocks together as

one and the three adjacent 128 KB main blocks) can be configured as One-Time Programmable

(OTP) so further program and erase operations are not allowed. This option is available for top or

bottom parameter devices.

Please see your local Intel representative for details about the Selectable OTP implementation.

Table 27. Selectable OTP B lock Mapping

Density Top Parameter Configuration Bottom Parameter Configuration

256-Mbit

blocks 258:255 (par ameters) bloc ks 3: 0 (parameters)

block 254 (main) block 4 (main)

block 253 (main) block 5 (main)

block 252 (main) block 6 (main)

128-Mbit

blocks 130:127 (par ameters) bloc ks 3: 0 (parameters)

block 126 (main) block 4 (main)

block 125 (main) block 5 (main)

block 124 (main) block 6 (main)

64-Mbit

blocks 66:63 (parameters) blocks 3:0 (parameters)

block 62 (main) block 4 (mai n)

block 61 (main) block 5 (mai n)

block 60 (main) block 6 (mai n)

Note: The 512-M bit and 1- G bit devices will have mult iple S elect able OTP Areas depending on

the number of 256-Mbit dies in the stack and the placement of the p aramet er blocks.

1-Gbit P30 Family

April 2005 Intel StrataFlas h® Embedded Memory (P30) Datasheet

72 Order Number: 306666, Revision: 001

13.3 Protection Registers

The device contains 17 Protection Registers (PRs) that can be used to implement system security

measures and/or device identification. Each Protection Register can be individually locked.

The first 128-bit Protection Register is comprised of two 64-bit (8-word) segments. The lower 64-

bit segment is pre-programmed at the Intel factory with a unique 64-bit number. The other 64-bit

segment, as well as the other sixteen 128-bit Protection Registers, are blank. Users can program

these registers as needed. When programmed, users can then lock the Protection Register(s) to

prevent additional bit programming (see Figure 33, “Protection Register Map” on page 73).

The user-programmable Protection Registers contain one-time programmable (OTP) bits; when

programmed, register bits cannot be erased. Each Protection Register can be accessed multiple

times to program individual bits, as long as the register remains unlocked.

Each Protection Register has an associated Lock Register bit. When a Lock Register bit is

programmed, the associated Protection Register can only be read; it can no longer be programmed.

Additionally, because the Lock Register bits themselves are OTP, when programmed, Lock

unlocked.

1-Gbit P30 Family

Datasheet Intel StrataFlash® Embedded Memory (P30) April 2005

Order Number: 306666, Revision: 001 73

13.3.1 Reading the Protection Registers

The Protection Registers can be read from any address. To read the Protection Register, first issue

the Read Device Identifier command at any address to place the device in the Read Device

Identifier state (see Section 9.2, “Device Commands” on page 50). Next, perform a read operation

using the address offset corresponding to the register to be read. Table 29, “Device Identifier

Information” on page 77 shows the address offsets of the Protection Registers and Lock Registers.

13.3.2 Programming the Protection Registers

To program any of the Protection Registers, first issue the Program Protection Register command

at the parameter’s base address plus the offset to the desired Protection Register (see Section 9.2,

“Device Commands” on page 50). Next, write the desired Protection Register data to the same

Protection Register address (see Figure 33, “Protection Register Map” on page 73).

Figure 33. Protection Register Map

0x89 Lock Register 1

15 14 13 12 11 10 9876543210

0x102

0x109

0x8A

0x91

128-bi t Protection Register 16

(User-Programmable)

128 - bit P r otection Register 1

(User-Programmable)

0x88

0x85

64-bit Segmen t

(User-Programmable)

0x84

0x81

0x80 Lock Register 0

64-bit Segmen t

(Factory-Programmed)

15 14 13 12 11 10 9876543210

128-Bit Pr ot ec tio n Re gister 0

1-Gbit P30 Family

April 2005 Intel StrataFlas h® Embedded Memory (P30) Datasheet

74 Order Number: 306666, Revision: 001

The device programs the 64-bit and 128-bit user-programmable Protection Register data 16 bits at

a time (see Figure 47, “Protection Register Programming Flowchart” on page 92). Issuing the

Program Protection Register command outside of the Protection Register’s address space causes a

program error (SR[4] set). Attempting to program a locked Protection Register causes a program

error (SR[4] set) and a lock error (SR[1] set).

13.3.3 Locking the Protection Registers

Each Protection Register can be locked by programming its respective lock bit in the Lock

issuing the Program Lock Register command, followed by the desired Lock Register data (see

Section 9.2, “Device Commands” on page 50). The physical addresses of the Lock Registers are

0x80 for register 0 and 0x89 for register 1. These addresses are used when programming the lock

registers (see Table 29, “Device Identifier Information” on page 77).

Bit 0 of Lock Register 0 is already programmed at the factory, locking the lower, pre-programmed

64-bit region of the first 128-bit Protection Register containing the unique identification number of

the device. Bit 1 of Lock Register 0 can be programmed by the user to lock the user -programmable,

64-bit region of the first 128-bit Protection Register. When programming Bit 1 of Lock Register 0,

all other bits need to be left as ‘1’ such that the data programmed is 0xFFFD.

Lock Register 1 controls the locking of the upper sixteen 128-bit Protection Registers. Each of the

16 bits of Lock Register 1 correspond to each of the upper sixteen 128-bit Protection Registers.

Programming a bit in Lock Register 1 locks the corresponding 128-bit Protection Register.

Caution: After being locked, the Protection Registers cannot be unlocked.

1-Gbit P30 Family

Datasheet Intel StrataFlash® Embedded Memory (P30) April 2005

Order Number: 306666, Revision: 001 75

14. 0 Specia l Read States

The following sections describe non-array read states. Non-array reads can be performed in

asynchronous read or synchronous burst mode. A non-array read operation occurs as asynchronous

single-word mode. When non-array reads are performed in asynchronous page mode only the first

data is valid and all subsequent data are undefined. When a non-array read operation occurs as

synchronous burst mode, the same word of data requested will be output on successive clock edges

until the burst length requirements are satisfied.

Refer to the following waveforms for more detailed information:

•Figure 16, “Asynchronous Single-Word Read (ADV# Low)” on page 38

•Figure 17, “Asynchronous Single-Word Read (ADV# Latch)” on page 38

•Figure 19, “Synchronous Single-Word Array or Non-array Read Timing” on page 39

14.1 Read Status Register

To read the Status Register , issue the Read Status Register command at any address. Status Register

information is available to which the Read Status Register, Word Program, or Block Erase

command was issued. Status Register data is automatically made available following a Word

Program, Block Erase, or Block Lock command sequence. Reads from the device after any of these

command sequences outputs the device’s status until another valid command is written (e.g. Read

Arr ay com m an d ).

The Status Register is read using single asynchronous-mode or synchronous burst mode reads.

Status Register data is output on DQ[7:0], while 0x00 is output on DQ[15:8]. In asynchronous

mode the falling edge of OE#, or CE# (whichever occurs first) updates and latches the Status

must be toggled to update status data.

The Device Write Status bit (SR[7]) provides overall status of the device. Status register bits

SR[6:1] present status and error information about the program, erase, suspend, VPP, and block-

locked operations.

Table 28. Status Register Description (Sheet 1 of 2)

S tatus Register (SR) Default Value = 0x80

Device

Write Status Erase

Suspend

Status Erase

Status Program

Status VPP Status Program

Suspend

Status

Block-

Locked

Status BEFP

Status

DWS ESS ES PS VPPS PSS BLS BWS

76543210

Bit Name Description

7Device Write Status

(DWS) 0 = Device is busy; program or erase cycle in progress; SR [0 ] valid.

1 = Devi ce is ready; S R[ 6:1] are va lid.

6Erase S uspend Status

(ESS) 0 = Erase suspend not in effect.

1 = Era se suspend in effect.

1-Gbit P30 Family

April 2005 Intel StrataFlas h® Embedded Memory (P30) Datasheet

76 Order Number: 306666, Revision: 001

Note: Always clear the Status Register prior to resuming erase operations. It avoids Status Register

ambiguity when issuing commands during Erase Suspend. If a command sequence error occurs

during an erase-suspend state, the Status Register contains the command sequence error status

(SR[7,5,4] set). When the erase operation resumes and finishes, possible errors during the erase

operation cannot be detected via the Status Register because it contains the previous error status.

14.1.1 Clear Status Register

The Clear Status Register command clears the status register. It functions independent of VPP. The

Write State Machine (WSM) sets and clears SR[7,6,2], but it sets bits SR[5:3,1] without clearing

them. The Status Register should be cleared before starting a command sequence to avoid any

ambiguity. A device reset also clears the Status Register.

14.2 Read Device Identifier

The Read Device Identifier command instructs the device to output manufacturer code, device

identifier code, block-lock status, protection register data, or configuration register data (see

Section 9.2, “Device Commands” on page 50 for details on issuing the Read Device Identifier

command). Table 29, “Device Identifier Information” on page 77 and Table 30, “Device ID codes”

on page 77 show the address offsets and data values for this device.

5 Erase Status (ES) 0 = Erase successful.

1 = Erase fail or program sequence error when set with SR[4,7].

4 Program S tatus (PS) 0 = Program successful.

1 = Program fail or program sequence error when set with SR[5,7]

PP Status (VPPS) 0 = VPP within acceptable limits during pr ogr am or era se operation.

1 = VPP < VP PLK during program or erase oper ation.

2Program Suspend Statu s

(PSS) 0 = Program suspend not in effect.

1 = Program suspend in effect.

1Block-Locked Status

(BLS) 0 = Block not locked during pro gr am or erase.

1 = Block locked during program or erase; oper ation aborted.

0 BEFP Status (BWS)

DWS

BWS

= WSM is busy and buff er is avail able for loading.

= WSM is busy and buff er is not av ailable for loading.

= WSM is not busy and buffer is available for loading.

= Reserved for Future Use (RFU).

Table 28. Status Register Description (Sheet 2 of 2)

Status Register (SR) Default Va lue = 0x80

1-Gbit P30 Family

Datasheet Intel StrataFlash® Embedded Memory (P30) April 2005

Order Number: 306666, Revision: 001 77

14.3 CFI Query

The CFI Query command instructs the device to output Common Flash Interface (CFI) data when

read. See Section 9.2, “Device Commands” on page 50 for details on issuing the CFI Query

command. Appendix C, “Common Flash Interface” on page 93 shows CFI information and address

offsets within the CFI database.

Table 29. Device Identifier Information

Item Address(1) Data

Manufacturer Code 0x00 0089h

Device ID C ode 0x01 ID (see Table 30)

Block Lock Confi guration :

BBA + 0x 02

Lock Bit:

• Block Is Unlocked DQ0 = 0b0

• Block Is Locked DQ0 = 0b1

• Block Is not L ocked-Down DQ1 = 0b0

• Block Is Locked-Down DQ1 = 0b1

Co nf iguration Register 0x05 Conf iguration Regi ster Dat a

Lock Register 0 0x80 PR-LK0

64-bit Factory- Progra mm ed Protection Regist er 0x81–0x84 Factory Protection Registe r Data

64-bit User-P r ogr ammable Protection Regi ster 0x85–0x88 User Protec ti on Registe r Data

Lock Register 1 0x89 Pro te cti on Regis ter Data

128-bit Us er - Pr ogrammable Pr otection R egisters 0x8A –0x109 PR-LK1

Notes:

1. BBA = Block Base Address.

Table 30. Device ID codes

ID Code Type Device Density Device Identifier Codes

–T

(Top Parameter) –B

(Bottom Pa rame ter)

Device Code 64-Mbit 8817 881A

128-Mbit 8818 881B

256-Mbit 8919 891C

1-Gbit P30 Family

April 2005 Intel StrataFlas h® Embedded Memory (P30) Datasheet

78 Order Number: 306666, Revision: 001

Appendix A Write State Machine

Figure 34 through Figure 39 show the command state transitions (Next State Table) based on

incoming commands. Only one partition can be actively programming or erasing at a time. Each

partition stays in its last read state (Read Array, Read Device ID, CFI Query or Read Status Register)

until a new command changes it. The next WSM state does not depend on the partition’s output state.

Figure 34. Write State Machine—Next State Table (Sheet 1 of 6)

Read

Array

(

)

Word

Program (3,4)

Buffered

Program

(BP)

Erase

Setup (3,4)

Buffered

Enhanced

Fact o ry Pg m

Setup (3, 4)

BE Confirm,

P/E

Resume,

ULB,

Confirm (8)

BP / Prg /

Erase

Suspend

Read

Status

Clear

Status

Read

ID/Query

Lock, Unlock,

Lock-down,

CR setup (4)

(FFH) (10H/40H) (E8H) (20H) (80H) (D0H) (B0H) (70H) (50H) (90H, 98H) (60H)

Ready Program

Setup BP Setup Erase

Setup BEFP Set up Lock/CR

Setup

Ready

(Unlock

Block)

Setup

Busy

Setup

Busy Word

Program

Suspend

Suspend Word

Program

Busy

Setup

BP Load 1

BP Load 2

Confirm BP Busy

BP Busy BP Suspend

Suspend BP Busy

Setup Erase Busy

Busy Erase

Suspend

Suspend Erase

Suspend

Word

Program

Setup in

Erase

Suspend

BP Setup in

Erase

Suspend Erase Busy

Lock/CR

Set up in

Erase

Suspend

BP Suspend

Erase

BP Busy

Erase Busy

Erase Suspend Erase Suspend

Ready (Error)

Era se Busy

BP Suspend

Ready (Error)

Word

Program

Program Busy

Word Program Suspend

Word Program Busy

OTP

Ready (Lock Error)

Ready Ready

Ready (Lock Error)

OTP Busy

Current Chip

State (7)

Command Input to Chip and resulting Chip Next State

BP Busy

Lock/CR Setup

BP Load 2

Ready (Error)Ready (Error)

Word Program Busy

BP Confirm if Data load into Program Buffer is complete; Else BP Load 2

Word Program Susp end

BP Load 1

1-Gbit P30 Family

Datasheet Intel StrataFlash® Embedded Memory (P30) April 2005

Order Number: 306666, Revision: 001 79

Figure 35. Write State Machine—Next State Table (Sheet 2 of 6)

Setup

Busy

Word

Program

Suspend in

Erase

Suspend

Word

Program

Busy in

Erase

Suspend

Setup

BP Load 1

BP Load 2

Confirm

BP Busy in

Erase

Suspend

BP Busy BP Suspend

in Erase

Suspend

BP Busy in

Erase

Suspend

Erase

Suspend

(Unlock

Block)

Setup BEFP

Data (X=32)

Erase Suspend (Error)

Erase Suspend (Lock Error [Botch])

Ready (Error) Ready (Error)

BP Suspend in Erase Suspend

Ready (Error in Erase Suspend)

BP Busy in Erase Suspend

BP Suspend in Erase Suspend

BP Busy in Erase Suspend

Word Program Busy in Erase Suspend

Word

Program in

Erase

Suspend

Word Program Busy in Erase Suspend

Word Program Suspend in Erase Suspend

Lock/CR Setup in Erase

Suspend Erase Suspend (Lock Error)

BP Con firm if Data load into Program Buffer is complete; Else BP Load 2

BP i n Eras e

Suspend

BP Load 2

Word Program Busy in Erase Suspend Busy

Word Program Suspend in Erase Suspend

BEFP Program and Verify Busy (if Block Address given matches address given on BEFP Setup command). Commands treated as data. (7)

BEFP

Busy

Buffered

Enhanced

Factory

Program

Mode

BP Load 1

Read

Array

(

)

Word

Progr am (3,4)

Buffered

Program

(BP)

Erase

Setup (3,4)

Buffered

Enhanced

Factory Pgm

Setup (3, 4)

BE Confirm,

P/E

Resume,

ULB,

Confirm (8)

BP / Prg /

Erase

Suspend

Read

Status

Clear

Status

Read

ID/Query

Lock, Unlock,

Lock-down,

CR set up (4)

(FFH) (10H/40H) (E8H) (20H) (80H) (D0H) (B0 H) (70H) (50H) (90H, 98H) (60H)

Current Chip

State (7)

Command Input to Chip and resulting Chip Next State

1-Gbit P30 Family

April 2005 Intel StrataFlas h® Embedded Memory (P30) Datasheet

80 Order Number: 306666, Revision: 001

Figure 36. Write State Machine—Next State Table (Sheet 3 of 6)

Setup

Busy

Setup

Busy

Suspend

Setup

BP Load 1

BP Load 2

Confirm

BP Busy

Suspend

Setup

Busy

Suspend

Erase

Word

Program

OTP

Ready

Current Chip

State (7)

Lock/CR Setup

OTP

Setup (4)

Lock

Block

Confirm (8)

Lock-Down

Block

Con fir m (8)

Write RCR

Confirm (8) Block Address

(?WA0) 9 Illegal Cmds or

BEFP Data (1)

(C0H) (01H) (2FH) (03H) (XXXXH) (all other codes)

OTP

Setup

Ready

(Lock

Error)

Ready

(Lock

Block)

Ready

(Lock Down

Blk)

Ready

(Set CR)

Ready

N/A

Ready

Ready (BP Load 2 BP Load 2

Ready

BP Confirm if

Data load in to

Program Bu ff er is

compl ete; ELSE

BP Load 2

Ready (Error)

(Proceed if

un locked or lock

error)

Ready (Error)

Ready

N/A

BP Confirm if Data load into Program Buffer is

complete; ELSE BP load 2

Ready (Error)

BP Busy

Erase Busy

Word Program Suspend

BP Load 1

BP Load 2

OTP Busy

Word Program Busy

WSM

Operation

Completes

Command Input to Chip and resultin

Chip Next State

N/A

Ready (Lock Error)

Ready

BP Suspend

Ready (Error)

Erase Suspend

N/A

1-Gbit P30 Family

Datasheet Intel StrataFlash® Embedded Memory (P30) April 2005

Order Number: 306666, Revision: 001 81

Figure 37. Write State Machine—Next State Table (Sheet 4 of 6)

OTP

Setup (4)

Lock

Block

Confirm (8)

Lock-Down

Block

Confirm (8)

Write RCR

Confirm (8) Block Address

(?WA0) 9 Illegal Cmds or

BEFP Data (1)

(C0H) (01H) (2FH) (03H) (XXXXH) (all other codes)

WSM

Operation

Completes

Command Input to Chip and resulting Chip Next S t ate

Current Chi p

State (7)

Erase Suspend

N/A

Ready (BP Load 2 BP Load 2

Ready

BP Confirm if

Data load into

Program Buffer is

complete; Else

BP Load 2

Ready (Error)

(Proce e d if

unlocked or lock

error)

Re a d y (Erro r)

Erase Suspend

Erase

Suspend

(Lock

Error)

Erase

Suspend

(Lock

Block)

Erase

Suspend

(Lock Down

Block)

Erase

Suspend

(Se t CR)

Ready (BEFP

Loading Data) Ready (Error)

BEFP Program and Verify Busy (if Block Address

given matches address given on BEFP Setup

command). Commands treated as data. (7)

BP Load 1

Ready (Error)

BP Confirm if Data load into Program Buff er is

complete; Else BP Load 2

Ready (Error in Erase Suspend)

Word Program Suspend in Erase Suspend

BP Load 2

Ready

Word Program Busy in Erase Suspend Bu sy

Word Program Busy in Erase Suspend

BEFP B usy

Ready

Erase Suspend (Lock Error) N/A

BP Busy in Erase Suspend

BP Suspend in Erase Suspend

N/A

Setup

Busy

Suspend

Setup

BP Load 1

BP Load 2

Confirm

BP Busy

Suspend

Setup

BEFP

Busy

Buffered

Enhanced

Factory

Program

Mode

Lock/CR Setup in Erase

Suspend

BP in Erase

Suspend

Word

Program in

Erase

Suspend

1-Gbit P30 Family

April 2005 Intel StrataFlas h® Embedded Memory (P30) Datasheet

82 Order Number: 306666, Revision: 001

Figure 38. Write State Machine—Next State Table (Sheet 5 of 6)

Read

Array

(

)

Word

Program

Setup (3,4) BP Setup Erase

Setup (3,4)

Buffered

Enhanced

Fact ory Pgm

Setup (3, 4)

BE Con fi rm,

P/E

Resume,

ULB Con firm

(8)

Program/

Erase

Suspend

Read

Status

Clear

Status

Read

ID/Query

Lock, Unlock,

Lock-down,

CR setup (4)

(FFH ) (10H/ 40H) (E8H) (20H) (3 0H) (D0H) (B0H) (70H) (50H) (90 H , 98H) (60H)

St atus Read

Command Input to Chip and resulting Output Mux Next State

Output Next State Table

St atus Read

Output mux

does not

change.

Status

Read

ID Read Status Read

Ready,

Erase Suspend,

BP Suspend

Status Read

Lock/CR Setup,

Lock /CR Setup in

Erase Susp

Output does not change. Status Read

BEFP Setup,

BEFP Pgm & Verify

Bus y,

Erase Setup,

OTP Setup,

BP: Setup, Load 1,

Load 2, Conf irm,

W o rd Pgm Setup,

Word Pgm Setup in

Erase Susp,

BP Setup, Load1,

Load 2, Conf irm in

Erase Suspend

Current chip state

OTP Busy

BP Busy,

Word Program

Busy,

Erase Busy,

BP Busy

BP Busy in Eras e

Suspend

Word Pgm

Suspend,

Word Pgm Busy in

Erase Suspend,

Pgm Suspend In

Erase Sus

end

Read Array

1-Gbit P30 Family

Datasheet Intel StrataFlash® Embedded Memory (P30) April 2005

Order Number: 306666, Revision: 001 83

Notes:

1. "Illeg al commands" include commands outside of the allow ed command set ( allowed comma nds: 40H [pgm], 20H [er ase],

etc.)

2. If a "Read Array" is att empted from a busy partition, the result will be invalid dat a. The ID an d Query dat a are located at

different locations in the address map.

3. 1st and 2nd cycles of "2 cycles write co mmands" must be given to the same partition ad dr ess, or unexpected result s w il l

occur.

4. To protect memo ry c ont ents against er r oneous command sequences, there ar e specific inst ances in a mult i-cycle

comm and sequence in which the seco nd cycle will be igno re d. For example, when t he device is program suspended and

an erase setup command (0 x20) is gi ven followed by a confir m /resume com mand (0xD0), the second command will be

ign or ed because it is unclear whether the user intends to era se the block or resume the program o peration.

Figure 39. Write State Machine—Next State Table (Sheet 6 of 6)

OTP Busy

BP B usy,

Word Program

Busy,

Erase Busy,

BP B usy

BP Busy in Erase

Suspend

Word Pgm

Suspend,

Word Pgm Busy in

Erase Susp end,

Pgm Susp end In

Erase S us

end

BEFP Setup,

BEFP Pgm & Verify

Busy,

Erase S etup,

OTP Setup,

BP: Setup, Load 1,

Load 2, Co nf irm,

Word Pgm Setup,

Word Pgm Setup in

Erase Susp,

BP Setup, Load1,

Load 2, Co nf irm in

Erase Susp end

Current chip state

Ready,

Erase Susp end,

BP Suspend

Lock/CR Setup,

Lock/CR Setup in

Erase Susp

OTP

Setup (4)

Lock

Block

Confirm (8)

Lock-Down

Block

Confirm (8)

Writ e CR

Confirm (8) Block Address

(?WA0) Illegal Cmds or

BEFP Data (1)

(C0H) (01H) (2FH) (03H) (FFFFH) (all other codes)

WSM

Operation

Completes

Output does

not change.

rray

Read Status Read

Array Read Output does not

change.

Output does not change.

Status

Read

Status Read

Command Input to Chip and resulting Output Mux Next State

Output Next State Table

1-Gbit P30 Family

April 2005 Intel StrataFlas h® Embedded Memory (P30) Datasheet

84 Order Number: 306666, Revision: 001

5. The Clear Status command only cl ears the error bits in the status regist er if th e device is not in th e follow ing modes: WSM

running (Pgm Busy, Eras e Busy, Pgm Busy In Erase Suspend, OTP Busy, BE FP modes).

6. BEFP writes ar e only allowed wh en the status regist er bit #0 = 0, or el se the data is ignored.

7. The "current state" is that of the "chip" and not of the "partition"; Each partition "remembers" which output (Array , ID/CFI or

Status) it was last pointed to on the last instructi on to the "chi p", but the next state of the chip does not depend on where

the p ar tition's outpu t mux is presently pointing to .

8. Confirm com m ands (Lock Block, U nlock Block, Lock-Down Block, Confi gur ation Register) perform the operat ion and then

mo ve t o t h e R eady Stat e .

9. WA0 refers to the block ad dr ess latched during the firs t write cycle of the current oper ation.

1-Gbit P30 Family

Datasheet Intel StrataFlash® Embedded Memory (P30) April 2005

Order Number: 306666, Revision: 001 85

Appendix B Flowcharts

Figure 40. Word Program Flowchart

Program

Suspend

Loop

Start

Write 0x40,

Word Addres s

Write Data,

Word Addres s

Read Status

SR[7 ] =

Full St atus

Check

(if desired)

Program

Complete

Suspend?

Yes

WORD PROGRA M PROCEDURE

Repeat for subsequent Word Progr am operations.

Full St atus Register chec k can be don e after each pro gr am , or

after a sequence of program operations.

Write 0xFF after the las t operation to set to the Rea d Ar ray

state.

Comments

Bus

Operation Command

Data = 0x40

Addr = Location to program

Write Program

Setup

Dat a = D ata to program

Addr = Location to program

Write Data

Sta tus regis ter dataRead None

Check SR[7]

1 = WS M R ea dy

0 = WSM Busy

Idle None

(Setup)

(Confirm)

FULL STATUS CHECK PROCEDURE

Read Status

Program

Successful

SR[3 ] =

SR[1 ] =

SR[4 ] =

1VPP Range

Error

Device

Protect Er r or

Program

Error

If an er ro r is detected, cl ea r the Status Register befo re

continuing operations - only the Clear Staus Register

command clears the Status Re gister erro r bi ts.

Idle

Bus

Operation

None

Command

Check SR[3]:

1 = VPP Error

Check SR[4]:

1 = Data Program Error

Comments

Idle None Check SR[1]:

1 = Bl ock lo cked; oper at io n aborted

1-Gbit P30 Family

April 2005 Intel StrataFlas h® Embedded Memory (P30) Datasheet

86 Order Number: 306666, Revision: 001

Figure 41. P r ogra m Suspend/Resume Flowchart

Read Status

SR.7 =

SR.2 =

Write FFh

Su sp Partit ion

Read Array

Data

Program

Completed

Done

Reading

Write FFh

Pgm'd Partition

Write D0h

Any Address

Program

Resumed Read Array

Data

Yes

PROGRAM SUSPEND / RESUM E PROCEDURE

Write Program

Resume Dat a = D0h

Addr = Suspended block (BA)

Bus

Operation Command Comments

Write Program

Suspend Dat a = B 0h

Addr = Block to suspend (BA)

Standby Ch eck S R.7

1 = WSM ready

0 = WSM busy

Standby Ch eck S R.2

1 = Program suspended

0 = Program completed

Write Read

Array

Dat a = FFh

Addr = Any address within the

suspended partition

Read Read array data from block other than

the one being programmed

Read Status register data

Addr = Suspended block (BA)

PGM_SUS.WMF

Start

Write B0h

Any Address

Program Suspend

Read Status

Program Resume R ead Array

R ead Array

Write 70h

Same Part itio n Write Read

Status Dat a = 70h

Addr = Same partition

If the suspended partition was placed in Read Array mode:

Write Read

Status

Return partition to Status mode:

Dat a = 7 0h

Addr = Same partition

Write 70h

Same Part itio n

Read Status

1-Gbit P30 Family

Datasheet Intel StrataFlash® Embedded Memory (P30) April 2005

Order Number: 306666, Revision: 001 87

Figure 42. Buffer Program Flowchart

Buffer Programm ing Procedure

Start

Get Next

Target A ddres s

Issue Buffer Prog. Cmd.

0xE8,

W ord A ddress

Read Status Register

at Word Address

W rite B uffe r

Available?

S R [7] =

1 = Yes

Device

Supports Buffer

Writes?

Set Timeout or

Loop Counter

Timeout

or Count

Expired?

Write Confirm 0xD0

and Word Address

(Note 5)

Yes

B u ffer P ro gra m Data ,

Start W ord Address

X = 0

0 = No Yes

Use Single Word

Programming

A b ort B u ffer

Program?

X = N?

W rite Buffer Data,

Word Address

X = X + 1

W rite to another

Block Address

Bu ffer Prog ram A b o rted

Yes

Write Word Count,

W ord A ddress

Suspend

Program

Loop

Read Status Register

(No te 7)

Is BP finished?

S R [7 ] =

Full S tatus

Check if Desired

Program Complete

Suspend

Program?

1=Yes

0=No Yes

Issue Read

Status Register

Command

1. Word co un t v alue on D[7:0] is loaded into the word coun t

2. The device outputs the Status Register when read.

3 . W rite Bu ffe r co nte n ts w ill be pro g ramm ed a t the iss ue d w o rd

address.

4. Align the start address on a Write Buffer boundary for

m aximum programming perform ance (i.e., A[4:0] of the Start

W ord Add ress = 0x00 ).

5. The Buffered Programming Confirm command must be

issued to an address in the same block, for example, the

original Start Word Address, or the last address used during the

loop that loaded the buffer data.

6. The Status Register indicates an improper command

seq uenc e if the Buffer Program com mand is aborted; use the

Clea r Status Re gister comman d to clear error bits.

7. The Status Register can be read from any address within

the program ming pa rtition.

Fu ll status check can be done after all erase and write

sequences complete. Write 0xFF after the last operation to

place the partition in the Read Array state.

Bus

Operation

Idle

Read

Command

None

Write Buffer Prog.

Setup

Read None

Idle None

Comments

C h eck SR[7 ]:

1 = W S M R eady

0 = W S M B usy

Status register Data

A d dr = N ote 7

D a ta = 0 xE 8

Addr = Word Address

SR[7] = Valid

Addr = Word Address

C h e ck SR[7 ]:

1 = Write Buffer available

0 = No Write Buffer available

Write

(Notes 5, 6) Buffer Prog.

Conf. Data = 0xD0

Ad dr = Original Wo rd Add ress

Write

(Notes 1, 2) None Data = N-1 = Word Count

N = 0 corresponds to count = 1

Addr = Word Address

Write

(Notes 3, 4) None D a ta = Write Bu ffe r D ata

Addr = Start Word Address

Write

(Note 3) None Da ta = Write B u ffer Data

Addr = Word Address

Other partitions of the device can be read by addressing those partitions

and driving OE# low. (Any write commands are not allowed during this

period.)

0xFF commands can be issued to read from

any blocks in other partitions

1-Gbit P30 Family

April 2005 Intel StrataFlas h® Embedded Memory (P30) Datasheet

88 Order Number: 306666, Revision: 001

Figure 43. BEFP Flowcha rt

NOTES:

1. First-word address to be programmed within the target block must be aligned on a write-buffer boundary.

2. Write-buffer contents are program med sequentially to the flash array starting at the first word address (WSM internally increments addressing).

BEFP E xit

Repeat for subsequent blocks;

After BEFP exit, a full Status Register check can

determine if any program error occurred;

See full Status Register check procedure in the

Word Program flowchart.

Write 0xFF to enter Read Array state.

Standby

Read

Bus

State Operation

Stat us

Check

Exit

Status

Comments

Data = Status Register Data

Address = 1st Word Addr.

Che ck SR[7]:

0 = Exit Not Comple ted

1 = Exit Completed

BEFP Setup

Comments

Bus

State Operation

Write

(Note 1) BEFP

Setup

Write BEFP

Confirm

Read Status

Standby BEF P

Setup

Done?

Write Unlock

Block

Data = 0x80 @ 1st Word

Address

Data = 0x80 @ 1st Word

Address1

Da ta = St atu s Re gis te r D a ta

Address = 1st Word Addr.

Check SR[7]:

0 = BEFP Ready

1 = BEFP Not Ready

VPPH applied to VPP

Standby Error

Condition

Check

If S R[7] is set, chec k:

SR[3] set = VPP Error

SR[1] set = Lo cked B lock

No (SR[0]=1)

Write Data @ 1st

W ord Address

Last

Data?

Write 0xFFFF,

Address Not within

Current Block

Program

Done?

Read

Status Reg.

Yes (SR[0]=0)

No (SR[7]=0)

Full Status Check

Procedure

Program

Complete

Read

Status Reg .

BEFP

Exited?

Y es (SR[7]=1)

Start

Write 80h @

1st Word Address

VPP applied

Block Unlocked

Write D0h @

1st Word Address

BEFP Setup

Done?

Read

Status Reg .

No (SR[7]=1)

Exit

Program & Verify Phase E xit Ph as eSetup Phase

BUFFERED ENHANCED FACTORY PROGRAMMING (BEFP) P ROCEDURE

Check

X = 32?

Initialize Count :

X = 0

Increment C ount:

X = X+1

Check VPP, Lock

er ro rs (S R[3 ,1 ])

Yes (SR[7]=0)

BEFP Setup delay

Data Stream

Ready?

Read

Status Reg.

Yes (SR[0] =0)

No (SR[0]=1)

BEFP Program & Verify

Comments

Bus

State

Write

(note 2) Load

Buffer

Standby Increment

Count

Standby Initialize

Count

Data = Dat a to Prog ram

Address = 1st Word Addr.

X = X+1

X = 0

Read Status

Standby Program

Done?

Data = Status Reg. Data

Address = 1st Word Addr.

Check SR [0]:

0 = Program Done

1 = Program in Progress

Write Exit Prog &

V e rify Phase Data = 0xFFFF @ address

not in current block

Standby Last

Data? No = Fill buffer again

Yes = Exit

Standby Buffer

Full?

X = 32?

Yes = Read SR[0]

No = Load Next Data W ord

Read

Standby

Status

Data Stream

Ready?

Data = Status Register Data

Address = 1st Word Addr.

Check SR [0]:

0 = Ready for Data

1 = Not R eady for Data

Operation

1-Gbit P30 Family

Datasheet Intel StrataFlash® Embedded Memory (P30) April 2005

Order Number: 306666, Revision: 001 89

Figure 44. Block Erase Flowchart

Start

FULL ERASE STATUS CHECK PROCEDURE

Repeat for subsequent block erasures.

Full Status register check can be done after each block erase

or after a sequence of block er asures .

Write 0xFF after the last operation to enter read arr ay mode.

Onl y the Cl ea r St atus Register command cl ea rs S R [1 , 3, 4, 5] .

If an error is detected, clear the Status register before

attempting an erase retry or other error recovery.

Suspend

Erase

1,1

0Yes

Suspend

Erase

Loop

Write 0x20,

Block Address

Write 0xD0,

Block Address

Read Status

SR[7 ] =

Full Erase

St atus Chec k

(if desired)

Bl ock Erase

Complete

Read Status

Bl ock Erase

Successful

SR[1 ] = Block Locked

Error

BLOCK ERASE PROCEDURE

Bus

Operation Command Comments

Write Block

Erase

Setup

Data = 0x20

Addr = Block to be erase d ( BA )

Write Erase

Confirm Data = 0xD0

Addr = Block to be erase d ( BA )

Read None Status Register data.

Idle None Check SR[7]:

1 = WS M re ad y

0 = WS M busy

Bus

Operation Command Comments

SR[3 ] = VPP Range

Error

SR[4 ,5 ] = Command

Sequence Error

SR[5 ] = Block Erase

Error

Idle None Check SR[3]:

1 = VPP Range Error

Idle None Check SR[4,5 ]:

Bot h 1 = Com mand Sequence Error

Idle None Check SR[5]:

1 = Bl ock Er ase Error

Idle None Check SR[1]:

1 = Attempted er ase of lock e d bl ock;

eras e abor ted.

(Block Erase)

(Era se Confirm)

1-Gbit P30 Family

April 2005 Intel StrataFlas h® Embedded Memory (P30) Datasheet

90 Order Number: 306666, Revision: 001

Figure 45. Erase Suspend/Resume Flowchart

Erase

Completed

Read Array

Data

Read

Program

Loop

Read Array

Data

Start

Read Status

SR[7] =

SR[6] =

Erase

Resumed

Read o r

Program?

Done

Write

Idle

Write

Erase

Suspend

Read A rray

or Prog ram

None

Program

Resume

Data = 0xB0

Addr = Same partition address as

above

Data = 0xFF or 0x40

Addr = Any address within the

suspended partition

Check SR[7]:

1 = WSM ready

0 = WSM busy

Check SR[6]:

1 = E ras e su spen de d

0 = Erase completed

Data = 0xD0

Addr = Any address

Bus

Operation Command Comments

Read None Status Register data.

Addr = Same partition

Read o r

Write None Read array or program data from/to

block other than the one being erased

ERAS E S US PE ND / RE SUME PROCE DURE

I f the s uspe nded pa rti tion was pla ced i n

Read Arr a y m ode or a P r ogram Loop:

Write 0xB0,

Any Address

(Erase Suspend)

Write 0x70,

Same Partition

(Rea d Sta tu s)

Write 0xD0,

Any Address

(Erase Resume)

Write 0x70,

Same Partition

(Read Status)

Write 0xFF,

Erased Partition

(Read Array)

Write Read

Status Data = 0x70

Addr = Any partition address

Write Read

Status

Return pa rtition to Sta tus mode :

Data = 0x7 0

Addr = Same partition

1-Gbit P30 Family

Datasheet Intel StrataFlash® Embedded Memory (P30) April 2005

Order Number: 306666, Revision: 001 91

Figure 46. Bloc k Lock Operations Flowchart

Start

Write 0x60,

Block Address

Writ e 0x 90

Read Block

Lock Status

Locking

Change?

Lock Change

Complete

Write either

0x01/0xD0/0x2F,

Block Address

Write 0xFF

Partitio n Address

Yes

Write

(Optional)

Read

(Optional)

Idle

Write

Lock

Setup

Lock,

Unl ock, or

Lock-Down

Confirm

Read

Device ID

Block Lock

Status

None

Read

Array

Data = 0x60

Addr = Block to lock/unlock/lock-down

Data = 0x01 (Block Lock)

0xD0 (Blo ck Unlock)

0x2F (Lock-Down Bloc k)

Addr = Block to lock/unlock/lock-down

Data = 0x90

Addr = Block address + offset 2

Block Lock status data

Addr = Block address + offset 2

Confirm locking change on D[1,0].

Data = 0xFF

Addr = Block address

Bus

Operation Command Comments

LOCKING OPERATIONS PROCEDURE

(Lock Confirm)

(Read Device ID)

(Read Array)

Optional

(Lock Set u p)

1-Gbit P30 Family

April 2005 Intel StrataFlas h® Embedded Memory (P30) Datasheet

92 Order Number: 306666, Revision: 001

Figure 47. P r ote ction Register Programming Flowchart

FULL STATUS CHECK PROCEDURE

Program Protecti on Regis ter operation addresse s must be

within the Protection Register address space. Addresses

outside this space wil l return an error.

Repeat for subsequent programming operations.

Full Status Re gi ster check can be don e af t e r ea c h pro g r am , or

after a sequence of program operations.

Write 0xFF after the las t operation to set Read Ar r ay state .

Only the Clear Stau s Regist er comm and cle ars SR[ 1, 3, 4].

If an error is detected, clear the Status register before

attemptin g a program retry or ot her error recovery.

PROTECTION REGISTER PROGRAMMING PROCEDURE

Start

Write 0xC0,

PR Address

Write PR

Address & Data

Read Status

SR[7 ] =

Full St atus

Check

(if desired)

Program

Complete

Read Status

Program

Successful

SR[3 ] =

SR[4 ] =

SR[1 ] =

VPP Rang e Error

Program Error

Program Aborted

Idle

Bus

Operation

None

Command

Check SR[3]:

1 =VPP Range Error

Check SR[4]:

1 =Programming Error

Comments

Write

Idle

Program

PR Setup

Protection

Program

None

Data = 0xC0

Addr = First Location to Program

Data = Data to Program

Addr = Location to Program

Check SR[7]:

1 = WS M R e ad y

0 = WS M B us y

Bus

Operation Command Comments

Read None Status Register Data.

Idle None Check SR[1]:

1 =Bloc k lo c ked; operation aborted

(Program Setup)

(Confirm Data)

1-Gbit P30 Family

Datasheet Intel StrataFlash® Embedded Memory (P30) April 2005

Order Number: 306666, Revision: 001 93

Appendix C Common Flash Interfac e

The Common Flash Interface (CFI) is part of an overall specification for multiple command-set

and control-interface descriptions. This appendix describes the database structure containing the

data returned by a read operation after issuing the CFI Query command (see Section 9.2, “Device

Commands” on page 50). System software can parse this database structure to obtain information

about the flash device, such as block size, density, bus width, and electrical specifications. The

system software will then know which command set(s) to use to properly perform flash writes,

block erases, reads and otherwise control the flash device.

C.1 Query Structure Output

The Query database allows system software to obtain information for controlling the flash device.

This section describes the device’s CFI-compliant interface that allows access to Query data.

Query data are presented on the lowest-order data outputs (DQ7-0) only . The numerical offset value

is the address relative to the maximum bus width supported by the device. On this family of

devices, the Query table device starting address is a 10h, which is a word address for x16 devices.

For a word-wide (x16) device, the first two Query-structure bytes, ASCII “Q” and “R,” appear on

the low byte at word addresses 10h and 11h. This CFI-compliant device outputs 00h data on upper

bytes. The device outputs ASCII “Q” in the low byte (DQ7-0) and 00h in the high byte (DQ15-8).

At Query addresses containing two or more bytes of information, the least significant data byte is

presented at the lower address, and the most significant data byte is presented at the higher address.

In all of the following tables, addresses and data are represented in hexadecimal notation, so the

“h” suffix has been dropped. In addition, since the upper byte of word-wide devices is always

“00h,” the leading “00” has been dropped from the table notation and only the lower byte value is

shown. Any x16 device outputs can be assumed to have 00h on the upper byte in this mode.

Table 32. Example of Query Structure Output of x16- Devices

Table 31. Summary of Query Structure Output as a Function of De vice and Mod e

Device Hex

Offset Hex

Code ASCII

Value

Device Addresses

00010: 51 “Q”

00011: 52 “R”

00012: 59 “Y”

1-Gbit P30 Family

April 2005 Intel StrataFlas h® Embedded Memory (P30) Datasheet

94 Order Number: 306666, Revision: 001

C.2 Query Structure Overview

The Query command causes the flash component to display the Common Flash Interface (CFI)

Query structure or “database.” The structure sub-sections and address locations are summarized

below.

Table 33. Query Structure

Notes:

1. Refer to the Quer y S tructur e Output sect ion and of fset 28h fo r the detai led defi nition of of fset add ress as

a func ti on of device bus width and mode.

2. BA = Block Address begin ning location (i.e., 08 000h is block 1 ’s begi nning location when the b lock size

is 16-KWord).

3. Offse t 15 defines “ P” which po ints to the Pri m ar y Intel-specific Extended Quer y Tabl e.

Word Addressing: Byte Addressing:

Offset Hex Code

alue Offset Hex Code

alue

–A

0 D15

–

–A

0 D7

–

00010h 0051 "Q" 00010h 51 "Q"

00011h 0052 "R" 00011h 52 "R"

00012h 0059 "Y" 00012h 59 "Y"

00013h P_IDLO PrVendor 00013h P_IDLO PrVendor

00014h P_IDHI ID # 00014h P_IDLO ID #

00015h PLO PrVendor 00015h P_IDHI ID #

00016h PHI Tbl Adr 00016h ... .. .

00017h

_IDLO

ltVendor 00017h

00018h

_IDHI ID # 00018h

... ... ... . ..

Offset Sub-Section Nam

Descri

tion(1)

0000 1-Fh Re served Reserve d for vendor-specific information

0001 0h CFI query iden tification string Co mm a nd set ID and ve ndor d ata offset

0001 Bh System interface information D evice timing & voltage information

0 0027 h Devic e geom etry defin ition F lash device layou t

(3) Primar

In te l- s

ecific Extended Quer

Table Vendor-defined additional information specific

1-Gbit P30 Family

Datasheet Intel StrataFlash® Embedded Memory (P30) April 2005

Order Number: 306666, Revision: 001 95

C.3 CFI Query Identification String

The Identification String provides verification that the component supports the Common Flash

Interface specification. It also indicates the specification version and supported vendor-specified

command set(s).

Table 34. CFI Identification

Table 35. System Interface Information

Offset Length Description Add. He

Code Value

10h 3 Query-unique ASC II string “QR Y“ 10: --51 "Q"

11: --52 "R"

12: --59 "Y"

13h 2 Primary vendor command set and control interface ID code. 1 3: --01

16-bit ID code for vendor-specified algorithms 14: --00

15h 2 Extended Query Table primary algorithm address 15: --0A

16: --01

17h 2 Alternate vendor command set and control interface ID code. 1 7: --00

0000 h mea ns no second ven dor-specified algorithm exists 18: --00

19h 2 Secondary algorithm Ex tended Q uery Table address. 19: --00

0000 h mea ns none exists 1 A: --00

Offset Length Description Add. Hex

Code Value

1Bh 1 1B: --17 1.7V

1Ch 1 1C: --20 2.0V

1Dh 1 1D: --85 8.5V

1Eh 1 1E: --95 9.5V

1Fh 1 “n” such that t

ical sin

le word

ra m ti me-out = 2n

-sec 1F: --08 256µs

20h 1 “n” suc h t hat t

ical max. buffer write time-out = 2n

-sec 20: --09 512µs

21h 1 “n” suc h t hat t

ical block erase time-out = 2n m-sec 21: --0A 1s

22h 1 “n” suc h t hat t

ical full chi

erase time- out = 2nm-sec 22: --00 NA

23h 1 “n” suc h t hat ma ximum word

ram time -out = 2ntime s t

ical 23: --01 512µs

24h 1 “n” suc h t hat ma ximum buf f er write t im e -o ut = 2n times t

ical 24: --01 1024µs

25h 1 “n” suc h t hat ma ximum blo ck e ras e time-out = 2ntimes t

ical 25: --02 4s

26h 1 “n” suc h t hat m aximum c hi

erase time-out = 2ntimes t

ical 26: --00 NA

VPP [programming] supply minimum program/erase voltage

bits 0–3 BCD 100 mV

bits 4–7 HEX volts

VPP [programm ing] supply maximum program/erase voltage

bits 0–3 BCD 100 mV

bits 4–7 HEX volts

VCC logic supply minimum program/erase voltage

bits 0–3 BCD 100 mV

bits 4–7 BCD volts

VCC logic supply maximum program/erase voltage

bits 0–3 BCD 100 mV

bits 4–7 BCD volts

1-Gbit P30 Family

April 2005 Intel StrataFlas h® Embedded Memory (P30) Datasheet

96 Order Number: 306666, Revision: 001

C.4 Device Geometry Definition

Table 36. Device Geometry Definition

Offset Length Description Code

27h 1“n” such that devi ce size = 2nin numb er of bytes 27: See table below

76543210

28h 2 — — — — x64 x32 x16 x8 28: --01 x16

15 14 13 12 11 10 9 8

————————29:--00

2Ah 2“n” such that maximum number of byt es in write buf fer = 2n2A: --06 64

2B: --00

2Ch 1 2C:

2Dh 4 Erase Block Region 1 Information 2D:

bits 0–15 = y, y+1 = number of identical-size erase bl ocks 2E:

bits 16–31 = z, regi on erase block(s) size are z x 256 bytes 2F:

30:

31h 4 Erase Block Region 2 Information 31:

bits 0–15 = y, y+1 = number of identical-size erase bl ocks 32:

bits 16–31 = z, regi on erase block(s) size are z x 256 bytes 33:

34:

35h 4 R eser ved for future er ase block region information 35:

36:

37:

38:

See table below

Flash device interface code assignment:

"n" such that n+1 specifies the bit field that repres ents the flash

device width capabilities as described in the table:

Numb er of er ase block r e gion s ( x) wi t hin devi c e:

1. x = 0 means no era s e bl ock ing; th e device eras e s in bul k

2. x specifies the number of device regions wi th one or

m ore c o nti guous s ame - s ize er ase block s.

3. Symmetrically blocked partitions have one blocking region

Address 64-Mbit

–B –T –B –T –B –T

27: --17 --17 --18 --18 --19 --19

28: --01 --01 --01 --01 --01 --01

29: --00 --00 --00 --00 --00 --00

2A: --06 --06 --06 --06 --06 --06

2B: --00 --00 --00 --00 --00 --00

2C: --02 --02 --02 --02 --02 --02

2D: --03 --3E --03 --7E --03 --FE

2E: --00 --00 --00 --00 --00 --00

2F: --80 --00 --80 --00 --80 --00

30: --00 --02 --00 --02 --00 --02

31: --3E --03 --7E --03 --FE --03

32: --00 --00 --00 --00 --00 --00

33: --00 --80 --00 --80 --00 --80

34: --02 --00 --02 --00 --02 --00

35: --00 --00 --00 --00 --00 --00

36: --00 --00 --00 --00 --00 --00

37: --00 --00 --00 --00 --00 --00

38: --00 --00 --00 --00 --00 --00

128-Mbit 256-Mbit

1-Gbit P30 Family

Datasheet Intel StrataFlash® Embedded Memory (P30) April 2005

Order Number: 306666, Revision: 001 97

C.5 Intel-Specific Extended Query Table

Table 37. Primary Vendor-Specific Extended Q uery

Offset(1) Length Description Hex

P = 1 0Ah (Optional fla sh features and comma nds) Add. Code Value

(P+0)h 3 Primary extended query table 10A --50 "P"

(P+1)h Un ique ASCII string “PRI“ 10B : --52 "R"

(P+2)h 10C: --49 "I"

(P+3)h 1 Major version number, ASCII 10D: --31 "1"

(P+4)h 1 Minor version number, ASCII 10E: --34 "4"

(P+5)h 4 Optional feature and command support (1=yes, 0=no) 10F : --E6

(P+6)h bits 10–31 are reserved; undefined bits are “0.” If bit 31 is 110: --01

(P+7)h “1” then another 31 bit field of Optional features follows at 111: --00

(P+8)h the end of the bit–30 field. 112: --00

bit 0 Chip erase supported bit 0 = 0 No

bit 1 Suspend erase supported bit 1 = 1 Yes

bit 2 Suspend program supported bi t 2 = 1 Yes

bit 3 Legacy l ock/unlock supported bit 3 = 0 No

bit 4 Queued erase supported bit 4 = 0 No

bit 5 Instant individual bl ock locking supported bit 5 = 1 Yes

bit 6 Protection bits supported bit 6 = 1 Yes

bit 7 Pagemode read supported bit 7 = 1 Yes

bit 8 Synchronous read supported bit 8 = 1 Yes

bit 9 Simultaneous operations supported bi t 9 = 0 No

bit 10 Extended F lash Array Bl ocks supported bit 10 = 0 No

bit 30 CFI Link(s) to follow bit 30 = 0 No

bit 31 Another "O pti onal Features" field to follow bi t 31 = 0 No

(P+9)h 1 113: --01

bit 0 Program supported after erase suspend bit 0 = 1 Yes

(P+A)h 2 Block status register mask 114: --03

(P+B)h bits 2–15 are Reserved; undefined bits are “0” 115: --00

bit 0 Block Lock-Bit Status regi ster active bi t 0 = 1 Yes

bit 1 Block Lock-Down Bit Status active bit 1 = 1 Yes

bit 4 EFA Block Lock -Bit Status register active bit 4 = 0 No

bit 5 EFA Block Lock -Down Bi t Status active bi t 5 = 0 No

(P+C)h 1 116: --18 1.8V

(P+D)h 1 117: --90 9.0V

Supported functions after suspend: read Array, Status, Q uery

O ther supported operations are:

bits 1–7 reserved; undefined bits are “0”

VCC logic supply highest performance program/erase voltage

bits 0–3 BCD value in 100 mV

bits 4–7 BCD value in volts

VPP optimum program/erase supply voltage

bits 0–3 BCD value in 100 mV

bits 4–7 HEX value in volts

1-Gbit P30 Family

April 2005 Intel StrataFlas h® Embedded Memory (P30) Datasheet

98 Order Number: 306666, Revision: 001

Table 38. Protection Register Information

Table 39. Burst Read Information

Offset(1) Length Descri

tion Hex

P = 10Ah (Optional flash features and commands)

dd. Code

alue

(P+E)h 1 118: --02 2

(P+F)h 4 Protection Field 1: Protection Description 119: --80 80h

(P+10) h This fi eld d esc r ibes user - a vai lable One Tim e Pro

rammable 11A: --00 00h

(P+11)h

(

OTP

)

Protection re

ister b

tes. Some a re

re-

ram m e d 11B: --03 8 byte

(P+12)h 11C: --03 8 byte

(P+13)h 10 Protection Field 2: Protection Description 11D: --89 89h

(P+14)h 11E: --00 00h

(P+15)h 11F: --00 00h

(P+16)h 120: --00 00h

(P+17)h 121: --00 0

(P+18)h bits 40 –47 = “n” ∴ n = f actory p gm'd gr oups (h igh by t e ) 122: --00 0

(P+19)h 123: --00 0

(P+1A)h 124: --10 16

(P+1B)h 125: --00 0

(P+1C)h 126: --04 16

bits 48–55 = “n” \ 2n = f actory pr o gramm abl e bytes/ g r oup

bits 56–63 = “n” ∴ n = us er pg m' d g r oups (lo w by te)

bits 64–71 = “n” ∴ n = user

m'd

rou

(

h b

)

bits 72–79 = “n” ∴ 2n = user pr ogrammable bytes/gr oup

wit h device-un ique s erial num bers . Other s ar e us er

programmable. Bits 0–15 point to the Protection register Loc k

byte, the section’s first byte. The following bytes are factory

pre-programmed and user-programmable.

bits 0–7 = Lock/ bytes Jedec-plane physical low address

bits 8–15 = Lock/bytes Jedec-plane physical high address

bits 16–23 = “n” such th a t 2 n = f a ct o r y pr e-p r ogra mmed byte s

bits 24–31 = “n” such th a t 2 n = user pr ogr ammable byte s

Bits 0–31 point to the Protection r e gi ster physical Lock-word

address in the Jedec-plane.

Following bytes are factory or user-programmable.

bits 32–39 = “n” ∴ n = f actory p gm'd gr oups (low byt e)

Number of Protection register fields in JEDEC ID space.

“00h,” i n dicat es that 25 6 pro t e ct ion f ields ar e available

Offset(1) Length Descri

tion Hex

P = 10Ah (Optional flash features and commands)

dd. Code

alue

(P+1D)h 1 127: --03 8 byte

(P+1E)h 1 128: --04 4

(P+1F)h 1 129: --01 4

(P+20)h 1 Synchronous mode read capability configuration 2 12A: --02 8

(P+21)h 1 Synchronous mode read capability configuration 3 12B: --03 16

(P+22)h 1 Synchronous mode read capability configuration 4 12C: --07 Cont

Page Mode Read capability

bits 0–7 = “n” such that 2n HEX value represents the number of

read-page bytes. See offset 28h for device word width to

determine page-mode data output width. 00h indicates no

read

e buffer.

Number of synchronous mode read configuration fields that

follow. 00h indi cates no burst capability.

Synchronous m ode read capability configuration 1

Bits 3–7 = Reserved

bits 0–2 “n” such that 2n+1 HEX value represents the

maximum number of continuous synchronous reads when

the device is configured for its m aximum word width. A value

of 07h indicates that the device is capable of continuous

linear bursts that will output data until the internal burst

counter reaches the end of the device’s burstab le address

space. This field’s 3-bit value can be written directly to the

Read Configuration Register bits 0–2 if the device is

configured for its maximum word width. See offset 28h for

word width to determine the burst data out

ut wi dth .

1-Gbit P30 Family

Datasheet Intel StrataFlash® Embedded Memory (P30) April 2005

Order Number: 306666, Revision: 001 99

Table 40. Partition and Erase-block Region Information

Offset(1)

P= 10Ah Description

Bottom Top (Opti onal flash fea tures a n d commands)

(P+23)h (P+23)h 12D: --00 0

Hex

CodeAdd. Value

Number of device hardware-partition regions within the device.

x = 0: a singl e hardware partiti on device (no fields foll ow).

x specifies the number of device parti ti o n regi ons contain i ng

one or more contiguous erase blo ck regions.

1-Gbit P30 Family

April 2005 Intel StrataFlas h® Embedded Memory (P30) Datasheet

100 Order Number: 306666, Revision: 001

Appendix D Additional Information

Order/Document

Number Document/Tool

290667 Int el Strat aFlash® Memory (J3) Datash eet

290737 Int el Strat aFlash® Synchronous Mem or y (K3/ K18) Dat asheet

290701 Intel® Wireless Flash Memory (W18 ) Datasheet

290702 Intel® Wireless Flash Memory (W30 ) Datasheet

252802 Intel® Flash M em ory Design for a Stacked Chip Scale Package ( SCSP)

298161 Intel® Flash Mem ory Chip Scal e Package Use r’s Gui de

253418 Intel® Wireless Comm unications and Comp uting Package User's Guide

296514 Intel® Small O ut line Pac k age Guide

297833 Intel® Flash D ata Inte gr ator (FDI) U ser’ s G uide

298136 Intel® Persis t ent Storage Mana ger User Gui de

300783 Using Intel ® Flash Mem or y : Asynchronous Page Mode and Synchronous Burst Mode

306667 Migration Guide fo r Intel StrataFlash® Memory (J3) to Intel S trataFlash® Embedd ed

Memory (P30) Application Note 812

306668 Mi gration Guide for Span sion* S29GL xxxN to Intel StrataFlash® Embedded Memory

(P30) Application Not e 813

306669 Migration Guide fo r Intel StrataFlash® Synchr onous Mem or y ( K3/K18) to In te l

StrataFlash® Embedded Memory (P30) Application N ote 825

Notes:

1. Please call the I ntel Lit er at ur e Center at ( 800) 548- 4725 t o request Intel documentation. Inter nation al

custom er s should contact their local In te l or distributi on sales office.

2. Visit Intel’s World Wide Web home page at http://www.intel.com for technical documentatio n and

tools.

3. For the most cur r ent infor m at ion on Intel ® Flash Memory, visit our website at

http://developer.intel.com/design/flash.

1-Gbit P30 Family

Datasheet Intel StrataFlash® Embedded Memory (P30) April 2005

Order Number: 306666, Revision: 001 101

Appendix E Ordering Information for Discrete Products

Figure 48. Decoder for Discrete Intel StrataFlash® Embedded Memo ry (P30)

F 6 4 P 3 0 B8E 2T 0

Product Line Desig nator

2 8 F = Intel® Flas h Me mory

Package Designator

TE = 56-Lead TSOP, leaded

JS = 56-Lea d TS O P , lead-free

RC = 64 -Ball Easy BG A , leaded

PC = 64-Ball Easy BGA, lead-free

Device Density

640 = 64-M bit

128 = 128-Mbit

256 = 256-Mbit

Product Family

P30 = Intel StrataFlash® Em b edd ed M em o ry

VCC = 1.7 – 2.0 V

VCCQ = 1.7 – 3.6 V

Access Speed

85 ns

P ar a me ter L o c a tio n

B = B ottom P a ram eter

T = Top P aram eter

8 5

Table 41. Valid Combinations for Discrete Products

64-Mbit 128-Mbit 256-Mbit

TE28F640P30B85 TE28F128P30B85 TE28F256P30B85

TE28F640P30T85 TE28F128P30T85 TE28F256P30T85

JS28F640P30B85 JS28F128P30B85 JS28F256P30B85

JS28F640P30T85 JS28F128P30T85 JS28F256P30T85

RC28F640P30B85 RC28F128P30B85 RC28F256P30B85

RC28F640P30T85 RC28F128P30T85 RC28F256P30T85

PC28F640P30B85 PC28F128P30B85 PC28F256P30B85

PC28F640P30T85 PC28F128P30T85 PC28F256P30T85

1-Gbit P30 Family

April 2005 Intel StrataFlas h® Embedded Memory (P30) Datasheet

102 Order Number: 306666, Revision: 001

Appendix F Ordering Information for SCSP Products

Figure 49. Decoder for SCSP Intel StrataFlash® Embedded Memory (P30)

F 4 0 P 0 Z B8D 4R 0 0 Q

Group Designator

48F = Flash Memory only

Package Designator

RD = Inte l® SCSP , lea ded

P F = Inte l® SC SP , lead -free

RC = 6 4-B all Easy B G A , leaded

PC = 64-B all Easy BGA, lead-free

Flash Density

0 = No die

2 = 64-Mbit

3 = 128-Mbit

4 = 256-Mbit

Flash #1

Flash #2

Flash #3

Flash #4

Flash Family 1/2

Flash Family 3/4

Product Family

P = Inte l StrataFlash® E m be dd ed M e m ory

0 = No die

D evic e Deta ils

0 = Original version of the pr oduct

(refer to the latest version of the

da ta she e t for de tails)

Ballout Designator

Q = Q UA D ba llout

0 = Discrete ballout

Parameter, Mux Configuration

B = Bottom Parameter, Non Mux

T = Top Parameter, Non Mux

I/O V o lt ag e , C E # C o n fig u r a tio n

Z = 3.0 V, Individual Chip Enable(s)

V = 3 .0 V, Virtual Chip E na ble(s)

Table 42. Valid Combinations for Stacked Products

64-Mbit 128-Mbit 256-Mbit 512-Mbit 1-Gbit

RD48F2000P0ZBQ0 RD48F3000P0ZBQ0 RD48F4000P0ZBQ0 RD48F4400P0VBQ0 RD48F4444PPVBQ0

RD48F2000P0ZTQ0 RD48F3000P0ZTQ0 RD48F4000P0ZTQ0 RD48F4400P0VTQ0 RD48F4444PPVTQ0

PF48F2000P0ZBQ0 PF48F3000P0ZBQ0 PF48F4000P0ZBQ0 PF48F4400P0VBQ0 PF48F4444PPVBQ0

PF48F2000P0ZTQ0 PF48F3000P0ZTQ0 PF48F4000P0ZTQ0 PF48F4400P0VTQ0 PF48F4444PPVTQ0

RC48F4400P0VB00

RC48F4400P0VT00

PC48F4400P0VB00

PC48F4400P0VT00