Intel StrataFlash(R) Embedded Memory (P30) 1-Gbit P30 Family Datasheet Product Features High performance Security -- 85/88 ns initial access -- One-Time Programmable Registers: * 64 unique factory device identifier bits -- 40 MHz with zero wait states, 20 ns clock-to* 64 user-programmable OTP bits data output synchronous-burst read mode * Additional 2048 user-programmable OTP bits -- 25 ns asynchronous-page read mode -- Selectable OTP Space in Main Array: -- 4-, 8-, 16-, and continuous-word burst mode * 4x32KB parameter blocks + 3x128KB main -- Buffered Enhanced Factory Programming blocks (top or bottom configuration) (BEFP) at 5 s/byte (Typ) -- Absolute write protection: VPP = VSS -- 1.8 V buffered programming at 7 s/byte (Typ) -- Power-transition erase/program lockout Architecture -- Individual zero-latency block locking -- Multi-Level Cell Technology: Highest Density -- Individual block lock-down at Lowest Cost Software -- Asymmetrically-blocked architecture -- 20 s (Typ) program suspend -- Four 32-KByte parameter blocks: top or -- 20 s (Typ) erase suspend bottom configuration -- Intel(R) Flash Data Integrator optimized -- 128-KByte main blocks -- Basic Command Set and Extended Command Voltage and Power Set compatible -- VCC (core) voltage: 1.7 V - 2.0 V -- Common Flash Interface capable -- VCCQ (I/O) voltage: 1.7 V - 3.6 V Density and Packaging -- Standby current: 55 A (Typ) for 256-Mbit -- 64/128/256-Mbit densities in 56-Lead TSOP -- 4-Word synchronous read current: package 13 mA (Typ) at 40 MHz -- 64/128/256/512-Mbit densities in 64-Ball Quality and Reliability Intel(R) Easy BGA package -- Operating temperature: -40 C to +85 C * 1-Gbit in SCSP is -30 C to +85 C -- 64/128/256/512-Mbit and 1-Gbit densities in Intel(R) QUAD+ SCSP -- Minimum 100,000 erase cycles per block -- 16-bit wide data bus -- ETOXTM VIII process technology (130 nm) The Intel StrataFlash(R) Embedded Memory (P30) product is the latest generation of Intel StrataFlash(R) memory devices. Offered in 64-Mbit up through 1-Gbit densities, the P30 device brings reliable, two-bit-per-cell storage technology to the embedded flash market segment. Benefits include more density in less space, high-speed interface, lowest cost-per-bit NOR device, and support for code and data storage. Features include high-performance synchronousburst read mode, fast asynchronous access times, low power, flexible security options, and three industry standard package choices. The P30 product family is manufactured using Intel(R) 130 nm ETOXTM VIII process technology. Order Number: 306666, Revision: 001 April 2005 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. This document contains information on products in the design phase of development. The information here is subject to change without notice. Do not finalize a design with this information. StrataFlash(R) Embedded Memory (P30) Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800548-4725 or by visiting Intel's website at http://www.intel.com. Copyright (c) 2005, Intel Corporation * Other names and brands may be claimed as the property of others. April 2005 2 Intel StrataFlash(R) Embedded Memory (P30) Order Number: 306666, Revision: 001 Datasheet 1-Gbit P30 Family Contents 1.0 Introduction ...............................................................................................................................7 1.1 1.2 1.3 Nomenclature .......................................................................................................................7 Acronyms ..............................................................................................................................7 Conventions..........................................................................................................................8 2.0 Functional Overview ..............................................................................................................9 3.0 Package Information ............................................................................................................10 3.1 3.2 3.3 56-Lead TSOP Package .....................................................................................................10 64-Ball Easy BGA Package ................................................................................................12 QUAD+ SCSP Packages....................................................................................................13 4.0 Ballout and Signal Descriptions......................................................................................17 4.1 4.2 4.3 4.4 Signal Ballout......................................................................................................................17 Signal Descriptions .............................................................................................................20 SCSP Configurations ..........................................................................................................22 Memory Maps .....................................................................................................................24 5.0 Maximum Ratings and Operating Conditions ...........................................................29 5.1 5.2 Absolute Maximum Ratings ................................................................................................29 Operating Conditions ..........................................................................................................30 6.0 Electrical Specifications .....................................................................................................31 6.1 6.2 DC Current Characteristics .................................................................................................31 DC Voltage Characteristics.................................................................................................32 7.0 AC Characteristics ................................................................................................................33 7.1 7.2 7.3 7.4 7.5 AC Test Conditions.............................................................................................................33 Capacitance ........................................................................................................................34 AC Read Specifications ......................................................................................................35 AC Write Specifications ......................................................................................................41 Program and Erase Characteristics ....................................................................................45 8.0 Power and Reset Specifications .....................................................................................46 8.1 8.2 8.3 Power Up and Down ...........................................................................................................46 Reset Specifications ...........................................................................................................46 Power Supply Decoupling...................................................................................................47 9.0 Device Operations .................................................................................................................48 9.1 9.2 9.3 Datasheet Bus Operations ...................................................................................................................48 9.1.1 Reads ....................................................................................................................48 9.1.2 Writes.....................................................................................................................49 9.1.3 Output Disable .......................................................................................................49 9.1.4 Standby..................................................................................................................49 9.1.5 Reset .....................................................................................................................49 Device Commands .............................................................................................................50 Command Definitions .........................................................................................................51 Intel StrataFlash(R) Embedded Memory (P30) Order Number: 306666, Revision: 001 April 2005 3 1-Gbit P30 Family 10.0 Read Operations .................................................................................................................... 53 10.1 10.2 10.3 Asynchronous Page-Mode Read........................................................................................ 53 Synchronous Burst-Mode Read.......................................................................................... 53 Read Configuration Register .............................................................................................. 54 10.3.1 Read Mode ............................................................................................................ 55 10.3.2 Latency Count........................................................................................................ 55 10.3.3 WAIT Polarity......................................................................................................... 57 10.3.4 Data Hold............................................................................................................... 58 10.3.5 WAIT Delay............................................................................................................ 59 10.3.6 Burst Sequence ..................................................................................................... 59 10.3.7 Clock Edge ............................................................................................................ 59 10.3.8 Burst Wrap............................................................................................................. 59 10.3.9 Burst Length .......................................................................................................... 60 11.0 Programming Operations .................................................................................................. 61 11.1 11.2 11.3 11.4 11.5 11.6 Word Programming............................................................................................................. 61 11.1.1 Factory Word Programming................................................................................... 62 Buffered Programming........................................................................................................ 62 Buffered Enhanced Factory Programming ......................................................................... 63 11.3.1 BEFP Requirements and Considerations .............................................................. 64 11.3.2 BEFP Setup Phase................................................................................................ 64 11.3.3 BEFP Program/Verify Phase ................................................................................. 64 11.3.4 BEFP Exit Phase ................................................................................................... 65 Program Suspend............................................................................................................... 65 Program Resume................................................................................................................ 66 Program Protection............................................................................................................. 66 12.0 Erase Operations ................................................................................................................... 67 12.1 12.2 12.3 12.4 Block Erase......................................................................................................................... 67 Erase Suspend ................................................................................................................... 67 Erase Resume .................................................................................................................... 68 Erase Protection ................................................................................................................. 68 13.0 Security Modes....................................................................................................................... 69 13.1 13.2 13.3 Block Locking...................................................................................................................... 69 13.1.1 Lock Block ............................................................................................................. 69 13.1.2 Unlock Block .......................................................................................................... 69 13.1.3 Lock-Down Block ................................................................................................... 69 13.1.4 Block Lock Status .................................................................................................. 70 13.1.5 Block Locking During Suspend.............................................................................. 70 Selectable One-Time Programmable Blocks...................................................................... 71 Protection Registers ........................................................................................................... 72 13.3.1 Reading the Protection Registers .......................................................................... 73 13.3.2 Programming the Protection Registers.................................................................. 73 13.3.3 Locking the Protection Registers ........................................................................... 74 14.0 Special Read States ............................................................................................................. 75 14.1 14.2 April 2005 4 Read Status Register.......................................................................................................... 75 14.1.1 Clear Status Register............................................................................................. 76 Read Device Identifier ........................................................................................................ 76 Intel StrataFlash(R) Embedded Memory (P30) Order Number: 306666, Revision: 001 Datasheet 1-Gbit P30 Family 14.3 CFI Query ...........................................................................................................................77 Appendix A Write State Machine ..........................................................................................78 Appendix B Flowcharts ............................................................................................................85 Appendix C Common Flash Interface ................................................................................93 Appendix D Additional Information ................................................................................... 100 Appendix E Ordering Information for Discrete Products ........................................ 101 Appendix F Ordering Information for SCSP Products ..............................................102 Datasheet Intel StrataFlash(R) Embedded Memory (P30) Order Number: 306666, Revision: 001 April 2005 5 1-Gbit P30 Family Revision History Revision Date Revision April 2005 -001 April 2005 6 Description Initial Release Intel StrataFlash(R) Embedded Memory (P30) Order Number: 306666, Revision: 001 Datasheet 1-Gbit P30 Family 1.0 Introduction This document provides information about the Intel StrataFlash(R) Embedded Memory (P30) device and describes its features, operation, and specifications. 1.1 1.2 Datasheet Nomenclature 1.8 V : VCC (core) voltage range of 1.7 V - 2.0 V 3.0 V : VCCQ (I/O) voltage range of 1.7 V - 3.6 V 9.0 V : VPP voltage range of 8.5 V - 9.5 V Block : A group of bits, bytes,1-Gbit P30 Family or words within the flash memory array that erase simultaneously when the Erase command is issued to the device. The 1-Gbit P30 Family has two block sizes: 32-KByte and 128-KByte. Main block : An array block that is usually used to store code and/or data. Main blocks are larger than parameter blocks. Parameter block : An array block that is usually used to store frequently changing data or small system parameters that traditionally would be stored in EEPROM. Top parameter device : A device with its parameter blocks located at the highest physical address of its memory map. Bottom parameter device : A device with its parameter blocks located at the lowest physical address of its memory map. Acronyms BEFP : Buffer Enhanced Factory Programming CUI : Command User Interface MLC : Multi-Level Cell OTP : One-Time Programmable PLR : Protection Lock Register PR : Protection Register RCR : Read Configuration Register Intel StrataFlash(R) Embedded Memory (P30) Order Number: 306666, Revision: 001 April 2005 7 1-Gbit P30 Family 1.3 April 2005 8 RFU : Reserved for Future Use SR : Status Register WSM : Write State Machine Conventions VCC : Signal or voltage connection VCC : Signal or voltage level 0x : Hexadecimal number prefix 0b : Binary number prefix SR[4] : Denotes an individual register bit. A[15:0] : Denotes a group of similarly named signals, such as address or data bus. A5 : Denotes one element of a signal group membership, such as an individual address bit. Bit : Binary unit Byte : Eight bits Word : Two bytes, or sixteen bits Kbit : 1024 bits KByte : 1024 bytes KWord : 1024 words Mbit : 1,048,576 bits MByte : 1,048,576 bytes MWord : 1,048,576 words Intel StrataFlash(R) Embedded Memory (P30) Order Number: 306666, Revision: 001 Datasheet 1-Gbit P30 Family 2.0 Functional Overview This section provides an overview of the features and capabilities of the 1-Gbit P30 Family device. The P30 family provides density upgrades from 64-Mbit through 1-Gbit. This family of devices provides high performance at low voltage on a 16-bit data bus. Individually erasable memory blocks are sized for optimum code and data storage. Upon initial power up or return from reset, the device defaults to asynchronous page-mode read. Configuring the Read Configuration Register enables synchronous burst-mode reads. In synchronous burst mode, output data is synchronized with a user-supplied clock signal. A WAIT signal provides an easy CPU-to-flash memory synchronization. In addition to the enhanced architecture and interface, the device incorporates technology that enables fast factory program and erase operations. Designed for low-voltage systems, the 1-Gbit P30 Family supports read operations with VCC at 1.8 V, and erase and program operations with VPP at 1.8 V or 9.0 V. Buffered Enhanced Factory Programming (BEFP) provides the fastest flash array programming performance with VPP at 9.0 V, which increases factory throughput. With VPP at 1.8 V, VCC and VPP can be tied together for a simple, ultra low power design. In addition to voltage flexibility, a dedicated VPP connection provides complete data protection when VPP VPPLK. A Command User Interface (CUI) is the interface between the system processor and all internal operations of the device. An internal Write State Machine (WSM) automatically executes the algorithms and timings necessary for block erase and program. A Status Register indicates erase or program completion and any errors that may have occurred. An industry-standard command sequence invokes program and erase automation. Each erase operation erases one block. The Erase Suspend feature allows system software to pause an erase cycle to read or program data in another block. Program Suspend allows system software to pause programming to read other locations. Data is programmed in word increments (16 bits). The 1-Gbit P30 Family's protection register allows unique flash device identification that can be used to increase system security. The individual Block Lock feature provides zero-latency block locking and unlocking. In addition, the P30 device also has four pre-defined spaces in the main array that can be configured as One-Time Programmable (OTP). Datasheet Intel StrataFlash(R) Embedded Memory (P30) Order Number: 306666, Revision: 001 April 2005 9 1-Gbit P30 Family 3.0 Package Information 3.1 56-Lead TSOP Package Figure 1. TSOP Mechanical Specifications Z A2 See Note 2 See Notes 1 and 3 Pin 1 e See Detail B E Y D1 A1 D Seating Plane See Detail A A Detail A Detail B C 0 b L [231369-90] Table 1. TSOP Package Dimensions (Sheet 1 of 2) Millimeters Product Information Package Height April 2005 10 Inches Sym Min Nom Max Min Nom Max A - - 1.200 - - 0.047 Standoff A1 0.050 - - 0.002 - - Package Body Thickness A2 0.965 0.995 1.025 0.038 0.039 0.040 Lead Width b 0.100 0.150 0.200 0.004 0.006 0.008 Lead Thickness c 0.100 0.150 0.200 0.004 0.006 0.008 Package Body Length D1 18.200 18.400 18.600 0.717 0.724 0.732 Package Body Width E 13.800 14.000 14.200 0.543 0.551 0.559 Lead Pitch e - 0.500 - - 0.0197 - Intel StrataFlash(R) Embedded Memory (P30) Order Number: 306666, Revision: 001 Datasheet 1-Gbit P30 Family Table 1. TSOP Package Dimensions (Sheet 2 of 2) Millimeters Product Information Datasheet Inches Sym Min Nom Max Min Nom Max Terminal Dimension D 19.800 20.00 20.200 0.780 0.787 0.795 Lead Tip Length L 0.500 0.600 0.700 0.020 0.024 0.028 Lead Count N - 56 - - 56 - Lead Tip Angle 0 3 5 0 3 5 Seating Plane Coplanarity Y - - 0.100 - - 0.004 Lead to Package Offset Z 0.150 0.250 0.350 0.006 0.010 0.014 Intel StrataFlash(R) Embedded Memory (P30) Order Number: 306666, Revision: 001 April 2005 11 1-Gbit P30 Family 3.2 64-Ball Easy BGA Package Figure 2. Easy BGA Mechanical Specifications Ball A1 Corner Ball A1 Corner D 1 2 3 S1 4 5 6 7 8 8 A A B B C C D D E E 7 6 5 4 3 2 1 S2 b E F F G G H H e Top View - Ball side down Bottom View - Ball Side Up A1 A2 A Seating Y Plane Note: Drawing not to scale Table 2. Easy BGA Package Dimensions Millimeters Product Information Inches Symbol Notes Min Nom Max Min Nom Max Package Height (64/128/256-Mbit) A - - 1.200 - - 0.0472 Package Height (512-Mbit) A - - 1.300 - - 0.0512 Ball Height (64/128/256-Mbit) A1 0.250 - - 0.0098 - - Ball Height (512-Mbit) A1 0.240 - - 0.0094 - - Package Body Thickness (64/128/256-Mbit) A2 - 0.780 - - 0.0307 - Package Body Thickness (512-Mbit) A2 - 0.910 - - 0.0358 - Ball (Lead) Width b 0.330 0.430 0.530 0.0130 0.0169 0.0209 Package Body Width D 9.900 10.000 10.100 0.3898 0.3937 0.3976 1 Package Body Length E 12.900 13.000 13.100 0.5079 0.5118 0.5157 1 Pitch [e] - 1.000 - - 0.0394 - Ball (Lead) Count N - 64 - - 64 - Seating Plane Coplanarity Y - - 0.100 - - 0.0039 Corner to Ball A1 Distance Along D S1 1.400 1.500 1.600 0.0551 0.0591 0.0630 1 Corner to Ball A1 Distance Along E S2 2.900 3.000 3.100 0.1142 0.1181 0.1220 1 Note: Daisy Chain Evaluation Unit information is at Intel(R) Flash Memory Packaging Technology http://developer.intel.com/ design/flash/packtech. April 2005 12 Intel StrataFlash(R) Embedded Memory (P30) Order Number: 306666, Revision: 001 Datasheet 1-Gbit P30 Family 3.3 QUAD+ SCSP Packages Figure 3. 64/128-Mbit, 88-ball (80 active) QUAD+ SCSP Specifications (8x10x1.2 mm) A1 Index Mark S1 1 2 3 4 5 6 7 8 8 A A B B C C D D E E F D 7 6 5 4 3 2 1 S2 F G G H H J K J e K L L M M b E Top View - Ball Down A2 Bottom View - Ball Up A1 A Y D raw ing not to scale. Dimensions Package Height Ball Height Package Body Thickness Ball (Lead) Width Package Body Width Package Body Length Pitch Ball (Lead) Count Seating Plane Coplanarity Corner to Ball A1 Distance Along E Corner to Ball A1 Distance Along D Datasheet Symbol A A1 A2 b D E e N Y S1 S2 Min 0.200 0.325 9.900 7.900 1.100 0.500 Millimeters Nom Max 1.200 0.860 0.375 0.425 10.000 10.100 8.000 8.100 0.800 88 0.100 1.200 1.300 0.600 0.700 Intel StrataFlash(R) Embedded Memory (P30) Order Number: 306666, Revision: 001 Min 0.0079 0.0128 0.3898 0.3110 0.0433 0.0197 Inches Nom 0.0339 0.0148 0.3937 0.3150 0.0315 88 0.0472 0.0236 Max 0.0472 0.0167 0.3976 0.3189 0.0039 0.0512 0.0276 April 2005 13 1-Gbit P30 Family Figure 4. 256-Mbit, 88-ball (80 active) QUAD+ SCSP Specifications (8x11x1.0 mm) S1 A 1 Index Mark 1 2 3 4 5 6 7 8 8 7 6 5 4 3 2 1 S2 A A B B C C D D E E F D F G G H H J J K K L L M M e b E Bottom View - Ball Up Top View - Ball Down A2 A1 A Y D raw ing not to s cale . N ote: Dimensions A1, A2, and b are preliminary Dimensions Package Height Ball Height Package Body Thickness Ball (Lead) Width Package Body Length Package Body Width Pitch Ball (Lead) Count Seating Plane Coplanarity Corner to Ball A1 Distance Along E Corner to Ball A1 Distance Along D April 2005 14 Symbol A A1 A2 b D E e N Y S1 S2 Min 0.117 0.300 10.900 7.900 1.100 1.000 Millimeters Nom Max 1.000 0.740 0.350 0.400 11.00 11.100 8.00 8.100 0.80 88 0.100 1.200 1.300 1.100 1.200 Intel StrataFlash(R) Embedded Memory (P30) Order Number: 306666, Revision: 001 Min 0.0046 0.0118 0.4291 0.3110 0.0433 0.0394 Inches Nom 0.0291 0.0138 0.4331 0.3150 0.0315 88 0.0472 0.0433 Max 0.0394 0.0157 0.4370 0.3189 0.0039 0.0512 0.0472 Datasheet 1-Gbit P30 Family Figure 5. 512-Mbit, 88-ball (80 active) QUAD+ SCSP Specifications (8x11x1.2 mm) S1 A 1 Index Mark 1 2 3 4 5 6 7 8 8 7 6 5 4 3 2 1 S2 A A B B C C D D E E F D F G G H H J K K e J L L M M b E Bottom View - Ball Up Top View - Ball Down A2 A1 A Y D raw ing not to scale . Dimensions Package Height Ball Height Package Body Thickness Ball (Lead) Width Package Body Length Package Body Width Pitch Ball (Lead) Count Seating Plane Coplanarity Corner to Ball A1 Distance Along E Corner to Ball A1 Distance Along D Datasheet Symbol A A1 A2 b D E e N Y S1 S2 Min 0.200 0.325 10.900 7.900 1.100 1.000 Millimeters Nom Max 1.200 0.860 0.375 0.425 11.000 11.100 8.000 8.100 0.800 88 0.100 1.200 1.300 1.100 1.200 Intel StrataFlash(R) Embedded Memory (P30) Order Number: 306666, Revision: 001 Min 0.0079 0.0128 0.4291 0.3110 0.0433 0.0394 Inches Nom 0.0339 0.0148 0.4331 0.3150 0.0315 88 0.0472 0.0433 Max 0.0472 0.0167 0.4370 0.3189 0.0039 0.0512 0.0472 April 2005 15 1-Gbit P30 Family Figure 6. 1-Gbit, 88-ball (80 active) QUAD+ SCSP Specifications (11x11x1.4 mm) S1 A1 Index Mark 1 2 3 4 5 6 7 8 8 7 6 5 4 3 2 1 S2 A A B B C C D D E E F D F G G H H J J K K L L M M e b E Bottom View - Ball Up Top View - Ball Down A2 A1 A Y Drawing not to scale. Dimens ions Packag e Height Ball Height Packag e Body Thicknes s Ball (Lead) W idth Packag e Body Length Packag e Body W idth Pitch Ball (Lead) Count Seating Plane Coplanarity Corner to Ball A 1 Dis tance A lon g E Corner to Ball A 1 Dis tance A lon g D April 2005 16 S ymbol A A1 A2 b D E e N Y S1 S2 Min 0.200 0.325 10.900 10.900 2.600 1.000 Millimeters Nom Max 1.400 1.070 0.375 0.425 11.000 11.100 11.000 11.100 0.800 88 0.100 2.700 2.800 1.100 1.200 Intel StrataFlash(R) Embedded Memory (P30) Order Number: 306666, Revision: 001 Min 0.0079 0.0128 0.4291 0.4291 0.1024 0.0394 Inches Nom 0.0421 0.0148 0.4331 0.4331 0.0315 88 0.1063 0.0433 Max 0.0551 0.0167 0.4370 0.4370 0.0039 0.1102 0.0472 Datasheet 1-Gbit P30 Family 4.0 Ballout and Signal Descriptions 4.1 Signal Ballout Figure 7. 56-Lead TSOP Pinout (64/128/256-Mbit) A 16 A15 A14 A13 A12 A11 A10 A9 A23 A22 A21 VSS VCC WE# WP# A20 A19 A18 A8 A7 A6 A5 A4 A3 A2 A24 RFU VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Intel StrataFlash(R) Embedded Memory (P 30) 56-Lead TSOP Pinout 14 mm x 20 mm Top View 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 WAIT A 17 DQ15 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 ADV# CLK RST# VPP DQ11 DQ3 DQ10 DQ2 VCCQ DQ9 DQ1 DQ8 DQ0 VCC OE # VSS CE# A1 Notes: 1. A1 is the least significant address bit. 2. A23 is valid for 128-Mbit densities and above; otherwise, it is a no connect (NC). 3. A24 is valid for 256-Mbit densities and above; otherwise, it is a no connect (NC). Datasheet Intel StrataFlash(R) Embedded Memory (P30) Order Number: 306666, Revision: 001 April 2005 17 1-Gbit P30 Family Figure 8. 64-Ball Easy BGA Ballout (64/128/256/512-Mbit) 1 2 3 4 5 6 7 8 8 7 A1 A6 A8 VPP A13 VCC A18 A22 A22 A18 A2 VSS A9 CE# A14 A25 A19 RFU RFU A3 A7 A10 A12 A15 WP# A20 A21 A4 A5 A11 RST# VCCQ VCCQ A16 A17 5 6 4 3 2 1 VCC A13 VPP A8 A6 A1 A19 A25 A14 CE# A9 VSS A2 A21 A20 WP# A15 A12 A10 A7 A3 A17 A16 VCCQ VCCQ RST# A11 A5 A4 A A B B C C D D E E DQ8 DQ1 DQ9 DQ3 DQ4 CLK DQ15 RFU RFU DQ15 CLK DQ4 DQ3 DQ9 DQ1 DQ8 RFU DQ0 DQ10 DQ11 DQ12 ADV# WAIT OE# OE# WAIT ADV# DQ12 DQ11 DQ10 DQ0 RFU A23 RFU WE# DQ14 DQ6 DQ5 VCCQ DQ2 RFU A23 RFU VSS VCC VSS DQ13 VSS DQ7 A24 DQ13 VSS VCC VSS RFU F F G G DQ2 VCCQ DQ5 DQ6 DQ14 WE# H H Easy BGA Top View- Ball side down Notes: 1. 2. 3. 4. April 2005 18 A24 DQ7 VSS Easy BGA Bottom View- Ball side up A1 is the least significant address bit. A23 is valid for 128-Mbit densities and above; otherwise, it is a no connect (NC). A24 is valid for 256-Mbit densities and above; otherwise, it is a no connect (NC). A25 is valid for 512-Mbit densities; otherwise, it is a no connect (NC). Intel StrataFlash(R) Embedded Memory (P30) Order Number: 306666, Revision: 001 Datasheet 1-Gbit P30 Family Figure 9. 88-Ball (80-Active Ball) QUAD+ SCSP Ballout Pin 1 Datasheet 1 2 3 4 5 6 7 8 A DU DU Depop Depop Depop Depop DU DU A B A4 A18 A19 VSS VCC VCC A21 A11 B C A5 RFU A23 VSS RFU CLK A22 A12 C D A3 A17 A24 VPP RFU RFU A9 A13 D E A2 A7 RFU WP# ADV# A20 A10 A15 E F A1 A6 RFU RST# WE# A8 A14 A16 F G A0 DQ8 DQ2 DQ10 DQ5 DQ13 WAIT F2-CE# G H RFU DQ0 DQ1 DQ3 DQ12 DQ14 DQ7 F2-OE# H J RFU F1-OE# DQ9 DQ11 DQ4 DQ6 DQ15 VCCQ J K F1-CE# RFU RFU RFU RFU VCC VCCQ RFU K L VSS VSS VCCQ VCC VSS VSS VSS VSS L M DU DU Depop Depop Depop Depop DU DU M 1 2 3 4 5 6 7 8 Intel StrataFlash(R) Embedded Memory (P30) Order Number: 306666, Revision: 001 April 2005 19 1-Gbit P30 Family 4.2 Signal Descriptions This section has signal descriptions for the various P30 packages. Table 3. Symbol A[MAX:1] TSOP and Easy BGA Signal Descriptions (Sheet 1 of 2) Type Input Name and Function ADDRESS INPUTS: Device address inputs. 64-Mbit: A[22:1]; 128-Mbit: A[23:1]; 256-Mbit: A[24:1]; 512-Mbit: A[25:1]. See Table 5 on page 22 and Figure 10 on page 23 for 512-Mbit addressing. DQ[15:0] Input/ Output DATA INPUT/OUTPUTS: Inputs data and commands during write cycles; outputs data during memory, Status Register, Protection Register, and Read Configuration Register reads. Data balls float when the CE# or OE# are deasserted. Data is internally latched during writes. ADDRESS VALID: Active low input. During synchronous read operations, addresses are latched on the rising edge of ADV#, or on the next valid CLK edge with ADV# low, whichever occurs first. ADV# CE# CLK Input Input Input In asynchronous mode, the address is latched when ADV# going high or continuously flows through if ADV# is held low. WARNING: Designs not using ADV# must tie it to VSS to allow addresses to flow through. FLASH CHIP ENABLE: Active low input. CE# low selects the associated flash memory die. When asserted, flash internal control logic, input buffers, decoders, and sense amplifiers are active. When deasserted, the associated flash die is deselected, power is reduced to standby levels, data and WAIT outputs are placed in high-Z state. WARNING: All chip enables must be high when device is not in use. CLOCK: Synchronizes the device with the system's bus frequency in synchronous-read mode. During synchronous read operations, addresses are latched on the rising edge of ADV#, or on the next valid CLK edge with ADV# low, whichever occurs first. WARNING: Designs not using CLK for synchronous read mode must tie it to VCCQ or VSS. OE# Input OUTPUT ENABLE: Active low input. OE# low enables the device's output data buffers during read cycles. OE# high places the data outputs and WAIT in High-Z. RST# Input RESET: Active low input. RST# resets internal automation and inhibits write operations. This provides data protection during power transitions. RST# high enables normal operation. Exit from reset places the device in asynchronous read array mode. WAIT Output WAIT: Indicates data valid in synchronous array or non-array burst reads. Read Configuration Register bit 10 (RCR[10], WT) determines its polarity when asserted. WAIT's active output is VOL or VOH when CE# and OE# are VIL. WAIT is high-Z if CE# or OE# is VIH. * In synchronous array or non-array read modes, WAIT indicates invalid data when asserted and valid data when deasserted. * In asynchronous page mode, and all write modes, WAIT is deasserted. WE# Input WRITE ENABLE: Active low input. WE# controls writes to the device. Address and data are latched on the rising edge of WE#. WP# Input WRITE PROTECT: Active low input. WP# low enables the lock-down mechanism. Blocks in lockdown cannot be unlocked with the Unlock command. WP# high overrides the lock-down function enabling blocks to be erased or programmed using software commands. Erase and Program Power: A valid voltage on this pin allows erasing or programming. Memory contents cannot be altered when VPP VPPLK. Block erase and program at invalid VPP voltages should not be attempted. VPP Power/ Input Set VPP = VCC for in-system program and erase operations. To accommodate resistor or diode drops from the system supply, the VIH level of VPP can be as low as VPPL min. VPP must remain above VPPL min to perform in-system flash modification. VPP may be 0 V during read operations. VPPH can be applied to main blocks for 1000 cycles maximum and to parameter blocks for 2500 cycles. VPP can be connected to 9 V for a cumulative total not to exceed 80 hours. Extended use of this pin at 9 V may reduce block cycling capability. VCC April 2005 20 Power Device Core Power Supply: Core (logic) source voltage. Writes to the flash array are inhibited when VCC VLKO. Operations at invalid VCC voltages should not be attempted. Intel StrataFlash(R) Embedded Memory (P30) Order Number: 306666, Revision: 001 Datasheet 1-Gbit P30 Family Table 3. Symbol TSOP and Easy BGA Signal Descriptions (Sheet 2 of 2) Type Name and Function VCCQ Power Output Power Supply: Output-driver source voltage. VSS Power Ground: Connect to system ground. Do not float any VSS connection. RFU -- Reserved for Future Use: Reserved by Intel for future device functionality and enhancement. These should be treated in the same way as a Do Not Use (DU) signal. DU -- Do Not Use: Do not connect to any other signal, or power supply; must be left floating. NC -- No Connect: No internal connection; can be driven or floated. Table 4. Symbol QUAD+ SCSP Signal Descriptions (Sheet 1 of 2) Type A[MAX:0] Input DQ[15:0] Input/ Output Name and Function ADDRESS INPUTS: Device address inputs. 64-Mbit: A[21:0]; 128-Mbit: A[22:0]; 256-Mbit: A[23:0]; 512-Mbit: A[24:0]. See Table 6 on page 22, Figure 11 on page 23, and Figure 12 on page 23 for 512-Mbit and 1-Gbit addressing. DATA INPUT/OUTPUTS: Inputs data and commands during write cycles; outputs data during memory, Status Register, Protection Register, and Read Configuration Register reads. Data balls float when the CE# or OE# are deasserted. Data is internally latched during writes. ADDRESS VALID: Active low input. During synchronous read operations, addresses are latched on the rising edge of ADV#, or on the next valid CLK edge with ADV# low, whichever occurs first. ADV# F1-CE# F2-CE# Input Input In asynchronous mode, the address is latched when ADV# going high or continuously flows through if ADV# is held low. WARNING: Designs not using ADV# must tie it to VSS to allow addresses to flow through. FLASH CHIP ENABLE: Active low input. CE# low selects the associated flash memory die. When asserted, flash internal control logic, input buffers, decoders, and sense amplifiers are active. When deasserted, the associated flash die is deselected, power is reduced to standby levels, data and WAIT outputs are placed in high-Z state. See Table 6 on page 22 for CE# assignment definitions. WARNING: All chip enables must be high when device is not in use. CLK Input CLOCK: Synchronizes the device with the system's bus frequency in synchronous-read mode. During synchronous read operations, addresses are latched on the rising edge of ADV#, or on the next valid CLK edge with ADV# low, whichever occurs first. WARNING: Designs not using CLK for synchronous read mode must tie it to VCCQ or VSS. F1-OE# F2-OE# RST# WAIT Input OUTPUT ENABLE: Active low input. OE# low enables the device's output data buffers during read cycles. OE# high places the data outputs and WAIT in High-Z. F1-OE# and F2-OE# should be tied together for all densities. Input Output RESET: Active low input. RST# resets internal automation and inhibits write operations. This provides data protection during power transitions. RST# high enables normal operation. Exit from reset places the device in asynchronous read array mode. WAIT: Indicates data valid in synchronous array or non-array burst reads. Read Configuration Register bit 10 (RCR[10], WT) determines its polarity when asserted. WAIT's active output is VOL or VOH when CE# and OE# are VIL. WAIT is high-Z if CE# or OE# is VIH. * In synchronous array or non-array read modes, WAIT indicates invalid data when asserted and valid data when deasserted. * In asynchronous page mode, and all write modes, WAIT is deasserted. WE# Datasheet Input WRITE ENABLE: Active low input. WE# controls writes to the device. Address and data are latched on the rising edge of WE#. Intel StrataFlash(R) Embedded Memory (P30) Order Number: 306666, Revision: 001 April 2005 21 1-Gbit P30 Family Table 4. Symbol WP# QUAD+ SCSP Signal Descriptions (Sheet 2 of 2) Type Input Name and Function WRITE PROTECT: Active low input. WP# low enables the lock-down mechanism. Blocks in lockdown cannot be unlocked with the Unlock command. WP# high overrides the lock-down function enabling blocks to be erased or programmed using software commands. Erase and Program Power: A valid voltage on this pin allows erasing or programming. Memory contents cannot be altered when VPP VPPLK. Block erase and program at invalid VPP voltages should not be attempted. VPP Power/ lnput Set VPP = VCC for in-system program and erase operations. To accommodate resistor or diode drops from the system supply, the VIH level of VPP can be as low as VPPL min. VPP must remain above VPPL min to perform in-system flash modification. VPP may be 0 V during read operations. VPPH can be applied to main blocks for 1000 cycles maximum and to parameter blocks for 2500 cycles. VPP can be connected to 9 V for a cumulative total not to exceed 80 hours. Extended use of this pin at 9 V may reduce block cycling capability. VCC Power Device Core Power Supply: Core (logic) source voltage. Writes to the flash array are inhibited when VCC VLKO. Operations at invalid VCC voltages should not be attempted. VCCQ Power Output Power Supply: Output-driver source voltage. VSS Power Ground: Connect to system ground. Do not float any VSS connection. RFU -- Reserved for Future Use: Reserved by Intel for future device functionality and enhancement. These should be treated in the same way as a Do Not Use (DU) signal. DU -- Do Not Use: Do not connect to any other signal, or power supply; must be left floating. NC -- No Connect: No internal connection; can be driven or floated. 4.3 SCSP Configurations Table 5. Stacked Easy BGA Chip Select Logic Table 6. Stack Combination Selected Flash Die #1 Selected Flash Die #2 1-die F1-CE# - 2-die F1-CE# + A25 (VIL) F1-CE# + A25 (VIH) QUAD+ SCSP Chip Select Logic Stack Combination April 2005 22 Selected Flash Die #1 Selected Flash Die #2 Selected Flash Die #3 Selected Flash Die #4 1-die F1-CE# - - - 2-die F1-CE# + A24 (VIL) F1-CE# + A24 (VIH) - - 4-die F1-CE# + A24 (VIL) F1-CE# + A24 (VIH) F2-CE# + A24 (VIL) F2-CE# + A24 (VIH) Intel StrataFlash(R) Embedded Memory (P30) Order Number: 306666, Revision: 001 Datasheet 1-Gbit P30 Family Figure 10. 512-Mbit Easy BGA Device Block Diagram Easy BGA 2-Die (512-Mbit) Device Configuration F1-CE# Flash Die #1 (256-Mbit) WP# OE# WE# RST# VCC VPP VCCQ VSS CLK ADV# Flash Die #2 (256-Mbit) DQ[15:0] A[MAX:1] WAIT Figure 11. 512-Mbit QUAD+ SCSP Device Block Diagram QUAD+ 2-Die (512-Mbit) Device Configuration F1-CE# Flash Die #1 (256-Mbit) WP# OE# WE# RST# VCC VPP CLK ADV# VCCQ VSS Flash Die #2 (256-Mbit) A[MAX:0] DQ[15:0] WAIT Figure 12. 1-Gbit QUAD+ SCSP Device Block Diagram QUAD+ 4-Die (1-Gbit) Device Configuration F1-CE# WP# OE# WE# F2-CE# Flash Die #1 (256-Mbit) Flash Die #3 (256-Mbit) CLK ADV# VCCQ VSS Flash Die #2 (256-Mbit) Flash Die #4 (256-Mbit) A[MAX:0] Datasheet RST# VCC VPP DQ[15:0] WAIT Intel StrataFlash(R) Embedded Memory (P30) Order Number: 306666, Revision: 001 April 2005 23 1-Gbit P30 Family 4.4 Memory Maps Table 7 through Table 10 show the P30 memory maps. See Section 11.0, "Programming Operations" on page 61 for Programming Region information. 258 FFC000 - FFFFFF 130 7FC000 - 7FFFFF 32 255 FF0000 - FF3FFF 127 7F0000 - FF3FFF 15 April 2005 24 66 3FC000 - 3FFFFF 32 63 3F0000 - 3F3FFF 128 62 3E0000 - 3EFFFF ... 111 6F0000 - 6FFFFF 5 128 47 2F0000 - 2FFFFF ... DF0000 - DFFFFF 300000 - 30FFFF ... 223 48 ... 128 128 ... 700000 - 70FFFF ... 112 ... E00000 - E0FFFF ... 224 ... 128 6 ... ... 370000 - 37FFFF ... ... 380000 - 38FFFF 55 ... ... 56 128 ... ... 128 770000 - 77FFFF ... ... 780000 - 78FFFF 119 ... ... 120 EF0000 - EFFFFF ... ... F00000 - F0FFFF 239 ... 240 128 128 208 D00000 - D0FFFF 104 680000 - 68FFFF 128 40 280000 - 28FFFF 128 207 CF0000 - CFFFFF 103 670000 - 67FFFF 128 39 270000 - 27FFFF ... ... ... ... ... 96 600000 - 60FFFF 128 32 200000 - 20FFFF 128 191 BF0000 - BFFFFF 95 5F0000 - 5FFFFF 128 31 1F0000 - 1FFFFF ... 24 180000 - 18FFFF 128 23 170000 - 17FFFF 1 128 15 0F0000 - 0FFFFF 900000 - 90FFFF 72 480000 - 48FFFF 128 8 080000 - 08FFFF 128 143 8F0000 - 8FFFFF 71 470000 - 47FFFF 128 7 070000 - 07FFFF 128 0 000000 - 00FFFF 128 800000 - 80FFFF 64 400000 - 40FFFF 128 127 7F0000 - 7FFFFF 63 3F0000 - 3FFFFF ... 128 ... ... 144 ... 128 ... ... 4F0000 - 4FFFFF ... 79 ... 9F0000 - 9FFFFF 100000 - 10FFFF ... 159 16 ... 128 128 ... 500000 - 50FFFF ... 80 ... A0000 - A0FFFF ... 160 ... 128 2 ... ... 128 570000 - 57FFFF ... ... 580000 - 58FFFF 87 ... 88 AF0000 - AFFFFF ... B00000 - B0FFFF 175 ... 176 128 ... 128 ... ... 3 ... ... ... C00000 - C0FFFF ... ... 192 ... ... 4 128 ... 7 32 128 ... 8 7E0000 - 7EFFFF ... 9 126 ... 10 64-Mbit ... 11 FE0000 - FEFFFF ... 12 254 ... 13 Blk 7 128 14 Size (KB) ... 32 Programming Region # ... 128-Mbit ... Blk ... 256-Mbit ... Blk ... Size (KB) ... Programming Region # Discrete Top Parameter Memory Maps (all packages) ... Table 7. 128 112 700000 - 70FFFF 56 380000 - 38FFFF 0 Intel StrataFlash(R) Embedded Memory (P30) Order Number: 306666, Revision: 001 Datasheet 1-Gbit P30 Family Datasheet ... 5F0000 - 5FFFFF 47 2F0000 - 2FFFFF 270000 - 27FFFF 200000 - 20FFFF 128 63 3F0000 - 3FFFFF 31 1F0000 - 1FFFFF 128 47 2F0000 - 2FFFFF 23 170000 - 17FFFF 128 31 1F0000 - 1FFFFF 15 0F0000 - 0FFFFF Blk 64-Mbit 128 62 3F0000 - 3FFFFF ... 100000 - 10FFFF 128 16 100000 - 10FFFF 8 080000 - 08FFFF 128 15 0F0000 - 0FFFFF 7 070000 - 07FFFF ... 16 ... 200000 - 20FFFF ... 32 ... 128 ... ... 180000 - 18FFFF ... 24 ... 300000 - 30FFFF ... 48 ... 128 ... ... 32 ... 400000 - 40FFFF ... 64 ... 128 ... ... 280000 - 28FFFF 38 ... 39 4F0000 - 4FFFFF ... 500000 - 50FFFF 79 ... 80 128 ... 128 Size (KB) ... ... 95 ... ... 128 ... ... 300000 - 30FFFF ... ... 48 ... 600000 - 60FFFF 128 0 000000 - 00FFFF 0 000000 - 00FFFF Discrete Bottom Parameter Memory Maps (all packages) 128 258 FF0000 - FFFFFF 130 7F0000 - 7FFFFF Programming Region 7 243 F00000 - F0FFFF 123 780000 - 78FFFF 128 56 380000 - 38FFFF 128 242 EF0000 - EFFFFF 122 770000 - 77FFFF 128 55 370000 - 37FFFF E00000 - E0FFFF 115 700000 - 70FFFF 128 48 300000 - 30FFFF 226 DF0000 - DFFFFF 114 6F0000 - 6FFFFF 128 47 2F0000 - 2FFFFF 128 211 D00000 - D0FFFF 107 680000 - 68FFFF 5 Intel StrataFlash(R) Embedded Memory (P30) Order Number: 306666, Revision: 001 ... ... 227 128 ... ... 128 ... ... 6 ... 128 ... ... 128-Mbit ... Blk ... 256-Mbit ... Blk ... Size (KB) ... 13 96 ... 14 128 64-Mbit ... 15 370000 - 37FFFF Blk ... Programming Region 55 ... Table 8. 6F0000 - 6FFFFF Size (KB) ... 0 111 Programming Region # ... 1 128 ... 2 128-Mbit ... 3 Blk ... 4 256-Mbit ... 5 Blk ... 6 Size (KB) ... Programming Region # Discrete Top Parameter Memory Maps (all packages) ... Table 7. 128 40 280000 - 28FFFF April 2005 25 1-Gbit P30 Family 99 600000 - 60FFFF 128 32 200000 - 20FFFF 128 194 BF0000 - BFFFFF 98 5F0000 - 5FFFFF 128 31 1F0000 - 1FFFFF ... 24 180000 - 18FFFF 128 23 170000 - 17FFFF 162 9F0000 - 9FFFFF 82 4F0000 - 4FFFFF 1 16 100000 - 10FFFF 128 15 0F0000 - 0FFFFF 480000 - 48FFFF 128 8 080000 - 08FFFF 128 146 8F0000 - 8FFFFF 74 470000 - 47FFFF 128 10 070000 - 07FFFF 128 131 800000 - 80FFFF 67 400000 - 40FFFF ... 75 ... 900000 - 90FFFF ... 147 ... 128 ... ... 128 128 ... 500000 - 50FFFF ... 83 ... A0000 - A0FFFF ... 163 ... 128 2 ... ... 128 570000 - 57FFFF ... 580000 - 58FFFF 90 ... 91 AF0000 - AFFFFF ... B00000 - B0FFFF 178 ... 179 128 ... ... 3 128 ... ... C00000 - C0FFFF ... 195 ... 128 ... ... 270000 - 27FFFF ... 39 ... 4 128 ... 670000 - 67FFFF 64-Mbit ... 106 Blk ... CF0000 - CFFFFF Size (KB) ... 210 Programming Region ... 128 ... 8 128-Mbit ... 9 Blk ... 10 256-Mbit ... 11 Blk ... 12 Size (KB) ... Programming Region Discrete Bottom Parameter Memory Maps (all packages) ... Table 8. 128 4 010000 - 01FFFF 32 3 00C000 - 00FFFF 0 April 2005 26 ... ... ... ... 128 114 6F0000 - 6FFFFF 58 370000 - 37FFFF 300000 - 30FFFF 128 98 5F0000 - 5FFFFF 50 2F0000 - 2FFFFF 43 280000 - 28FFFF 128 82 4F0000 - 4FFFFF 42 270000 - 27FFFF 35 200000 - 20FFFF 128 66 3F0000 - 3FFFFF 34 1F0000 - 1FFFFF 300000 - 30FFFF 27 180000 - 18FFFF 50 2F0000 - 2FFFFF 26 170000 - 17FFFF 35 200000 - 20FFFF 19 100000 - 10FFFF 128 34 1F0000 - 1FFFFF 18 0F0000 - 0FFFFF ... 128 ... ... 51 128 ... 128 ... ... 400000 - 40FFFF ... 67 ... 128 ... ... 500000 - 50FFFF ... 83 ... 128 ... ... 51 ... 600000 - 60FFFF ... 99 ... 128 ... ... ... 000000 - 003FFF ... ... 0 ... ... 32 ... 380000 - 38FFFF ... 59 ... 1 700000 - 70FFFF ... 2 115 ... 3 128 ... 4 3F0000 - 3FFFFF ... 5 66 ... 6 7F0000 - 7FFFFF ... 7 130 ... 128 128 19 100000 - 10FFFF 11 080000 - 08FFFF Intel StrataFlash(R) Embedded Memory (P30) Order Number: 306666, Revision: 001 Datasheet 1-Gbit P30 Family 10 070000 - 07FFFF ... 0F0000 - 0FFFFF 128 4 010000 - 01FFFF 4 010000 - 01FFFF 32 3 00C000 - 00FFFF 3 00C000 - 00FFFF ... 18 ... 128 ... 128-Mbit ... Blk ... 256-Mbit ... Blk ... Size (KB) ... Programming Region Discrete Bottom Parameter Memory Maps (all packages) ... Table 8. 32 0 000000 - 03FFFF 0 000000 - 00FFFF Programming Region Size (KB) Blk 64-Mbit 0 Table 9. 512-Mbit Memory Map (Easy BGA and QUAD+ SCSP) 512-Mbit Flash (2x256-Mbit w/ 1CE) Flash Die # Die Stack Config. Size (KB) 32 ... ... 32 255 FF0000 - FF3FFF 128 254 FE0000 - FEFFFF ... 0 000000 - 00FFFF 128 258 FF0000 - FFFFFF ... ... ... 128 128 4 010000 - 01FFFF 32 3 00C000 - 00FFFF ... ... ... Datasheet FFC000 - FFFFFF ... Note: Flash Die #1 (Bottom Parameter) 258 ... 1 Flash Die #2 (Top Parameter) Address Range ... 2 Blk 32 0 000000 - 003FFF Refer to 256-Mbit Memory Map (Table 7 and Table 8) for Programming Region Information. Intel StrataFlash(R) Embedded Memory (P30) Order Number: 306666, Revision: 001 April 2005 27 1-Gbit P30 Family Table 10. 1-Gbit Memory Map (QUAD+ SCSP only) 1-Gbit Flash (4x256-Mbit w/ 2CE) Flash Die # Die Stack Config. Size (KB) 32 ... ... FF0000 - FF3FFF 128 254 FE0000 - FEFFFF ... ... 128 0 000000 - 00FFFF 128 258 FF0000 - FFFFFF ... ... 128 5 020000 - 02FFFF 32 3 00C000 - 00FFFF ... ... 32 0 000000 - 003FFF 32 258 FFC000 - FFFFFF ... ... 32 255 FF0000 - FF3FFF 128 254 FE0000 - FEFFFF ... ... 128 0 000000 - 00FFFF 128 258 FF0000 - FFFFFF ... ... ... ... 128 4 010000 - 01FFFF 32 3 00C000 - 00FFFF ... ... ... April 2005 28 255 ... Note: Flash Die #1 (Bottom Parameter) 32 ... 1 Flash Die #2 (Top Parameter) FFC000 - FFFFFF ... 2 Flash Die #3 (Bottom Parameter) 258 ... 3 Flash Die #4 (Top Parameter) Address Range ... 4 Blk 32 0 000000 - 003FFF Refer to 256-Mbit Memory Map (Table 7 and Table 8) for Programming Region Information. Intel StrataFlash(R) Embedded Memory (P30) Order Number: 306666, Revision: 001 Datasheet 1-Gbit P30 Family 5.0 Maximum Ratings and Operating Conditions 5.1 Absolute Maximum Ratings Warning: Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. Parameter Maximum Rating Notes Temperature under bias -40 C to +85 C Storage temperature -65 C to +125 C 1 Voltage on any signal (except VCC, VPP) -0.5 V to +4.1 V 2 VPP voltage -0.2 V to +10 V 2,3,4 VCC voltage -0.2 V to +2.5 V 2 VCCQ voltage -0.2 V to +4.1 V 2 Output short circuit current 100 mA 5 Notes: 1. Temperature for 1-Gbit SCSP is -30 C to +85 C. 2. Voltages shown are specified with respect to VSS. Minimum DC voltage is -0.5 V on input/output signals and -0.2 V on VCC, VCCQ, and VPP. During transitions, this level may undershoot to -2.0 V for periods < 20 ns. Maximum DC voltage on VCC is VCC + 0.5 V, which, during transitions, may overshoot to VCC + 2.0 V for periods < 20 ns. Maximum DC voltage on input/output signals and VCCQ is VCCQ + 0.5 V, which, during transitions, may overshoot to VCCQ + 2.0 V for periods < 20 ns. 3. Maximum DC voltage on VPP may overshoot to +11.5 V for periods < 20 ns. 4. Program/erase voltage is typically 1.7 V - 2.0 V. 9.0 V can be applied for 80 hours maximum total, to any blocks for 1000 cycles maximum. 9.0 V program/erase voltage may reduce block cycling capability. 5. Output shorted for no more than one second. No more than one output shorted at a time. Datasheet Intel StrataFlash(R) Embedded Memory (P30) Order Number: 306666, Revision: 001 April 2005 29 1-Gbit P30 Family 5.2 Operating Conditions Note: Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions" may affect device reliability. Table 11. Operating Conditions Symbol TC VCC Parameter Min Max Units Notes Operating Temperature -40 +85 C 1,2 VCC Supply Voltage 1.7 2.0 CMOS inputs 1.7 3.6 TTL inputs VCCQ I/O Supply Voltage 2.4 3.6 VPPL VPP Voltage Supply (Logic Level) 0.9 3.6 VPPH Factory word programming VPP 8.5 9.5 tPPH Maximum VPP Hours VPP = VPPH - 80 Main and Parameter Blocks VPP = VCC 100,000 - Main Blocks VPP = VPPH - 1000 Parameter Blocks VPP = VPPH - 2500 Block Erase Cycles V Hours 3 Cycles NOTES: 1. TC = Case Temperature 2. Temperature for 1-Gbit SCSP is -30 C to +85 C. 3. In typical operation, the VPP program voltage is VPPL. VPP can be connected to 8.5 V - 9.5 V for 80 hours. April 2005 30 Intel StrataFlash(R) Embedded Memory (P30) Order Number: 306666, Revision: 001 Datasheet 1-Gbit P30 Family 6.0 Electrical Specifications 6.1 DC Current Characteristics Table 12. DC Current Characteristics (Sheet 1 of 2) Sym Parameter ILI Input Load Current ILO Output Leakage Current DQ[15:0], WAIT ICCS, VCC Standby, ICCD Power Down ICCR CMOS Inputs (VCCQ = 1.7 V - 3.6 V) Average VCC Read Current TTL Inputs (VCCQ = 2.4 V - 3.6 V) Typ Max Typ Max - 1 - 2 - 1 - 10 64-Mbit 20 35 20 35 128-Mbit 30 75 30 75 256-Mbit 55 115 55 200 512-Mbit 110 230 110 400 1-Gbit VCC = VCCMax VCCQ = VCCQMax VIN = VCCQ or VSS A VCC = VCCMax VCCQ = VCCQMax VIN = VCCQ or VSS A VCC = VCCMax VCCQ = VCCQMax CE# = VCCQ RST# = VCCQ (for ICCS) RST# = VSS (for ICCD) WP# = VIH 460 220 800 14 16 14 16 mA 1-Word Read Page-Mode Read f = 13 MHz (5 CLK) 9 10 9 10 mA 4-Word Read 13 17 n/a n/a mA BL = 4W 15 19 n/a n/a mA BL = 8W 17 21 n/a n/a mA BL = 16W 21 26 n/a n/a mA 51 36 51 Synchronous Burst f = 40 MHz VCC Program Current, ICCE VCC Erase Current 26 33 26 33 64-Mbit 20 35 20 35 128-Mbit 30 75 30 75 256-Mbit 55 115 55 200 512-Mbit 110 230 110 400 1-Gbit 220 460 220 800 0.2 5 0.2 2 15 2 IPPS, A 220 ICCW, ICCES Test Conditions Asynchronous SingleWord f = 5 MHz (1 CLK) 36 ICCWS, Unit VCC Program Suspend Current, VCC Erase Suspend Current mA Notes 1 1,2 VCC = VCCMax CE# = VIL 1 OE# = VIH Inputs: VIL or VIH BL = Cont. VPP = VPPL, pgm/ers in progress 1,3,4,7 VPP = VPPH, pgm/ers in progress 1,3,5,7 A CE# = VCCQ; suspend in progress 5 A VPP = VPPL, suspend in progress 1,3 15 A VPP VCC 1,3 1,3,6 VPP Standby Current, IPPWS, VPP Program Suspend Current, IPPES VPP Erase Suspend Current IPPR VPP Read Datasheet Intel StrataFlash(R) Embedded Memory (P30) Order Number: 306666, Revision: 001 April 2005 31 1-Gbit P30 Family Table 12. DC Current Characteristics (Sheet 2 of 2) Sym Parameter IPPW VPP Program Current IPPE VPP Erase Current Notes: 1. 2. 3. 4. 5. 6. 7. CMOS Inputs (VCCQ = 1.7 V - 3.6 V) TTL Inputs (VCCQ = 2.4 V - 3.6 V) Typ Max Typ Max 0.05 0.10 0.05 0.10 Unit mA 8 22 8 22 0.05 0.10 0.05 0.10 8 22 8 22 Test Conditions Notes VPP = VPPL, program in progress VPP = VPPH, program in progress mA VPP = VPPL, erase in progress VPP = VPPH, erase in progress All currents are RMS unless noted. Typical values at typical VCC, TC = +25 C. ICCS is the average current measured over any 5 ms time interval 5 s after CE# is deasserted. Sampled, not 100% tested. VCC read + program current is the sum of VCC read and VCC program currents. VCC read + erase current is the sum of VCC read and VCC erase currents. ICCES is specified with the device deselected. If device is read while in erase suspend, current is ICCES plus ICCR. ICCW, ICCE measured over typical or max times specified in Section 7.5, "Program and Erase Characteristics" on page 45. 6.2 DC Voltage Characteristics Table 13. DC Voltage Characteristics Sym Parameter CMOS Inputs (VCCQ = 1.7 V - 3.6 V) TTL Inputs (1) (VCCQ = 2.4 V - 3.6 V) Min Max Min Max Unit Test Condition VIL Input Low Voltage 0 0.4 0 0.6 V VIH Input High Voltage VCCQ - 0.4 VCCQ 2.0 VCCQ V VOL Output Low Voltage - 0.1 - 0.1 V VCC = VCCMin VCCQ = VCCQMin IOL = 100 A VOH Output High Voltage VCCQ - 0.1 - VCCQ - 0.1 - V VCC = VCCMin VCCQ = VCCQMin IOH = -100 A - 0.4 - 0.4 V 2 VPPLK VPP Lock-Out Voltage VLKO VCC Lock Voltage 1.0 - 1.0 - V VCCQ Lock Voltage 0.9 - 0.9 - V VLKOQ Notes 3 NOTES: 1. Synchronous read mode is not supported with TTL inputs. 2. VIL can undershoot to -0.4 V and VIH can overshoot to VCCQ+ 0.4 V for durations of 20 ns or less. 3. VPP VPPLK inhibits erase and program operations. Do not use VPPL and VPPH outside their valid ranges. April 2005 32 Intel StrataFlash(R) Embedded Memory (P30) Order Number: 306666, Revision: 001 Datasheet 1-Gbit P30 Family 7.0 AC Characteristics 7.1 AC Test Conditions Figure 13. AC Input/Output Reference Waveform VCCQ Input VCCQ/2 Test Points VCCQ/2 Output 0V Note: Figure 14. AC test inputs are driven at VCCQ for Logic "1" and 0.0 V for Logic "0." Input/output timing begins/ends at VCCQ/2. Input rise and fall times (10% to 90%) < 5 ns. Worst case speed occurs at VCC = VCCMin. Transient Equivalent Testing Load Circuit Device Under Test Out CL NOTES: 1. See the following table for component values. 2. Test configuration component value for worst case speed conditions. 3. CL includes jig capacitance . Table 14. Test configuration component value for worst case speed conditions Test Configuration CL (pF) VCCQMin Standard Test Figure 15. 30 Clock Input AC Waveform R201 CLK [C] VIH VIL R202 Datasheet R203 Intel StrataFlash(R) Embedded Memory (P30) Order Number: 306666, Revision: 001 April 2005 33 1-Gbit P30 Family 7.2 Capacitance Table 15. Capacitance Symbol CIN Parameter Input Capacitance Signals Address, Data, CE#, WE#, OE#, RST#, CLK, ADV#, WP# Data, WAIT Min Typ Max Unit 2 6 7 pF Condition Note Typ temp = 25 C, Max temp = 85 C, VCC = VCCQ = (0 V - 1.95 V), Discrete silicon die 1,2,3 2 4 5 pF COUT Output Capacitance NOTES: 1. Capacitance values are for a single die; for 2-die and 4-die stacks multiple the above values by the number of die in the stack. 2. Sampled, not 100% tested. 3. Silicon die capacitance only, add 1 pF for discrete packages. April 2005 34 Intel StrataFlash(R) Embedded Memory (P30) Order Number: 306666, Revision: 001 Datasheet 1-Gbit P30 Family 7.3 AC Read Specifications Table 16. AC Read Specifications for 64/128-Mbit Densities (Sheet 1 of 2) Num Symbol Parameter Min Max Unit Notes Asynchronous Specifications R1 tAVAV Read cycle time 85 - ns R2 tAVQV Address to output valid - 85 ns R3 tELQV CE# low to output valid - 85 ns R4 tGLQV OE# low to output valid - 25 ns 1,2 R5 tPHQV RST# high to output valid - 150 ns 1 R6 tELQX CE# low to output in low-Z 0 - ns 1,3 R7 tGLQX OE# low to output in low-Z 0 - ns 1,2,3 R8 tEHQZ CE# high to output in high-Z - 24 ns R9 tGHQZ OE# high to output in high-Z - 24 ns 1,3 R10 tOH Output hold from first occurring address, CE#, or OE# change 0 - ns R11 tEHEL CE# pulse width high 20 - ns R12 tELTV CE# low to WAIT valid - 17 ns R13 tEHTZ CE# high to WAIT high-Z - 20 ns 1,3 R15 tGLTV OE# low to WAIT valid - 17 ns 1 R16 tGLTX OE# low to WAIT in low-Z 0 - ns R17 tGHTZ OE# high to WAIT in high-Z - 20 ns tAVVH Address setup to ADV# high 10 - ns R102 tELVH CE# low to ADV# high 10 - ns R103 tVLQV ADV# low to output valid - 85 ns R104 tVLVH ADV# pulse width low 10 - ns R105 tVHVL ADV# pulse width high 10 - ns R106 tVHAX Address hold from ADV# high 9 - ns R108 tAPA Page address access - 25 ns R111 tphvh RST# high to ADV# high 30 - ns 1 1,3 Latching Specifications R101 1 1,4 1 Clock Specifications R200 fCLK CLK frequency - 40 MHz R201 tCLK CLK period 25 - ns R202 tCH/CL CLK high/low time 5 - ns R203 tFCLK/RCLK CLK fall/rise time - 3 ns 1,3,6 Synchronous Specifications R301 tAVCH/L Address setup to CLK 9 - ns R302 tVLCH/L ADV# low setup to CLK 9 - ns R303 tELCH/L CE# low setup to CLK 9 - ns R304 tCHQV / tCLQV CLK to output valid - 20 ns Datasheet 1 Intel StrataFlash(R) Embedded Memory (P30) Order Number: 306666, Revision: 001 April 2005 35 1-Gbit P30 Family Table 16. AC Read Specifications for 64/128-Mbit Densities (Sheet 2 of 2) Num Symbol R305 tCHQX R306 R307 Parameter Min Max Unit Notes Output hold from CLK 3 - ns 1,5 tCHAX Address hold from CLK 10 - ns 1,4,5 tCHTV CLK to WAIT valid - 20 ns 1,5 R311 tCHVL CLK Valid to ADV# Setup 3 - ns 1 R312 tCHTX WAIT Hold from CLK 3 - ns 1,5 NOTES: 1. See Figure 13, "AC Input/Output Reference Waveform" on page 33 for timing measurements and max allowable input slew rate. 2. OE# may be delayed by up to tELQV - tGLQV after CE#'s falling edge without impact to tELQV. 3. Sampled, not 100% tested. 4. Address hold in synchronous burst mode is tCHAX or tVHAX, whichever timing specification is satisfied first. 5. Applies only to subsequent synchronous reads. 6. See your local Intel representative for designs requiring higher than 40 MHz synchronous operation. Table 17. Num AC Read Specifications for 256/512-Mbit and 1-Gbit Densities (Sheet 1 of 2) Symbol Parameter Speed Min Max Vcc = 1.8 V - 2.0 V 85 - Vcc = 1.7 V - 2.0 V 88 - Vcc = 1.8 V - 2.0 V - 85 Vcc = 1.7 V - 2.0 V - 88 Vcc = 1.8 V - 2.0 V - 85 Vcc = 1.7 V - 2.0 V - 88 Unit Notes Asynchronous Specifications R1 tAVAV Read cycle time tAVQV Address to output valid tELQV CE# low to output valid R4 tGLQV OE# low to output valid - 25 ns 1,2 R5 tPHQV RST# high to output valid - 150 ns 1 R6 tELQX CE# low to output in low-Z 0 - ns 1,3 R7 tGLQX OE# low to output in low-Z 0 - ns 1,2,3 R8 tEHQZ CE# high to output in high-Z - 24 ns R9 tGHQZ OE# high to output in high-Z - 24 ns R2 R3 ns ns ns 1,3 R10 tOH Output hold from first occurring address, CE#, or OE# change 0 - ns R11 tEHEL CE# pulse width high 20 - ns R12 tELTV CE# low to WAIT valid - 17 ns R13 tEHTZ CE# high to WAIT high-Z - 20 ns 1,3 R15 tGLTV OE# low to WAIT valid - 17 ns 1 R16 tGLTX OE# low to WAIT in low-Z 0 - ns R17 tGHTZ OE# high to WAIT in high-Z - 20 ns 1 1,3 Latching Specifications April 2005 36 Intel StrataFlash(R) Embedded Memory (P30) Order Number: 306666, Revision: 001 Datasheet 1-Gbit P30 Family Table 17. AC Read Specifications for 256/512-Mbit and 1-Gbit Densities (Sheet 2 of 2) Num Symbol Parameter R101 tAVVH Address setup to ADV# high R102 tELVH CE# low to ADV# high Speed Min Max Unit 10 - ns ns 10 - Vcc = 1.8 V - 2.0 V - 85 Vcc = 1.7 V - 2.0 V - 88 - tVLQV ADV# low to output valid tVLVH ADV# pulse width low 10 R105 tVHVL ADV# pulse width high 10 - ns R106 tVHAX Address hold from ADV# high 9 - ns R108 tAPA Page address access R111 tphvh RST# high to ADV# high R103 R104 ns Notes 1 ns - 25 ns 30 - ns 1,4 1 Clock Specifications R200 fCLK CLK frequency - 40 MHz R201 tCLK CLK period 25 - ns R202 tCH/CL CLK high/low time 5 - ns R203 tFCLK/RCLK CLK fall/rise time - 3 ns 1,3,6 Synchronous Specifications R301 tAVCH/L Address setup to CLK 9 - ns R302 tVLCH/L ADV# low setup to CLK 9 - ns R303 tELCH/L CE# low setup to CLK 9 - ns R304 tCHQV / tCLQV CLK to output valid - 20 ns R305 tCHQX Output hold from CLK 3 - ns 1,5 R306 tCHAX Address hold from CLK 10 - ns 1,4,5 R307 tCHTV CLK to WAIT valid - 20 ns 1,5 R311 tCHVL CLK Valid to ADV# Setup 3 - ns 1 R312 tCHTX WAIT Hold from CLK 3 - ns 1,5 1 NOTES: 1. See Figure 13, "AC Input/Output Reference Waveform" on page 33 for timing measurements and max allowable input slew rate. 2. OE# may be delayed by up to tELQV - tGLQV after CE#'s falling edge without impact to tELQV. 3. Sampled, not 100% tested. 4. Address hold in synchronous burst mode is tCHAX or tVHAX, whichever timing specification is satisfied first. 5. Applies only to subsequent synchronous reads. 6. See your local Intel representative for designs requiring higher than 40 MHz synchronous operation. Datasheet Intel StrataFlash(R) Embedded Memory (P30) Order Number: 306666, Revision: 001 April 2005 37 1-Gbit P30 Family Figure 16. Asynchronous Single-Word Read (ADV# Low) R1 R2 Address [A] ADV# R3 R8 CE# [E} R4 R9 OE# [G] R15 R17 WAIT [T] R7 R6 Data [D/Q] R5 RST# [P] Note: Figure 17. WAIT shown deasserted during asynchronous read mode (RCR[10]=0, Wait asserted low). Asynchronous Single-Word Read (ADV# Latch) R1 R2 Address [A] A[1:0][A] R101 R105 R106 ADV# R3 R8 CE# [E} R4 R9 OE# [G] R15 R17 WAIT [T] R7 R6 R10 Data [D/Q] Note: April 2005 38 WAIT shown deasserted during asynchronous read mode (RCR[10]=0, Wait asserted low). Intel StrataFlash(R) Embedded Memory (P30) Order Number: 306666, Revision: 001 Datasheet 1-Gbit P30 Family Figure 18. Asynchronous Page-Mode Read Timing R1 R2 A[Max:2] [A] A[1:0] R101 R105 R106 ADV# R3 R8 CE# [E] R4 R10 OE# [G] R15 R17 WAIT [T] R7 R9 R108 DATA [D/Q] Note: Figure 19. WAIT shown deasserted during asynchronous read mode (RCR[10]=0, Wait asserted low). Synchronous Single-Word Array or Non-array Read Timing R301 R306 CLK [C] R2 Address [A] R101 R106 R105 R104 ADV# [V] R303 R102 R3 R8 CE# [E] R7 R9 OE# [G] R15 R307 R312 R17 WAIT [T] R4 R304 R305 Data [D/Q] 1. 2. Datasheet WAIT is driven per OE# assertion during synchronous array or non-array read, and can be configured to assert either during or one data cycle before valid data. This diagram illustrates the case in which an n-word burst is initiated to the flash memory array and it is terminated by CE# deassertion after the first word in the burst. Intel StrataFlash(R) Embedded Memory (P30) Order Number: 306666, Revision: 001 April 2005 39 1-Gbit P30 Family Figure 20. Continuous Burst Read, showing an Output Delay Timing R301 R302 R306 R304 R304 R304 CLK [C] R2 R101 Address [A] R106 R105 ADV# [V] R303 R102 R3 CE# [E] OE# [G] R15 R307 R312 WAIT [T] R304 R4 R7 R305 R305 R305 R305 Data [D/Q] Notes: 1. WAIT is driven per OE# assertion during synchronous array or non-array read, and can be configured to assert either during or one data cycle before valid data. 2. At the end of Word Line; the delay incurred when a burst access crosses a 16-word boundary and the starting address is not 4-word boundary aligned. April 2005 40 Intel StrataFlash(R) Embedded Memory (P30) Order Number: 306666, Revision: 001 Datasheet 1-Gbit P30 Family Figure 21. Synchronous Burst-Mode Four-Word Read Timing y R302 R301 R306 CLK [C] R2 Address [A] R101 A R105 R102 R106 ADV# [V] R303 R3 R8 CE# [E] R9 OE# [G] R15 R17 R307 WAIT [T] R4 R7 R304 Data [D/Q] Note: R304 R305 Q0 AC Write Specifications Table 18. AC Write Specifications (Sheet 1 of 2) Datasheet Q2 Q3 WAIT is driven per OE# assertion during synchronous array or non-array read. WAIT asserted during initial latency and deasserted during valid data (RCR[10] = 0, Wait asserted low). 7.4 Num R10 Q1 Symbol Parameter Min Max Units Notes 150 - ns 1,2,3 W1 tPHWL RST# high recovery to WE# low W2 tELWL CE# setup to WE# low 0 - ns 1,2,3 W3 tWLWH WE# write pulse width low 50 - ns 1,2,4 W4 tDVWH Data setup to WE# high 50 - ns W5 tAVWH Address setup to WE# high 50 - ns W6 tWHEH CE# hold from WE# high 0 - ns W7 tWHDX Data hold from WE# high 0 - ns W8 tWHAX Address hold from WE# high 0 - ns W9 tWHWL WE# pulse width high 20 - ns W10 tVPWH VPP setup to WE# high 200 - ns W11 tQVVL VPP hold from Status read 0 - ns W12 tQVBL WP# hold from Status read 0 - ns W13 tBHWH WP# setup to WE# high 200 - ns 1,2 1,2,5 1,2,3,7 1,2,3,7 Intel StrataFlash(R) Embedded Memory (P30) Order Number: 306666, Revision: 001 April 2005 41 1-Gbit P30 Family Table 18. AC Write Specifications (Sheet 2 of 2) Num Symbol Parameter Min Max Units Notes W14 tWHGL WE# high to OE# low 0 - ns 1,2,9 W16 tWHQV WE# high to read valid tAVQV + 35 - ns 1,2,3,6,1 0 0 - ns 1,2,3,6,8 1,2,3,6,1 0 Write to Asynchronous Read Specifications W18 tWHAV WE# high to Address valid Write to Synchronous Read Specifications W19 tWHCH/L WE# high to Clock valid 19 - ns W20 tWHVH WE# high to ADV# high 19 - ns Write Specifications with Clock Active W21 tVHWL ADV# high to WE# low - 20 ns W22 tCHWL Clock high to WE# low - 20 ns Notes: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. Figure 22. 1,2,3,11 Write timing characteristics during erase suspend are the same as write-only operations. A write operation can be terminated with either CE# or WE#. Sampled, not 100% tested. Write pulse width low (tWLWH or tELEH) is defined from CE# or WE# low (whichever occurs last) to CE# or WE# high (whichever occurs first). Hence, tWLWH = tELEH = tWLEH = tELWH. Write pulse width high (tWHWL or tEHEL) is defined from CE# or WE# high (whichever occurs first) to CE# or WE# low (whichever occurs last). Hence, tWHWL = tEHEL = tWHEL = tEHWL). tWHVH or tWHCH/L must be met when transitioning from a write cycle to a synchronous burst read. VPP and WP# should be at a valid level until erase or program success is determined. This specification is only applicable when transitioning from a write cycle to an asynchronous read. See spec W19 and W20 for synchronous read. When doing a Read Status operation following any command that alters the Status Register, W14 is 20 ns. Add 10 ns if the write operations results in a RCR or block lock status change, for the subsequent read operation to reflect this change. These specs are required only when the device is in a synchronous mode and clock is active during address setup phase. Write-to-Write Timing W5 W8 W5 W8 Address [A] W2 W6 W2 W6 CE# [E} W3 W9 W3 WE# [W] OE# [G] W4 W7 W4 W7 Data [D/Q] W1 RST# [P] April 2005 42 Intel StrataFlash(R) Embedded Memory (P30) Order Number: 306666, Revision: 001 Datasheet 1-Gbit P30 Family Figure 23. Asynchronous Read-to-Write Timing R1 R2 W5 W8 Address [A] R3 R8 CE# [E} R4 R9 OE# [G] W2 W3 W6 WE# [W] R15 R17 WAIT [T] R7 W7 R6 R10 Data [D/Q] W4 Q D R5 RST# [P] Note: Figure 24. WAIT deasserted during asynchronous read and during write. WAIT High-Z during write per OE# deasserted. Write-to-Asynchronous Read Timing W5 W8 R1 Address [A] ADV# [V] W2 W6 R10 CE# [E} W3 W18 WE# [W] W14 OE# [G] R15 R17 WAIT [T] R4 W4 Data [D/Q] W7 R2 R3 D R8 R9 Q W1 RST# [P] Datasheet Intel StrataFlash(R) Embedded Memory (P30) Order Number: 306666, Revision: 001 April 2005 43 1-Gbit P30 Family Figure 25. Synchronous Read-to-Write Timing Lat ency Count R301 R302 R306 CLK [C] R2 W5 R101 W18 Address [A] R105 R102 R106 R104 ADV# [ V] R303 R11 R13 R3 W6 CE# [E] R4 R8 OE# [G] W21 W22 W15 W21 W22 W2 W8 W3 W9 WE# R16 R307 R312 WAIT [T] R304 R7 R305 W7 Q Data [D/Q] D D Note: WAIT shown deasserted and High-Z per OE# deassertion during write operation (RCR[10]=0, Wait asserted low). Clock is ignored during write operation. Figure 26. Write-to-Synchronous Read Timing R302 R301 R2 CLK W5 W8 R306 Address [ A] R106 R104 ADV# W6 W2 R303 R11 CE# [ E} W18 W19 W20 W3 WE# [W] R4 OE# [ G] R15 R307 WAIT [T] W7 W4 R304 D Data [D/Q] R305 R304 R3 Q Q W1 RST# [P] Note: WAIT shown deasserted and High-Z per OE# deassertion during write operation (RCR[10]=0, Wait asserted low). April 2005 44 Intel StrataFlash(R) Embedded Memory (P30) Order Number: 306666, Revision: 001 Datasheet 1-Gbit P30 Family 7.5 Program and Erase Characteristics Num Symbol VPPL Parameter Conventional Word Programming Single word Program W200 tPROG/W Time Single cell Buffered Programming Single word W200 tPROG/W Program Time 32-word buffer W251 tBUFF Buffered Enhanced Factory Programming Single word W451 tBEFP/W Program tBEFP/ BEFP Setup W452 VPPH Units Notes Min Typ Max Min Typ Max - 90 30 200 60 - 85 30 190 60 s 1 - 90 440 200 880 - 85 340 190 680 s 1 n/a n/a n/a - 10 - n/a n/a n/a 5 - - 1,2 s 1 Setup Erasing and Suspending 32-KByte Parameter 0.4 2.5 0.4 2.5 W500 tERS/PB Erase Time s 128-KByte Main 1.2 4.0 1.0 4.0 W501 tERS/MB 1 20 25 20 25 W600 tSUSP/P Suspend Program suspend s Latency Erase suspend 20 25 20 25 W601 tSUSP/E Notes: 1. Typical values measured at TC = +25 C and nominal voltages. Performance numbers are valid for all speed versions. Excludes system overhead. Sampled, but not 100% tested. 2. Averaged over entire device. Datasheet Intel StrataFlash(R) Embedded Memory (P30) Order Number: 306666, Revision: 001 April 2005 45 1-Gbit P30 Family 8.0 Power and Reset Specifications 8.1 Power Up and Down Power supply sequencing is not required if VCC, VCCQ, and VPP are connected together; If VCCQ and/or VPP are not connected to the VCC supply, then VCC should attain VCCMIN before applying VCCQ and VPP. Device inputs should not be driven before supply voltage equals VCCMIN. Power supply transitions should only occur when RST# is low. This protects the device from accidental programming or erasure during power transitions. 8.2 Reset Specifications Asserting RST# during a system reset is important with automated program/erase devices because systems typically expect to read from flash memory when coming out of reset. If a CPU reset occurs without a flash memory reset, proper CPU initialization may not occur. This is because the flash memory may be providing status information, instead of array data as expected. Connect RST# to the same active low reset signal used for CPU initialization. Also, because the device is disabled when RST# is asserted, it ignores its control inputs during power-up/down. Invalid bus conditions are masked, providing a level of memory protection. Num Symbol P1 tPLPH P2 tPLRH Parameter RST# pulse width low RST# low to device reset during erase RST# low to device reset during program VCC Power valid to RST# de-assertion (high) Min Max Unit Notes 100 60 25 25 - ns 1,2,3,4 1,3,4,7 1,3,4,7 1,4,5,6 s P3 tVCCPH Notes: 1. These specifications are valid for all device versions (packages and speeds). 2. The device may reset if tPLPH is < tPLPH MIN, but this is not guaranteed. 3. Not applicable if RST# is tied to Vcc. 4. Sampled, but not 100% tested. 5. If RST# is tied to the VCC supply, device will not be ready until tVCCPH after VCC VCCMIN. 6. If RST# is tied to any supply/signal with VCCQ voltage levels, the RST# input voltage must not exceed VCC until VCC VCCMIN. 7. Reset completes within tPLPH if RST# is asserted while no erase or program operation is executing. April 2005 46 Intel StrataFlash(R) Embedded Memory (P30) Order Number: 306666, Revision: 001 Datasheet 1-Gbit P30 Family Figure 27. Reset Operation Waveforms P1 (A) Reset during read mode RST# [P] R5 VIH VIL P2 (B) Reset during program or block erase P1 P2 RST# [P] R5 VIH VIL P2 (C) Reset during program or block erase P1 P2 Abort Complete RST# [P] Abort Complete R5 VIH VIL P3 (D) VCC Power-up to RST# high 8.3 VCC VCC 0V Power Supply Decoupling Flash memory devices require careful power supply de-coupling. Three basic power supply current considerations are: 1) standby current levels; 2) active current levels; and 3) transient peaks produced when CE# and OE# are asserted and deasserted. When the device is accessed, many internal conditions change. Circuits within the device enable charge-pumps, and internal logic states change at high speed. All of these internal activities produce transient signals. Transient current magnitudes depend on the device outputs' capacitive and inductive loading. Two-line control and correct de-coupling capacitor selection suppress transient voltage peaks. Because Intel(R) Multi-Level Cell (MLC) flash memory devices draw their power from VCC, VPP, and VCCQ, each power connection should have a 0.1 F ceramic capacitor to ground. Highfrequency, inherently low-inductance capacitors should be placed as close as possible to package leads. Additionally, for every eight devices used in the system, a 4.7 F electrolytic capacitor should be placed between power and ground close to the devices. The bulk capacitor is meant to overcome voltage droop caused by PCB trace inductance. Datasheet Intel StrataFlash(R) Embedded Memory (P30) Order Number: 306666, Revision: 001 April 2005 47 1-Gbit P30 Family 9.0 Device Operations This section provides an overview of device operations. The system CPU provides control of all insystem read, write, and erase operations of the device via the system bus. The on-chip Write State Machine (WSM) manages all block-erase and word-program algorithms. Device commands are written to the Command User Interface (CUI) to control all flash memory device operations. The CUI does not occupy an addressable memory location; it is the mechanism through which the flash device is controlled. 9.1 Bus Operations CE# low and RST# high enable device read operations. The device internally decodes upper address inputs to determine the accessed block. ADV# low opens the internal address latches. OE# low activates the outputs and gates selected data onto the I/O bus. In asynchronous mode, the address is latched when ADV# goes high or continuously flows through if ADV# is held low. In synchronous mode, the address is latched by the first of either the rising ADV# edge or the next valid CLK edge with ADV# low (WE# and RST# must be VIH; CE# must be VIL). Bus cycles to/from the P30 device conform to standard microprocessor bus operations. Table 19 summarizes the bus operations and the logic levels that must be applied to the device control signal inputs. Table 19. Bus Operations Summary Bus Operation RST# CLK ADV# CE# OE# WE# WAIT DQ[15:0] Asynchronous VIH X L L L H Deasserted Output Synchronous VIH Running L L L H Driven Output Write VIH X L L H L High-Z Input 1 Output Disable VIH X X L H H High-Z High-Z 2 Standby VIH X X H X X High-Z High-Z 2 Reset VIL X X X X X High-Z High-Z 2,3 Read Notes Notes: 1. Refer to the Table 20, "Command Bus Cycles" on page 50 for valid DQ[15:0] during a write operation. 2. X = Don't Care (H or L). 3. RST# must be at VSS 0.2 V to meet the maximum specified power-down current. 9.1.1 Reads To perform a read operation, RST# and WE# must be deasserted while CE# and OE# are asserted. CE# is the device-select control. When asserted, it enables the flash memory device. OE# is the data-output control. When asserted, the addressed flash memory data is driven onto the I/O bus. See Section 10.0, "Read Operations" on page 53 for details on the available read modes, and see Section 14.0, "Special Read States" on page 75 for details regarding the available read states. April 2005 48 Intel StrataFlash(R) Embedded Memory (P30) Order Number: 306666, Revision: 001 Datasheet 1-Gbit P30 Family 9.1.2 Writes To perform a write operation, both CE# and WE# are asserted while RST# and OE# are deasserted. During a write operation, address and data are latched on the rising edge of WE# or CE#, whichever occurs first. Table 20, "Command Bus Cycles" on page 50 shows the bus cycle sequence for each of the supported device commands, while Table 21, "Command Codes and Definitions" on page 51 describes each command. See Section 7.0, "AC Characteristics" on page 33 for signal-timing details. Note: Write operations with invalid VCC and/or VPP voltages can produce spurious results and should not be attempted. 9.1.3 Output Disable When OE# is deasserted, device outputs DQ[15:0] are disabled and placed in a high-impedance (High-Z) state, WAIT is also placed in High-Z. 9.1.4 Standby When CE# is deasserted the device is deselected and placed in standby, substantially reducing power consumption. In standby, the data outputs are placed in High-Z, independent of the level placed on OE#. Standby current, ICCS, is the average current measured over any 5 ms time interval, 5 s after CE# is deasserted. During standby, average current is measured over the same time interval 5 s after CE# is deasserted. When the device is deselected (while CE# is deasserted) during a program or erase operation, it continues to consume active power until the program or erase operation is completed. 9.1.5 Reset As with any automated device, it is important to assert RST# when the system is reset. When the system comes out of reset, the system processor attempts to read from the flash memory if it is the system boot device. If a CPU reset occurs with no flash memory reset, improper CPU initialization may occur because the flash memory may be providing status information rather than array data. Flash memory devices from Intel allow proper CPU initialization following a system reset through the use of the RST# input. RST# should be controlled by the same low-true reset signal that resets the system CPU. After initial power-up or reset, the device defaults to asynchronous Read Array, and the Status Register is set to 0x80. Asserting RST# de-energizes all internal circuits, and places the output drivers in High-Z. When RST# is asserted, the device shuts down the operation in progress, a process which takes a minimum amount of time to complete. When RST# has been deasserted, the device is reset to asynchronous Read Array state. Note: If RST# is asserted during a program or erase operation, the operation is terminated and the memory contents at the aborted location (for a program) or block (for an erase) are no longer valid, because the data may have been only partially written or erased. When returning from a reset (RST# deasserted), a minimum wait is required before the initial read access outputs valid data. Also, a minimum delay is required after a reset before a write cycle can be initiated. After this wake-up interval passes, normal operation is restored. See Section 7.0, "AC Characteristics" on page 33 for details about signal-timing. Datasheet Intel StrataFlash(R) Embedded Memory (P30) Order Number: 306666, Revision: 001 April 2005 49 1-Gbit P30 Family 9.2 Device Commands Device operations are initiated by writing specific device commands to the Command User Interface (CUI). See Table 20, "Command Bus Cycles" on page 50. Several commands are used to modify array data including Word Program and Block Erase commands. Writing either command to the CUI initiates a sequence of internally-timed functions that culminate in the completion of the requested task. However, the operation can be aborted by either asserting RST# or by issuing an appropriate suspend command. Table 20. Mode Command Bus Cycles (Sheet 1 of 2) Command Program Erase First Bus Cycle Second Bus Cycle Oper Addr(1) Data(2) Oper Addr(1) Data(2) 1 Write DBA 0xFF - - - Read Device Identifier 2 Write DBA 0x90 Read DBA + IA ID CFI Query Read Array Read Bus Cycles 2 Write DBA 0x98 Read DBA + QA QD Read Status Register 2 Write DBA 0x70 Read DBA SRD Clear Status Register 1 Write DBA 0x50 - - - Word Program 2 Write WA 0x40/ 0x10 Write WA WD Buffered Program(3) >2 Write WA 0xE8 Write WA N-1 Buffered Enhanced Factory Program (BEFP)(4) >2 Write WA 0x80 Write WA 0xD0 Block Erase 2 Write BA 0x20 Write BA 0xD0 Program/Erase Suspend 1 Write DBA 0xB0 - - - Program/Erase Resume 1 Write DBA 0xD0 - - - Lock Block 2 Write BA 0x60 Write BA 0x01 Unlock Block 2 Write BA 0x60 Write BA 0xD0 Lock-down Block 2 Write BA 0x60 Write BA 0x2F Suspend Block Locking/ Unlocking April 2005 50 Intel StrataFlash(R) Embedded Memory (P30) Order Number: 306666, Revision: 001 Datasheet 1-Gbit P30 Family Table 20. Command Bus Cycles (Sheet 2 of 2) Mode Command Bus Cycles First Bus Cycle Second Bus Cycle Oper Addr(1) Data(2) Oper Addr(1) Data(2) Program Protection Register 2 Write PRA 0xC0 Write PRA PD Program Lock Register 2 Write LRA 0xC0 Write LRA LRD Program Read Configuration Register 2 Write RCD 0x60 Write RCD 0x03 Protection Configuration Notes: 1. First command cycle address should be the same as the operation's target address. DBA = Device Base Address (NOTE: needed for 2 or more die stacks) IA = Identification code address offset. QA = CFI Query address offset. WA = Word address of memory location to be written. BA = Address within the block. PRA = Protection Register address. LRA = Lock Register address. RCD = Read Configuration Register data on A[15:0]. 2. ID = Identifier data. QD = Query data on DQ[15:0]. SRD = Status Register data. WD = Word data. N = Word count of data to be loaded into the write buffer. PD = Protection Register data. LRD = Lock Register data. 3. The second cycle of the Buffered Program Command is the word count of the data to be loaded into the write buffer. This is followed by up to 32 words of data.Then the confirm command (0xD0) is issued, triggering the array programming operation. 4. The confirm command (0xD0) is followed by the buffer data. 9.3 Command Definitions Valid device command codes and descriptions are shown in Table 21. Table 21. Mode Command Codes and Definitions (Sheet 1 of 2) Code 0xFF 0x70 Read 0x90 0x98 0x50 Write Datasheet 0x40 Device Mode Description Read Array Places the device in Read Array mode. Array data is output on DQ[15:0]. Places the device in Read Status Register mode. The device enters this mode Read Status Register after a program or erase command is issued. Status Register data is output on DQ[7:0]. Read Device ID Places device in Read Device Identifier mode. Subsequent reads output or Configuration manufacturer/device codes, Configuration Register data, Block Lock status, or Register Protection Register data on DQ[15:0]. Places the device in Read Query mode. Subsequent reads output Common Read Query Flash Interface information on DQ[7:0]. The WSM can only set Status Register error bits. The Clear Status Register Clear Status Register command is used to clear the SR error bits. First cycle of a 2-cycle programming command; prepares the CUI for a write operation. On the next write cycle, the address and data are latched and the WSM executes the programming algorithm at the addressed location. During program operations, the device responds only to Read Status Register and Word Program Setup Program Suspend commands. CE# or OE# must be toggled to update the Status Register in asynchronous read. CE# or ADV# must be toggled to update the Status Register Data for synchronous Non-array reads. The Read Array command must be issued to read array data after programming has finished. Intel StrataFlash(R) Embedded Memory (P30) Order Number: 306666, Revision: 001 April 2005 51 1-Gbit P30 Family Table 21. Mode Command Codes and Definitions (Sheet 2 of 2) Code 0x10 0xE8 0xD0 Write 0x80 0xD0 0x20 Erase 0xD0 0xB0 Suspend 0xD0 0x60 Block Locking/ Unlocking 0x01 0xD0 0x2F Protection 0xC0 0x60 Configuration 0x03 April 2005 52 Device Mode Alternate Word Program Setup Description Equivalent to the Word Program Setup command, 0x40. This command loads a variable number of words up to the buffer size of 32 words onto the program buffer. The confirm command is Issued after the data streaming for writing into the Buffered Program buffer is done. This instructs the WSM to perform the Buffered Program Confirm algorithm, writing the data from the buffer to the flash memory array. First cycle of a 2-cycle command; initiates Buffered Enhanced Factory Program mode (BEFP). The CUI then waits for the BEFP Confirm command, BEFP Setup 0xD0, that initiates the BEFP algorithm. All other commands are ignored when BEFP mode begins. If the previous command was BEFP Setup (0x80), the CUI latches the address BEFP Confirm and data, and prepares the device for BEFP mode. First cycle of a 2-cycle command; prepares the CUI for a block-erase operation. The WSM performs the erase algorithm on the block addressed by Block Erase Setup the Erase Confirm command. If the next command is not the Erase Confirm (0xD0) command, the CUI sets Status Register bits SR[4] and SR[5], and places the device in read status register mode. If the first command was Block Erase Setup (0x20), the CUI latches the address and data, and the WSM erases the addressed block. During blockerase operations, the device responds only to Read Status Register and Erase Block Erase Confirm Suspend commands. CE# or OE# must be toggled to update the Status Register in asynchronous read. CE# or ADV# must be toggled to update the Status Register Data for synchronous Non-array reads This command issued to any device address initiates a suspend of the currently-executing program or block erase operation. The Status Register Program or Erase indicates successful suspend operation by setting either SR[2] (program Suspend suspended) or SR[6] (erase suspended), along with SR[7] (ready). The Write State Machine remains in the suspend mode regardless of control signal states (except for RST# asserted). This command issued to any device address resumes the suspended program Suspend Resume or block-erase operation. First cycle of a 2-cycle command; prepares the CUI for block lock configuration changes. If the next command is not Block Lock (0x01), Block Unlock (0xD0), Lock Block Setup or Block Lock-Down (0x2F), the CUI sets Status Register bits SR[4] and SR[5], indicating a command sequence error. If the previous command was Block Lock Setup (0x60), the addressed block is Lock Block locked. If the previous command was Block Lock Setup (0x60), the addressed block is Unlock Block unlocked. If the addressed block is in a lock-down state, the operation has no effect. If the previous command was Block Lock Setup (0x60), the addressed block is Lock-Down Block locked down. First cycle of a 2-cycle command; prepares the device for a Protection Register Program Protection or Lock Register program operation. The second cycle latches the register Register Setup address and data, and starts the programming algorithm First cycle of a 2-cycle command; prepares the CUI for device read Read Configuration configuration. If the Set Read Configuration Register command (0x03) is not Register Setup the next command, the CUI sets Status Register bits SR[4] and SR[5], indicating a command sequence error. If the previous command was Read Configuration Register Setup (0x60), the Read Configuration CUI latches the address and writes A[15:0] to the Read Configuration Register. Register Following a Configure Read Configuration Register command, subsequent read operations access array data. Buffered Program Intel StrataFlash(R) Embedded Memory (P30) Order Number: 306666, Revision: 001 Datasheet 1-Gbit P30 Family 10.0 Read Operations The device supports two read modes: asynchronous page mode and synchronous burst mode. Asynchronous page mode is the default read mode after device power-up or a reset. The Read Configuration Register must be configured to enable synchronous burst reads of the flash memory array (see Section 10.3, "Read Configuration Register" on page 54). The device can be in any of four read states: Read Array, Read Identifier, Read Status or Read Query. Upon power-up, or after a reset, the device defaults to Read Array. To change the read state, the appropriate read command must be written to the device (see Section 9.2, "Device Commands" on page 50). See Section 14.0, "Special Read States" on page 75 for details regarding Read Status, Read ID, and CFI Query modes. The following sections describe read-mode operations in detail. 10.1 Asynchronous Page-Mode Read Following a device power-up or reset, asynchronous page mode is the default read mode and the device is set to Read Array. However, to perform array reads after any other device operation (e.g. write operation), the Read Array command must be issued in order to read from the flash memory array. Note: Asynchronous page-mode reads can only be performed when Read Configuration Register bit RCR[15] is set (see Section 10.3, "Read Configuration Register" on page 54). To perform an asynchronous page-mode read, an address is driven onto the Address bus, and CE# and ADV# are asserted. WE# and RST# must already have been deasserted. WAIT is deasserted during asynchronous page mode. ADV# can be driven high to latch the address, or it must be held low throughout the read cycle. CLK is not used for asynchronous page-mode reads, and is ignored. If only asynchronous reads are to be performed, CLK should be tied to a valid VIH level, WAIT signal can be floated and ADV# must be tied to ground. Array data is driven onto DQ[15:0] after an initial access time tAVQV delay. (see Section 7.0, "AC Characteristics" on page 33). In asynchronous page mode, four data words are "sensed" simultaneously from the flash memory array and loaded into an internal page buffer. The buffer word corresponding to the initial address on the Address bus is driven onto DQ[15:0] after the initial access delay. The lowest two address bits determine which word of the 4-word page is output from the data buffer at any given time. 10.2 Synchronous Burst-Mode Read To perform a synchronous burst- read, an initial address is driven onto the Address bus, and CE# and ADV# are asserted. WE# and RST# must already have been deasserted. ADV# is asserted, and then deasserted to latch the address. Alternately, ADV# can remain asserted throughout the burst access, in which case the address is latched on the next valid CLK edge while ADV# is asserted. During synchronous array and non-array read modes, the first word is output from the data buffer on the next valid CLK edge after the initial access latency delay (see Section 10.3.2, "Latency Count" on page 55). Subsequent data is output on valid CLK edges following a minimum delay. Datasheet Intel StrataFlash(R) Embedded Memory (P30) Order Number: 306666, Revision: 001 April 2005 53 1-Gbit P30 Family However, for a synchronous non-array read, the same word of data will be output on successive clock edges until the burst length requirements are satisfied. Refer to the following waveforms for more detailed information: * Figure 19, "Synchronous Single-Word Array or Non-array Read Timing" on page 39 * Figure 20, "Continuous Burst Read, showing an Output Delay Timing" on page 40 * Figure 21, "Synchronous Burst-Mode Four-Word Read Timing" on page 41 10.3 Read Configuration Register The Read Configuration Register (RCR) is used to select the read mode (synchronous or asynchronous), and it defines the synchronous burst characteristics of the device. To modify RCR settings, use the Configure Read Configuration Register command (see Section 9.2, "Device Commands" on page 50). RCR contents can be examined using the Read Device Identifier command, and then reading from offset 0x05 (see Section 14.2, "Read Device Identifier" on page 76). The RCR is shown in Table 22. The following sections describe each RCR bit. Table 22. Read Configuration Register Description (Sheet 1 of 2) Read Configuration Register (RCR) Read Mode RES Latency Count WAIT Polarity Data Hold WAIT Delay Burst Seq CLK Edge RES RES Burst Wrap Burst Length RM R LC[2:0] WP DH WD BS CE R R BW BL[2:0] 15 14 10 9 8 7 6 5 4 3 Bit 12 11 Name Read Mode (RM) 14 Reserved (R) Reserved bits should be cleared (0) Latency Count (LC[2:0]) 010 =Code 2 011 =Code 3 100 =Code 4 101 =Code 5 110 =Code 6 111 =Code 7 (default) (Other bit settings are reserved) 10 Wait Polarity (WP) 0 =WAIT signal is active low 1 =WAIT signal is active high (default) 9 Data Hold (DH) 0 =Data held for a 1-clock data cycle 1 =Data held for a 2-clock data cycle (default) 8 Wait Delay (WD) 0 =WAIT deasserted with valid data 1 =WAIT deasserted one data cycle before valid data (default) 7 Burst Sequence (BS) 0 =Reserved 1 =Linear (default) 6 Clock Edge (CE) 0 = Falling edge 1 = Rising edge (default) Reserved (R) Reserved bits should be cleared (0) 5:4 2 1 0 Description 15 13:11 April 2005 54 13 0 = Synchronous burst-mode read 1 = Asynchronous page-mode read (default) Intel StrataFlash(R) Embedded Memory (P30) Order Number: 306666, Revision: 001 Datasheet 1-Gbit P30 Family Table 22. Read Configuration Register Description (Sheet 2 of 2) 3 2:0 Note: 10.3.1 Burst Wrap (BW) 0 = Wrap; Burst accesses wrap within burst length set by BL[2:0] 1 = No Wrap; Burst accesses do not wrap within burst length (default) Burst Length (BL[2:0]) 001 =4-word burst 010 =8-word burst 011 =16-word burst 111 =Continuous-word burst (default) (Other bit settings are reserved) Latency Code 2, Data Hold for a 2-clock data cycle (DH = 1) WAIT must be deasserted with valid data (WD = 0). Latency Code 2, Data Hold for a 2-cock data cycle (DH=1) WAIT deasserted one data cycle before valid data (WD = 1) combination is not supported. Read Mode The Read Mode (RM) bit selects synchronous burst-mode or asynchronous page-mode operation for the device. When the RM bit is set, asynchronous page mode is selected (default). When RM is cleared, synchronous burst mode is selected. 10.3.2 Latency Count The Latency Count bits, LC[2:0], tell the device how many clock cycles must elapse from the rising edge of ADV# (or from the first valid clock edge after ADV# is asserted) until the first data word is to be driven onto DQ[15:0]. The input clock frequency is used to determine this value. Figure 28 shows the data output latency for the different settings of LC[2:0]. Synchronous burst with a Latency Count setting of Code 4 will result in zero WAIT state; however, a Latency Count setting of Code 5 will cause 1 WAIT state (Code 6 will cause 2 WAIT states, and Code 7 will cause 3 WAIT states) after every four words, regardless of whether a 16-word boundary is crossed. If RCR[9] (Data Hold) bit is set (data hold of two clocks) this WAIT condition will not occur because enough clocks elapse during each burst cycle to eliminate subsequent WAIT states. Refer to Table 23, "LC and Frequency Support" on page 56 for Latency Code Settings. Datasheet Intel StrataFlash(R) Embedded Memory (P30) Order Number: 306666, Revision: 001 April 2005 55 1-Gbit P30 Family Figure 28. First-Access Latency Count CLK [C] Address [A] Valid Address ADV# [V] Code 0 (Reserved) Valid Output DQ15-0 [D/Q] Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Code 1 (Reserved DQ15-0 [D/Q] Code 2 DQ15-0 [D/Q] Code 3 DQ15-0 [D/Q] Code 4 DQ15-0 [D/Q] Code 5 DQ15-0 [D/Q] Code 6 DQ15-0 [D/Q] Code 7 DQ15-0 [D/Q] Table 23. Valid Output LC and Frequency Support Latency Count Settings Frequency Support (MHz) 2 27 3 40 See Figure 29, "Example Latency Count Setting using Code 3. April 2005 56 Intel StrataFlash(R) Embedded Memory (P30) Order Number: 306666, Revision: 001 Datasheet 1-Gbit P30 Family Figure 29. Example Latency Count Setting using Code 3 0 1 2 3 tData 4 CLK CE# ADV# A[MAX:0] Address Code 3 High-Z D[15:0] Data R103 10.3.3 WAIT Polarity The WAIT Polarity bit (WP), RCR[10] determines the asserted level (VOH or VOL) of WAIT. When WP is set, WAIT is asserted high (default). When WP is cleared, WAIT is asserted low. WAIT changes state on valid clock edges during active bus cycles (CE# asserted, OE# asserted, RST# deasserted). 10.3.3.1 WAIT Signal Function The WAIT signal indicates data valid when the device is operating in synchronous mode (RCR[15]=0). The WAIT signal is only "deasserted" when data is valid on the bus. When the device is operating in synchronous non-array read mode, such as read status, read ID, or read query. The WAIT signal is also "deasserted" when data is valid on the bus. WAIT behavior during synchronous non-array reads at the end of word line works correctly only on the first data access. When the device is operating in asynchronous page mode, asynchronous single word read mode, and all write operations, WAIT is set to a deasserted state as determined by RCR[10]. See Figure 17, "Asynchronous Single-Word Read (ADV# Latch)" on page 38, and Figure 18, "Asynchronous Page-Mode Read Timing" on page 39. Datasheet Intel StrataFlash(R) Embedded Memory (P30) Order Number: 306666, Revision: 001 April 2005 57 1-Gbit P30 Family Table 24. WAIT Functionality Table Condition WAIT Notes CE# = `1', OE# = `X' or CE# = `0', OE# = `1' High-Z 1 CE# ='0', OE# = `0' Active 1 Synchronous Array Reads Active 1 Synchronous Non-Array Reads Active 1 All Asynchronous Reads Deasserted All Writes High-Z 1 1,2 Notes: 1. Active: WAIT is asserted until data becomes valid, then deasserts 2. When OE# = VIH during writes, WAIT = High-Z 10.3.4 Data Hold For burst read operations, the Data Hold (DH) bit determines whether the data output remains valid on DQ[15:0] for one or two clock cycles. This period of time is called the "data cycle". When DH is set, output data is held for two clocks (default). When DH is cleared, output data is held for one clock (see Figure 30). The processor's data setup time and the flash memory's clock-to-data output delay should be considered when determining whether to hold output data for one or two clocks. A method for determining the Data Hold configuration is shown below: To set the device at one clock data hold for subsequent reads, the following condition must be satisfied: tCHQV (ns) + tDATA (ns) One CLK Period (ns) tDATA = Data set up to Clock (defined by CPU) For example, with a clock frequency of 40 MHz, the clock period is 25 ns. Assuming tCHQV = 20 ns and tDATA = 4 ns. Applying these values to the formula above: 20 ns + 4 ns 25 ns The equation is satisfied and data will be available at every clock period with data hold setting at one clock. If tCHQV (ns) + tDATA (ns) > One CLK Period (ns), data hold setting of 2 clock periods must be used. Figure 30. Data Hold Timing CLK [C] April 2005 58 1 CLK Data Hold D[15:0] [Q] 2 CLK Data Hold D[15:0] [Q] Valid Output Valid Output Valid Output Intel StrataFlash(R) Embedded Memory (P30) Order Number: 306666, Revision: 001 Valid Output Valid Output Datasheet 1-Gbit P30 Family 10.3.5 WAIT Delay The WAIT Delay (WD) bit controls the WAIT assertion-delay behavior during synchronous burst reads. WAIT can be asserted either during or one data cycle before valid data is output on DQ[15:0]. When WD is set, WAIT is deasserted one data cycle before valid data (default). When WD is cleared, WAIT is deasserted during valid data. 10.3.6 Burst Sequence The Burst Sequence (BS) bit selects linear-burst sequence (default). Only linear-burst sequence is supported. Table 25 shows the synchronous burst sequence for all burst lengths, as well as the effect of the Burst Wrap (BW) setting. Table 25. Burst Sequence Word Ordering Start Burst Wrap Addr. (RCR[3]) (DEC) 0 0 0 0 0 0 0 0 14-15-16-17-18-19-20-... 15-16-17-18-19-20-21-... 0-1-2-3-4-5-6-... 1-2-3-4-5-6-7-... 2-3-4-5-6-7-8-... 3-4-5-6-7-8-9-... 4-5-6-7-8-9-10... 5-6-7-8-9-10-11... 6-7-8-9-10-11-12-... 7-8-9-10-11-12-13... ... ... 14-15-16-17-18...28-29 15-16-17-18-19...29-30 0-1-2-3-4-5-6-... 1-2-3-4-5-6-7-... 2-3-4-5-6-7-8-... 3-4-5-6-7-8-9-... 4-5-6-7-8-9-10... 5-6-7-8-9-10-11... 6-7-8-9-10-11-12-... 7-8-9-10-11-12-13... ... 0-1-2-3-4...14-15 1-2-3-4-5...15-16 2-3-4-5-6...16-17 3-4-5-6-7...17-18 4-5-6-7-8...18-19 5-6-7-8-9...19-20 6-7-8-9-10...20-21 7-8-9-10-11...21-22 Continuous Burst (BL[2:0] = 0b111) ... ... 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-8 2-3-4-5-6-7-8-9 3-4-5-6-7-8-9-10 4-5-6-7-8-9-10-11 5-6-7-8-9-10-11-12 6-7-8-9-10-11-12-13 7-8-9-10-11-12-13-14 ... ... 1 1 ... ... 14 15 0-1-2-3 1-2-3-4 2-3-4-5 3-4-5-6 ... ... 1 1 1 1 1 1 1 1 0-1-2-3-4...14-15 1-2-3-4-5...15-0 2-3-4-5-6...15-0-1 3-4-5-6-7...15-0-1-2 4-5-6-7-8...15-0-1-2-3 5-6-7-8-9...15-0-1-2-3-4 6-7-8-9-10...15-0-1-2-3-4-5 7-8-9-10...15-0-1-2-3-4-5-6 14-15-0-1-2...12-13 15-0-1-2-3...13-14 ... ... 0 1 2 3 4 5 6 7 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 16-Word Burst (BL[2:0] = 0b011) ... 0 0 8-Word Burst (BL[2:0] = 0b010) ... ... 14 15 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 ... ... 10.3.7 0 1 2 3 4 5 6 7 Burst Addressing Sequence (DEC) 4-Word Burst (BL[2:0] = 0b001) 14-15-16-17-18-19-20-... 15-16-17-18-19-20-21-... Clock Edge The Clock Edge (CE) bit selects either a rising (default) or falling clock edge for CLK. This clock edge is used at the start of a burst cycle, to output synchronous data, and to assert/deassert WAIT. 10.3.8 Burst Wrap The Burst Wrap (BW) bit determines whether 4-word, 8-word, or 16-word burst length accesses wrap within the selected word-length boundaries or cross word-length boundaries. When BW is set, burst wrapping does not occur (default). When BW is cleared, burst wrapping occurs. When performing synchronous burst reads with BW set (no wrap), an output delay may occur when the burst sequence crosses its first device-row (16-word) boundary. If the burst sequence's start address is 4-word aligned, then no delay occurs. If the start address is at the end of a 4-word Datasheet Intel StrataFlash(R) Embedded Memory (P30) Order Number: 306666, Revision: 001 April 2005 59 1-Gbit P30 Family boundary, the worst case output delay is one clock cycle less than the first access Latency Count. This delay can take place only once, and doesn't occur if the burst sequence does not cross a device-row boundary. WAIT informs the system of this delay when it occurs. 10.3.9 Burst Length The Burst Length bit (BL[2:0]) selects the linear burst length for all synchronous burst reads of the flash memory array. The burst lengths are 4-word, 8-word, 16-word, and continuous word. Continuous-burst accesses are linear only, and do not wrap within any word length boundaries (see Table 25, "Burst Sequence Word Ordering" on page 59). When a burst cycle begins, the device outputs synchronous burst data until it reaches the end of the "burstable" address space. April 2005 60 Intel StrataFlash(R) Embedded Memory (P30) Order Number: 306666, Revision: 001 Datasheet 1-Gbit P30 Family 11.0 Programming Operations The device supports three programming methods: Word Programming (40h/10h), Buffered Programming (E8h, D0h), and Buffered Enhanced Factory Programming (80h, D0h). See Section 9.0, "Device Operations" on page 48 for details on the various programming commands issued to the device. The following sections describe device programming in detail. Successful programming requires the addressed block to be unlocked. If the block is locked down, WP# must be deasserted and the block must be unlocked before attempting to program the block. Attempting to program a locked block causes a program error (SR[4] and SR[1] set) and termination of the operation. See Section 13.0, "Security Modes" on page 69 for details on locking and unlocking blocks. The Intel StrataFlash(R) Embedded Memory (P30) is segmented into multiple Programming Regions. Programming Regions are made up of 8 or 16 blocks depending on the density. The 64and 128-Mbit devices have 8 blocks per Programming Region, while the 256-Mbit has 16 blocks in each Programming Region (see Table 26). See Section 4.4, "Memory Maps" on page 24 for address ranges of each Programming Region per density. Table 26. Programming Regions per Device Device Density Number of blocks per Programming Region Number of Programming Regions per Device 64-Mbit 8 blocks 8 128-Mbit 8 blocks 16 256-Mbit 16 blocks 16 512-Mbit 16 blocks 32 1-Gbit 16 blocks 64 Execute in Place (XIP) is defined as the ability to execute code directly from the flash memory. XIP applications must partition the memory such that code and data are in separate programming regions (see Table 26, "Programming Regions per Device" on page 61). Each Programming Region should contain only code or data, and not both. The following terms define the difference between code and data. System designs must use these definitions when partitioning their code and data for the P30 device. 11.1 Code : Execution code ran out of the flash device on a continuous basis in the system. Data : Information periodically programmed into the flash device and read back (e.g. execution code shadowed and executed in RAM, pictures, log files, etc.). Word Programming Word programming operations are initiated by writing the Word Program Setup command to the device (see Section 9.0, "Device Operations" on page 48). This is followed by a second write to the device with the address and data to be programmed. The device outputs Status Register data when read. See Figure 40, "Word Program Flowchart" on page 85. VPP must be above VPPLK, and within the specified VPPL min/max values (nominally 1.8 V). Datasheet Intel StrataFlash(R) Embedded Memory (P30) Order Number: 306666, Revision: 001 April 2005 61 1-Gbit P30 Family During programming, the Write State Machine (WSM) executes a sequence of internally-timed events that program the desired data bits at the addressed location, and verifies that the bits are sufficiently programmed. Programming the flash memory array changes "ones" to "zeros". Memory array bits that are zeros can be changed to ones only by erasing the block (see Section 12.0, "Erase Operations" on page 67). The Status Register can be examined for programming progress and errors by reading at any address. The device remains in the Read Status Register state until another command is written to the device. Status Register bit SR[7] indicates the programming status while the sequence executes. Commands that can be issued to the device during programming are Program Suspend, Read Status Register, Read Device Identifier, CFI Query, and Read Array (this returns unknown data). When programming has finished, Status Register bit SR[4] (when set) indicates a programming failure. If SR[3] is set, the WSM could not perform the word programming operation because VPP was outside of its acceptable limits. If SR[1] is set, the word programming operation attempted to program a locked block, causing the operation to abort. Before issuing a new command, the Status Register contents should be examined and then cleared using the Clear Status Register command. Any valid command can follow, when word programming has completed. 11.1.1 Factory Word Programming Factory word programming is similar to word programming in that it uses the same commands and programming algorithms. However, factory word programming enhances the programming performance with VPP = VPPH. This can enable faster programming times during OEM manufacturing processes. Factory word programming is not intended for extended use. See Section 5.2, "Operating Conditions" on page 30 for limitations when VPP = VPPH. Note: When VPP = VPPL, the device draws programming current from the VCC supply. If VPP is driven by a logic signal, VPPL must remain above VPPL MIN to program the device. When VPP = VPPH, the device draws programming current from the VPP supply. Figure 31, "Example VPP Supply Connections" on page 66 shows examples of device power supply configurations. 11.2 Buffered Programming The device features a 32-word buffer to enable optimum programming performance. For Buffered Programming, data is first written to an on-chip write buffer. Then the buffer data is programmed into the flash memory array in buffer-size increments. This can improve system programming performance significantly over non-buffered programming. When the Buffered Programming Setup command is issued (see Section 9.2, "Device Commands" on page 50), Status Register information is updated and reflects the availability of the buffer. SR[7] indicates buffer availability: if set, the buffer is available; if cleared, the buffer is not available. To retry, issue the Buffered Programming Setup command again, and re-check SR[7]. When SR[7] is set, the buffer is ready for loading. (see Figure 42, "Buffer Program Flowchart" on page 87). On the next write, a word count is written to the device at the buffer address. This tells the device how many data words will be written to the buffer, up to the maximum size of the buffer. April 2005 62 Intel StrataFlash(R) Embedded Memory (P30) Order Number: 306666, Revision: 001 Datasheet 1-Gbit P30 Family On the next write, a device start address is given along with the first data to be written to the flash memory array. Subsequent writes provide additional device addresses and data. All data addresses must lie within the start address plus the word count. Optimum programming performance and lower power usage are obtained by aligning the starting address at the beginning of a 32-word boundary (A[4:0] = 0x00). Crossing a 32-word boundary during programming will double the total programming time. After the last data is written to the buffer, the Buffered Programming Confirm command must be issued to the original block address. The WSM begins to program buffer contents to the flash memory array. If a command other than the Buffered Programming Confirm command is written to the device, a command sequence error occurs and Status Register bits SR[7,5,4] are set. If an error occurs while writing to the array, the device stops programming, and Status Register bits SR[7,4] are set, indicating a programming failure. When Buffered Programming has completed, additional buffer writes can be initiated by issuing another Buffered Programming Setup command and repeating the buffered program sequence. Buffered programming may be performed with VPP = VPPL or VPPH (see Section 5.2, "Operating Conditions" on page 30 for limitations when operating the device with VPP = VPPH). If an attempt is made to program past an erase-block boundary using the Buffered Program command, the device aborts the operation. This generates a command sequence error, and Status Register bits SR[5,4] are set. If Buffered programming is attempted while VPP is below VPPLK, Status Register bits SR[4,3] are set. If any errors are detected that have set Status Register bits, the Status Register should be cleared using the Clear Status Register command. 11.3 Buffered Enhanced Factory Programming Buffered Enhanced Factory Programing (BEFP) speeds up Multi-Level Cell (MLC) flash programming. The enhanced programming algorithm used in BEFP eliminates traditional programming elements that drive up overhead in device programmer systems. BEFP consists of three phases: Setup, Program/Verify, and Exit (see Figure 43, "BEFP Flowchart" on page 88). It uses a write buffer to spread MLC program performance across 32 data words. Verification occurs in the same phase as programming to accurately program the flash memory cell to the correct bit state. A single two-cycle command sequence programs the entire block of data. This enhancement eliminates three write cycles per buffer: two commands and the word count for each set of 32 data words. Host programmer bus cycles fill the device's write buffer followed by a status check. SR[0] indicates when data from the buffer has been programmed into sequential flash memory array locations. Following the buffer-to-flash array programming sequence, the Write State Machine (WSM) increments internal addressing to automatically select the next 32-word array boundary. This aspect of BEFP saves host programming equipment the address-bus setup overhead. With adequate continuity testing, programming equipment can rely on the WSM's internal verification to ensure that the device has programmed properly. This eliminates the external postprogram verification and its associated overhead. Datasheet Intel StrataFlash(R) Embedded Memory (P30) Order Number: 306666, Revision: 001 April 2005 63 1-Gbit P30 Family 11.3.1 BEFP Requirements and Considerations BEFP requirements: * * * * * Case temperature: TC = 25 C 5 C VCC within specified operating range VPP driven to VPPH Target block unlocked before issuing the BEFP Setup and Confirm commands The first-word address (WA0) for the block to be programmed must be held constant from the setup phase through all data streaming into the target block, until transition to the exit phase is desired * WA0 must align with the start of an array buffer boundary1 BEFP considerations: * * * * For optimum performance, cycling must be limited below 100 erase cycles per block2 BEFP programs one block at a time; all buffer data must fall within a single block3 BEFP cannot be suspended Programming to the flash memory array can occur only when the buffer is full4 NOTES: 1. Word buffer boundaries in the array are determined by A[4:0] (0x00 through 0x1F). The alignment start point is A[4:0] = 0x00. 2. Some degradation in performance may occur if this limit is exceeded, but the internal algorithm continues to work properly. 3. If the internal address counter increments beyond the block's maximum address, addressing wraps around to the beginning of the block. 4. If the number of words is less than 32, remaining locations must be filled with 0xFFFF. 11.3.2 BEFP Setup Phase After receiving the BEFP Setup and Confirm command sequence, Status Register bit SR[7] (Ready) is cleared, indicating that the WSM is busy with BEFP algorithm startup. A delay before checking SR[7] is required to allow the WSM enough time to perform all of its setups and checks (Block-Lock status, VPP level, etc.). If an error is detected, SR[4] is set and BEFP operation terminates. If the block was found to be locked, SR[1] is also set. SR[3] is set if the error occurred due to an incorrect VPP level. Note: Reading from the device after the BEFP Setup and Confirm command sequence outputs Status Register data. Do not issue the Read Status Register command; it will be interpreted as data to be loaded into the buffer. 11.3.3 BEFP Program/Verify Phase After the BEFP Setup Phase has completed, the host programming system must check SR[7,0] to determine the availability of the write buffer for data streaming. SR[7] cleared indicates the device is busy and the BEFP program/verify phase is activated. SR[0] indicates the write buffer is available. April 2005 64 Intel StrataFlash(R) Embedded Memory (P30) Order Number: 306666, Revision: 001 Datasheet 1-Gbit P30 Family Two basic sequences repeat in this phase: loading of the write buffer, followed by buffer data programming to the array. For BEFP, the count value for buffer loading is always the maximum buffer size of 32 words. During the buffer-loading sequence, data is stored to sequential buffer locations starting at address 0x00. Programming of the buffer contents to the flash memory array starts as soon as the buffer is full. If the number of words is less than 32, the remaining buffer locations must be filled with 0xFFFF. Caution: The buffer must be completely filled for programming to occur. Supplying an address outside of the current block's range during a buffer-fill sequence causes the algorithm to exit immediately. Any data previously loaded into the buffer during the fill cycle is not programmed into the array. The starting address for data entry must be buffer size aligned, if not the BEFP algorithm will be aborted and the program fails and (SR[4]) flag will be set. Data words from the write buffer are directed to sequential memory locations in the flash memory array; programming continues from where the previous buffer sequence ended. The host programming system must poll SR[0] to determine when the buffer program sequence completes. SR[0] cleared indicates that all buffer data has been transferred to the flash array; SR[0] set indicates that the buffer is not available yet for the next fill cycle. The host system may check full status for errors at any time, but it is only necessary on a block basis after BEFP exit. After the buffer fill cycle, no write cycles should be issued to the device until SR[0] = 0 and the device is ready for the next buffer fill. Note: Any spurious writes are ignored after a buffer fill operation and when internal program is proceeding. The host programming system continues the BEFP algorithm by providing the next group of data words to be written to the buffer. Alternatively, it can terminate this phase by changing the block address to one outside of the current block's range. The Program/Verify phase concludes when the programmer writes to a different block address; data supplied must be 0xFFFF. Upon Program/Verify phase completion, the device enters the BEFP Exit phase. 11.3.4 BEFP Exit Phase When SR[7] is set, the device has returned to normal operating conditions. A full status check should be performed at this time to ensure the entire block programmed successfully. When exiting the BEFP algorithm with a block address change, the read mode will not change. After BEFP exit, any valid command can be issued to the device. 11.4 Program Suspend Issuing the Program Suspend command while programming suspends the programming operation. This allows data to be accessed from the device other than the one being programmed. The Program Suspend command can be issued to any device address. A program operation can be suspended to perform reads only. Additionally, a program operation that is running during an erase suspend can be suspended to perform a read operation (see Figure 41, "Program Suspend/Resume Flowchart" on page 86). Datasheet Intel StrataFlash(R) Embedded Memory (P30) Order Number: 306666, Revision: 001 April 2005 65 1-Gbit P30 Family When a programming operation is executing, issuing the Program Suspend command requests the WSM to suspend the programming algorithm at predetermined points. The device continues to output Status Register data after the Program Suspend command is issued. Programming is suspended when Status Register bits SR[7,2] are set. Suspend latency is specified in Section 7.5, "Program and Erase Characteristics" on page 45. To read data from the device, the Read Array command must be issued. Read Array, Read Status Register, Read Device Identifier, CFI Query, and Program Resume are valid commands during a program suspend. During a program suspend, deasserting CE# places the device in standby, reducing active current. VPP must remain at its programming level, and WP# must remain unchanged while in program suspend. If RST# is asserted, the device is reset. 11.5 Program Resume The Resume command instructs the device to continue programming, and automatically clears Status Register bits SR[7,2]. This command can be written to any address. If error bits are set, the Status Register should be cleared before issuing the next instruction. RST# must remain deasserted (see Figure 41, "Program Suspend/Resume Flowchart" on page 86). 11.6 Program Protection When VPP = VIL, absolute hardware write protection is provided for all device blocks. If VPP is at or below VPPLK, programming operations halt and SR[3] is set indicating a VPP-level error. Block lock registers are not affected by the voltage level on VPP; they may still be programmed and read, even if VPP is less than VPPLK. Figure 31. Example VPP Supply Connections VCC VPP VCC VPP VPP=VPPH VCC VPP * Low-voltage Programming only * Logic Control of Device Protection VCC VPP * Low Voltage and Factory Programming April 2005 66 PROT # VCC 10K * Factory Programming with VPP = VPPH * Complete write/Erase Protection when VPP VPPLK VCC VCC VCC VPP * Low Voltage Programming Only * Full Device Protection Unavailable Intel StrataFlash(R) Embedded Memory (P30) Order Number: 306666, Revision: 001 Datasheet 1-Gbit P30 Family 12.0 Erase Operations Flash erasing is performed on a block basis. An entire block is erased each time an erase command sequence is issued, and only one block is erased at a time. When a block is erased, all bits within that block read as logical ones. The following sections describe block erase operations in detail. 12.1 Block Erase Block erase operations are initiated by writing the Block Erase Setup command to the address of the block to be erased (see Section 9.2, "Device Commands" on page 50). Next, the Block Erase Confirm command is written to the address of the block to be erased. If the device is placed in standby (CE# deasserted) during an erase operation, the device completes the erase operation before entering standby.VPP must be above VPPLK and the block must be unlocked (see Figure 44, "Block Erase Flowchart" on page 89). During a block erase, the Write State Machine (WSM) executes a sequence of internally-timed events that conditions, erases, and verifies all bits within the block. Erasing the flash memory array changes "zeros" to "ones". Memory array bits that are ones can be changed to zeros only by programming the block (see Section 11.0, "Programming Operations" on page 61). The Status Register can be examined for block erase progress and errors by reading any address. The device remains in the Read Status Register state until another command is written. SR[0] indicates whether the addressed block is erasing. Status Register bit SR[7] is set upon erase completion. Status Register bit SR[7] indicates block erase status while the sequence executes. When the erase operation has finished, Status Register bit SR[5] indicates an erase failure if set. SR[3] set would indicate that the WSM could not perform the erase operation because VPP was outside of its acceptable limits. SR[1] set indicates that the erase operation attempted to erase a locked block, causing the operation to abort. Before issuing a new command, the Status Register contents should be examined and then cleared using the Clear Status Register command. Any valid command can follow once the block erase operation has completed. 12.2 Erase Suspend Issuing the Erase Suspend command while erasing suspends the block erase operation. This allows data to be accessed from memory locations other than the one being erased. The Erase Suspend command can be issued to any device address. A block erase operation can be suspended to perform a word or buffer program operation, or a read operation within any block except the block that is erase suspended (see Figure 41, "Program Suspend/Resume Flowchart" on page 86). When a block erase operation is executing, issuing the Erase Suspend command requests the WSM to suspend the erase algorithm at predetermined points. The device continues to output Status Register data after the Erase Suspend command is issued. Block erase is suspended when Status Register bits SR[7,6] are set. Suspend latency is specified in Section 7.5, "Program and Erase Characteristics" on page 45. Datasheet Intel StrataFlash(R) Embedded Memory (P30) Order Number: 306666, Revision: 001 April 2005 67 1-Gbit P30 Family To read data from the device (other than an erase-suspended block), the Read Array command must be issued. During Erase Suspend, a Program command can be issued to any block other than the erase-suspended block. Block erase cannot resume until program operations initiated during erase suspend complete. Read Array, Read Status Register, Read Device Identifier, CFI Query, and Erase Resume are valid commands during Erase Suspend. Additionally, Clear Status Register, Program, Program Suspend, Block Lock, Block Unlock, and Block Lock-Down are valid commands during Erase Suspend. During an erase suspend, deasserting CE# places the device in standby, reducing active current. VPP must remain at a valid level, and WP# must remain unchanged while in erase suspend. If RST# is asserted, the device is reset. 12.3 Erase Resume The Erase Resume command instructs the device to continue erasing, and automatically clears status register bits SR[7,6]. This command can be written to any address. If status register error bits are set, the Status Register should be cleared before issuing the next instruction. RST# must remain deasserted (see Figure 41, "Program Suspend/Resume Flowchart" on page 86). 12.4 Erase Protection When VPP = VIL, absolute hardware erase protection is provided for all device blocks. If VPP is below VPPLK, erase operations halt and SR[3] is set indicating a VPP-level error. April 2005 68 Intel StrataFlash(R) Embedded Memory (P30) Order Number: 306666, Revision: 001 Datasheet 1-Gbit P30 Family 13.0 Security Modes The device features security modes used to protect the information stored in the flash memory array. The following sections describe each security mode in detail. 13.1 Block Locking Individual instant block locking is used to protect user code and/or data within the flash memory array. All blocks power up in a locked state to protect array data from being altered during power transitions. Any block can be locked or unlocked with no latency. Locked blocks cannot be programmed or erased; they can only be read. Software-controlled security is implemented using the Block Lock and Block Unlock commands. Hardware-controlled security can be implemented using the Block Lock-Down command along with asserting WP#. Also, VPP data security can be used to inhibit program and erase operations (see Section 11.6, "Program Protection" on page 66 and Section 12.4, "Erase Protection" on page 68). The P30 device also offers four pre-defined areas in the main array that can be configured as OneTime Programmable (OTP) for the highest level of security. These include the four 32 KB parameter blocks together as one and the three adjacent 128 KB main blocks. This is available for top or bottom parameter devices. 13.1.1 Lock Block To lock a block, issue the Lock Block Setup command. The next command must be the Lock Block command issued to the desired block's address (see Section 9.2, "Device Commands" on page 50 and Figure 46, "Block Lock Operations Flowchart" on page 91). If the Set Read Configuration Register command is issued after the Block Lock Setup command, the device configures the RCR instead. Block lock and unlock operations are not affected by the voltage level on VPP. The block lock bits may be modified and/or read even if VPP is at or below VPPLK. 13.1.2 Unlock Block The Unlock Block command is used to unlock blocks (see Section 9.2, "Device Commands" on page 50). Unlocked blocks can be read, programmed, and erased. Unlocked blocks return to a locked state when the device is reset or powered down. If a block is in a lock-down state, WP# must be deasserted before it can be unlocked (see Figure 32, "Block Locking State Diagram" on page 70). 13.1.3 Lock-Down Block A locked or unlocked block can be locked-down by writing the Lock-Down Block command sequence (see Section 9.2, "Device Commands" on page 50). Blocks in a lock-down state cannot be programmed or erased; they can only be read. However, unlike locked blocks, their locked state cannot be changed by software commands alone. A locked-down block can only be unlocked by issuing the Unlock Block command with WP# deasserted. To return an unlocked block to locked- Datasheet Intel StrataFlash(R) Embedded Memory (P30) Order Number: 306666, Revision: 001 April 2005 69 1-Gbit P30 Family down state, a Lock-Down command must be issued prior to changing WP# to VIL. Locked-down blocks revert to the locked state upon reset or power up the device (see Figure 32, "Block Locking State Diagram" on page 70). 13.1.4 Block Lock Status The Read Device Identifier command is used to determine a block's lock status (see Section 14.2, "Read Device Identifier" on page 76). Data bits DQ[1:0] display the addressed block's lock status; DQ0 is the addressed block's lock bit, while DQ1 is the addressed block's lock-down bit. Figure 32. Block Locking State Diagram Power-Up/Reset LockedDown 4,5 [011] Locked [X01] Hardware Locked 5 [011] WP# Hardware Control Software Locked [111] Unlocked [X00] Unlocked [110] Software Block Lock (0x60/0x01) or Software Block Unlock (0x60/0xD0) Software Block Lock -Down (0x60/0x2F) W P# hardware control Notes: 13.1.5 1. [a,b,c] represents [WP#, DQ1, DQ0]. X = Don't Care. 2. DQ1 indicates Block Lock-Down status. DQ1 = `0', Lock-Down has not been issued to this block. DQ1 = `1', Lock-Down has been issued to this block. 3. DQ0 indicates block lock status. DQ0 = `0', block is unlocked. DQ0 = `1', block is locked. 4. Locked-down = Hardware + Software locked. 5. [011] states should be tracked by system software to determine difference between Hardware Locked and Locked-Down states. Block Locking During Suspend Block lock and unlock changes can be performed during an erase suspend. To change block locking during an erase operation, first issue the Erase Suspend command. Monitor the Status Register until SR[7] and SR[6] are set, indicating the device is suspended and ready to accept another command. Next, write the desired lock command sequence to a block, which changes the lock state of that block. After completing block lock or unlock operations, resume the erase operation using the Erase Resume command. Note: April 2005 70 A Lock Block Setup command followed by any command other than Lock Block, Unlock Block, or Lock-Down Block produces a command sequence error and set Status Register bits SR[4] and Intel StrataFlash(R) Embedded Memory (P30) Order Number: 306666, Revision: 001 Datasheet 1-Gbit P30 Family SR[5]. If a command sequence error occurs during an erase suspend, SR[4] and SR[5] remains set, even after the erase operation is resumed. Unless the Status Register is cleared using the Clear Status Register command before resuming the erase operation, possible erase errors may be masked by the command sequence error. If a block is locked or locked-down during an erase suspend of the same block, the lock status bits change immediately. However, the erase operation completes when it is resumed. Block lock operations cannot occur during a program suspend. See Appendix A, "Write State Machine" on page 78, which shows valid commands during an erase suspend. 13.2 Selectable One-Time Programmable Blocks Any of four pre-defined areas from the main array (the four 32 KB parameter blocks together as one and the three adjacent 128 KB main blocks) can be configured as One-Time Programmable (OTP) so further program and erase operations are not allowed. This option is available for top or bottom parameter devices. Table 27. Selectable OTP Block Mapping Density Top Parameter Configuration Bottom Parameter Configuration blocks 258:255 (parameters) blocks 3:0 (parameters) block 254 (main) block 4 (main) block 253 (main) block 5 (main) block 252 (main) block 6 (main) blocks 130:127 (parameters) blocks 3:0 (parameters) block 126 (main) block 4 (main) block 125 (main) block 5 (main) block 124 (main) block 6 (main) blocks 66:63 (parameters) blocks 3:0 (parameters) block 62 (main) block 4 (main) block 61 (main) block 5 (main) block 60 (main) block 6 (main) 256-Mbit 128-Mbit 64-Mbit Note: The 512-Mbit and 1-Gbit devices will have multiple Selectable OTP Areas depending on the number of 256-Mbit dies in the stack and the placement of the parameter blocks. Please see your local Intel representative for details about the Selectable OTP implementation. Datasheet Intel StrataFlash(R) Embedded Memory (P30) Order Number: 306666, Revision: 001 April 2005 71 1-Gbit P30 Family 13.3 Protection Registers The device contains 17 Protection Registers (PRs) that can be used to implement system security measures and/or device identification. Each Protection Register can be individually locked. The first 128-bit Protection Register is comprised of two 64-bit (8-word) segments. The lower 64bit segment is pre-programmed at the Intel factory with a unique 64-bit number. The other 64-bit segment, as well as the other sixteen 128-bit Protection Registers, are blank. Users can program these registers as needed. When programmed, users can then lock the Protection Register(s) to prevent additional bit programming (see Figure 33, "Protection Register Map" on page 73). The user-programmable Protection Registers contain one-time programmable (OTP) bits; when programmed, register bits cannot be erased. Each Protection Register can be accessed multiple times to program individual bits, as long as the register remains unlocked. Each Protection Register has an associated Lock Register bit. When a Lock Register bit is programmed, the associated Protection Register can only be read; it can no longer be programmed. Additionally, because the Lock Register bits themselves are OTP, when programmed, Lock Register bits cannot be erased. Therefore, when a Protection Register is locked, it cannot be unlocked. April 2005 72 Intel StrataFlash(R) Embedded Memory (P30) Order Number: 306666, Revision: 001 Datasheet 1-Gbit P30 Family . Figure 33. Protection Register Map 0x109 128-bit Protection Register 16 (User-Programmable) 0x102 0x91 128-bit Protection Register 1 (User-Programmable) 0x8A Lock Register 1 0x89 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 0x88 64-bit Segment (User-Programmable) 0x85 0x84 128-Bit Protection Register 0 64-bit Segment (Factory-Programmed) 0x81 Lock Register 0 0x80 13.3.1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 Reading the Protection Registers The Protection Registers can be read from any address. To read the Protection Register, first issue the Read Device Identifier command at any address to place the device in the Read Device Identifier state (see Section 9.2, "Device Commands" on page 50). Next, perform a read operation using the address offset corresponding to the register to be read. Table 29, "Device Identifier Information" on page 77 shows the address offsets of the Protection Registers and Lock Registers. Register data is read 16 bits at a time. 13.3.2 Programming the Protection Registers To program any of the Protection Registers, first issue the Program Protection Register command at the parameter's base address plus the offset to the desired Protection Register (see Section 9.2, "Device Commands" on page 50). Next, write the desired Protection Register data to the same Protection Register address (see Figure 33, "Protection Register Map" on page 73). Datasheet Intel StrataFlash(R) Embedded Memory (P30) Order Number: 306666, Revision: 001 April 2005 73 1-Gbit P30 Family The device programs the 64-bit and 128-bit user-programmable Protection Register data 16 bits at a time (see Figure 47, "Protection Register Programming Flowchart" on page 92). Issuing the Program Protection Register command outside of the Protection Register's address space causes a program error (SR[4] set). Attempting to program a locked Protection Register causes a program error (SR[4] set) and a lock error (SR[1] set). 13.3.3 Locking the Protection Registers Each Protection Register can be locked by programming its respective lock bit in the Lock Register. To lock a Protection Register, program the corresponding bit in the Lock Register by issuing the Program Lock Register command, followed by the desired Lock Register data (see Section 9.2, "Device Commands" on page 50). The physical addresses of the Lock Registers are 0x80 for register 0 and 0x89 for register 1. These addresses are used when programming the lock registers (see Table 29, "Device Identifier Information" on page 77). Bit 0 of Lock Register 0 is already programmed at the factory, locking the lower, pre-programmed 64-bit region of the first 128-bit Protection Register containing the unique identification number of the device. Bit 1 of Lock Register 0 can be programmed by the user to lock the user-programmable, 64-bit region of the first 128-bit Protection Register. When programming Bit 1 of Lock Register 0, all other bits need to be left as `1' such that the data programmed is 0xFFFD. Lock Register 1 controls the locking of the upper sixteen 128-bit Protection Registers. Each of the 16 bits of Lock Register 1 correspond to each of the upper sixteen 128-bit Protection Registers. Programming a bit in Lock Register 1 locks the corresponding 128-bit Protection Register. Caution: April 2005 74 After being locked, the Protection Registers cannot be unlocked. Intel StrataFlash(R) Embedded Memory (P30) Order Number: 306666, Revision: 001 Datasheet 1-Gbit P30 Family 14.0 Special Read States The following sections describe non-array read states. Non-array reads can be performed in asynchronous read or synchronous burst mode. A non-array read operation occurs as asynchronous single-word mode. When non-array reads are performed in asynchronous page mode only the first data is valid and all subsequent data are undefined. When a non-array read operation occurs as synchronous burst mode, the same word of data requested will be output on successive clock edges until the burst length requirements are satisfied. Refer to the following waveforms for more detailed information: * Figure 16, "Asynchronous Single-Word Read (ADV# Low)" on page 38 * Figure 17, "Asynchronous Single-Word Read (ADV# Latch)" on page 38 * Figure 19, "Synchronous Single-Word Array or Non-array Read Timing" on page 39 14.1 Read Status Register To read the Status Register, issue the Read Status Register command at any address. Status Register information is available to which the Read Status Register, Word Program, or Block Erase command was issued. Status Register data is automatically made available following a Word Program, Block Erase, or Block Lock command sequence. Reads from the device after any of these command sequences outputs the device's status until another valid command is written (e.g. Read Array command). The Status Register is read using single asynchronous-mode or synchronous burst mode reads. Status Register data is output on DQ[7:0], while 0x00 is output on DQ[15:8]. In asynchronous mode the falling edge of OE#, or CE# (whichever occurs first) updates and latches the Status Register contents. However, reading the Status Register in synchronous burst mode, CE# or ADV# must be toggled to update status data. The Device Write Status bit (SR[7]) provides overall status of the device. Status register bits SR[6:1] present status and error information about the program, erase, suspend, VPP, and blocklocked operations. Table 28. Status Register Description (Sheet 1 of 2) Status Register (SR) Device Write Status Erase Suspend Status Erase Status Program Status VPP Status Program Suspend Status BlockLocked Status BEFP Status DWS ESS ES PS VPPS PSS BLS BWS 7 6 5 4 3 2 1 0 Bit Datasheet Default Value = 0x80 Name Description 7 Device Write Status (DWS) 0 = Device is busy; program or erase cycle in progress; SR[0] valid. 1 = Device is ready; SR[6:1] are valid. 6 Erase Suspend Status (ESS) 0 = Erase suspend not in effect. 1 = Erase suspend in effect. Intel StrataFlash(R) Embedded Memory (P30) Order Number: 306666, Revision: 001 April 2005 75 1-Gbit P30 Family Table 28. Status Register Description (Sheet 2 of 2) Status Register (SR) Default Value = 0x80 5 Erase Status (ES) 0 = Erase successful. 1 = Erase fail or program sequence error when set with SR[4,7]. 4 Program Status (PS) 0 = Program successful. 1 = Program fail or program sequence error when set with SR[5,7] 3 VPP Status (VPPS) 0 = VPP within acceptable limits during program or erase operation. 1 = VPP < VPPLK during program or erase operation. 2 Program Suspend Status (PSS) 0 = Program suspend not in effect. 1 = Program suspend in effect. 1 Block-Locked Status (BLS) 0 = Block not locked during program or erase. 1 = Block locked during program or erase; operation aborted. BEFP Status (BWS) DWS BWS = WSM is busy and buffer is available for loading. 0 0 = WSM is busy and buffer is not available for loading. 0 1 = WSM is not busy and buffer is available for loading. 1 0 = Reserved for Future Use (RFU). 1 1 0 Note: Always clear the Status Register prior to resuming erase operations. It avoids Status Register ambiguity when issuing commands during Erase Suspend. If a command sequence error occurs during an erase-suspend state, the Status Register contains the command sequence error status (SR[7,5,4] set). When the erase operation resumes and finishes, possible errors during the erase operation cannot be detected via the Status Register because it contains the previous error status. 14.1.1 Clear Status Register The Clear Status Register command clears the status register. It functions independent of VPP. The Write State Machine (WSM) sets and clears SR[7,6,2], but it sets bits SR[5:3,1] without clearing them. The Status Register should be cleared before starting a command sequence to avoid any ambiguity. A device reset also clears the Status Register. 14.2 Read Device Identifier The Read Device Identifier command instructs the device to output manufacturer code, device identifier code, block-lock status, protection register data, or configuration register data (see Section 9.2, "Device Commands" on page 50 for details on issuing the Read Device Identifier command). Table 29, "Device Identifier Information" on page 77 and Table 30, "Device ID codes" on page 77 show the address offsets and data values for this device. April 2005 76 Intel StrataFlash(R) Embedded Memory (P30) Order Number: 306666, Revision: 001 Datasheet 1-Gbit P30 Family Table 29. Device Identifier Information Address(1) Item Data Manufacturer Code 0x00 0089h Device ID Code 0x01 ID (see Table 30) Block Lock Configuration: Lock Bit: * Block Is Unlocked DQ0 = 0b0 * Block Is Locked BBA + 0x02 DQ0 = 0b1 * Block Is not Locked-Down DQ1 = 0b0 * Block Is Locked-Down DQ1 = 0b1 Configuration Register 0x05 Lock Register 0 Configuration Register Data 0x80 PR-LK0 64-bit Factory-Programmed Protection Register 0x81-0x84 Factory Protection Register Data 64-bit User-Programmable Protection Register 0x85-0x88 User Protection Register Data Lock Register 1 0x89 128-bit User-Programmable Protection Registers Protection Register Data 0x8A-0x109 PR-LK1 Notes: 1. BBA = Block Base Address. Table 30. Device ID codes Device Identifier Codes ID Code Type Device Code 14.3 Device Density -T -B (Top Parameter) (Bottom Parameter) 64-Mbit 128-Mbit 256-Mbit 8817 8818 8919 881A 881B 891C CFI Query The CFI Query command instructs the device to output Common Flash Interface (CFI) data when read. See Section 9.2, "Device Commands" on page 50 for details on issuing the CFI Query command. Appendix C, "Common Flash Interface" on page 93 shows CFI information and address offsets within the CFI database. Datasheet Intel StrataFlash(R) Embedded Memory (P30) Order Number: 306666, Revision: 001 April 2005 77 1-Gbit P30 Family Appendix A Write State Machine Figure 34 through Figure 39 show the command state transitions (Next State Table) based on incoming commands. Only one partition can be actively programming or erasing at a time. Each partition stays in its last read state (Read Array, Read Device ID, CFI Query or Read Status Register) until a new command changes it. The next WSM state does not depend on the partition's output state. Figure 34. Write State Machine--Next State Table (Sheet 1 of 6) Command Input to Chip and resulting Chip Next State Current Chip State (7) Ready Read Array (2) Word Program (3,4) Buffered Program (BP) Erase Setup (3,4) Buffered Enhanced Factory Pgm Setup (3, 4) (FFH) (10H/40H) (E8H) (20H) (80H) Ready Program Setup BP Setup Erase Setup BEFP Setup Setup OTP Read Status Clear Status Register Lock, Unlock, Lock-down, Read ID/Query (5) CR setup (4) (8) (D0H) (B0H) (70H) (50H) (90H, 98H) (60H) Lock/CR Setup Ready Ready (Lock Error) OTP Busy Busy Word Program Busy Setup Word Program Suspend Program Busy Busy Word Program Confirm BP / Prg / Erase Suspend Ready (Unlock Block) Ready (Lock Error) Lock/CR Setup BE Confirm, P/E Resume, ULB, Word Program Busy Word Program Suspend Suspend Word Program Busy Word Program Suspend Setup BP Load 1 BP Load 1 BP Load 2 BP Load 2 BP Confirm if Data load into Program Buffer is complete; Else BP Load 2 BP BP Confirm Ready (Error) BP Busy BP Busy BP Suspend BP Busy Setup Ready (Error) Erase Busy Suspend April 2005 78 Erase Suspend Word Program Setup in Erase Suspend BP Setup in Erase Suspend Erase Suspend BP Suspend Ready (Error) Erase Suspend Erase Busy Busy BP Busy BP Suspend BP Suspend Erase Ready (Error) BP Busy Erase Busy Erase Busy Erase Suspend Intel StrataFlash(R) Embedded Memory (P30) Order Number: 306666, Revision: 001 Lock/CR Setup in Erase Suspend Datasheet 1-Gbit P30 Family Figure 35. Write State Machine--Next State Table (Sheet 2 of 6) Command Input to Chip and resulting Chip Next State Current Chip (7) State Read Array (2) (FFH) Word Program (3,4) (10H/40H) Buffered Program (BP) (E8H) Buffered Erase Enhanced (3,4) Factory Pgm Setup Setup (3, 4) (20H) Busy Suspend BP in Erase Suspend Read Status Clear Status Register (5) Read ID/Query Lock, Unlock, Lock-down, CR setup (4) (B0H) (70H) (50H) (90H, 98H) (60H) (8) (D0H) Word Program Suspend in Erase Suspend Word Program Busy in Erase Suspend Word Program Suspend in Erase Suspend Word Program Busy in Erase Suspend Word Program Busy in Erase Suspend Busy Word Program Suspend in Erase Suspend Setup BP Load 1 BP Load 1 BP Load 2 BP Load 2 BP Confirm if Data load into Program Buffer is complete; Else BP Load 2 BP Confirm BP Busy BP Suspend Lock/CR Setup in Erase Suspend Buffered Enhanced Factory Program Mode Confirm BP / Prg / Erase Suspend Word Program Busy in Erase Suspend Setup Word Program in Erase Suspend (80H) BE Confirm, P/E Resume, ULB, Setup BEFP Busy Datasheet Erase Suspend (Error) BP Busy in Erase Suspend Ready (Error in Erase Suspend) BP Suspend in Erase Suspend BP Busy in Erase Suspend BP Busy in Erase Suspend BP Suspend in Erase Suspend BP Busy in Erase Suspend BP Suspend in Erase Suspend Erase Suspend (Lock Error) Erase Suspend (Unlock Block) Erase Suspend (Lock Error [Botch]) Ready (Error) BEFP Loading Data (X=32) Ready (Error) BEFP Program and Verify Busy (if Block Address given matches address given on BEFP Setup command). Commands treated as data. (7) Intel StrataFlash(R) Embedded Memory (P30) Order Number: 306666, Revision: 001 April 2005 79 1-Gbit P30 Family Figure 36. Write State Machine--Next State Table (Sheet 3 of 6) Command Input to Chip and resulting Chip Next State Current Chip (7) State OTP Setup (4) (C0H) Ready OTP Setup Lock/CR Setup Ready (Lock Error) OTP Lock Block Confirm (01H) Lock-Down Block (8) Confirm (2FH) Write RCR Confirm (8) Block Address (?WA0) 9 Illegal Cmds or BEFP Data (1) (03H) (XXXXH) (all other codes) Ready (Lock Block) Ready (Lock Down Blk) Setup Ready (Set CR) Ready (Lock Error) OTP Busy Busy N/A Ready Busy Word Program Busy N/A Word Program Busy Ready Word Program Suspend Suspend BP Load 1 Setup BP Load 1 WSM Operation Completes Ready Setup Word Program (8) BP Load 2 Ready (BP Load 2 BP Load 2 BP Load 2 BP Confirm if Data load into Program Buffer is complete; ELSE BP load 2 BP Confirm Ready (Error) Ready BP Ready (Error) (Proceed if unlocked or lock error) BP Confirm if Data load into Program Buffer is complete; ELSE BP Load 2 N/A Ready (Error) BP Busy BP Busy BP Suspend BP Suspend Setup Ready (Error) Busy Erase Busy Ready Suspend Erase Suspend N/A Ready N/A Erase April 2005 80 Intel StrataFlash(R) Embedded Memory (P30) Order Number: 306666, Revision: 001 Datasheet 1-Gbit P30 Family Figure 37. Write State Machine--Next State Table (Sheet 4 of 6) Command Input to Chip and resulting Chip Next State Current Chip State (7) OTP Setup (4) (C0H) Lock-Down Block Confirm (8) (01H) Confirm (8) Write RCR Confirm (8) Block Address (?WA0) 9 Illegal Cmds or BEFP Data (1) (03H) (XXXXH) (all other codes) (2FH) WSM Operation Completes Setup Word Program Busy in Erase Suspend NA Busy Word Program Busy in Erase Suspend Busy Erase Suspend Suspend Word Program Suspend in Erase Suspend N/A Setup BP Load 1 Word Program in Erase Suspend BP in Erase Suspend Lock Block BP Load 1 BP Load 2 BP Load 2 BP Confirm if Data load into Program Buffer is complete; Else BP Load 2 BP Confirm Ready (Error in Erase Suspend) Ready (BP Load 2 BP Load 2 Ready Ready (Error) (Proceed if unlocked or lock error) BP Busy BP Busy in Erase Suspend BP Suspend BP Suspend in Erase Suspend Lock/CR Setup in Erase Suspend Buffered Enhanced Factory Program Mode Datasheet Erase Suspend (Lock Error) Erase Suspend (Lock Block) Erase Suspend (Lock Down Block) Erase Suspend (Set CR) BP Confirm if Data load into Program Buffer is complete; Else BP Load 2 N/A Ready (Error) Erase Suspend Erase Suspend (Lock Error) Setup Ready (Error) Ready (BEFP Loading Data) Ready (Error) BEFP Busy BEFP Program and Verify Busy (if Block Address given matches address given on BEFP Setup command). Commands treated as data. (7) Ready BEFP Busy N/A Ready Intel StrataFlash(R) Embedded Memory (P30) Order Number: 306666, Revision: 001 April 2005 81 1-Gbit P30 Family Figure 38. Write State Machine--Next State Table (Sheet 5 of 6) Output Next State Table Command Input to Chip and resulting Output Mux Next State Read Current chip state Array (2) (FFH) Word Program Setup (3,4) (10H/40H) BP Setup Erase Setup (3,4) Buffered Enhanced Factory Pgm Setup (3, 4) (E8H) (20H) (30H) BE Confirm, P/E Resume, ULB Confirm Program/ Erase Suspend Read Status (B0H) (70H) Clear Status Register (5) (D0H) Status Read Lock/CR Setup, Lock/CR Setup in Erase Susp Status Read (50H) CR setup (4) (90H, 98H) (60H) Status Read OTP Busy April 2005 82 Lock, Unlock, Lock-down, (8) BEFP Setup, BEFP Pgm & Verify Busy, Erase Setup, OTP Setup, BP: Setup, Load 1, Load 2, Confirm, Word Pgm Setup, Word Pgm Setup in Erase Susp, BP Setup, Load1, Load 2, Confirm in Erase Suspend Ready, Erase Suspend, BP Suspend BP Busy, Word Program Busy, Erase Busy, BP Busy BP Busy in Erase Suspend Word Pgm Suspend, Word Pgm Busy in Erase Suspend, Pgm Suspend In Erase Suspend Read ID/Query Read Array Status Read Output does not change. Status Read Intel StrataFlash(R) Embedded Memory (P30) Order Number: 306666, Revision: 001 Output mux does not change. Status Read ID Read Datasheet 1-Gbit P30 Family Figure 39. Write State Machine--Next State Table (Sheet 6 of 6) Output Next State Table Command Input to Chip and resulting Output Mux Next State Current chip state OTP Setup (4) Lock Block Confirm (8) Lock-Down Block Confirm (8) Write CR Confirm (8) Block Address (?WA0) Illegal Cmds or BEFP Data (1) (C0H) (01H) (2FH) (03H) (FFFFH) (all other codes) BEFP Setup, BEFP Pgm & Verify Busy, Erase Setup, OTP Setup, BP: Setup, Load 1, Load 2, Confirm, Word Pgm Setup, Word Pgm Setup in Erase Susp, BP Setup, Load1, Load 2, Confirm in Erase Suspend Status Read Lock/CR Setup, Lock/CR Setup in Erase Susp Status Read Array Read Status Read Output does not change. OTP Busy Ready, Erase Suspend, BP Suspend BP Busy, Word Program Busy, Erase Busy, BP Busy BP Busy in Erase Suspend Word Pgm Suspend, Word Pgm Busy in Erase Suspend, Pgm Suspend In Erase Suspend WSM Operation Completes Status Read Output does not change. Array Read Output does not change. Notes: 1. "Illegal commands" include commands outside of the allowed command set (allowed commands: 40H [pgm], 20H [erase], etc.) 2. If a "Read Array" is attempted from a busy partition, the result will be invalid data. The ID and Query data are located at different locations in the address map. 3. 1st and 2nd cycles of "2 cycles write commands" must be given to the same partition address, or unexpected results will occur. 4. To protect memory contents against erroneous command sequences, there are specific instances in a multi-cycle command sequence in which the second cycle will be ignored. For example, when the device is program suspended and an erase setup command (0x20) is given followed by a confirm/resume command (0xD0), the second command will be ignored because it is unclear whether the user intends to erase the block or resume the program operation. Datasheet Intel StrataFlash(R) Embedded Memory (P30) Order Number: 306666, Revision: 001 April 2005 83 1-Gbit P30 Family 5. 6. 7. 8. 9. The Clear Status command only clears the error bits in the status register if the device is not in the following modes: WSM running (Pgm Busy, Erase Busy, Pgm Busy In Erase Suspend, OTP Busy, BEFP modes). BEFP writes are only allowed when the status register bit #0 = 0, or else the data is ignored. The "current state" is that of the "chip" and not of the "partition"; Each partition "remembers" which output (Array, ID/CFI or Status) it was last pointed to on the last instruction to the "chip", but the next state of the chip does not depend on where the partition's output mux is presently pointing to. Confirm commands (Lock Block, Unlock Block, Lock-Down Block, Configuration Register) perform the operation and then move to the Ready State. WA0 refers to the block address latched during the first write cycle of the current operation. April 2005 84 Intel StrataFlash(R) Embedded Memory (P30) Order Number: 306666, Revision: 001 Datasheet 1-Gbit P30 Family Appendix B Flowcharts Figure 40. Word Program Flowchart WORD PROGRAM PROCEDURE Bus Command Operation Start Write Write 0x40, Word Address (Setup) Write Data, Word Address Program Data = 0x40 Setup Addr = Location to program Write Data Data = Data to program Addr = Location to program Read None Status register data Idle None Check SR[7] 1 = WSM Ready 0 = WSM Busy (Confirm) Program Suspend Loop Read Status Register No SR[7] = Comments 0 Suspend? Yes Repeat for subsequent Word Program operations. Full Status Register check can be done after each program, or after a sequence of program operations. 1 Full Status Check (if desired) Write 0xFF after the last operation to set to the Read Array state. Program Complete FULL STATUS CHECK PROCEDURE Read Status Register SR[3] = Bus Command Operation 1 SR[4] = Idle None Check SR[3]: 1 = VPP Error Idle None Check SR[4]: 1 = Data Program Error Idle None Check SR[1]: 1 = Block locked; operation aborted VPP Range Error 0 1 Program Error 1 Device Protect Error Comments 0 SR[1] = If an error is detected, clear the Status Register before continuing operations - only the Clear Staus Register command clears the Status Register error bits. 0 Program Successful Datasheet Intel StrataFlash(R) Embedded Memory (P30) Order Number: 306666, Revision: 001 April 2005 85 1-Gbit P30 Family Figure 41. Program Suspend/Resume Flowchart PROGRAM SUSPEND / RESUME PROCEDURE Start Bus Command Operation Program Suspend Write B0h Any Address Write Read Status Write 70h Same Partition Write Read Status Register Read SR.7 = 0 Program Data = B0h Suspend Addr = Block to suspend (BA) Read Status 0 Program Completed 1 Read Standby Check SR.7 1 = WSM ready 0 = WSM busy Standby Check SR.2 1 = Program suspended 0 = Program completed Write Array Write FFh Susp Partition Read Array Done Reading Yes Program Resume Write Program Data = D0h Resume Addr = Suspended block (BA) If the suspended partition was placed in Read Array mode: No Write Read Array Write D0h Any Address Write FFh Pgm'd Partition Program Resumed Read Array Data Read Data = FFh Addr = Any address within the suspended partition Read array data from block other than the one being programmed Read Read Array Data Data = 70h Addr = Same partition Status register data Addr = Suspended block (BA) 1 SR.2 = Comments Read Status Return partition to Status mode: Data = 70h Addr = Same partition Status Write 70h Same Partition April 2005 86 PGM_SUS.WMF Intel StrataFlash(R) Embedded Memory (P30) Order Number: 306666, Revision: 001 Datasheet 1-Gbit P30 Family Figure 42. Buffer Program Flowchart Buffer Programming Procedure Start Device Supports Buffer Writes? No Use Single Word Programming Yes Set Timeout or Loop Counter Get Next Target Address 0xFF commands can be issued to read from any blocks in other partitions Other partitions of the device can be read by addressing those partitions and driving OE# low. (Any write commands are not allowed during this period.) Issue Buffer Prog. Cmd. 0xE8, Word Address Datasheet Read Status Register at Word Address No Write Buffer Available? SR[7] = 0 = No Timeout or Count Expired? Bus Operation Command Write Buffer Prog. Setup Data = 0xE8 Addr = Word Address Read None SR[7] = Valid Addr = Word Address Idle None Check SR[7]: 1 = Write Buffer available 0 = No Write Buffer available Write (Notes 1, 2) None Data = N-1 = Word Count N = 0 corresponds to count = 1 Addr = Word Address Write (Notes 3, 4) None Data = Write Buffer Data Addr = Start Word Address Write (Note 3) None Data = Write Buffer Data Addr = Word Address Write (Notes 5, 6) Buffer Prog. Conf. Read None Status register Data Addr = Note 7 Idle None Check SR[7]: 1 = WSM Ready 0 = WSM Busy Yes 1 = Yes Write Word Count, Word Address Buffer Program Data, Start Word Address X=X+1 X=0 Write Buffer Data, Word Address No Abort Buffer Program? Yes Yes Write Confirm 0xD0 and Word Address (Note 5) Write to another Block Address Buffer Program Aborted Read Status Register (Note 7) 0=No Suspend Program? Issue Read Status Register Command Full status check can be done after all erase and write sequences complete. Write 0xFF after the last operation to place the partition in the Read Array state. Suspend Program Loop No Is BP finished? SR[7] = Data = 0xD0 Addr = Original Word Address 1. Word count value on D[7:0] is loaded into the word count register. Count ranges for this device are N = 0x00 to 0x1F. 2. The device outputs the Status Register when read. 3. Write Buffer contents will be programmed at the issued word address. 4. Align the start address on a Write Buffer boundary for maximum programming performance (i.e., A[4:0] of the Start Word Address = 0x00). 5. The Buffered Programming Confirm command must be issued to an address in the same block, for example, the original Start Word Address, or the last address used during the loop that loaded the buffer data. 6. The Status Register indicates an improper command sequence if the Buffer Program command is aborted; use the Clear Status Register command to clear error bits. 7. The Status Register can be read from any address within the programming partition. No X = N? Comments Yes 1=Yes Full Status Check if Desired Program Complete Intel StrataFlash(R) Embedded Memory (P30) Order Number: 306666, Revision: 001 April 2005 87 1-Gbit P30 Family Figure 43. BEFP Flowchart BUFFERED ENHANCED FACTORY PROGRAMMING (BEFP) PROCEDURE Setup Phase Program & Verify Phase Exit Phase Start Read Status Reg. Read Status Reg. V PP applied Block Unlocked No (SR[0]=1) No (SR[7]=0) Data Stream Ready? BEFP Exited? Yes (SR[0]=0) Write 80h @ 1 st Word Address Write D0h @ 1 st Word Address BEFP Setup delay Full Status Check Procedure W rite Data @ 1 st W ord Address Program Complete Increment Count: X = X+1 Read Status Reg. BEFP Setup Done? Yes (SR[7]=1) Initialize Count: X=0 N Check X = 32? Yes (SR[7]=0) Y Read Status Reg. No (SR[7]=1) No (SR[0]=1) Check V PP , Lock errors (SR[3,1]) Program Done? Yes (SR[0]=0) Exit N Last Data? Y W rite 0xFFFF, Address Not within Current Block BEFP Setup Operation W rite Unlock Block V PPH applied to VPP W rite (Note 1) BEFP Setup Data = 0x80 @ 1 st W ord Address W rite BEFP Confirm Data = 0x80 @ 1 st Word Address 1 Read Status Register Data = Status Register Data Address = 1 st Word Addr. Standby BEFP Setup Done? Standby Error Condition Check Comments Check SR[7]: 0 = BEFP Ready 1 = BEFP Not Ready If SR [7] is set, check: SR[3] set = V PP Error SR[1] set = Locked Block BEFP Exit BEFP Program & Verify Bus State Bus State Operation Comments Bus State Operation Comm ents Read Status Register Data = Status Register Data Address = 1 st Word Addr. Read Status Register Data = Status Register Data Address = 1st W ord Addr. Standby Data Stream Ready? Check SR [0]: 0 = Ready for Data 1 = Not Ready for Data Standby Check Exit Status Standby Initialize Count X=0 Repeat for subsequent blocks ; Write (note 2) Load Buffer Data = Data to Program Address = 1 st Word Addr. After BEFP exit, a full Status Register check can determine if any program error occurred ; Standby Increment Count X = X+1 See full Status Register check procedure in the Word Program flowchart. X = 32? Yes = Read SR[0] No = Load Next Data Word Write 0xFF to enter Read Array state . Standby Buffer Full? Read Status Register Data = Status Reg. Data Address = 1 st Word Addr. Standby Program Done? Check SR [0]: 0 = Program Done 1 = Program in Progress Standby Last Data? Write Check SR[7]: 0 = Exit Not Completed 1 = Exit Completed No = Fill buffer again Yes = Exit Exit Prog & Data = 0xFFFF @ address Verify Phase not in current block NOTES: 1. First-word address to be programmed within the target block must be aligned on a write -buffer boundary . 2. Write-buffer contents are programmed sequentially to the flash array starting at the first word address (WSM internally increments addressing ). April 2005 88 Intel StrataFlash(R) Embedded Memory (P30) Order Number: 306666, Revision: 001 Datasheet 1-Gbit P30 Family Figure 44. Block Erase Flowchart BLOCK ERASE PROCEDURE Bus Operation Command Start Write Write 0x20, (Block Erase) Block Address Write Write 0xD0, (Erase Confirm) Block Address Suspend Erase Loop Read Status Register No 0 SR[7] = Suspend Erase 1 Block Erase Setup Comments Data = 0x20 Addr = Block to be erased (BA) Erase Data = 0xD0 Confirm Addr = Block to be erased (BA) Read None Status Register data. Idle None Check SR[7]: 1 = WSM ready 0 = WSM busy Yes Repeat for subsequent block erasures. Full Status register check can be done after each block erase or after a sequence of block erasures. Full Erase Status Check (if desired) Write 0xFF after the last operation to enter read array mode. Block Erase Complete FULL ERASE STATUS CHECK PROCEDURE Read Status Register SR[3] = Bus Command Operation VPP Range Error 1 0 SR[4,5] = 1,1 Command Sequence Error Idle None Check SR[3]: 1 = VPP Range Error Idle None Check SR[4,5]: Both 1 = Command Sequence Error Idle None Check SR[5]: 1 = Block Erase Error Idle None Check SR[1]: 1 = Attempted erase of locked block; erase aborted. 0 SR[5] = 1 Block Erase Error 1 Block Locked Error 0 SR[1] = Comments Only the Clear Status Register command clears SR[1, 3, 4, 5]. If an error is detected, clear the Status register before attempting an erase retry or other error recovery. 0 Block Erase Successful Datasheet Intel StrataFlash(R) Embedded Memory (P30) Order Number: 306666, Revision: 001 April 2005 89 1-Gbit P30 Family Figure 45. Erase Suspend/Resume Flowchart ERASE SUSPEND / RESUME PROCEDURE Start Write 0x70, Same Partition Write 0xB0, Any Address Bus Command Operation (Read Status) (Erase Suspend) Read Status Register SR[7] = SR[6] = Read Array Data Read or Program? No Read Status Write Erase Suspend Read None Status Register data. Addr = Same partition Idle None Check SR[7]: 1 = WSM ready 0 = WSM busy Idle None Check SR[6]: 1 = Erase suspended 0 = Erase completed Erase Completed 0 Write 1 Read Write 0 1 Program Read or Write Program Loop Write Done (Erase Resume) (Read Status) April 2005 90 Write 0x70, Same Partition Data = 0x70 Addr = Any partition address Data = 0xB0 Addr = Same partition address as above Read Array Data = 0xFF or 0x40 Addr = Any address within the or Program suspended partition None Read array or program data from/to block other than the one being erased Program Data = 0xD0 Resume Addr = Any address If the suspended partition was placed in Read Array mode or a Program Loop: Write 0xD0, Any Address Erase Resumed Comments Write Read Status Register Return partition to Status mode: Data = 0x70 Addr = Same partition Write 0xFF, (Read Array) Erased Partition Read Array Data Intel StrataFlash(R) Embedded Memory (P30) Order Number: 306666, Revision: 001 Datasheet 1-Gbit P30 Family Figure 46. Block Lock Operations Flowchart LOCKING OPERATIONS PROCEDURE Start Bus Command Operation Write 0x60, Block Address (Lock Setup) Write either 0x01/0xD0/0x2F, (Lock Confirm) Block Address Optional Write 0x90 (Read Device ID) Write Lock Setup Data = 0x60 Addr = Block to lock/unlock/lock-down Lock, Data = 0x01 (Block Lock) Unlock, or 0xD0 (Block Unlock) Lock-Down 0x2F (Lock-Down Block) Confirm Addr = Block to lock/unlock/lock-down Write Read Data = 0x90 (Optional) Device ID Addr = Block address + offset 2 Read Block Lock Block Lock status data (Optional) Status Addr = Block address + offset 2 Read Block Lock Status Locking Change? Write Comments No Yes Idle None Confirm locking change on D[1,0]. Write Read Array Data = 0xFF Addr = Block address Write 0xFF (Read Array) Partition Address Lock Change Complete Datasheet Intel StrataFlash(R) Embedded Memory (P30) Order Number: 306666, Revision: 001 April 2005 91 1-Gbit P30 Family Figure 47. Protection Register Programming Flowchart PROTECTION REGISTER PROGRAMMING PROCEDURE Bus Command Operation Start Write 0xC0, PR Address Program Data = 0xC0 PR Setup Addr = First Location to Program Write Protection Data = Data to Program Program Addr = Location to Program (Confirm Data) Read Status Register SR[7] = Write (Program Setup) Write PR Address & Data Comments Read None Status Register Data. Idle None Check SR[7]: 1 = WSM Ready 0 = WSM Busy Program Protection Register operation addresses must be within the Protection Register address space. Addresses outside this space will return an error. 0 1 Repeat for subsequent programming operations. Full Status Check (if desired) Full Status Register check can be done after each program, or after a sequence of program operations. Write 0xFF after the last operation to set Read Array state. Program Complete FULL STATUS CHECK PROCEDURE Read Status Register Data SR[3] = Bus Command Operation 1 1 Program Error 0 SR[1] = Idle None Check SR[3]: 1 =VPP Range Error Idle None Check SR[4]: 1 =Programming Error Idle None Check SR[1]: 1 =Block locked; operation aborted VPP Range Error 0 SR[4] = Comments Only the Clear Staus Register command clears SR[1, 3, 4]. 1 Register Locked; Program Aborted If an error is detected, clear the Status register before attempting a program retry or other error recovery. 0 Program Successful April 2005 92 Intel StrataFlash(R) Embedded Memory (P30) Order Number: 306666, Revision: 001 Datasheet 1-Gbit P30 Family Appendix C Common Flash Interface The Common Flash Interface (CFI) is part of an overall specification for multiple command-set and control-interface descriptions. This appendix describes the database structure containing the data returned by a read operation after issuing the CFI Query command (see Section 9.2, "Device Commands" on page 50). System software can parse this database structure to obtain information about the flash device, such as block size, density, bus width, and electrical specifications. The system software will then know which command set(s) to use to properly perform flash writes, block erases, reads and otherwise control the flash device. C.1 Query Structure Output The Query database allows system software to obtain information for controlling the flash device. This section describes the device's CFI-compliant interface that allows access to Query data. Query data are presented on the lowest-order data outputs (DQ7-0) only. The numerical offset value is the address relative to the maximum bus width supported by the device. On this family of devices, the Query table device starting address is a 10h, which is a word address for x16 devices. For a word-wide (x16) device, the first two Query-structure bytes, ASCII "Q" and "R," appear on the low byte at word addresses 10h and 11h. This CFI-compliant device outputs 00h data on upper bytes. The device outputs ASCII "Q" in the low byte (DQ7-0) and 00h in the high byte (DQ15-8). At Query addresses containing two or more bytes of information, the least significant data byte is presented at the lower address, and the most significant data byte is presented at the higher address. In all of the following tables, addresses and data are represented in hexadecimal notation, so the "h" suffix has been dropped. In addition, since the upper byte of word-wide devices is always "00h," the leading "00" has been dropped from the table notation and only the lower byte value is shown. Any x16 device outputs can be assumed to have 00h on the upper byte in this mode. Table 31. Summary of Query Structure Output as a Function of Device and Mode Device Device Addresses Table 32. Datasheet Hex Offset Hex Code ASCII Value 00010: 51 "Q" 00011: 52 "R" 00012: 59 "Y" Example of Query Structure Output of x16- Devices Intel StrataFlash(R) Embedded Memory (P30) Order Number: 306666, Revision: 001 April 2005 93 1-Gbit P30 Family Offset AX-A0 00010h 00011h 00012h 00013h 00014h 00015h 00016h 00017h 00018h ... C.2 Word Addressing: Hex Code D15-D0 0051 0052 0059 P_IDLO P_IDHI PLO PHI A_IDLO A_IDHI ... Value "Q" "R" "Y" PrVendor ID # PrVendor TblAdr AltVendor ID # ... Offset AX-A0 00010h 00011h 00012h 00013h 00014h 00015h 00016h 00017h 00018h ... Byte Addressing: Hex Code D7-D0 51 52 59 P_IDLO P_IDLO P_IDHI ... Value "Q" "R" "Y" PrVendor ID # ID # ... Query Structure Overview The Query command causes the flash component to display the Common Flash Interface (CFI) Query structure or "database." The structure sub-sections and address locations are summarized below. Table 33. Query Structure Offset 00001-Fh 00010h 0001Bh 00027h (3) P Description(1) Reserved Reserved for vendor-specific information CFI query identification string Command set ID and vendor data offset System interface information Device timing & voltage information Device geometry definition Flash device layout Primary Intel-specific Extended Query Table Vendor-defined additional information specific Sub-Section Name Notes: 1. Refer to the Query Structure Output section and offset 28h for the detailed definition of offset address as a function of device bus width and mode. 2. BA = Block Address beginning location (i.e., 08000h is block 1's beginning location when the block size is 16-KWord). 3. Offset 15 defines "P" which points to the Primary Intel-specific Extended Query Table. April 2005 94 Intel StrataFlash(R) Embedded Memory (P30) Order Number: 306666, Revision: 001 Datasheet 1-Gbit P30 Family C.3 CFI Query Identification String The Identification String provides verification that the component supports the Common Flash Interface specification. It also indicates the specification version and supported vendor-specified command set(s). Table 34. Table 35. Datasheet CFI Identification Offset Length Description 10h 3 Query-unique ASCII string "QRY" 13h 2 15h 2 Primary vendor command set and control interface ID code. 16-bit ID code for vendor-specified algorithms Extended Query Table primary algorithm address 17h 2 19h 2 Alternate vendor command set and control interface ID code. 0000h means no second vendor-specified algorithm exists Secondary algorithm Extended Query Table address. 0000h means none exists Hex Add. Code Value 10: --51 "Q" 11: --52 "R" 12: --59 "Y" 13: --01 14: --00 15: --0A 16: --01 17: --00 18: --00 19: --00 1A: --00 System Interface Information Offset Length 1Bh 1 1Ch 1 1Dh 1 1Eh 1 1Fh 20h 21h 22h 23h 24h 25h 26h 1 1 1 1 1 1 1 1 Description Hex Add. Code 1B: --17 VCC logic supply minimum program/erase voltage bits 0-3 BCD 100 mV bits 4-7 BCD volts 1C: VCC logic supply maximum program/erase voltage bits 0-3 BCD 100 mV bits 4-7 BCD volts 1D: VPP [programming] supply minimum program/erase voltage bits 0-3 BCD 100 mV bits 4-7 HEX volts 1E: VPP [programming] supply maximum program/erase voltage bits 0-3 BCD 100 mV bits 4-7 HEX volts n 1F: "n" such that typical single word program time-out = 2 -sec n 20: "n" such that typical max. buffer write time-out = 2 -sec n 21: "n" such that typical block erase time-out = 2 m-sec n 22: "n" such that typical full chip erase time-out = 2 m-sec n "n" such that maximum word program time-out = 2 times typical 23: n 24: "n" such that maximum buffer write time-out = 2 times typical n 25: "n" such that maximum block erase time-out = 2 times typical n 26: "n" such that maximum chip erase time-out = 2 times typical Intel StrataFlash(R) Embedded Memory (P30) Order Number: 306666, Revision: 001 Value 1.7V --20 2.0V --85 8.5V --95 9.5V --08 256s --09 512s --0A 1s --00 NA --01 512s --01 1024s --02 4s --00 NA April 2005 95 1-Gbit P30 Family C.4 Device Geometry Definition Table 36. Device Geometry Definition Offset 27h 28h Length Description n "n" such that device size = 2 in number of bytes 1 Flash device interface code assignment: "n" such that n+1 specifies the bit field that represents the flash device width capabilities as described in the table: 2 2Ah 2 2Ch 1 2Dh 31h 35h 5 4 3 2 1 0 -- -- x64 x32 x16 x8 15 14 13 12 11 10 9 8 Number of erase block regions (x) within device: 1. x = 0 means no erase blocking; the device erases in bulk 2. x specifies the number of device regions with one or more contiguous same-size erase blocks. 3. Symmetrically blocked partitions have one blocking region Erase Block Region 1 Information bits 0-15 = y, y+1 = number of identical-size erase blocks bits 16-31 = z, region erase block(s) size are z x 256 bytes 4 Erase Block Region 2 Information bits 0-15 = y, y+1 = number of identical-size erase blocks bits 16-31 = z, region erase block(s) size are z x 256 bytes 4 Reserved for future erase block region information A ddress April 2005 96 6 -- -- -- -- -- -- -- -- -- n "n" such that maximum number of bytes in write buffer = 2 4 27: 28: 29: 2A: 2B: 2C: 2D: 2E: 2F: 30: 31: 32: 33: 34: 35: 36: 37: 38: 7 -- 64-Mbit -B -T --17 --17 --01 --01 --00 --00 --06 --06 --00 --00 --02 --02 --03 --3E --00 --00 --80 --00 --00 --02 --3E --03 --00 --00 --00 --80 --02 --00 --00 --00 --00 --00 --00 --00 --00 --00 128-Mbit -B -T --18 --18 --01 --01 --00 --00 --06 --06 --00 --00 --02 --02 --03 --7E --00 --00 --80 --00 --00 --02 --7E --03 --00 --00 --00 --80 --02 --00 --00 --00 --00 --00 --00 --00 --00 --00 Intel StrataFlash(R) Embedded Memory (P30) Order Number: 306666, Revision: 001 Code 27: See table below 28: --01 x16 29: 2A: 2B: 2C: --00 --06 --00 64 See table below 2D: 2E: 2F: 30: 31: 32: 33: 34: 35: 36: 37: 38: See table below See table below See table below 256-Mbit -B -T --19 --19 --01 --01 --00 --00 --06 --06 --00 --00 --02 --02 --03 --FE --00 --00 --80 --00 --00 --02 --FE --03 --00 --00 --00 --80 --02 --00 --00 --00 --00 --00 --00 --00 --00 --00 Datasheet 1-Gbit P30 Family C.5 Intel-Specific Extended Query Table Table 37. Primary Vendor-Specific Extended Query Offset(1) Length Description P = 10Ah (Optional flash features and commands) (P+0)h 3 Primary extended query table (P+1)h Unique ASCII string "PRI" (P+2)h (P+3)h 1 Major version number, ASCII (P+4)h 1 Minor version number, ASCII (P+5)h 4 Optional feature and command support (1=yes, 0=no) (P+6)h bits 10-31 are reserved; undefined bits are "0." If bit 31 is (P+7)h "1" then another 31 bit field of Optional features follows at (P+8)h the end of the bit-30 field. bit 0 Chip erase supported bit 1 Suspend erase supported bit 2 Suspend program supported bit 3 Legacy lock/unlock supported bit 4 Queued erase supported bit 5 Instant individual block locking supported bit 6 Protection bits supported bit 7 Pagemode read supported bit 8 Synchronous read supported bit 9 Simultaneous operations supported bit 10 Extended Flash Array Blocks supported bit 30 CFI Link(s) to follow bit 31 Another "Optional Features" field to follow (P+9)h 1 Supported functions after suspend: read Array, Status, Query Other supported operations are: bits 1-7 reserved; undefined bits are "0" bit 0 Program supported after erase suspend (P+A)h 2 Block status register mask (P+B)h bits 2-15 are Reserved; undefined bits are "0" bit 0 Block Lock-Bit Status register active bit 1 Block Lock-Dow n Bit Status active bit 4 EFA Block Lock-Bit Status register active bit 5 EFA Block Lock-Dow n Bit Status active V CC logic supply highest performance program/erase voltage (P+C)h 1 bits 0-3 BCD value in 100 mV bits 4-7 BCD value in volts V PP optimum program/erase supply voltage (P+D)h 1 bits 0-3 BCD value in 100 mV bits 4-7 HEX value in volts Datasheet Intel StrataFlash(R) Embedded Memory (P30) Order Number: 306666, Revision: 001 Hex Add. Code Value 10A --50 "P" 10B: --52 "R" 10C: --49 "I" 10D: --31 "1" 10E: --34 "4" 10F: --E6 110: --01 111: --00 112: --00 bit 0 = 0 No bit 1 = 1 Yes bit 2 = 1 Yes bit 3 = 0 No bit 4 = 0 No bit 5 = 1 Yes bit 6 = 1 Yes bit 7 = 1 Yes bit 8 = 1 Yes bit 9 = 0 No bit 10 = 0 No bit 30 = 0 No bit 31 = 0 No 113: --01 bit 0 114: 115: bit 0 bit 1 bit 4 bit 5 116: =1 --03 --00 =1 =1 =0 =0 --18 Yes Yes Yes No No 1.8V 117: --90 9.0V April 2005 97 1-Gbit P30 Family Table 38. Protection Register Information (1) Length Description Offset P = 10Ah (Optional flash features and commands) (P+E)h 1 Number of Protection register fields in JEDEC ID space. "00h," indicates that 256 protection fields are available (P+F)h 4 Protection Field 1: Protection Description (P+10)h This field describes user-available One Time Programmable (OTP) Protection register bytes. Some are pre-programmed (P+11)h (P+12)h with device-unique serial numbers. Others are user programmable. Bits 0-15 point to the Protection register Lock byte, the section's first byte. The following bytes are factory pre-programmed and user-programmable. Hex Add. Code 118: --02 Value 2 119: 11A: 11B: 11C: --80 --00 --03 --03 80h 00h 8 byte 8 byte 11D: 11E: 11F: 120: 121: 122: 123: 124: 125: 126: --89 --00 --00 --00 --00 --00 --00 --10 --00 89h 00h 00h 00h 0 0 0 16 0 16 bits 0-7 = Lock/bytes Jedec-plane physical low address bits 8-15 = Lock/bytes Jedec-plane physical high address n bits 16-23 = "n" such that 2 = factory pre-programmed bytes n bits 24-31 = "n" such that 2 = user programmable bytes (P+13)h (P+14)h (P+15)h (P+16)h (P+17)h (P+18)h (P+19)h (P+1A)h (P+1B)h (P+1C)h Table 39. 10 Protection Field 2: Protection Description Bits 0-31 point to the Protection register physical Lock-word address in the Jedec-plane. Following bytes are factory or user-programmable. bits 32-39 = "n" n = factory pgm'd groups (low byte) bits 40-47 = "n" n = factory pgm'd groups (high byte) bits 48-55 = "n" \ 2n = factory programmable bytes/group bits 56-63 = "n" n = user pgm'd groups (low byte) bits 64-71 = "n" n = user pgm'd groups (high byte) n bits 72-79 = "n" 2 = user programmable bytes/group Burst Read Information (1) Length Description Offset P = 10Ah (Optional flash features and commands) (P+1D)h 1 Page Mode Read capability n bits 0-7 = "n" such that 2 HEX value represents the number of read-page bytes. See offset 28h for device word width to determine page-mode data output width. 00h indicates no read page buffer. (P+1E)h 1 Number of synchronous mode read configuration fields that follow. 00h indicates no burst capability. (P+1F)h 1 Synchronous mode read capability configuration 1 Bits 3-7 = Reserved n+1 bits 0-2 "n" such that 2 HEX value represents the maximum number of continuous synchronous reads when the device is configured for its maximum word width. A value of 07h indicates that the device is capable of continuous linear bursts that will output data until the internal burst counter reaches the end of the device's burstable address space. This field's 3-bit value can be written directly to the Read Configuration Register bits 0-2 if the device is configured for its maximum word width. See offset 28h for word width to determine the burst data output width. (P+20)h 1 Synchronous mode read capability configuration 2 (P+21)h 1 Synchronous mode read capability configuration 3 (P+22)h 1 Synchronous mode read capability configuration 4 April 2005 98 --04 Intel StrataFlash(R) Embedded Memory (P30) Order Number: 306666, Revision: 001 Hex Add. Code Value 127: --03 8 byte 128: --04 4 129: --01 4 12A: 12B: 12C: --02 --03 --07 8 16 Cont Datasheet 1-Gbit P30 Family Table 40. Partition and Erase-block Region Information Offset (1) P= 10Ah Description Hex Bottom Top (Optional flash features and commands) Add. Code Value (P+23)h (P+23)h Number of device hardw are-partition regions w ithin the device. 12D: --00 0 x = 0: a single hardw are partition device (no fields follow ). x specifies the number of device partition regions containing one or more contiguous erase block regions. Datasheet Intel StrataFlash(R) Embedded Memory (P30) Order Number: 306666, Revision: 001 April 2005 99 1-Gbit P30 Family Appendix D Additional Information Order/Document Number Document/Tool 290667 Intel StrataFlash(R) Memory (J3) Datasheet 290737 Intel StrataFlash(R) Synchronous Memory (K3/K18) Datasheet 290701 Intel(R) Wireless Flash Memory (W18) Datasheet 290702 Intel(R) Wireless Flash Memory (W30) Datasheet 252802 Intel(R) Flash Memory Design for a Stacked Chip Scale Package (SCSP) 298161 Intel(R) Flash Memory Chip Scale Package User's Guide 253418 Intel(R) Wireless Communications and Computing Package User's Guide 296514 Intel(R) Small Outline Package Guide 297833 Intel(R) Flash Data Integrator (FDI) User's Guide 298136 Intel(R) Persistent Storage Manager User Guide 300783 Using Intel(R) Flash Memory: Asynchronous Page Mode and Synchronous Burst Mode 306667 Migration Guide for Intel StrataFlash(R) Memory (J3) to Intel StrataFlash(R) Embedded Memory (P30) Application Note 812 306668 Migration Guide for Spansion* S29GLxxxN to Intel StrataFlash(R) Embedded Memory (P30) Application Note 813 306669 Migration Guide for Intel StrataFlash(R) Synchronous Memory (K3/K18) to Intel StrataFlash(R) Embedded Memory (P30) Application Note 825 Notes: 1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International customers should contact their local Intel or distribution sales office. 2. Visit Intel's World Wide Web home page at http://www.intel.com for technical documentation and tools. 3. For the most current information on Intel(R) Flash Memory, visit our website at http://developer.intel.com/design/flash. April 2005 100 Intel StrataFlash(R) Embedded Memory (P30) Order Number: 306666, Revision: 001 Datasheet 1-Gbit P30 Family Appendix E Ordering Information for Discrete Products Figure 48. Decoder for Discrete Intel StrataFlash(R) Embedded Memory (P30) T E 2 8 F 6 4 0 P 3 0 B 8 5 Package Designator Access Speed TE = 56-Lead TSOP, leaded JS = 56-Lead TSOP, lead-free RC = 64-Ball Easy BGA, leaded PC = 64-Ball Easy BGA, lead-free 85 ns Parameter Location B = Bottom Parameter T = Top Parameter Product Line Designator 28F = Intel(R) Flash Memory Product Family Device Density P30 = Intel StrataFlash(R) Embedded Memory V CC = 1.7 - 2.0 V V CCQ = 1.7 - 3.6 V 640 = 64-Mbit 128 = 128-Mbit 256 = 256-Mbit Table 41. Datasheet Valid Combinations for Discrete Products 64-Mbit 128-Mbit 256-Mbit TE28F640P30B85 TE28F128P30B85 TE28F256P30B85 TE28F640P30T85 TE28F128P30T85 TE28F256P30T85 JS28F640P30B85 JS28F128P30B85 JS28F256P30B85 JS28F640P30T85 JS28F128P30T85 JS28F256P30T85 RC28F640P30B85 RC28F128P30B85 RC28F256P30B85 RC28F640P30T85 RC28F128P30T85 RC28F256P30T85 PC28F640P30B85 PC28F128P30B85 PC28F256P30B85 PC28F640P30T85 PC28F128P30T85 PC28F256P30T85 Intel StrataFlash(R) Embedded Memory (P30) Order Number: 306666, Revision: 001 April 2005 101 1-Gbit P30 Family Appendix F Ordering Information for SCSP Products Flash Family 3/4 Flash Family 1/2 Flash #4 Flash #3 Flash #2 Decoder for SCSP Intel StrataFlash(R) Embedded Memory (P30) Flash #1 Figure 49. R D 4 8 F 4 0 0 0 P 0 Z B Q 0 Package Designator Device Details RD = Intel(R) SCSP, leaded PF = Intel(R) SCSP, lead-free RC = 64-Ball Easy BGA, leaded PC = 64-Ball Easy BGA, lead-free 0 = Original version of the product (refer to the latest version of the datasheet for details) Group Designator Ballout Designator 48F = Flash Memory only Q = QUAD ballout 0 = Discrete ballout Flash Density 0 2 3 4 = = = = No die 64-Mbit 128-Mbit 256-Mbit Parameter, Mux Configuration B = Bottom Parameter, Non Mux T = Top Parameter, Non Mux Product Family I/O Voltage, CE# Configuration P = Intel StrataFlash(R) Embedded Memory 0 = No die Z = 3.0 V, Individual Chip Enable(s) V = 3.0 V, Virtual Chip Enable(s) Table 42. Valid Combinations for Stacked Products 64-Mbit 128-Mbit 256-Mbit 512-Mbit 1-Gbit RD48F2000P0ZBQ0 RD48F3000P0ZBQ0 RD48F4000P0ZBQ0 RD48F4400P0VBQ0 RD48F4444PPVBQ0 RD48F2000P0ZTQ0 RD48F3000P0ZTQ0 RD48F4000P0ZTQ0 RD48F4400P0VTQ0 RD48F4444PPVTQ0 PF48F2000P0ZBQ0 PF48F3000P0ZBQ0 PF48F4000P0ZBQ0 PF48F4400P0VBQ0 PF48F4444PPVBQ0 PF48F2000P0ZTQ0 PF48F3000P0ZTQ0 PF48F4000P0ZTQ0 PF48F4400P0VTQ0 PF48F4444PPVTQ0 RC48F4400P0VB00 RC48F4400P0VT00 PC48F4400P0VB00 PC48F4400P0VT00 April 2005 102 Intel StrataFlash(R) Embedded Memory (P30) Order Number: 306666, Revision: 001 Datasheet