Data Sheet Please read the Important Notice and Warnings at the end of this document Revision 2.3
www.infineon.com 2017-09-12
ICE2QR1765G
Quasi-Resonant, 650V CoolSET™ in DS0-12 Package
Product Highlights
Active Burst Mode to reach the lowest standby power requirement <100 mW @ no
load
Quasi resonant operation
Digital frequency reduction for better overall system efficiency
650 V avalanche rugged CoolMOS™ with startup cell
Pb-free lead plating, halogen free mold compound, RoHS compliant
PG-DSO-12
Features
650V avalanche rugged CoolMOSTM with built-in startup cell
Quasi resonant operation till very low load
Active burst mode operation for low standby input power (<
0.1W)
Digital frequency reduction with decreasing load for reduced
switching loss
Built-in digital soft-start
Foldback point correction, cycle-by-cycle peak current
limitation and maximum on time limitation
Auto restart mode for VCC over-voltage protection, under-
voltage protection, over-load protection and over-
temperature protection
Latch-off mode for adjustable output over-voltage protection
and transformer short-winding protection
Applications
Adapter/Charger, Blue Ray/DVD player, Set-top Box, Digital
Photo Frame
Auxiliary power supply of Server, PC, Printer, TV, Home
theater/Audio System, White Goods, etc.
Description
The CoolSETTM-Q1 series (ICE2QRxx65G) is the first generation of
quasi-resonant integrated power ICs. It is optimized for off-line
switch mode power supply applications such as LCD monitor, DVD
R/W, DVD Combo, Blue-ray DVD, set top box, etc. Operating the
MOSFET switch in quasi-resonant mode, lower EMI, higher
efficiency and lower voltage stress on secondary diodes are
expected for the SMPS. Based on the BiCMOS technology, the
CoolSETTM-Q1 series has a wide operation range (up to 25 V) of IC
power supply and lower power consumption. It also offers many
advantages such as a quasi-resonant operation till very low load
increasing the average system efficiency compared to the other
conventional solutions; the Active Burst Mode operation enables
an ultra-low power consumption at standby mode with small and
a controllable output voltage ripple.
85 ~ 265 VAC
Snubber
Cbus
Dr1~Dr4
RCS
TL431
Optocoupler
Rb1
Rb2
Rc1
Cc1 Cc2
Rovs2
Rovs1
CVCC DVCC
DO
CO
LfCfVO
CPS
Startup Cell
CoolSETTM-Q1
CoolMOSTM
WpWs
Wa
RVCC
CZC RZC2 RZC1
Drain
Zero Crossing Block
Power Management
Cycle-by-Cycle
current limitation
Active Burst Mode
PWM controller
Current Mode Control
Protections
VCC
CS
Control Unit
ZC
FB
GND
Figure 1 Typical application
Type
Package
Marking
VDS
RDSon1
230VAC ±15%2
85-265 VAC2
ICE2QR1765G
PG-DSO-12
ICE2QR1765G
650 V
1.70 Ω
49 W
28 W
1
typ at T=25°C
2
Calculated maximum input power rating at Ta=50°C, Ti=125°C and without copper area pin as heat sink.
Data Sheet 2 Revision 2.3
2017-09-12
Quasi-Resonant, 650V CoolSET™ in DS0-12 Package
Table of contents
Table of contents
Table of contents ............................................................................................................................ 2
1 Pin Configuration and Functionality ................................................................................ 3
2 Representative Block Diagram ........................................................................................ 4
3 Functional Description ................................................................................................... 5
3.1 Introduction ............................................................................................................................................. 5
3.2 Soft-start .................................................................................................................................................. 5
3.3 Normal Operation ................................................................................................................................... 6
3.3.1 Digital Frequency Reduction ............................................................................................................. 6
3.3.1.1 Up/down counter .......................................................................................................................... 6
3.3.1.2 Zero crossing (ZC counter) ........................................................................................................... 7
3.3.2 Ringing suppression time .................................................................................................................. 8
3.3.2.1 Switch on determination .............................................................................................................. 8
3.3.3 Switch off determination ................................................................................................................... 8
3.4 Current Limitation ................................................................................................................................... 9
3.4.1 Foldback Point Correction ................................................................................................................. 9
3.5 Active Burst Mode .................................................................................................................................. 10
3.5.1 Entering Active Burst Mode Operation ............................................................................................ 10
3.5.2 During Active Burst Mode Operation ............................................................................................... 10
3.5.3 Leaving Active Burst Mode Operation ............................................................................................. 11
3.6 Protection Functions ............................................................................................................................. 12
4 Electrical Characteristics ............................................................................................... 13
4.1 Absolute Maximum Ratings .................................................................................................................. 13
4.2 Operating Range .................................................................................................................................... 14
4.3 Characteristics ....................................................................................................................................... 14
4.3.1 Supply Section ................................................................................................................................. 14
4.3.2 Internal Voltage Reference .............................................................................................................. 15
4.3.3 PWM Section ..................................................................................................................................... 15
4.3.4 Current Sense ................................................................................................................................... 15
4.3.5 Soft Start ........................................................................................................................................... 15
4.3.6 Foldback Point Correction ............................................................................................................... 16
4.3.7 Digital Zero Crossing ........................................................................................................................ 16
4.3.8 Active Burst Mode ............................................................................................................................ 17
4.3.9 Protection ......................................................................................................................................... 17
4.3.10 CoolMOS™ Section ........................................................................................................................... 18
5 CoolMOS™ Performance Characteristics .......................................................................... 19
6 Input Power Curve ........................................................................................................ 21
7 Outline Dimension ........................................................................................................ 22
8 Marking ....................................................................................................................... 23
Revision History ............................................................................................................................ 23
Data Sheet 3 Revision 2.3
2017-09-12
Quasi-Resonant, 650V CoolSET™ in DS0-12 Package
Pin Configuration and Functionality
1 Pin Configuration and Functionality
Table 1 Pin definitions and functions
Pin
Symbol
Function
1
ZC
ZC (Zero Crossing)
At this pin, the voltage from the auxiliary winding after a time delay circuit is applied.
Internally, this pin is connected to the zero-crossing detector for switch-on determination.
Additionally, the output overvoltage detection is realized by comparing the voltage VZC with
an internal preset threshold.
2
FB
FB (Feedback)
Normally an external capacitor is connected to this pin for a smooth voltage VFB.
Internally this pin is connected to the PWM signal generator block for switch-off
determination (together with the current sensing signal), to the digital signal processing
block for the frequency reduction with decreasing load during normal operation, and to
the Active Burst Mode controller block for entering Active Burst Mode operation
determination and burst ratio control during Active Burst Mode operation. Additionally,
the open-loop / over-load protection is implemented by monitoring the voltage at this
pin.
3, 9, 10
N.C.
Not Connected
4
CS
CS (Current Sense/650V CoolMOS™ Source)
This pin is connected to the shunt resistor for the primary current sensing externally and to
the PWM signal generator block for switch-off determination (together with the feedback
voltage) internally. Moreover, short-winding protection is realized by monitoring the
voltage VCS during on-time of the main power switch.
5, 6, 7, 8
Drain
650V CoolMOS™ Drain
Pin Drain is the connection to the Drain of the integrated CoolMOS™.
11
VCC
VCC (Power supply)
VCC pin is the positive supply of the IC. The operating range is between VVCCoff and VVCCOVP.
12
GND
GND (Ground)
This is the common ground of the controller.
10
11
12
9
VCCFB
N.C.
CS
ZC
N.C.
GND
N.C.
Drain
Drain
8
7
3
2
1
4
Drain
Drain
5
6
Figure 2 Pin configuration PG-DSO-12(top view)
Data Sheet 4 Revision 2.3
2017-09-12
Quasi-Resonant, 650V CoolSET™ in DS0-12 Package
Representative Block Diagram
2 Representative Block Diagram
Figure 3 Representative Block Diagram
Data Sheet 5 Revision 2.3
2017-09-12
Quasi-Resonant, 650V CoolSET™ in DS0-12 Package
Functional Description
3 Functional Description
3.1 Introduction
In ICE2QR1765G a startup cell is integrated into the CoolMOSTM. As shown in Figure 3, the start cell consists of a
high voltage device and a controller, whereby the high voltage device is controlled by the controller. The startup
cell provides a pre-charging of the VCC capacitor till VCC voltage reaches the VCC turned-on threshold VVCCon and
the IC begins to operate.
Once the mains input voltage is applied, a rectified voltage shows across the capacitor Cbus. The high voltage
device provides a current to charge the VCC capacitor CVCC. Before the VCC voltage reaches a certain value, the
amplitude of the current through the high voltage device is only determined by its channel resistance and can
be as high as several mA. After the VCC voltage is high enough, the controller controls the high voltage device so
that a constant current around 1 mA is provided to charge the VCC capacitor further, until the VCC voltage
exceeds the turned-on threshold VVCCon. As shown as the time phase I in Figure 4, the VCC voltage increase near
linearly and the charging speed is independent of the mains voltage level.
VVCCon
VVCC
VVCCoff
t1 t
t2
I II III
Figure 4 VCC voltage at start up
The time taking for the VCC pre-charging can then be approximately calculated as:
(1)
where IVCCcharge2 is the charging current from the startup cell which is 1.05 mA, typically.
When the VCC voltage exceeds the VCC turned-on threshold VVCCon at time t1, the startup cell is switched off and
the IC begins to operate with soft-start. Due to power consumption of the IC and the fact that there is still no
energy from the auxiliary winding to charge the VCC capacitor before the output voltage is built up, the VCC
voltage drops (Phase II). Once the output voltage is high enough, the VCC capacitor receives the energy from
the auxiliary winding from the time point t2 onward. The VCC then will reach a constant value depending on
output load.
3.2 Soft-start
As shown in Figure 5, at the time ton, the IC begins to operate with a soft-start. By this soft-start the switching
stresses for the switch, diode and transformer are minimized. The soft-start implemented in CoolSET™ Q1 is a
digital time-based function. The preset soft-start time is tSS (12 ms) with 4 steps. If not limited by other
functions, the peak voltage on CS pin will increase step by step from 0.32 V to 1 V finally.
Data Sheet 6 Revision 2.3
2017-09-12
Quasi-Resonant, 650V CoolSET™ in DS0-12 Package
Functional Description
ton 3 6 9 12
0.32
0.49
0.66
0.83
1.00
Vcs_sst
(V)
Time(ms)
Figure 5 Maximum current sense voltage during soft start
3.3 Normal Operation
The PWM controller during normal operation consists of a digital signal processing circuit including an
up/down counter, a zero-crossing counter (ZC counter) and a comparator, and an analog circuit including a
current measurement unit and a comparator. The switch-on and -off time points are each determined by the
digital circuit and the analog circuit, respectively. As input information for the switch-on determination, the
zero-crossing input signal and the value of the up/down counter are needed, while the feedback signal VFB and
the current sensing signal VCS are necessary for the switch-off determination. Details about the full operation of
the PWM controller in normal operation are illustrated in the following paragraphs.
3.3.1 Digital Frequency Reduction
As mentioned above, the digital signal processing circuit consists of an up/down counter, a ZC counter and a
comparator. These three parts are keys to implement digital frequency reduction with decreasing load. In
addition, a ringing suppression time controller is implemented to avoid mis-triggering by the high frequency
oscillation, when the output voltage is very low under conditions such as soft start period or output short
circuit. Functionality of these parts is described as in the following.
3.3.1.1 Up/down counter
The up/down counter stores the number of the zero crossing where the main power switch is switched on after
demagnetization of the transformer. This value is fixed according to the feedback voltage, VFB, which contains
information about the output power. Indeed, in a typical peak current mode control, a high output power
results in a high feedback voltage, and a low output power leads to a low regulation voltage. Hence, according
to VFB, the value in the up/down counter is changed to vary the power MOSFET off-time according to the
output power. In the following, the variation of the up/down counter value according to the feedback voltage is
explained.
The feedback voltage VFB is internally compared with three threshold voltages VFBZL, VFBZH and VFBR1, at each clock
period of 48 ms. The up/down counter counts then upward, keep unchanged or count downward, as shown in
Table 2.
Data Sheet 7 Revision 2.3
2017-09-12
Quasi-Resonant, 650V CoolSET™ in DS0-12 Package
Functional Description
Table 2
VFB
up/down counter action
Always lower than VFBZL
Count upwards till 7
Once higher than VFBZL, but always lower than VFBZH
Stop counting, no value changing
Once higher than VFBZH, but always lower than VFBR1
Count downwards till 1
Once higher than VFBR1
Set up/down counter to 1
In the CoolSETTM-Q1, the number of zero crossing is limited to 7. Therefore, the counter varies between 1 and 7,
and any attempt beyond this range is ignored. When VFB exceeds VFBR1 voltage, the up/down counter is reset to
1, in order to allow the system to react rapidly to a sudden load increase. The up/down counter value is also
reset to 1 at the start-up time, to ensure an efficient maximum load start up. Figure 6 shows some examples on
how up/down counter is changed according to the feedback voltage over time.
The use of two different thresholds VFBZL and VFBZH to count upward or downward is to prevent frequency
jittering when the feedback voltage is close to the threshold point. However, for a stable operation, these two
thresholds must not be affected by the foldback current limitation (see 3.4.1), which limits the VCS voltage.
Hence, to prevent such situation, the threshold voltages, VFBZL and VFBZH, are changed internally depending on
the line voltage levels.
1Case 3
Case 2
Case 1
Up/down
counter
n
n+1
n+2
n+2
n+2
n+2
n+1
n
n-1
4 5 6 6 6 6 5 4 3
1
1
2 3 4 4 4 4 3 2 1
7 7 7 7 7 7 6 5 4
t
t
VFB
VFBR1
VFBZH
VFBZL
clock T=48ms
1
Figure 6 Up/down counter operation
3.3.1.2 Zero crossing (ZC counter)
In the system, the voltage from the auxiliary winding is applied to the zero-crossing pin through a RC network,
which provides a time delay to the voltage from the auxiliary winding. Internally this pin is connected to a
clamping network, a zero-crossing detector, an output overvoltage detector and a ringing suppression time
controller.
During on-state of the power switch a negative voltage applies to the ZC pin. Through the internal clamping
network, the voltage at the pin is clamped to certain level.
Data Sheet 8 Revision 2.3
2017-09-12
Quasi-Resonant, 650V CoolSET™ in DS0-12 Package
Functional Description
The ZC counter has a minimum value of 0 and maximum value of 7. After the internal MOSFET is turned off,
every time when the falling voltage ramp of on ZC pin crosses the VZCCT (100 mV) threshold, a zero crossing is
detected and ZC counter will increase by 1. It is reset every time after the DRIVER output is changed to high.
The voltage VZC is also used for the output overvoltage protection. Once the voltage at this pin is higher than the
threshold VZCOVP during off-time of the main switch, the IC is latched off after a fixed blanking time.
To achieve the switch-on at voltage valley, the voltage from the auxiliary winding is fed to a time delay network
(the RC network consists of DZC, RZC1, R ZC2 and C ZC as shown in Figure 1) before it is applied to the zero-crossing
detector through the ZC pin. The needed time delay to the main oscillation signal Δt should be approximately
one fourth of the oscillation period, TOSC (by transformer primary inductor and drain-source capacitor) minus
the propagation delay from the detected zero-crossing to the switch-on of the main switch tdelay.
(2)
This time delay should be matched by adjusting the time constant of the RC network which is calculated as:
(3)
3.3.2 Ringing suppression time
After MOSFET is turned off, there will be some oscillation on VDS, which will also appear on the voltage on ZC
pin. To avoid mis-triggering by such oscillations to turn on the MOSFET, a ringing suppression timer is
implemented. This suppression time is depended on the voltage VZC. If the voltage VZC is lower than the
threshold VZCRS, a longer preset time tZCRS2 is applied. However, if the voltage VZC is higher than the threshold, a
shorter time tZCRS1 is set.
3.3.2.1 Switch on determination
After the gate drive goes to low, it cannot be changed to high during ring suppression time.
After ring suppression time, the gate drive can be turned on when the ZC counter value is higher or equal to
up/down counter value.
However, it is also possible that the oscillation between primary inductor and drain-source capacitor damps
very fast and IC cannot detect enough zero crossings and ZC counter value will not be high enough to turn on
the gate drive. In this case, a maximum off time is implemented. After gate drive has been remained off for the
period of TOffMax, the gate drive will be turned on again regardless of the counter values and VZC. This function
can effectively prevent the switching frequency from going lower than 20 kHz. Otherwise it will cause audible
noise during start up.
3.3.3 Switch off determination
In the converter system, the primary current is sensed by an external shunt resistor, which is connected
between low-side terminal of the main power switch and the common ground. The sensed voltage across the
shunt resistor VCS is applied to an internal current measurement unit, and its output voltage V1 is compared
with the regulation voltage VFB. Once the voltage V1 exceeds the voltage VFB, the output flip-flop is reset. As a
result, the main power switch is switched off. The relationship between the V1 and the VCS is described by:
(4)
Data Sheet 9 Revision 2.3
2017-09-12
Quasi-Resonant, 650V CoolSET™ in DS0-12 Package
Functional Description
To avoid mis-triggering caused by the voltage spike across the shunt resistor at the turn on of the main power
switch, a leading edge blanking time, tLEB, is applied to the output of the comparator. In other words, once the
gate drive is turned on, the minimum on time of the gate drive is the leading edge blanking time.
In addition, there is a maximum on time, tOnMax, limitation implemented in the IC. Once the gate drive has been
in high state longer than the maximum on time, it will be turned off to prevent the switching frequency from
going too low because of long on time.
3.4 Current Limitation
There is a cycle by cycle current limitation realized by the current limit comparator to provide an over-current
detection. The source current of the MOSFET is sensed via a sense resistor RCS. By means of RCS the source
current is transformed to a sense voltage VCS which is fed into the pin CS. If the voltage VCS exceeds an internal
voltage limit, adjusted according to the Mains voltage, the comparator immediately turns off the gate drive.
To prevent the Current Limitation process from distortions caused by leading edge spikes, a Leading Edge
Blanking time (tLEB) is integrated in the current sensing path.
A further comparator is implemented to detect dangerous current levels (VCSSW) which could occur if one or
more transformer windings are shorted or if the secondary diode is shorted. To avoid an accidental latch off, a
spike blanking time of tCSSW is integrated in the output path of the comparator.
3.4.1 Foldback Point Correction
When the main bus voltage increases, the switch on time becomes shorter and therefore the operating
frequency is also increased. As a result, for a constant primary current limit, the maximum possible output
power is increased which is beyond the converter design limit.
To avoid such a situation, the internal foldback point correction circuit varies the VCS voltage limit according to
the bus voltage. This means the VCS will be decreased when the bus voltage increases. To keep a constant
maximum input power of the converter, the required maximum VCS versus various input bus voltage can be
calculated, which is shown in Figure 7.
Figure 7 Variation of the VCS limit voltage according to the IZC current
According to the typical application circuit, when MOSFET is turned on, a negative voltage proportional to bus
voltage will be coupled to auxiliary winding. Inside CoolSET™ Q1, an internal circuit will clamp the voltage on
ZC pin to nearly 0 V. As a result, the current flowing out from ZC pin can be calculated as
Data Sheet 10 Revision 2.3
2017-09-12
Quasi-Resonant, 650V CoolSET™ in DS0-12 Package
Functional Description
(5)
When this current is higher than IZC_FS, the amount of current exceeding this threshold is used to generate an
offset to decrease the maximum limit on VCS. Since the ideal curve shown in Figure 7 is a nonlinear one, a digital
block in CoolSETTM Q1 is implemented to get a better control of maximum output power. Additional advantage
to use digital circuit is the production tolerance is smaller compared to analog solutions. The typical maximum
limit on VCS versus the ZC current is shown in Figure 8.
Figure 8 VCS_max versus IZC
3.5 Active Burst Mode
At light load condition, the IC enters Active Burst Mode operation to minimize the power consumption. Details
about Active Burst Mode operation are explained in the following paragraphs.
3.5.1 Entering Active Burst Mode Operation
For determination of entering Active Burst Mode operation, three conditions apply:
the feedback voltage is lower than the threshold of VFBEB (1.25 V). Accordingly, the peak current sense
voltage across the shunt resistor is 0.17 V;
the up/down counter is NZC_ABM (7) and
a certain blanking time tBEB (24 ms).
Once all of these conditions are fulfilled, the Active Burst Mode flip-flop is set and the controller enters Active
Burst Mode operation. This multi-condition determination for entering Active Burst Mode operation prevents
mis-triggering of entering Active Burst Mode operation, so that the controller enters Active Burst Mode
operation only when the output power is really low during the preset blanking time.
3.5.2 During Active Burst Mode Operation
After entering the Active Burst Mode the feedback voltage rises as VOUT starts to decrease due to the inactive
PWM section. One comparator observes the feedback signal if the voltage level VFBBOn (3.6 V) is exceeded. In that
case the internal circuit is again activated by the internal bias to start with switching.
Turn-on of the power MOSFET is triggered by the timer. The PWM generator for Active Burst Mode operation
composes of a timer with a fixed frequency of fsB (52 kHz, typical) and an analog comparator. Turn-off is
Data Sheet 11 Revision 2.3
2017-09-12
Quasi-Resonant, 650V CoolSET™ in DS0-12 Package
Functional Description
resulted if the voltage across the shunt resistor at CS pin hits the threshold VcsB (0.34 V). A turn-off can also be
triggered if the duty ratio exceeds the maximal duty ratio DmaxB (50%). In operation, the output flip-flop will be
reset by one of these signals which come first.
If the output load is still low, the feedback signal decreases as the PWM section is operating. When feedback
signal reaches the low threshold VFBBOff (3.0 V), the internal bias is reset again and the PWM section is disabled
until next time regulation signal increases beyond the VFBBOn (3.6 V) threshold. If working in Active Burst Mode
the feedback signal is changing like a saw tooth between VFBBOff and VFBBOn shown in Figure 9.
3.5.3 Leaving Active Burst Mode Operation
The feedback voltage immediately increases if there is a high load jump. This is observed by a comparator. As
the current limit is 34% during Active Burst Mode a certain load is needed so that feedback voltage can exceed
VFBLB (4.5 V). After leaving active burst mode, maximum current can now be provided to stabilize VOUT. In
addition, the up/down counter will be set to 1 immediately after leaving Active Burst Mode. This is helpful to
decrease the output voltage undershoot.
VFBEB
VFBBOn
VFBLB
VFB
t
VCSB
1.0V
VCS
VVCCoff
VVCC t
t
VO
t
VFBBOff
Time to 7th zero and
Blanking Window (tBEB)
Current limit level during
Active Burst Mode
Leaving
Active Burst
Mode
Entering
Active Burst
Mode
Max. Ripple < 1%
Figure 9 Signals in Active Burst Mode
Data Sheet 12 Revision 2.3
2017-09-12
Quasi-Resonant, 650V CoolSET™ in DS0-12 Package
Functional Description
3.6 Protection Functions
The IC provides full protection functions. The following table summarizes these protection functions.
During operation, the VCC voltage is continuously monitored. In case of an under-voltage or an over-voltage,
the IC is reset and the main power switch is then kept off. After the VCC voltage falls below the threshold VVCCoff,
the startup cell is activated. The VCC capacitor is then charged up. Once the voltage exceeds the threshold
VVCCon, the IC begins to operate with a new soft-start.
Table 3
Protection Function
Failure Condition
Protection Mode
VCC Overvoltage
VVCC > 25 V & last for 10 μs (normal
mode only)
Auto Restart
VCC Undervoltage/ Short
Optocoupler
VVCC < 10.5 V
Auto Restart
Overload/Open Loop
VFB > 4.5 V & last for 30 ms
Auto Restart
Over Temperature (Controller
Junction)
TJ > 130 °C
Auto Restart
Output Overvoltage
VZCOVP > 3.7 V & last for 100 μs
Latch
Short Winding
VCSSW > 1.68 V & last for 190 ns
Latch
In case of open control loop or output over load, the feedback voltage will be pulled up. After a blanking time of
tOLP_B (30 ms), the IC enters auto-restart mode. The blanking time here enables the converter to provide a peak
power in case the increase in VFB is due to a sudden load increase. This output over load protection is disabled
during burst mode.
During off-time of the power switch, the voltage at the zero-crossing pin is monitored for output over-voltage
detection. If the voltage is higher than the preset threshold VZCOVP, the IC is latched off after the preset blanking
time tZCOVP. This latch off mode can only be reset if the VVCC < VVCCPD.
If the junction temperature of IC controller exceeds TjCon (130 °C), the IC enters into OTP auto restart mode. This
OTP is disabled during burst mode.
If the voltage at the current sensing pin is higher than the preset threshold VCSSW during on-time of the power
switch, the IC is latched off. This is short-winding protection. The short winding protection is disabled during
burst mode.
During latch-off protection mode, the VCC voltage drops to VVCCoff (10.5 V) and then the startup cell is activated.
The VCC voltage is then charged to VVCCon (18 V). The startup cell is shut down again. This action repeats again
and again.
There is also a maximum on time limitation implemented inside the CoolSET™ Q1. Once the gate voltage is high
and longer than tOnMax, the switch is turned off immediately.
Data Sheet 13 Revision 2.3
2017-09-12
Quasi-Resonant, 650V CoolSET™ in DS0-12 Package
Electrical Characteristics
4 Electrical Characteristics
Note: All voltages are measured with respect to ground (Pin 12). The voltage levels are valid if other ratings
are not violated.
4.1 Absolute Maximum Ratings
Note: Absolute maximum ratings are defined as ratings, which when being exceeded may lead to
destruction of the integrated circuit. For the same reason make sure, that any capacitor that will be
connected to pin 11 (VCC) is discharged before assembling the application circuit. Ta=25 ˚C unless
otherwise specified.
Table 4 Absolute Maximum Ratings
Parameter
Symbol
Limit Values
Unit
Remarks
min.
max.
Drain Source Voltage
VDS
-
650
V
Tj=110 °C
Switching drain current, pulse width tp
limited by Tjmax
IS
-
4.03
A
Pulse drain current, tp limited by Tjmax
ID_Plus
-
6.12
A
Avalanche energy, repetitive tAR limited
by max. Tj=150 °C1
EAR
-
0.15
mJ
Avalanche current, repetitive tAR
limited by max. Tj=150 °C1
IAR
-
1.5
A
VCC Supply Voltage
VVCC
-0.3
27
V
FB Voltage
VFB
-0.3
5.5
V
ZC Voltage
VZC
-0.3
5.5
V
CS Voltage
VCS
-0.3
5.5
V
Maximum current out from ZC pin
IZCMAX
3
-
mA
Junction Temperature
Tj
-40
150
°C
Controller & CoolMOS™
Storage Temperature
TS
-55
150
°C
Thermal Resistance
(Junction–Ambient)
RthJA
-
110
K/W
Soldering temperature, wavesoldering
only allowed at leads
Tsold
-
260
°C
1.6mm (0.063in.) from case
for 10s
ESD Capability (incl. Drain Pin)
VESD
-
2
kV
Human body model2
1
Repetitive avalanche causes additional power losses that can be calculated as PAV=EAR*f
2
According to EIA/JESD22-A114-B (discharging a 100 pF capacitor through a 1.5 kW series resistor
Data Sheet 14 Revision 2.3
2017-09-12
Quasi-Resonant, 650V CoolSET™ in DS0-12 Package
Electrical Characteristics
4.2 Operating Range
Note: Within the operating range the IC operates as described in the functional description.
Table 5 Operating Range
Parameter
Symbol
Limit Values
Unit
Remarks
min.
max.
VCC Supply Voltage
VVCC
VVCCoff
VVCCOVP
V
Junction Temperature of Controller
TjCon
-40
130
°C
Limited by over
temperature protection.
Junction Temperature of CoolMOS™
TjCoolMOS
-40
150
°C
4.3 Characteristics
4.3.1 Supply Section
Note: The electrical characteristics involve the spread of values within the specified supply voltage and
junction temperature range TJ from – 40 °C to 125 °C. Typical values represent the median values,
which are related to 25°C. If not otherwise stated, a supply voltage of VCC = 18 V is assumed.
Table 6 Supply Section
Parameter
Symbol
Limit Values
Unit
Test Condition
min.
typ.
max.
Start Up Current
IVCCstart
-
300
550
μA
VVCC =VVCCon -0.2 V
VCC Charge Current
IVCCcharge1
-
1.22
5
mA
VVCC = 0 V
IVCCcharge2
0.8
1.1
-
mA
VVCC = 1 V
IVCCcharge3
-
1
-
mA
VVCC =VVCCon -0.2 V
Maximum Input Current of Startup Cell
and CoolMOS™
IDrainIn
-
-
2
mA
VVCC =VVCCon -0.2 V
Leakage Current of
Startup Cell and CoolMOS™
IDrainLeak
-
0.2
50
μA
VDrain = 600 V at Tj=100 °C
Supply Current in normal operation
IVCCNM
-
1.5
2.3
mA
IFB = 0 A
Supply Current in
Auto Restart Mode with Inactive Gate
IVCCAR
-
300
-
μA
IFB = 0 A
Supply Current in Latch-off Mode
IVCClatch
-
300
-
μA
IFB = 0 A
Supply Current in Burst Mode with
inactive Gate
IVCCburst
-
500
950
μA
VFB = 2.5 V, exclude the
current flowing out from
FB pin
VCC Turn-On Threshold
VVCCon
17.0
18.0
19.0
V
VCC Turn-Off Threshold
VVCCoff
9.8
10.5
11.2
V
VCC Turn-On/Off Hysteresis
VVCChys
-
7.5
-
V
Data Sheet 15 Revision 2.3
2017-09-12
Quasi-Resonant, 650V CoolSET™ in DS0-12 Package
Electrical Characteristics
4.3.2 Internal Voltage Reference
Table 7 Internal Voltage Reference
Parameter
Symbol
Limit Values
Unit
Test Condition
min.
typ.
max.
Trimmed Reference Voltage
VREF
4.80
5.00
5.20
V
measured at pin FB
IFB = 0
4.3.3 PWM Section
Table 8 PWM Section
Parameter
Symbol
Limit Values
Unit
Test Condition
min.
typ.
max.
Feedback Pull-Up Resistor
RFB
14
23
33
kΩ
PWM-OP Gain
GPWM
3.18
3.3
-
-
Offset for Voltage Ramp
VPWM
0.6
0.7
-
V
Maximum on time in normal operation
tOnMax
22
30
41
μs
4.3.4 Current Sense
Table 9 Current sense
Parameter
Symbol
Limit Values
Unit
Test Condition
min.
typ.
max.
Peak current limitation in normal
operation
VCSth
0.97
1.03
1.09
V
Leading Edge Blanking time
tLEB
200
330
460
ns
Peak Current Limitation in Active Burst
Mode
VCSB
0.29
0.34
0.39
V
4.3.5 Soft Start
Table 10 Soft Start
Parameter
Symbol
Limit Values
Unit
Test Condition
min.
typ.
max.
Soft-Start time
tSS
8.5
12
-
ms
Soft-start time step
tSS_s1
tSS_S1
-
3
-
ms
Internal regulation voltage at first step
VSS11
-
1.76
-
V
Internal regulation voltage step at soft
start
VSS_S 1
-
0.56
-
V
1
The parameter is not subjected to production test - verified by design/characterization
Data Sheet 16 Revision 2.3
2017-09-12
Quasi-Resonant, 650V CoolSET™ in DS0-12 Package
Electrical Characteristics
4.3.6 Foldback Point Correction
Table 11 Foldback Point Correction
Parameter
Symbol
Limit Values
Unit
Test Condition
min.
typ.
max.
ZC current first step threshold
IZC_FS
0.350
0.500
0.621
mA
ZC current last step threshold
IZC_LS
1.3
1.7
2.2
mA
CS threshold minimum
VCSMF
-
0.66
-
V
Izc=2.2 mA, VFB=3.8 V
4.3.7 Digital Zero Crossing
Table 12 Digital Zero Crossing
Parameter
Symbol
Limit Values
Unit
Test Condition
min.
typ.
max.
Zero crossing threshold voltage
VZCCT
50
100
170
mV
Ringing suppression threshold
VZCRS
-
0.7
-
V
Minimum ringing suppression time
tZCRS1
1.62
2.5
4.5
μs
VZC > VZCRS
Maximum ringing suppression time
tZCRS2
-
25
-
μs
VZC < VZCRS
Threshold to set Up/Down Counter to
one
VFBR1
-
3.9
-
V
Threshold for downward counting at
low line
VFBZHL
-
3.2
-
V
Threshold for upward counting at low
line
VFBZLL
-
2.5
-
V
Threshold for downward counting at
high line
VFBZHH
-
2.9
-
V
Threshold for upward counting at
highline
VFBZLH
-
2.3
-
V
ZC current for IC switch threshold to
high line
IZCSH
-
1.3
-
mA
ZC current for IC switch threshold to
low line
IZCSL
-
0.8
-
mA
Counter time1
tCOUNT
-
48
-
ms
Maximum restart time in normal
operation
tOffMax
30
42
57.5
μs
1
The parameter is not subjected to production test - verified by design/characterization
Data Sheet 17 Revision 2.3
2017-09-12
Quasi-Resonant, 650V CoolSET™ in DS0-12 Package
Electrical Characteristics
4.3.8 Active Burst Mode
Table 13 Digital Zero Crossing
Parameter
Symbol
Limit Values
Unit
Test Condition
min.
typ.
max.
Feedback voltage for entering Active
Burst Mode
VFBEB
-
1.25
-
V
Minimum Up/down value for entering
Active Burst Mode
NZC_ABM
-
7
-
Blanking time for entering Active
Burst Mode
tBEB
-
24
-
ms
Feedback voltage for leaving Active
Burst Mode
VFBLB
-
4.5
-
V
Feedback voltage for burst-on
VFBBOn
-
3.6
-
V
Feedback voltage for burst-off
VFBBOff
-
3.0
-
V
Fixed Switching Frequency in Active
Burst Mode
fsB
39
52
65
kHz
Max. Duty Cycle in Active Burst
Mode
DmaxB
-
0.5
-
4.3.9 Protection
Table 14 Protection
Parameter
Symbol
Limit Values
Unit
Test Condition
min.
typ.
max.
VCC overvoltage threshold
VVCCOVP
24.0
25.0
26.0
V
Over Load or Open Loop Detection
threshold for OLP protection at FB pin
VFBOLP
-
4.5
-
V
Over Load or Open Loop Protection
Blanking Time
tOLP_B
20
30
44
ms
Output Overvoltage
detectionthreshold at the ZC pin
VZCOVP
3.55
3.7
3.84
V
Blanking time for Output Overvoltage
protection
tZCOVP
-
100
-
μs
Threshold for short winding
protection
VCSSW
1.63
1.68
1.78
V
Blanking time for short-winding
protection
tCSSW
-
190
-
ns
Over temperature protection1
TjCon
130
140
150
°C
Power Down Reset threshold for
Latched Mode
VVCCPD
5.2
-
7.8
°C
After Latched Off Mode is
entered
1
The parameter is not subjected to production test - verified by design/characterization
Data Sheet 18 Revision 2.3
2017-09-12
Quasi-Resonant, 650V CoolSET™ in DS0-12 Package
Electrical Characteristics
Note: The trend of all the voltage levels in the Control Unit is the same regarding the deviation except VVCCOVP
& VVCCOVP
4.3.10 CoolMOS™ Section
Table 15 CoolMOS™ Section
Parameter
Symbol
Limit Values
Unit
Test Condition
min.
typ.
max.
Drain Source Breakdown Voltage
V(BR)DSS
650
-
-
V
Tj = 110 °C
Drain Source On-Resistance
RDSon
-
1.70
3.57
1.96
4.12
Ω
Tj = 25 °C
Tj=125 °C1
at ID = 1.5 A
Effective output capacitance, energy
related
Co(er)
-
11.631
-
pF
VDS = 0 V to 480 V
Rise Time
trise
-
302
-
ns
Fall Time
tfall
-
302
-
ns
1
The parameter is not subjected to production test - verified by design/characterization
2
Measured in a Typical Flyback Converter Application
Data Sheet 19 Revision 2.3
2017-09-12
Quasi-Resonant, 650V CoolSET™ in DS0-12 Package
CoolMOS™ Performance Characteristics
5 CoolMOS™ Performance Characteristics
Figure 10 Safe Operating Area (SOA) curve for ICE2QR1765G
Figure 11 Power dissipation; Ptot=f(Ta)
Data Sheet 20 Revision 2.3
2017-09-12
Quasi-Resonant, 650V CoolSET™ in DS0-12 Package
CoolMOS™ Performance Characteristics
Figure 12 Drain-source breakdown voltage; VBR(DSS)=f(Tj), ID=0.25mA
Data Sheet 21 Revision 2.3
2017-09-12
Quasi-Resonant, 650V CoolSET™ in DS0-12 Package
Input Power Curve
6 Input Power Curve
Two input power curves gives typical input power versus ambient temperature are showed below; Vin=85~265
VAC (Figure 13) and Vin=230 VAC (Figure 14). The curves are derived based on a typical discontinuous mode
flyback model which considers either 50 % duty ratio or 115 V maximum secondary to primary reflected voltage
(high priority). The calculation is based on no copper area as heatsink for the device. The input power already
includes power loss at input common mode choke and bridge rectifier and the CoolMOSTM. The device
saturation current (ID_plus @ Tj=125 °C) is also considered.
To estimate the out power of the device, it is simply multiplying the input power at a particular ambient
temperature with the estimated efficiency for the application. For example, a wide range input voltage (Figure
13), operating temperature is 50 °C, estimated efficiency is 85 %,the output power is 23.8 W (28 W*0.85).
Figure 13 Input power curve VIN=85~265 VAC; Pin=f(Ta)
Figure 14 Input power curve VIN=230 VAC; Pin=f(Ta)
Data Sheet 22 Revision 2.3
2017-09-12
Quasi-Resonant, 650V CoolSET™ in DS0-12 Package
Outline Dimension
7 Outline Dimension
Figure 15 PG-DSO-12 (Pb-free lead plating Plastic Dual-in-Line Outline)
Data Sheet 23 Revision 2.3
2017-09-12
Quasi-Resonant, 650V CoolSET™ in DS0-12 Package
Marking
8 Marking
Figure 16 Marking for ICE2QR1765G
Revision History
Major changes since the last revision
Page or Reference
Description of change
1, 23
Revise wrong marking text
Published by
Infineon Technologies AG
81726 München, Germany
© 2017 Infineon Technologies AG.
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Edition 2017-09-12
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