FDMC86184 - ON SEMICONDUCTOR

Semiconductor Components Industries, LLC, 2016 Publication Order Number:

June, 2017, Rev. 1.1 FDMC86184/D

1

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FDMC86184 N-Channel Shielded Gate PowerTrench® MOSFET

FDMC86184

N-Channel Shielded Gate PowerTrench® MOSFET

100 V, 57 A, 8.5 mΩ

Features

Shielded Gate MOSFET Technology

Max rDS(on) = 8.5 mΩ at VGS = 10 V, ID =21 A

Max rDS(on) = 24.8 mΩ at VGS = 6 V, ID = 10 A

50% Lower Qrr than Other MOSFET Suppliers

Lowers Switching Noise/EMI

MSL1 Robust Package Design

100% UIL Tested

RoHS Compliant

General Description

This N-Channel MV MOSFET is produced using ON

Semiconductor’s advanced PowerTrench® process that

incorporates Shielded Gate technology. This process has been

optimized to minimize on-state resistance and yet maintain

superior switching performance with best in class soft body

diode.

Applications

Primary DC-DC MOSFET

Synchronous Rectifier in DC-DC and AC-DC

Motor Drive

Solar

BottomTop

Pin 1

G

D

S

D

DD

S

G

D

MOSFET Maximum Ratings TA = 25 °C unless otherwise noted.

Thermal Characteristics

Package Marking and Ordering Information

Symbol Parameter Ratings Units

VDS Drain to Source Voltage 100 V

VGS Gate to Source Voltage ±20 V

ID

Drain Current -Continuous TC = 25 °C (Note 5) 57

A

-Continuous TC = 100 °C (Note 5) 36

-Continuous TA = 25 °C (Note 1a) 12

-Pulsed (Note 4) 266

EAS Single Pulse Avalanche Energy (Note 3) 121 mJ

PDPower Dissipation TC = 25 °C 54 W

Power Dissipation TA = 25 °C (Note 1a) 2.3

TJ, TSTG Operating and Storage Junction Temperature Range -55 to +150 °C

RθJC Thermal Resistance, Junction to Case 2.3 °C/W

RθJA Thermal Resistance, Junction to Ambient (Note 1a) 53

Device Marking Device Package Reel Size Tape Width Quantity

FDMC86184 FDMC86184 Pow er 33 1 3 ’’ 12 mm 3000 units

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2

FDMC86184 N-Channel Shielded Gate PowerTrench® MOSFET

Electrical Characteristics TJ = 25 °C unless otherwise noted.

Off Characteristics

On Characteristics

Dynamic Characteristics

Switching Characteristics

Drain-Source Diode Characteristics

Symbol Parameter Test Conditions Min. Typ . Max. Units

BVDSS Drain to Source Breakdown Voltage ID = 250 μA, VGS = 0 V 100 V

ΔBVDSS

ΔTJ

Breakdown Voltage Temperature

Coefficient ID = 250 μA, referenced to 25 °C 59 mV/°C

IDSS Zero Gate Voltage Drain Current VDS = 80 V, VGS = 0 V 1 μA

IGSS Gate to Source Leakage Current VGS = ±20 V, VDS = 0 V 100 nA

VGS(th) Gate to Source Threshold Voltage VGS = VDS, ID = 110 μA 2.0 3.1 4.0 V

ΔVGS(th)

ΔTJ

Gate to Source Threshold Voltage

Temperature Coefficient ID = 110 μA, referenced to 25 °C -9 mV/°C

rDS(on) Static Drain to Source On Resistance VGS = 10 V, ID = 21 A 6.4 8.5 mΩVGS = 6 V, ID = 10 A 11 24.8

VGS = 10 V, ID = 21 A, TJ = 125 °C 11 18

gFS Forward Transconductance VDS = 5 V, ID = 21 A 49 S

Ciss Input Capacitance VDS = 50 V, VGS = 0 V,

f = 1 MHz

1490 2090 pF

Coss Output Capacitance 906 1270 pF

Crss Reverse Transfer Capacitance 13 25 pF

RgGate Resistance 0.1 0.4 1.2 Ω

td(on) Turn-On Delay Time VDD = 50 V, ID = 21 A,

VGS = 10 V, RGEN = 6 Ω

12 22 ns

trRise Time 410ns

td(off) Turn-Off Delay Time 17 31 ns

tfFall Time 410ns

QgTotal Gate Charge VGS = 0 V to 10 V VDD = 50 V,

ID = 21 A

21 30 nC

QgTotal Gate Charge VGS = 0 V to 6 V 14 20 nC

Qgs Gate to Source Charge 6.5 nC

Qgd Gate to Drain “Miller” Charge 4.6 nC

Qoss Output Charge VDD = 50 V, VGS = 0 V 61 nC

VSD Source to Drain Diode Forward Voltage VGS = 0 V, IS = 2.1 A (Note 2) 0.7 1.2 V

VGS = 0 V, IS = 21 A (Note 2) 0.8 1.3

trr Reverse Reco very Time IF = 10 A, di/dt = 300 A/μs27 44 ns

Qrr Reverse Recovery Charge 46 74 nC

trr Reverse Reco very Time IF = 10 A, di/dt = 1000 A/μs21 34 ns

Qrr Reverse Recovery Charge 96 154 nC

Notes:

1. RθJA is determined with the device mounted on a 1 in2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. RθCA is determined by the user's board design.

2. Pulse Test: Pulse Width < 300 μs, Duty cycle < 2.0%.

3. EAS of 121 mJ is based on starting TJ = 25 °C; N-ch: L = 3 mH, IAS = 9 A, VDD = 100 V, VGS =10 V. 100% test at L = 0.3 mH, IAS = 21 A.

4. Pulsed Id please refer to Fig 11 SOA graph for more details.

5. Computed continuous current limited to Max Junction Temperature only, actual continuous current will be limited by thermal & electro-mechanical application board design.

53 °C/W when mounted

on a 1 in2 pad of 2 oz

copper

125 °C/W when mounted

on a minimum pad of 2 oz

copper

G

DF

DS

SF

SS

G

DF

DS

SF

SS

a. b.

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3

FDMC86184 N-Channel Shielded Gate PowerTrench® MOSFET

Typical Characteristics TJ = 25 °C unless otherwise noted.

Figure 1.

012345

0

50

100

150

200

VGS = 6.5 V

VGS = 6 V

VGS = 8 V

PULSE DURATION = 80 μs

DUTY CYCLE = 0.5% MAX

VGS = 5.5 V

VGS = 10 V

ID, DRAIN CURRENT (A)

VDS, DRA IN TO SOURCE VOLTAGE (V)

On-Region Characteristics Figure 2.

0 50 100 150 200

0

1

2

3

4

VGS = 8 V

PULSE DURATION = 80 μs

DUTY CYCLE = 0.5% MAX

NORMALIZED

DRAIN TO SOURCE ON-RESISTANCE

ID, DRAIN CURRENT (A)

VGS = 6.5 V

VGS = 6 V

VGS = 10 V

VGS = 5.5 V

Normalized On-Resistance

vs. Drain Current and Gate Voltage

Figure 3. Normalized On- Resistance

-75 -50 -25 0 25 50 75 100 125 150

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

ID = 21 A

VGS = 10 V

NORMALIZED

DRAIN TO SOURCE ON-RESIST ANCE

TJ, JUNCTION TEMPERATURE (oC)

vs. Junction Temperature Figure 4.

45678910

0

10

20

30

40

50

TJ = 125 oC

ID = 21 A

TJ = 25 oC

VGS, GATE TO SOURCE VOLTAG E (V)

rDS(on), DRAIN TO

SOURCE ON-RESIS TANCE (mΩ)

PULSE DURA TION = 80 μs

DUTY CYCLE = 0.5% MAX

On-Resistance vs. Gate to

Source Voltage

Figure 5. Transfer Characteristics

246810

0

50

100

150

200

TJ = 150 oC

VDS = 5 V

PULSE DURA T ION = 80 μs

DUTY CYCLE = 0.5% MAX

TJ = -55 oC

TJ = 25 oC

ID, DRAIN CURRENT (A)

VGS, GATE TO SOURCE VOLTAGE (V)

Figure 6.

0.00.20.40.60.81.01.2

0.001

0.01

0.1

1

10

100

200

TJ = -55 oC

TJ = 25 oC

TJ = 150 oC

VGS = 0 V

IS, REVERSE DRAIN CURRENT (A)

VSD, BODY DIODE FORWARD VOLTAGE (V)

Source to Drain Diode

Forward Voltage vs. Source Current

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FDMC86184 N-Channel Shielded Gate PowerTrench® MOSFET

Figure 7.

0 6 12 18 24

0

2

4

6

8

10 ID = 21 A

VDD = 75 V

VDD = 25 V

VGS, GATE TO SOURCE VOLTAGE (V)

Qg, GATE CH ARGE ( n C )

VDD = 50 V

Gate Charge Characteristics Figure 8.

0.1 1 10 100

1

10

100

1000

10000

f = 1 MHz

VGS = 0 V

CAPACITANCE (pF)

VDS, DRA IN TO SOURCE VOLTAGE (V)

Crss

Coss

Ciss

Cap a cit a nce vs. D rai n

to Source Voltage

Figure 9.

0.01 0.1 1 10 100

1

10

50

TJ = 100 oC

TJ = 25 oC

TJ = 125 oC

tAV, TIME IN AVA LANCHE (ms)

IAS, AVALANCHE CURRENT (A)

Uncl a mpe d Ind u cti ve

Switching Capability Figure 10.

25 50 75 100 125 150

0

10

20

30

40

50

60

VGS = 6 V

RθJC = 2.3 oC/W

VGS = 10 V

ID, DRAIN CURRENT (A)

TC, CASE TEMPERA TURE (oC)

Maximum Continuous Drain

Current vs. Case Temperature

Figure 11.

0.1 1 10 100 500

0.1

1

10

100

300

10 μs

CURVE BENT TO

MEASURED DATA

100 μs

10 ms

100 ms

1 ms

ID, DRAIN CURRENT (A)

VDS, DRAIN to SOURCE VOLTAGE (V)

THIS AREA IS

LIMITED BY rDS(on)

SINGLE PULSE

TJ = MAX RA T E D

RθJC = 2.3 oC/W

TC = 25 oC

Forward Bias Safe

Operating Area Figure 12. Single Pulse Maximum

Power Dissipation

10-5 10-4 10-3 10-2 10-1 1

10

100

1000

10000

SINGLE PULSE

RθJC = 2.3 oC/W

TC = 25 oC

P(PK), PEAK TRANSIENT POWER (W)

t, PULSE WIDTH (sec)

Typical Characteristics TJ = 25 °C unless otherwise noted.

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5

FDMC86184 N-Channel Shielded Gate PowerTrench® MOSFET

Figure 13. Junction-to-Case Transient Thermal Response Curve

10-5 10-4 10-3 10-2 10-1 1

0.001

0.01

0.1

1

2

SINGLE PULSE

DUTY CYCLE-DESCENDING ORDER

r(t), NORMALIZED EF FE CT IVE TRANSIENT

THERMAL RESISTANCE

t, RECTANGULAR PULSE DURA T ION (sec)

D = 0.5

0.2

0.1

0.05

0.02

0.01

PDM

t1t2

NOTES:

ZθJC(t) = r(t) x RθJC

RθJC = 2.3 oC/W

Duty Cycle, D = t1 / t2

Peak TJ = PDM x ZθJC(t) + TC

Typical Characteristics TJ = 25 °C unless otherwise noted.

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6

FDMC86184 N-Channel Shielded Gate PowerTrench® MOSFET

Dimensional Outline and Pad Layout

NOTES: UNLESS OT HERWISE SPECIFIED

A) PACKAGE STAND ARD REFERENCE:

JEDEC MO-240, ISSUE A, VAR. BA,

DAT ED O CT OBER 2002.

B) AL L DIMENSION S ARE IN MILLIM ETER S.

C) DIMENSIONS DO NOT INCLUDE BURRS

OR MOLD FLASH. MOL D FLASH OR

BURRS DOES NOT EXCEED 0.10MM.

D) DIMENSIONING AND TOLERANCING PER

ASME Y14.5M -1994.

E) DRAWIN G FILE NAM E: PQFN08HREV1

8

1

5

4

41

85

LAND PATTERN

RECOMMENDATION

14

85

PKG

C

L

PKG

L

C

PKG L

C

L

C

SYM

PKG

C

L

A

B

DE TA IL A

SCALE: 2X

SEE

DETAIL A

3.40

3.20

3.40

3.20

1.95

0.65

0.37

0.27 (8X)

0.50

0.30

2.05

1.85

0.10 C A B

(0.34)

(2.27)(0.52 TYP)

0.25

0.15

0.80

0.70

0.10 C

0.08 C 0.05

0.00 C

SEATING

PLANE

2.37 M IN

(0.45)

(0.40)

(0.65)

2.15 M IN

0.70 M IN

0.42 M IN

(8X)

1.95

0.65

PIN 1

INDICATOR

( 0.33 ) TYP

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