Freescale Semicondu ctor
Data Sheet Document Number: MR0A16A
Rev. 2, 11/2007
© Freescal e Semiconductor , In c., 2007. All right s reserv ed.
This document contains information on a new product unde r develop me nt. Freescale
reserves the ri ght to chan ge or di sconti nue this product without notice.
Introduction
The MR0A16A is a 1,048,576-bit magnetoresistive
random access memory (MRAM) device
organized as 65,536 words of 16 bits. The
MR0A16 A is eq uipped with c hip en able (E ), write
enable (W), and output enable (G) pins , allowing
for significant system design flexibility without bus
co nten t ion. Becaus e t he MR0A16A has s epara t e
byte-enable controls (LB and UB) , ind i vi dual byt es
ca n be writt en and re ad.
MRAM is a nonvolatile mem ory technology that
prot ec t s data in th e ev ent of pow er loss an d does
not require periodic refreshing. The MR0A16A is
the id eal mem ory so lution f or app lic at ions th at
must perm anen t ly store an d retriev e c ritica l data
quickly.
The MR0A16A is available in a 400-mil, 44-lead
plastic small-outline TSOP type-II package with an
industry-standard center power and ground SRAM
pinout.
The MR0A16A is available in Com mercial (0°C to
70°C ), In dustr ial (-40 °C t o 85°C) and Ex t ende d
(-40°C t o 105°C) am bien t tem pera t ure ran ges.
Features
• Single 3.3-V power su pply
• C ommerc ial temp erat ure ran ge (0°C to
70°C ), Indust rial t em perature r ange (-40°C
to 85°C) and Extended temperature range
(-40°C t o 105°C )
•
Symmetrical
hi gh -s peed r ead a nd w ri te wi th
fast access time (35 ns)
• F lexible data bus c ontrol — 8 bit or 16 bi t
access
• Equ al address and chip-en able a ccess
times
• Automatic data protection with low-voltage
inhibit ci rc uitry t o prevent wr ite s on power
loss
• All in put s and ou tp ut s are
tra ns is t or-transis to r logic (T T L) c ompatible
• Fully static operation
• F ull no nv olat ile oper at ion wit h 20 years
minimum data retention
64K x 16-Bit 3.3-V
Asynchronous
Magnetoresistive RAM
MR0A16A
44-TSOP
Case 924A-02
MR0A16A Advanc ed Information Data Sheet, Rev. 2
2Freescale Semiconductor
Device Pin Assignm ent
Figure 1. Block Diagram
Device Pin Assignment
Figure 2. MR0 A16A in 44-Pin TSOP Type II P ackage
UPPER BYTE OUTPUT ENABLE
LOWER BYTE OUTPUT ENABLE
COLUMN
DECODER
ROW
DECODER
64K x 16
BIT
MEMORY
ARRAY
FINAL
WRITE
DRIVERS
SENSE
AMPS
UPPER BYTE WRITE ENABLE
LOWER BYTE WRITE ENAB LE
OUTPUT
ENABLE
BUFFER
CHIP
ENABLE
BUFFER
WRITE
ENABLE
BUFFER
BYTE
ENABLE
BUFFER
ADDRESS
BUFFERS UPPER
BYTE
OUTPUT
BUFFER
LOWER
BYTE
OUTPUT
BUFFER
UPPER
BYTE
WRITE
DRIVER
LOWER
BYTE
WRITE
DRIVER DQL[7:0]
DQU[15:8]
G
E
W
UB
LB
8
88
8
8
8
16
16
16
A[15:0]
8
8
8
8
UB
LB
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
A15
A14
A13
G
UB
LB
DQU15
DQU14
DQU13
DQU12
VSS
VDD
DQU11
DQU10
DQU9
DQU8
NC
VDD
VSS
A12
A11
A10
A0
A1
A2
A3
A4
E
DQL0
DQL1
DQL2
DQL3
VDD
VSS
DQL4
DQL5
DQL6
DQL7
W
A5
A6
A7
A8
A9
Table 1. Pin Functions
Signal Name Function
A Address input
EChip enable
WWrite enable
GOutput enable
UB Upper byte select
LB Lower byte select
DQL Data I/O, lower byte
DQU Data I/O, upper byte
VDD Power supply
VSS Ground
NC Do not connect this pin
Electrical Specifications
MR0A16A Advanc ed Information Data Sheet, Rev. 2
Freescale Semiconductor 3
Electrical Specifications
Absolute Maximum Ratings
This device contains circuitry to protect the inputs against damage caused by high static voltages or
el ect ri c f iel d s; ho wev er , i t is ad vi se d tha t no r mal prec au ti on s be ta ke n to avoi d app l ic at ion o f an y vo lt age
greater than maximum rated voltages to these high-impedance (Hi-Z) circuits.
The device also contains protection against external magnetic fields. Precautions should be taken to
avoid application of any magnetic field more intense than the maximum field intensity specified in the
maximum ratings.
Ta ble 2. Operating Modes
E1G1W1LB1UB1Mode VDD
Current DQL[7:0]2DQU[15:8]2
H XXXXNot selected I
SB1, ISB2 Hi-Z Hi-Z
L H H X X Output disabled IDDR Hi-Z Hi-Z
L X X H H Output disabled IDDR Hi-Z Hi-Z
L L H L H Lower byte read IDDR DOut Hi-Z
L L H H L Upper byte read IDDR Hi-Z DOut
L L H L L Word read IDDR DOut DOut
L X L L H Lower byte write IDDW DIn Hi-Z
L X L H L Upper byte write IDDW Hi-Z DIn
LXLLLWord write I
DDW DIn DIn
NOTES:
1H = high, L = low, X = don’t care
2Hi-Z = high impedance
MR0A16A Advanc ed Information Data Sheet, Rev. 2
4Freescale Semiconductor
Electrical Speci fications
Table 3. Absolute Maximum Ratings1
Parameter Symbol Value Unit
Supply voltage2VDD –0.5 to 4.0 V
Voltage on any pin2VIn – 0.5 to VDD + 0.5 V
Output current per pin IOut ±20 mA
Package power dissipation3PD0.600 W
Temperature under bias
MR0A16AYS35 (Commercial)
MR0A16ACYS35 (Industrial)
MR0A 16A VYS35 (E xtende d)
TBias –10 to 85
–45 to 95
–45 to 110
°C
Storage temperature Tstg –55 t o 150 °C
Lead temperature during solder (3 minute max) TLead 260 °C
Maximum magnetic field during write
MR0A16AYS35 (Commercial)
MR0A16ACYS35 (Industrial)
MR0A 16A VYS35 (E xtende d)
Hmax_write 15
25
25
Oe
Maximu m magnet ic field during read or standby Hmax_read 100 Oe
NOTES:
1Permanent device damage may occur if absolute maximum ratings are exceeded. Functional operation
shoul d be restr ic ted to reco mmended op erating c onditions. Exposur e to excess ive volt ages or magnetic fiel ds
could affect device reliability.
2All voltages are ref erenced to VSS.
3Power dissipatio n capability depends on package charact eris tics and use environment.
Table 4. Operating Conditions
Parameter Symbol Min Typ Max Unit
Power supply voltage VDD 3.013.3 3.6 V
Write inhibit voltage VWI 2.5 2.7 3.01V
Input high voltage VIH 2.2 — VDD +
0.32V
Input low voltage VIL –0.53—0.8V
Operating temperature
MR0A16AYS 35 (Com me rcial)
MR0A1 6ACYS35 (In dustrial)
MR0A1 6AVYS 35 (Extended )
TA0
-40
-40
70
85
105
°C
NOTES:
1After power up or if VDD fal ls below VWI, a waiting period of 2 ms must be observed, and E and W
must remain high for 2 ms. Memory is designed to prevent writing for all input pin conditions if VDD
falls belo w m in imum VWI.
2VIH (max) = VDD + 0.3 Vdc; VIH (max) = VDD + 2.0 Vac (pulse width ≤ 10 ns) for I ≤ 20.0 mA.
3VIL (min) = –0.5 Vdc; VIL (m in) = –2.0 Vac (pulse width ≤ 10 ns) for I ≤ 20.0 mA.
Electrical Specifications
MR0A16A Advanc ed Information Data Sheet, Rev. 2
Freescale Semiconductor 5
Direct Curre nt (dc)
Table 5. dc Characteristics
Parameter Symbol Min Typ Max Unit
Input leakage current Ilkg(I) ——±1μA
Outp ut leakage current Ilkg(O) ——±1μA
Outp ut low voltage
(IOL = +4 mA )
(IOL = +100 μA) VOL — — 0.4
VSS + 0. 2 V
Outp ut high voltage
(IOH = –4 mA)
(IOH = –100 mA) VOH 2.4
VDD – 0.2 ——V
Table 6. Power Supply Characteristics
Parameter Symbol Typ Max Unit
ac active supply current — read modes1
(IOut = 0 m A , VDD = max) IDDR 55 80 mA
ac active supply current — write mo des1
(VDD = max )
MR0A16AYS35 (Commercial)
MR0A16ACYS35 (Industrial)
MR0A1 6 AVYS35 (Exte nded)
IDDW 105
105
105
155
165
165
mA
ac standby current
(VDD = max , E = V IH)
(no other restrictions on other inputs) ISB1 18 28 mA
CMOS standby current
(E ≥ VDD – 0.2 V and VIn ≤ VSS + 0.2 V or ≥ VDD – 0.2 V)
(VDD = max , f = 0 MHz) ISB2 912mA
NOTES:
1All active current measurements are meas ured with one address transit ion per cycle .
Table 7. Capacitance1
Parameter Symbol Typ Max Unit
Address inpu t capacita nce CIn —6pF
Control input capacitance CIn —6pF
Input/output capacitance CI/O —8pF
NOTES:
1f = 1.0 MHz, dV = 3.0 V, TA = 25°C, periodically sampled rather than 100% tested.
MR0A16A Advanc ed Information Data Sheet, Rev. 2
6Freescale Semiconductor
Electrical Speci fications
Figure 3. O utput Load for ac Test
Table 8. ac Measure m ent Conditions
Parameter Value
Logic input timing measurement reference level 1.5 V
Logic output timing measurement reference level 1.5 V
Logic input pulse levels 0 or 3.0 V
Input rise/fall time 2 ns
Output load for low and high imped anc e parameters See Figure 3A
Output load for all other timing parameters See Figure 3B
AB
OUTPUT
RL = 50 Ω
VL = 1.5 V
ZD = 50 Ω
OUTPUT
600 Ω
725 Ω
5 pF
+3.3 V
Electrical Specifications
MR0A16A Advanc ed Information Data Sheet, Rev. 2
Freescale Semiconductor 7
This page is intentionally blank.
MR0A16A Advanc ed Information Data Sheet, Rev. 2
8Freescale Semiconductor
Timing Specif ications
Timin g Sp ecif icati ons
Read Mode
Table 9. Read Cycle Timing1, 2
Parameter Symbol Min Max Unit
Read cycle time tAVAV 35 — ns
Address access time tAVQV —35ns
Enable access time 3tELQV —35ns
Output enable access time tGLQV —15ns
Byte enab le access time tBLQV —15ns
Output hold fro m address change tAXQX 3—ns
Enabl e low to output active4, 5 tELQX 3—ns
Output enable low to output active4, 5 tGLQX 0—ns
Byte enable low to output active4, 5 tBLQX 0—ns
Enabl e high to output Hi-Z4, 5 tEHQZ 015ns
Output enable high to output Hi-Z4, 5 tGHQZ 010ns
Byte high to output Hi-Z4, 5 tBHQZ 010ns
NOTES:
1W is high for read cycle.
2Due to product sensitivities to noise, power supplies must be properly grounded and
decoupled, and bus contention condition s must be minimized or el iminated durin g read and
write cycles.
3Addresses valid before or at the same time E goes low.
4This parameter is sam pled and not 100% tested.
5Transition is measured ±200 mV f rom steady-state vol tage.
Timing Specif ications
MR0A16A Advanc ed Information Data Sheet, Rev. 2
Freescale Semiconductor 9
Figure 4. Read Cycle 1
Figure 5. Read Cycle 2
tAVAV
tAXQX
tAVQV
DATA VALIDPREVIOUS DATA VAL IDQ (DATA OUT)
A (ADDRESS)
NOTES:
Device is continuously sel ected (E ≤ VIL, G ≤ VIL).
tAVAV
tAVQV
A (ADDRESS)
tELQX
tGLQV
DATA VALID
E (CHIP ENABLE)
G (OUTPUT ENABLE)
LB, UB (BY TE ENABLE)
Q (DATA OUT)
tELQV
tGLQX
tBLQV
tBLQX
tBHQZ
tGHQZ
tEHQZ
MR0A16A Advanc ed Information Data Sheet, Rev. 2
10 Freescale Semiconductor
Timing Specif ications
Write Mode
Table 10. Wr it e C ycle Timi n g 1 (W Controlled)1, 2, 3, 4, 5
Parameter Symbol Min Max Unit
Write cycl e time6tAVAV 35 — ns
Address set-up time tAVWL 0—ns
Address valid to end of write (G high ) tAVWH 18 — ns
Address valid to end of write (G lo w) tAVWH 20 — ns
Write pulse width (G high) tWLWH
tWLEH 15 — ns
Write pulse width (G low) tWLWH
tWLEH 15 — ns
Data val id to end of writ e tDVWH 10 — ns
Data hold time tWHDX 0—ns
Write low to data Hi-Z7, 8, 9 tWLQZ 012ns
Write high to output active7, 8, 9 tWHQX 3—ns
Write reco very ti me tWHAX 12 — ns
NOTES:
1A writ e occurs during the overlap of E low and W lo w .
2Due to product sensi tivities to noise, power supplies must be pr operly grounded and decoupled and
bus contention conditions must be minimized or eli minated during read and writ e cycles.
3If G goes low at the same time or after W goes low, the output wil l remai n in a hig h-i m pedance state.
4Afte r W, E, or UB/LB has been b rought high, th e signal mus t remai n in s teady- sta te hig h for a mi nimum
of 2 ns.
5The mini mum tim e between E bei ng as serte d low in one cycle t o E bei ng assert ed low i n a subsequen t
cycle is t he sam e as the mini mu m cyc le time al lowed for the device.
6All writ e cycle timings ar e referenced from the last valid ad dress to t he fi rst transition address.
7This parameter is sampl ed and not 100% test ed.
8Transition is measured ±200 mV from st eady-state volt age.
9At any giv en voltage or temperat ure, tWLQZ max < tWHQX min.
Timing Specif ications
MR0A16A Advanc ed Information Data Sheet, Rev. 2
Freescale Semiconductor 11
Figur e 6. W r i te C ycle 1 (W Controlled)
tAVAV
tAVWH
A (ADDRESS)
tWLEH
DATA VA L ID
E (CHIP ENABLE)
W (WRITE ENABLE)
LB, UB (BYTE ENAB LE)
Q (DATA OUT)
tDVWH
tWLQZ
tWHDX
D (DATA IN)
tWHAX
Hi-ZHi-Z
tAVWL
tWLWH
tWHQX
MR0A16A Advanc ed Information Data Sheet, Rev. 2
12 Freescale Semiconductor
Timing Specif ications
Ta b l e 11. Wr it e C ycle Timi n g 2 (E Controlled)1, 2, 3, 4, 5
Parameter Symbol Min Max Unit
Write cycle time6tAVAV 35 — ns
Address set-up time tAVEL 0—ns
Address valid to end of write (G high) tAVEH 18 — ns
Address valid to end of write (G low) tAVEH 20 — ns
Enable to end of write (G high) tELEH
tELWH 15 — ns
Enable to end of write (G low)7, 8 tELEH
tELWH 15 — ns
Da ta val id to e n d of wr ite t DVEH 10 — ns
Data hold ti me tEHDX 0—ns
Wri te recovery tim e t EHAX 12 — ns
NOTES:
1A writ e occurs during the ove rl ap of E lo w and W low.
2Due to product sensitivities to noise, power supplies must be properly grounded and decoupled
and bus contention conditions must be min imized or el iminated duri ng read and wri te cycles.
3If G goes low at the same time or after W goes low, the output will remain in a high-impedance
state.
4After W, E, or UB/LB has been brought high, the signal must remain in steady-state high for a
minimum of 2 ns.
5The minimum time between E being asserted low in one cycle to E being asserted low in a
subsequent cycle is the same as the mini mu m cy cle ti me all owed for the device.
6All write cyc le timings are referenced fro m the last val id address to the first tr ansition addr ess.
7If E goes low at the same time or after W goes low, the outp ut will remain in a high-imped ance state.
8If E goes high at the same time or before W goes high, the output will rem ain in a high-im pedance
state.
Timing Specif ications
MR0A16A Advanc ed Information Data Sheet, Rev. 2
Freescale Semiconductor 13
Figur e 7. Wr i te Cycl e 2 (E Controlled)
tAVAV
tAVEH
A (ADDRESS)
DATA VALID
E (CHIP ENABLE)
W (WRITE ENABLE)
LB, UB (BYTE ENAB LE)
Q (DATA OUT)
D (DATA IN)
tEHAX
Hi-Z
tELEH
tDVEH
tAVEL tELWH
tEHDX
MR0A16A Advanc ed Information Data Sheet, Rev. 2
14 Freescale Semiconductor
Timing Specif ications
Ta ble 1 2. Wri te C ycle Timing 3 (L B /UB Controlled)1, 2, 3, 4, 5, 6
Parameter Symbol Min Max Unit
Write cycle time7tAVAV 35 — ns
Address set-u p tim e tAVBL 0—ns
Address valid to end of write (G high) tAVBH 18 — ns
Address valid to end of write (G low) tAVBH 20 — ns
Byte pulse width (G high) tBLEH
tBLWH 15 — ns
Byte pulse width (G lo w) tBLEH
tBLWH 15 — ns
Da ta val id to end of w rite t DVBH 10 — ns
Data hold time tBHDX 0—ns
Write recovery time tBHAX 12 — ns
NOTES:
1A writ e occurs during the overlap of E low and W low.
2Due to product sensiti vi ties to noise, power supplies must be properl y grounded and decoupled and
bus contention condit ions must be minimized or elim inated during r ead and wri te cycles.
3If G goes low at the same ti m e or afte r W goes low, the output will rem ain in a high-im pedance state.
4After W, E , o r UB/LB has b een b rought high, the si gnal m ust remain in steady- st ate hi gh for a mi nimum
of 2 ns.
5If both byte control signals are asserted, the two signals must have no more than 2 ns skew between
them.
6The mini mum time between E bei ng asser ted low in one cycle t o E being as ser ted low i n a subsequ ent
cycle is the same as the minimum cycle t ime allowed for the device.
7All write cycl e ti m ings are refe renced fr om the l ast valid address to the first tr ansition address.
Timing Specif ications
MR0A16A Advanc ed Information Data Sheet, Rev. 2
Freescale Semiconductor 15
Figure 8. Write Cycle 3 (LB/UB Controlled)
MR0A16A Advanc ed Information Data Sheet, Rev. 2
16 Freescale Semiconductor
Orderi ng Inf ormation
Ordering Information
This prod uc t i s a va ilable in Commerc ial, In dustri al, and Ext ende d t em pera tu re vers ions.
Freescale 's semiconductor products can be classified into the fo llowing tiers: “ Commercial”, “Industrial”
and “Extended.” A product should only be used in applications appropriate to its tier as shown below. For
question s, please contact a Freescale sale s representative.
•Commercial — Typically 5 year applications - personal computers, PDA's, portable telecom
products, consumer electronics, etc.
•Industria l, Ex tende d — Typically 10 year applications - installed telecom equipment,
workstations, servers, etc. These products can also be used in Commercial applications.
Par t Numb ering Syst em
Pack age Info r mat ion
Tabl e 13. Package Informatio n
Device Pin
Count P ackage
Type Designator Case No. Documen t No. RoHS
Compliant
MR0A16A 44 TSOP
Type II YS 924A-02 98ASS23673W True
(Order by Full Part Number)
MR
Freescale MRAM Memory Prefix
Densit y Code (0 = 1 Mb, 1 = 2 Mb,
Timing Set (35 = 35 ns)
Revisi on (A = rev 1)
I/O Configuration (08 = 8 bits, 16 = 16 bits)
016A A V YS 35
Memory Type (A = async, S = sync)
2 = 4 Mb, 4 = 16 Mb)
Package Type (YS = TSOP II)
Operati ng Tem perature Range
(Missing = 0°C to 70°C,
C = -40°C to 85 °C, V = -40 °C to 105°C)
Revision History
MR0A16A Advanc ed Information Data Sheet, Rev. 2
Freescale Semiconductor 17
Revision History
Mechanical Drawing
The following pages detail the package available to MR0A16A.
R evision History
Revision Date Description of Change
0 18 Jun 2007 Initial Advance Informat ion Release
1 21 Sep 2007 Page 1: Removed Advance In format ion label next to Data Sheet.
Table 6: Applied values to TBD’ s in IDD specifications.
2 12 Nov 2007 Table 2: Changed IDDA to IDDR or IDDW.
MR0A16A Advanc ed Information Data Sheet, Rev. 2
18 Freescale Semiconductor
Mech anical Drawing
Mecha nical Drawing
MR0A16A Advanc ed Information Data Sheet, Rev. 2
Freescale Semiconductor 19
MR0A16A Advanc ed Information Data Sheet, Rev. 2
20 Freescale Semiconductor
Mech anical Drawing
Mecha nical Drawing
MR0A16A Advanc ed Information Data Sheet, Rev. 2
Freescale Semiconductor 21
MR0A16A
Rev. 2, 11/2007
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