32 Mbit (x8/x16) Concurrent SuperFlash SST36VF3203 / SST36VF3204 SST36VF3201C / 1602C32Mb (x8/x16) Concurrent SuperFlash Data Sheet FEATURES: * Organized as 2M x16 or 4M x8 * Dual Bank Architecture for Concurrent Read/Write Operation - 32 Mbit Bottom Sector Protection (in the smaller bank) - SST36VF3203: 8 Mbit + 24 Mbit - 32 Mbit Top Sector Protection (in the smaller bank) - SST36VF3204: 24 Mbit + 8 Mbit * Single 2.7-3.6V for Read and Write Operations * Superior Reliability - Endurance: 100,000 cycles (typical) - Greater than 100 years Data Retention * Low Power Consumption: - Active Current: 6 mA typical - Standby Current: 4 A typical - Auto Low Power Mode: 4 A typical * Hardware Sector Protection/WP# Input Pin - Protects 8 KWord in the smaller bank by driving WP# low and unprotects by driving WP# high * Hardware Reset Pin (RST#) - Resets the internal state machine to reading array data * Byte# Pin - Selects 8-bit or 16-bit mode * Sector-Erase Capability - Uniform 2 KWord sectors * Chip-Erase Capability * Block-Erase Capability - Uniform 32 KWord blocks * Erase-Suspend / Erase-Resume Capabilities * Security ID Feature - SST: 128 bits - User: 256 Bytes * Fast Read Access Time - 70 ns * Latched Address and Data * Fast Erase and Program (typical): - Sector-Erase Time: 18 ms - Block-Erase Time: 18 ms - Chip-Erase Time: 35 ms - Program Time: 7 s * Automatic Write Timing - Internal VPP Generation * End-of-Write Detection - Toggle Bit - Data# Polling - Ready/Busy# pin * CMOS I/O Compatibility * Conforms to Common Flash Memory Interface (CFI) * JEDEC Standards - Flash EEPROM Pinouts and command sets * Packages Available - 48-ball TFBGA (6mm x 8mm) - 48-lead TSOP (12mm x 20mm) * All non-Pb (lead-free) devices are RoHS compliant PRODUCT DESCRIPTION The SST36VF320x are 2M x16 or 4M x8 CMOS Concurrent Read/Write Flash Memory manufactured with SST's proprietary, high performance CMOS SuperFlash technology. The split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The devices write (Program or Erase) with a 2.7-3.6V power supply and conform to JEDEC standard pinouts for x8/x16 memories. Featuring high performance Word-Program, these devices provide a typical Program time of 7 sec and use the Toggle Bit, Data# Polling, or RY/BY# to detect the completion of the Program or Erase operation. To protect against inadvertent write, the devices have on-chip hardware and Software Data Protection schemes. Designed, manufactured, (c)2009 Silicon Storage Technology, Inc. S71270-04-000 11/09 1 and tested for a wide spectrum of applications, these devices are offered with a guaranteed endurance of 10,000 cycles. Data retention is rated at greater than 100 years. These devices are suited for applications that require convenient and economical updating of program, configuration, or data memory. For all system applications, the devices significantly improve performance and reliability, while lowering power consumption. Since for any given voltage range, the SuperFlash technology uses less current to program and has a shorter erase time, the total energy consumed during any Erase or Program operation is less than alternative flash technologies. These devices also improve flexibility while lowering the cost for program, data, and configuration storage applications. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. CSF is a trademark of Silicon Storage Technology, Inc. These specifications are subject to change without notice. 32 Mbit Concurrent SuperFlash SST36VF3203 / SST36VF3204 Data Sheet Read Operation SuperFlash technology provides fixed Erase and Program times, independent of the number of Erase/Program cycles that have occurred. Therefore the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Program times increase with accumulated Erase/Program cycles. The Read operation is controlled by CE# and OE#; both have to be low for the system to obtain data from the outputs. CE# is used for device selection. When CE# is high, the chip is deselected and only standby power is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in a high impedance state when either CE# or OE# is high. Refer to the Read cycle timing diagram for further details (Figure 4). To meet high-density, surface-mount requirements, these devices are offered in 48-ball TFBGA and 48-lead TSOP packages. See Figures 2 and 3 for pin assignments. Program Operation Device Operation These devices are programmed on a word-by-word or byte-by-byte basis depending on the state of the BYTE# pin. Before programming, one must ensure that the sector which is being programmed is fully erased. Memory operation functions are initiated using standard microprocessor write sequences. A command is written by asserting WE# low while keeping CE# low. The address bus is latched on the falling edge of WE# or CE#, whichever occurs last. The data bus is latched on the rising edge of WE# or CE#, whichever occurs first. The Program operation is accomplished in three steps: 1. Software Data Protection is initiated using the three-byte load sequence. Auto Low Power Mode 2. Address and data are loaded. These devices also have the Auto Lower Power mode which puts them in a near standby mode within 500 ns after data has been accessed with a valid Read operation. This reduces the IDD active Read current to 4 A typically. While CE# is low, the devices exit Auto Low Power mode with any address transition or control signal transition used to initiate another Read cycle, with no access time penalty. During the Program operation, the addresses are latched on the falling edge of either CE# or WE#, whichever occurs last. The data is latched on the rising edge of either CE# or WE#, whichever occurs first. 3. The internal Program operation is initiated after the rising edge of the fourth WE# or CE#, whichever occurs first. The Program operation, once initiated, will be completed typically within 7 s. Concurrent Read/Write Operation The dual bank architecture of these devices allows the Concurrent Read/Write operation whereby the user can read from one bank while programming or erasing in the other bank. For example, reading system code in one bank while updating data in the other bank. See Figures 5 and 6 for WE# and CE# controlled Program operation timing diagrams and Figure 20 for flowcharts. During the Program operation, the only valid reads are Data# Polling and Toggle Bit. During the internal Program operation, the host is free to perform additional tasks. Any commands issued during an internal Program operation are ignored. Concurrent Read/Write State Bank 1 Bank 2 Read No Operation Read Write Write Read Write No Operation No Operation Read No Operation Write Note: For the purposes of this table, write means to perform Blockor Sector-Erase or Program operations as applicable to the appropriate bank. (c)2009 Silicon Storage Technology, Inc. S71270-04-000 2 11/09 32 Mbit Concurrent SuperFlash SST36VF3203 / SST36VF3204 Data Sheet Sector- (Block-) Erase Operation Erase-Suspend/Erase-Resume Operations These devices offer both Sector-Erase and Block-Erase operations. These operations allow the system to erase the devices on a sector-by-sector (or block-by-block) basis. The sector architecture is based on a uniform sector size of 2 KWord. The Block-Erase mode is based on a uniform block size of 32 KWord. The Sector-Erase operation is initiated by executing a six-byte command sequence with a SectorErase command (50H) and sector address (SA) in the last bus cycle. The Block-Erase operation is initiated by executing a six-byte command sequence with Block-Erase command (30H) and block address (BA) in the last bus cycle. The sector or block address is latched on the falling edge of the sixth WE# pulse, while the command (30H or 50H) is latched on the rising edge of the sixth WE# pulse. The internal Erase operation begins after the sixth WE# pulse. Any commands issued during the Sector- or Block-Erase operation are ignored except Erase-Suspend and EraseResume. See Figures 10 and 11 for timing waveforms. The Erase-Suspend operation temporarily suspends a Sector- or Block-Erase operation thus allowing data to be read from any memory location, or program data into any sector/block that is not suspended for an Erase operation. The operation is executed by issuing a one-byte command sequence with Erase-Suspend command (B0H). The device automatically enters read mode no more than 10 s after the Erase-Suspend command had been issued. (TES maximum latency equals 10 s.) Valid data can be read from any sector or block that is not suspended from an Erase operation. Reading at address location within erasesuspended sectors/blocks will output DQ2 toggling and DQ6 at "1". While in Erase-Suspend mode, a Program operation is allowed except for the sector or block selected for Erase-Suspend. The Software ID Entry command can also be executed. To resume Sector-Erase or Block-Erase operation which has been suspended, the system must issue an Erase-Resume command. The operation is executed by issuing a one-byte command sequence with Erase Resume command (30H) at any address in the last byte sequence. Chip-Erase Operation The devices provide a Chip-Erase operation, which allows the user to erase all sectors/blocks to the "1" state. This is useful when a device must be quickly erased. Write Operation Status Detection These devices provide one hardware and two software means to detect the completion of a Write (Program or Erase) cycle in order to optimize the system Write cycle time. The hardware detection uses the Ready/Busy# (RY/ BY#) output pin. The software detection includes two status bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The End-of-Write detection mode is enabled after the rising edge of WE#, which initiates the internal Program or Erase operation. The Chip-Erase operation is initiated by executing a sixbyte command sequence with Chip-Erase command (10H) at address 555H in the last byte sequence. The Erase operation begins with the rising edge of the sixth WE# or CE#, whichever occurs first. During the Erase operation, the only valid Read is Toggle Bit or Data# Polling. Any commands issued during the Chip-Erase operation are ignored. See Table 7 for the command sequence, Figure 9 for timing diagram, and Figure 23 for the flowchart. When WP# is low, any attempt to Chip-Erase will be ignored. The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a Ready/Busy# (RY/ BY#), a Data# Polling (DQ7), or Toggle Bit (DQ6) Read may be simultaneous with the completion of the Write cycle. If this occurs, the system may get an erroneous result, i.e., valid data may appear to conflict with either DQ7 or DQ6. In order to prevent spurious rejection if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. If both Reads are valid, then the Write cycle has completed, otherwise the rejection is valid. (c)2009 Silicon Storage Technology, Inc. S71270-04-000 3 11/09 32 Mbit Concurrent SuperFlash SST36VF3203 / SST36VF3204 Data Sheet Ready/Busy# (RY/BY#) Toggle Bits (DQ6 and DQ2) The devices include a Ready/Busy# (RY/BY#) output signal. RY/BY# is an open drain output pin that indicates whether an Erase or Program operation is in progress. Since RY/BY# is an open drain output, it allows several devices to be tied in parallel to VDD via an external pull-up resistor. After the rising edge of the final WE# pulse in the command sequence, the RY/BY# status is valid. During the internal Program or Erase operation, any consecutive attempts to read DQ6 will produce alternating "1"s and "0"s, i.e., toggling between 1 and 0. When the internal Program or Erase operation is completed, the DQ6 bit will stop toggling. The device is then ready for the next operation. The toggle bit is valid after the rising edge of the fourth WE# (or CE#) pulse for Program operations. For Sector-, Block-, or Chip-Erase, the toggle bit (DQ6) is valid after the rising edge of sixth WE# (or CE#) pulse. DQ6 will be set to "1" if a Read operation is attempted on an Erase-suspended Sector/Block. If Program operation is initiated in a sector/block not selected in Erase-Suspend mode, DQ6 will toggle. When RY/BY# is actively pulled low, it indicates that an Erase or Program operation is in progress. When RY/BY# is high (Ready), the devices may be read or left in standby mode. Byte/Word (BYTE#) An additional Toggle Bit is available on DQ2, which can be used in conjunction with DQ6 to check whether a particular sector is being actively erased or erase-suspended. Table 1 shows detailed status bit information. The Toggle Bit (DQ2) is valid after the rising edge of the last WE# (or CE#) pulse of a Write operation. See Figure 8 for Toggle Bit timing diagram and Figure 21 for a flowchart. The device includes a BYTE# pin to control whether the device data I/O pins operate x8 or x16. If the BYTE# pin is at logic "1" (VIH) the device is in x16 data configuration: all data I/0 pins DQ0-DQ15 are active and controlled by CE# and OE#. If the BYTE# pin is at logic "0", the device is in x8 data configuration: only data I/O pins DQ0-DQ7 are active and controlled by CE# and OE#. The remaining data pins DQ8DQ14 are at Hi-Z, while pin DQ15 is used as the address input A-1 for the Least Significant Bit of the address bus. TABLE 1: Write Operation Status Status DQ7 DQ6 DQ2 RY/BY# DQ7# Toggle No Toggle 0 Standard Erase 0 Toggle Toggle 0 Read From Erase Suspended Sector/Block 1 1 Toggle 1 Read From Non-Erase Suspended Sector/Block Data Data Data 1 Program DQ7# Toggle N/A Normal Standard Operation Program Data# Polling (DQ7) When the devices are in an internal Program operation, any attempt to read DQ7 will produce the complement of the true data. Once the Program operation is completed, DQ7 will produce true data. During internal Erase operation, any attempt to read DQ7 will produce a `0'. Once the internal Erase operation is completed, DQ7 will produce a `1'. The Data# Polling is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For Sector-, Block-, or Chip-Erase, the Data# Polling is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 7 for Data# Polling (DQ7) timing diagram and Figure 21 for a flowchart. EraseSuspend Mode 0 T1.1 1270 Note: DQ7, DQ6, and DQ2 require a valid address when reading status information. The address must be in the bank where the operation is in progress in order to read the operation status. If the address is pointing to a different bank (not busy), the device will output array data. Data Protection The devices provide both hardware and software features to protect nonvolatile data from inadvertent writes. (c)2009 Silicon Storage Technology, Inc. S71270-04-000 4 11/09 32 Mbit Concurrent SuperFlash SST36VF3203 / SST36VF3204 Data Sheet Hardware Data Protection Software Data Protection (SDP) Noise/Glitch Protection: A WE# or CE# pulse of less than 5 ns will not initiate a Write cycle. These devices provide the JEDEC standard Software Data Protection scheme for all data alteration operations, i.e., Program and Erase. Any Program operation requires the inclusion of the three-byte sequence. The three-byte load sequence is used to initiate the Program operation, providing optimal protection from inadvertent Write operations, e.g., during the system power-up or power-down. Any Erase operation requires the inclusion of the six-byte sequence. The devices are shipped with the Software Data Protection permanently enabled. See Table 7 for the specific software command codes. During SDP command sequence, invalid commands will abort the device to Read mode within TRC. The contents of DQ15-DQ8 can be VIL or VIH, but no other value during any SDP command sequence. VDD Power Up/Down Detection: The Write operation is inhibited when VDD is less than 1.5V. Write Inhibit Mode: Forcing OE# low, CE# high, or WE# high will inhibit the Write operation. This prevents inadvertent writes during power-up or power-down. Hardware Block Protection The devices provide hardware block protection which protects the outermost 8 KWord in the smaller bank. The block is protected when WP# is held low. When WP# is held low and a Block-Erase command is issued to the protected black, the data in the outermost 8 KWord/16 KByte section will be protected. The rest of the block will be erased. See Tables 3 and 4 for Block-Protection location. Common Flash Memory Interface (CFI) These devices also contain the CFI information to describe the characteristics of the devices. In order to enter the CFI Query mode, the system must write the three-byte sequence, same as the Software ID Entry command with 98H (CFI Query command) to address BKX555H in the last byte sequence. In order to enter the CFI Query mode, the system can also use the one-byte sequence with BKX55H on Address and 98H on Data Bus. See Figure 13 for CFI Entry and Read timing diagram. Once the device enters the CFI Query mode, the system can read CFI data at the addresses given in Tables 8 through 10. The system must write the CFI Exit command to return to Read mode from the CFI Query mode. A user can disable block protection by driving WP# high. This allows data to be erased or programmed into the protected sectors. WP# must be held high prior to issuing the Write command and remain stable until after the entire Write operation has completed. If WP# is left floating, it is internally held high via a pull-up resistor, and the Boot Block is unprotected, enabling Program and Erase operations on that block. Hardware Reset (RST#) The RST# pin provides a hardware method of resetting the devices to read array data. When the RST# pin is held low for at least TRP, any in-progress operation will terminate and return to Read mode (see Figure 17) and all output pins are set to High-Z. When no internal Program/Erase operation is in progress, a minimum period of TRHR is required after RST# is driven high before a valid Read can take place (see Figure 16). The Erase operation that has been interrupted needs to be reinitiated after the device resumes normal operation mode to ensure data integrity. (c)2009 Silicon Storage Technology, Inc. S71270-04-000 5 11/09 32 Mbit Concurrent SuperFlash SST36VF3203 / SST36VF3204 Data Sheet Security ID address from the same bank without issuing a new Software ID Entry command. The Software ID Entry command may be written to an address within a bank that is in Read Mode or in Erase-Suspend mode. The Software ID Entry command may not be written while the device is programming or erasing in the other bank. The SST36VF320x devices offer a 136-word Security ID space. The Secure ID space is divided into two segments--one 128-bit factory programmed segment and one 128-word (256-byte) user-programmed segment. The first segment is programmed and locked at SST with a unique, 128-bit number. The user segment is left un-programmed for the customer to program as desired. To program the user segment of the Security ID, the user must use the Security ID Program command. End-of-Write status is checked by reading the toggle bits. Data# Polling is not used for Security ID End-of-Write detection. Once programming is complete, the Sec ID should be locked using the User Sec ID Program Lock-Out. This disables any future corruption of this space. Note that regardless of whether or not the Sec ID is locked, neither Sec ID segment can be erased. The Secure ID space can be queried by executing a three-byte command sequence with Query Sec ID command (88H) at address 555H in the last byte sequence. See Figure 15 for timing diagram. To exit this mode, the Exit Sec ID command should be executed. Refer to Table 7 for more details. TABLE 2: Product Identification BKX0000H 00BFH SST36VF3203 BKX0001H 7354H SST36VF3204 BKX0001H 7353H Manufacturer's ID T2.1 1270 Note: BKX = Bank Address (A20-A18) Product Identification Mode Exit/CFI Mode Exit In order to return to the standard Read mode, the Software Product Identification mode must be exited. Exit is accomplished by issuing the Software ID Exit command sequence, which returns the device to the Read mode. This command may also be used to reset the device to the Read mode after any inadvertent transient condition that apparently causes the device to behave abnormally, e.g., not read correctly. Please note that the Software ID Exit/CFI Exit command is ignored during an internal Program or Erase operation. See Table 7 for the software command code, Figure 14 for timing waveform and Figure 22 for a flowchart. The Product Identification mode identifies the devices and manufacturer. For details, see Table 2 for software operation, Figure 12 for the Software ID Entry and Read timing diagram and Figure 22 for the Software ID Entry command sequence flowchart. The addresses A20 and A18 indicate a bank address. When the addressed bank is switched to Product Identification mode, it is possible to read another Address Buffers Data Device ID Product Identification Memory Address Address (8 KWord / 16 KByte Sector Protection) SuperFlash Memory Bank 1 BYTE# SuperFlash Memory Bank 2 RST# CE# WP# Control Logic I/O Buffers WE# DQ15/A-1 - DQ0 OE# 1270 B01.0 RY/BY# FIGURE 1: Functional Block Diagram (c)2009 Silicon Storage Technology, Inc. S71270-04-000 6 11/09 32 Mbit Concurrent SuperFlash SST36VF3203 / SST36VF3204 Data Sheet TABLE 3: SST36VF3203, 2M x16 CSF Bottom Dual-Bank Memory Organization (1 of 2) SST36VF3203 Block BA0 Bank 1 Bank 2 Block Size Address Range x8 Address Range x16 8 KW / 16 KB 000000H-003FFFH 000000H-001FFFH 24 KW / 48 KB 004000H-00FFFFH 002000H-007FFFH BA1 32 KW / 64 KB 010000H-01FFFFH 008000H-00FFFFH BA2 32 KW / 64 KB 020000H-02FFFFH 010000H-017FFFH BA3 32 KW / 64 KB 030000H-03FFFFH 018000H-01FFFFH BA4 32 KW / 64 KB 040000H-04FFFFH 020000H-027FFFH BA5 32 KW / 64 KB 050000H-05FFFFH 028000H-02FFFFH BA6 32 KW / 64 KB 060000H--06FFFFH 030000H-037FFFH BA7 32 KW / 64 KB 070000H--07FFFFH 038000H-03FFFFH BA8 32 KW / 64 KB 080000H--08FFFFH 040000H-047FFFH BA9 32 KW / 64 KB 090000H--09FFFFH 048000H-04FFFFH BA10 32 KW / 64 KB 0A0000H--0AFFFFH 050000H-057FFFH BA11 32 KW / 64 KB 0B0000H--0BFFFFH 058000H-05FFFFH BA12 32 KW / 64 KB 0C0000H--0CFFFFH 060000H-067FFFH BA13 32 KW / 64 KB 0D0000H--0DFFFFH 068000H-06FFFFH BA14 32 KW / 64 KB 0E0000H--0EFFFFH 070000H-077FFFH BA15 32 KW / 64 KB 0F0000H--0FFFFFH 078000H-07FFFFH BA16 32 KW / 64 KB 100000H--10FFFFH 080000H-087FFFH BA17 32 KW / 64 KB 110000H--11FFFFH 088000H-08FFFFH BA18 32 KW / 64 KB 120000H--12FFFFH 090000H-097FFFH BA19 32 KW / 64 KB 130000H--13FFFFH 098000H-09FFFFH BA20 32 KW / 64 KB 140000H--14FFFFH 0A0000H-0A7FFFH BA21 32 KW / 64 KB 150000H--15FFFFH 0A8000H-0AFFFFH BA22 32 KW / 64 KB 160000H--16FFFFH 0B0000H-0B7FFFH BA23 32 KW / 64 KB 170000H--17FFFFH 0B8000H-0BFFFFH BA24 32 KW / 64 KB 180000H--18FFFFH 0C0000H-0C7FFFH BA25 32 KW / 64 KB 190000H--19FFFFH 0C8000H-0CFFFFH BA26 32 KW / 64 KB 1A0000H--1AFFFFH 0D0000H-0D7FFFH BA27 32 KW / 64 KB 1B0000H--1BFFFFH 0D8000H-0DFFFFH BA28 32 KW / 64 KB 1C0000H--1CFFFFH 0E0000H--0E7FFFH BA29 32 KW / 64 KB 1D0000H--1DFFFFH 0E8000H--0EFFFFH BA30 32 KW / 64 KB 1E0000H--1EFFFFH 0F0000H--0F7FFFH BA31 32 KW / 64 KB 1F0000H--1FFFFFH 0F8000H--0FFFFFH BA32 32 KW / 64 KB 200000H--20FFFFH 100000H--107FFFH BA33 32 KW / 64 KB 210000H--21FFFFH 108000H--10FFFFH BA34 32 KW / 64 KB 220000H--22FFFFH 110000H--117FFFH BA35 32 KW / 64 KB 230000H--23FFFFH 118000H--11FFFFH BA36 32 KW / 64 KB 240000H--24FFFFH 120000H--127FFFH BA37 32 KW / 64 KB 250000H--25FFFFH 128000H--12FFFFH BA38 32 KW / 64 KB 260000H--26FFFFH 130000H--137FFFH BA39 32 KW / 64 KB 270000H--27FFFFH 138000H--13FFFFH BA40 32 KW / 64 KB 280000H--28FFFFH 140000H--147FFFH BA41 32 KW / 64 KB 290000H--29FFFFH 148000H--14FFFFH (c)2009 Silicon Storage Technology, Inc. S71270-04-000 7 11/09 32 Mbit Concurrent SuperFlash SST36VF3203 / SST36VF3204 Data Sheet TABLE 3: SST36VF3203, 2M x16 CSF Bottom Dual-Bank Memory Organization (Continued) (2 of 2) SST36VF3203 Bank 2 Block Block Size Address Range x8 Address Range x16 BA42 32 KW / 64 KB 2A0000H--2AFFFFH 150000H--157FFFH BA43 32 KW / 64 KB 2B0000H-2BFFFFH 158000H-15FFFFH BA44 32 KW / 64 KB 2C0000H-2CFFFFH 160000H-167FFFH BA45 32 KW / 64 KB 2D0000H-2DFFFFH 168000H-16FFFFH BA46 32 KW / 64 KB 2E0000H-2EFFFFH 170000H-177FFFH BA47 32 KW / 64 KB 2F0000H-2FFFFFH 178000H-17FFFFH BA48 32 KW / 64 KB 300000H-30FFFFH 180000H-187FFFH BA49 32 KW / 64 KB 310000H-31FFFFH 188000H-18FFFFH BA50 32 KW / 64 KB 320000H-32FFFFH 190000H-197FFFH BA51 32 KW / 64 KB 330000H-33FFFFH 198000H-19FFFFH BA52 32 KW / 64 KB 340000H-34FFFFH 1A0000H-1A7FFFH BA53 32 KW / 64 KB 350000H-35FFFFH 1A8000H-1AFFFFH BA54 32 KW / 64 KB 360000H-36FFFFH 1B0000H-1B7FFFH BA55 32 KW / 64 KB 370000H-37FFFFH 1B8000H-1BFFFFH BA56 32 KW / 64 KB 380000H-38FFFFH 1C0000H-1C7FFFH BA57 32 KW / 64 KB 390000H-39FFFFH 1C8000H-1CFFFFH BA58 32 KW / 64 KB 3A0000H-3AFFFFH 1D0000H-1D7FFFH BA59 32 KW / 64 KB 3B0000H-3BFFFFH 1D8000H-1DFFFFH BA60 32 KW / 64 KB 3C0000H-3CFFFFH 1E0000H-1E7FFFH BA61 32 KW / 64 KB 3D0000H-3DFFFFH 1E8000H-1EFFFFH BA62 32 KW / 64 KB 3E0000H-3EFFFFH 1F0000H-1F7FFFH BA63 32 KW / 64 KB 3F0000H-3FFFFFH 1F8000H-1FFFFFH T3.0 1270 (c)2009 Silicon Storage Technology, Inc. S71270-04-000 8 11/09 32 Mbit Concurrent SuperFlash SST36VF3203 / SST36VF3204 Data Sheet TABLE 4: SST36VF3204, 2M x16 CSF Top Dual-Bank Memory Organization (1 of 2) SST36VF3204 Bank 2 Block Block Size Address Range x8 Address Range x16 BA0 32 KW / 64 KB 000000H-00FFFFH 000000H-007FFFH BA1 32 KW / 64 KB 010000H-01FFFFH 008000H-00FFFFH BA2 32 KW / 64 KB 020000H-02FFFFH 010000H-017FFFH BA3 32 KW / 64 KB 030000H-03FFFFH 018000H-01FFFFH BA4 32 KW / 64 KB 040000H-04FFFFH 020000H-027FFFH BA5 32 KW / 64 KB 050000H-05FFFFH 028000H-02FFFFH BA6 32 KW / 64 KB 060000H--06FFFFH 030000H-037FFFH BA7 32 KW / 64 KB 070000H--07FFFFH 038000H-03FFFFH BA8 32 KW / 64 KB 080000H--08FFFFH 040000H-047FFFH BA9 32 KW / 64 KB 090000H--09FFFFH 048000H-04FFFFH BA10 32 KW / 64 KB 0A0000H--0AFFFFH 050000H-057FFFH BA11 32 KW / 64 KB 0B0000H--0BFFFFH 058000H-05FFFFH BA12 32 KW / 64 KB 0C0000H--0CFFFFH 060000H-067FFFH BA13 32 KW / 64 KB 0D0000H--0DFFFFH 068000H-06FFFFH BA14 32 KW / 64 KB 0E0000H--0EFFFFH 070000H-077FFFH BA15 32 KW / 64 KB 0F0000H--0FFFFFH 078000H-07FFFFH BA16 32 KW / 64 KB 100000H--10FFFFH 080000H-087FFFH BA17 32 KW / 64 KB 110000H--11FFFFH 088000H-08FFFFH BA18 32 KW / 64 KB 120000H--12FFFFH 090000H-097FFFH BA19 32 KW / 64 KB 130000H--13FFFFH 098000H-09FFFFH BA20 32 KW / 64 KB 140000H--14FFFFH 0A0000H-0A7FFFH BA21 32 KW / 64 KB 150000H--15FFFFH 0A8000H-0AFFFFH BA22 32 KW / 64 KB 160000H--16FFFFH 0B0000H-0B7FFFH BA23 32 KW / 64 KB 170000H--17FFFFH 0B8000H-0BFFFFH BA24 32 KW / 64 KB 180000H--18FFFFH 0C0000H-0C7FFFH BA25 32 KW / 64 KB 190000H--19FFFFH 0C8000H-0CFFFFH BA26 32 KW / 64 KB 1A0000H--1AFFFFH 0D0000H-0D7FFFH BA27 32 KW / 64 KB 1B0000H--1BFFFFH 0D8000H-0DFFFFH BA28 32 KW / 64 KB 1C0000H--1CFFFFH 0E0000H-0E7FFFH BA29 32 KW / 64 KB 1D0000H--1DFFFFH 0E8000H-0EFFFFH BA30 32 KW / 64 KB 1E0000H--1EFFFFH 0F0000H-0F7FFFH BA31 32 KW / 64 KB 1F0000H--1FFFFFH 0F8000H-0FFFFFH BA32 32 KW / 64 KB 200000H--20FFFFH 100000H-107FFFH BA33 32 KW / 64 KB 210000H--21FFFFH 108000H-10FFFFH BA34 32 KW / 64 KB 220000H--22FFFFH 110000H-117FFFH BA35 32 KW / 64 KB 230000H--23FFFFH 118000H-11FFFFH BA36 32 KW / 64 KB 240000H--24FFFFH 120000H-127FFFH BA37 32 KW / 64 KB 250000H--25FFFFH 128000H-12FFFFH BA38 32 KW / 64 KB 260000H--26FFFFH 130000H-137FFFH BA39 32 KW / 64 KB 270000H--27FFFFH 138000H-13FFFFH BA40 32 KW / 64 KB 280000H--28FFFFH 140000H-147FFFH BA41 32 KW / 64 KB 290000H--29FFFFH 148000H-14FFFFH BA42 32 KW / 64 KB 2A0000H--2AFFFFH 150000H-157FFFH (c)2009 Silicon Storage Technology, Inc. S71270-04-000 9 11/09 32 Mbit Concurrent SuperFlash SST36VF3203 / SST36VF3204 Data Sheet TABLE 4: SST36VF3204, 2M x16 CSF Top Dual-Bank Memory Organization (Continued) (2 of 2) SST36VF3204 Bank 2 Bank 1 Block Block Size Address Range x8 Address Range x16 BA43 32 KW / 64 KB 2B0000H-2BFFFFH 158000H-15FFFFH BA44 32 KW / 64 KB 2C0000H-2CFFFFH 160000H-167FFFH BA45 32 KW / 64 KB 2D0000H-2DFFFFH 168000H-16FFFFH BA46 32 KW / 64 KB 2E0000H-2EFFFFH 170000H-177FFFH BA47 32 KW / 64 KB 2F0000H-2FFFFFH 178000H-17FFFFH BA48 32 KW / 64 KB 300000H-30FFFFH 180000H-187FFFH BA49 32 KW / 64 KB 310000H-31FFFFH 188000H-18FFFFH BA50 32 KW / 64 KB 320000H-32FFFFH 190000H-197FFFH BA51 32 KW / 64 KB 330000H-33FFFFH 198000H-19FFFFH BA52 32 KW / 64 KB 340000H-34FFFFH 1A0000H-1A7FFFH BA53 32 KW / 64 KB 350000H-35FFFFH 1A8000H-1AFFFFH BA54 32 KW / 64 KB 360000H-36FFFFH 1B0000H-1B7FFFH BA55 32 KW / 64 KB 370000H-37FFFFH 1B8000H-1BFFFFH BA56 32 KW / 64 KB 380000H-38FFFFH 1C0000H-1C7FFFH BA57 32 KW / 64 KB 390000H-39FFFFH 1C8000H-1CFFFFH BA58 32 KW / 64 KB 3A0000H-3AFFFFH 1D0000H-1D7FFFH BA59 32 KW / 64 KB 3B0000H-3BFFFFH 1D8000H-1DFFFFH BA60 32 KW / 64 KB 3C0000H-3CFFFFH 1E0000H-1E7FFFH BA61 32 KW / 64 KB 3D0000H-3DFFFFH 1E8000H-1EFFFFH BA62 32 KW / 64 KB 3E0000H-3EFFFFH 1F0000H-1F7FFFH 24 KW / 48 KB 3F0000H-3FBFFFH 1F8000H-1FDFFFH 8 KW / 16 KB 3FC000H-3FFFFFH 1FE000H-1FFFFFH BA63 T4.0 1270 (c)2009 Silicon Storage Technology, Inc. S71270-04-000 10 11/09 32 Mbit Concurrent SuperFlash SST36VF3203 / SST36VF3204 Data Sheet TOP VIEW (balls facing down) 6 5 A13 A12 A14 A15 A16 BYTE# A9 A8 NOTE* VSS A10 A11 DQ7 DQ14 DQ13 DQ6 4 WE# RST# NC 3 A19 DQ5 DQ12 VDD DQ4 1 DQ0 DQ8 DQ9 DQ1 A7 A17 A6 A5 A3 A4 A2 A1 A0 A B C D E CE# OE# VSS F G 1270 48-tfbga P1.0 RY/BY# WP# A18 A20 DQ2 DQ10 DQ11 DQ3 2 H Note* = DQ15/A-1 FIGURE 2: Pin Assignments for 48-ball TFBGA (6mm x 8mm) A15 A14 A13 A12 A11 A10 A9 A8 A19 A20 WE# RST# NC WP# RY/BY# A18 A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Standard Pinout Top View Die Up 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16 BYTE# VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VDD DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# VSS CE# A0 1270 48-tsop P02.0 FIGURE 3: Pin Assignments for 48-lead TSOP (12mm x 20mm) (c)2009 Silicon Storage Technology, Inc. S71270-04-000 11 11/09 32 Mbit Concurrent SuperFlash SST36VF3203 / SST36VF3204 Data Sheet TABLE 5: Pin Description Symbol Name A20-A0 Address Inputs Functions To provide memory addresses. During Sector-Erase and Hardware Sector Protection, A20-A11 address lines will select the sector. During Block-Erase A20-A15 address lines will select the block. DQ14-DQ0 Data Input/Output To output data during Read cycles and receive input data during Write cycles Data is internally latched during a Write cycle. The outputs are in tri-state when OE# or CE# is high. DQ15/A-1 DQ15 is used as data I/O pin when in x16 mode (BYTE# = "1") A-1 is used as the LSB address pin when in x8 mode (BYTE# = "0") Data Input/Output and LBS Address CE# Chip Enable To activate the device when CE# is low. OE# Output Enable To gate the data output buffers WE# Write Enable To control the Write operations RST# Hardware Reset To reset and return the device to Read mode RY/BY# Ready/Busy# To output the status of a Program or Erase operation RY/BY# is a open drain output, so a 10K - 100K pull-up resistor is required to allow RY/BY# to transition high indicating the device is ready to read. WP# Write Protect To protect and unprotect top or bottom 8 KWord (4 outermost sectors) from Erase or Program operation. BYTE# Word/Byte Configuration To select 8-bit or 16-bit mode. VDD Power Supply VSS Ground NC No Connection To provide 2.7-3.6V power supply voltage Unconnected pins T5.0 1270 TABLE 6: Operation Modes Selection DQ15-DQ8 Mode RST# DQ7-DQ0 BYTE# = VIH BYTE# = VIL Address VIL VIL VIH VIH DOUT DOUT DQ14-DQ8 = High Z AIN Program VIL VIH VIL VIH DIN DIN DQ15 = A-1 AIN Erase VIL VIH VIL VIH X1 X High Z Sector or Block address, 555H for Chip-Erase VIHC X X VIHC High Z High Z High Z X X VIL X VIH High Z / DOUT High Z / DOUT High Z X X X VIH VIH High Z / DOUT High Z / DOUT High Z X VIL VIL VIH VIH Manufacturer's ID (BFH) Manufacturer's ID (00H) High Z See Table 7 Device ID2 Device ID2 High Z High Z High Z High Z Read Standby Write Inhibit CE# OE# WE# Product Identification Software Mode Reset X X X VIL X T6.1 1270 1. X can be VIL or VIH, but no other value. 2. Device ID = SST36VF3203 = 7354H, SST36VF3204 = 7353H (c)2009 Silicon Storage Technology, Inc. S71270-04-000 12 11/09 32 Mbit Concurrent SuperFlash SST36VF3203 / SST36VF3204 Data Sheet TABLE 7: Software Command Sequence Command Sequence 1st Bus Write Cycle Addr1 Data2 2nd Bus Write Cycle Addr1 Data2 3rd Bus Write Cycle Addr1 4th Bus Write Cycle Data2 Addr1 Data2 Data AAH Word-Program 555H AAH 2AAH 55H 555H A0H WA3 Sector-Erase 555H AAH 2AAH 55H 555H 80H 555H 5th Bus Write Cycle 6th Bus Write Cycle Addr1 Data2 Addr1 Data2 2AAH 55H SAX4 50H 4 30H 10H Block-Erase 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H BAX Chip-Erase 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H 555H Erase-Suspend XXXH B0H Erase-Resume XXXH 30H ID5 Query Sec 555H AAH 2AAH 55H 555H 88H User Security ID Word-Program 555H AAH 2AAH 55H 555H A5H SIWA6 Data User Security ID Program Lock-out7 555H AAH 2AAH 55H 555H 85H XXXH 0000H Software ID Entry8,9 555H AAH 2AAH 55H BKX4 555H 90H CFI Query Entry9 555H AAH 2AAH 55H BKX4 555H 98H CFI Query Entry9 BKX4 55H 98H Software ID Exit/ CFI Exit/ Sec ID Exit10,11 555H AAH 2AAH 55H 555H F0H Software ID Exit/ CFI Exit/ Sec ID Exit10,11 XXH F0H T7.1 1270 1. Address format A10-A0 (Hex), Addresses A20-A11 can be VIL or VIH, but no other value (unless otherwise stated), for the command sequence when in x16 mode. When in x8 mode, Addresses A20-A12, Address A-1, and DQ14-DQ8 can be VIL or VIH, but no other value (unless otherwise stated), for the command sequence. 2. DQ15-DQ8 can be VIL or VIH, but no other value, for the command sequence 3. WA = Program word address 4. SAX for Sector-Erase; uses A20-A11 address lines BAX for Block-Erase; uses A20-A15 address lines BKX for Bank Address; uses A20-A18 address lines 5. For SST36VF3203 the Security ID Address Range is: (x16 mode) = 100000H to 100087H,(x8 mode) = 100000H to 10010FH SST ID is read at Address Range(x16 mode) = 100000H to 100007H (x8 mode) = 100000H to 10000FH User ID is read at Address Range(x16 mode) = 100008H to 100087H (x8 mode) = 100010H to 10010FH Lock status is read at Address 1000FFH (x16) or 1001FFH (x8). Unlocked: DQ3 = 1 / Locked: DQ3 = 0. For SST36VF3204 the Security ID Address Range is:(x16 mode) = 000000H to 000087H, (x8 mode) = 000000H to 00010FH SST ID is read at Address Range (x16 mode) = 000000H to 000007H (x8 mode) = 000000H to 00000FH User ID is read at Address Range (x16 mode) = 000008H to 000087H (x8 mode) = 000010H to 00010FH Lock Status is read at Address 0000FFH (x16) or 0001FFH (x8). Unlocked: DQ3 = 1 / Locked: DQ3 = 0 6. SIWA = Valid Word addresses for user Sec ID For SST36VF3203 User ID valid Address Range is (x16 mode) = 100008H-100087H (x8 mode) = 100010H-10010FH. For SST36VF3204 User ID valid Address Range is (x16 mode) = 000008H-000087H (x8 mode) = 000010H-00010FH. All 4 cycles of User Security ID Program and Program Lock-out must be completed before going back to Read-Array mode. 7. The User Security ID Program Lock-out command must be executed in x16 mode (BYTE#=VIH). 8. The device does not remain in Software Product Identification mode if powered down. 9. A20, A19, and A18 = BKX (Bank Address): address of the bank that is switched to Software ID/CFI Mode With A17-A1 = 0;SST Manufacturer's ID = 00BFH, is read with A0 = 0 SST36VF3203 Device ID = 7354H, is read with A0 = 1 SST36VF3204 Device ID = 7353H, is read with A0 = 1 10. Both Software ID Exit operations are equivalent 11. If users never lock after programming, User Sec ID can be programmed over the previously unprogrammed bits (data=1) using the User Sec ID mode again (the programmed "0" bits cannot be reversed to "1"). (c)2009 Silicon Storage Technology, Inc. S71270-04-000 13 11/09 32 Mbit Concurrent SuperFlash SST36VF3203 / SST36VF3204 Data Sheet TABLE 8: CFI Query Identification String1 Address x16 Mode 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH Address x8 Mode 20H 22H 24H 26H 28H 2AH 2CH 2EH 30H 32H 34H Data2 0051H 0052H 0059H 0002H 0000H 0000H 0000H 0000H 0000H 0000H 0000H Description Query Unique ASCII string "QRY" Primary OEM command set Address for Primary Extended Table Alternate OEM command set (00H = none exists) Address for Alternate OEM extended Table (00H = none exits) T8.1 1270 1. Refer to CFI publication 100 for more details. 2. In x8 mode, only the lower byte of data is output. TABLE 9: System Interface Information Address x16 Mode Address x8 Mode Data1 Description 1BH 36H 0027H VDD Min (Program/Erase) 1CH 38H 0036H VDD Max (Program/Erase) DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts 1DH 3AH 0000H VPP min (00H = no VPP pin) 1EH 3CH 0000H VPP max (00H = no VPP pin) 1FH 3EH 0004H Typical time out for Program 2N s (24 = 16 s) 20H 40H 0000H Typical time out for min size buffer program 2N s (00H = not supported) 21H 42H 0004H Typical time out for individual Sector/Block-Erase 2N ms (24 = 16 ms) 22H 44H 0006H Typical time out for Chip-Erase 2N ms (26 = 64 ms) 23H 46H 0001H Maximum time out for Program 2N times typical (21 x 24 = 32 s) 24H 48H 0000H Maximum time out for buffer program 2N times typical 25H 4AH 0001H Maximum time out for individual Sector-/Block-Erase 2N times typical (21 x 24 = 32 ms) 26H 4CH 0001H Maximum time out for Chip-Erase 2N times typical (21 x 26 = 128 ms) T9.0 1270 1. In x8 mode, only the lower byte of data is output. (c)2009 Silicon Storage Technology, Inc. S71270-04-000 14 11/09 32 Mbit Concurrent SuperFlash SST36VF3203 / SST36VF3204 Data Sheet TABLE 10: Device Geometry Information Address x16 Mode 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H Address x8 Mode 4EH 50H 52H 54H 56H 58H 5AH 5CH 5EH 60H 62H 64H 66H 68H Data1 0016H 0002H 0000H 0000H 0000H 0002H 003FH 0000H 0000H 0001H 00FFH 0003H 0010H 0000H Description Device size = 2N Bytes (16H = 22; 222 = 4 MByte) Flash Device Interface description; 0002H = x8/x16 asynchronous interface Maximum number of bytes in multi-byte write = 2N (00H = not supported) Number of Erase Sector/Block sizes supported by device Block Information (y + 1 = Number of blocks; z x 256B = block size) y = 63 + 1 = 64 blocks (003FH = 63) z = 256 x 256 Bytes = 64 KByte/block (0100H = 256) Sector Information (y + 1 = Number of sectors; z x 256B = sector size) y = 1023 + 1 = 1024 sectors (03FFH = 1023) z = 16 x 256 Bytes = 4 KByte/sector (0010H = 16) T10.2 1270 1. In x8 mode, only the lower byte of data is output. (c)2009 Silicon Storage Technology, Inc. S71270-04-000 15 11/09 32 Mbit Concurrent SuperFlash SST36VF3203 / SST36VF3204 Data Sheet Absolute Maximum Stress Ratings (Applied conditions greater than those listed under "Absolute Maximum Stress Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55C to +125C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to +150C D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0V to VDD+2.0V Package Power Dissipation Capability (TA = 25C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W Surface Mount Solder Reflow Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C for 10 seconds Output Short Circuit Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Operating Range Range Ambient Temp VDD Extended -20C to +85C 2.7-3.6V Industrial -40C to +85C 2.7-3.6V AC Conditions of Test Input Rise/Fall Time . . . . . . . . . . . . . . 5 ns Output Load . . . . . . . . . . . . . . . . . . . . CL = 30 pF See Figures 18 and 19 (c)2009 Silicon Storage Technology, Inc. S71270-04-000 16 11/09 32 Mbit Concurrent SuperFlash SST36VF3203 / SST36VF3204 Data Sheet TABLE 11: DC Operating Characteristics VDD = 2.7-3.6V Limits Symbol Parameter IDD1 Active VDD Current Read Freq Min Max Units 5 MHz 15 mA 1 MHz 4 mA Program and Erase Concurrent Read/Write 30 mA 5 MHz 45 mA 1 MHz 35 mA Test Conditions CE#=VIL, WE#=OE#=VIH CE#=WE#=VIL, OE#=VIH CE#=VIL, OE#=VIH ISB Standby VDD Current 20 A CE#, RST#=VDD0.3V IALP Auto Low Power VDD Current 20 A CE#=0.1V, VDD=VDD Max WE#=VDD-0.1V Address inputs=0.1V or VDD-0.1V IRT Reset VDD Current 20 A RST#=GND ILI Input Leakage Current 1 A VIN =GND to VDD, VDD=VDD Max ILIW Input Leakage Current on WP# pin and RST# pin 10 A WP#=GND to VDD, VDD=VDD Max RST#=GND to VDD, VDD=VDD Max ILO Output Leakage Current 1 A VOUT =GND to VDD, VDD=VDD Max VIL Input Low Voltage 0.8 V VDD=VDD Min VILC Input Low Voltage (CMOS) 0.3 V VDD=VDD Max VIH Input High Voltage 0.7 VDD VDD+0.3 V VDD=VDD Max VIHC Input High Voltage (CMOS) VDD-0.3 VDD+0.3 V VDD=VDD Max VOL Output Low Voltage 0.2 V IOL=100 A, VDD=VDD Min VOH Output High Voltage V IOH=-100 A, VDD=VDD Min VDD-0.2 T11.1 1270 1. Address input = VILT/VIHT, VDD=VDD Max (See Figure 18) TABLE 12: Recommended System Power-up Timings Symbol TPU-READ Parameter 1 TPU-WRITE1 Minimum Units Power-up to Read Operation 100 s Power-up to Write Operation 100 s T12.0 1270 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 13: Capacitance (TA = 25C, f=1 Mhz, other pins open) Parameter Description Test Condition Maximum CI/O1 I/O Pin Capacitance VI/O = 0V 10 pF Input Capacitance VIN = 0V 10 pF CIN 1 T13.0 1270 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 14: Reliability Characteristics Symbol NEND 1 Parameter Minimum Specification Endurance TDR1 Data Retention ILTH1 Latch Up Units Test Method 10,000 Cycles JEDEC Standard A117 100 Years JEDEC Standard A103 100 + IDD mA JEDEC Standard 78 T14.0 1270 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. (c)2009 Silicon Storage Technology, Inc. S71270-04-000 17 11/09 32 Mbit Concurrent SuperFlash SST36VF3203 / SST36VF3204 Data Sheet AC CHARACTERISTICS TABLE 15: Read Cycle Timing Parameters VDD = 2.7-3.6V Symbol Parameter TRC Read Cycle Time TCE Chip Enable Access Time 70 TAA Address Access Time 70 ns TOE Output Enable Access Time 35 ns TCLZ1 CE# Low to Active Output 0 ns TOLZ1 OE# Low to Active Output 0 ns TCHZ1 CE# High to High-Z Output 16 ns TOHZ1 OE# High to High-Z Output 16 ns TOH1 Output Hold from Address Change 0 ns TRP1 RST# Pulse Width 500 ns RST# High before Read 50 TRHR 1 TRY1,2 Min Max Units 70 RST# Pin Low to Read Mode ns ns ns 20 s T15.1 1270 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. 2. This parameter applies to Sector-Erase, Block-Erase, and Program operations. This parameter does not apply to Chip-Erase operations. TABLE 16: Program/Erase Cycle Timing Parameters Symbol Parameter TBP Program Time TAS Address Setup Time 0 ns TAH Address Hold Time 40 ns TCS WE# and CE# Setup Time 0 ns TCH WE# and CE# Hold Time 0 ns TOES OE# High Setup Time 0 ns TOEH OE# High Hold Time 10 ns TCP CE# Pulse Width 40 ns TWP WE# Pulse Width 40 ns TWPH1 WE# Pulse Width High 30 ns TCPH1 CE# Pulse Width High 30 ns TDS Data Setup Time 30 ns TDH1 Data Hold Time 0 ns TIDA 1 Min Max Units 10 s Software ID Access and Exit Time 150 ns TSE Sector-Erase 25 ms TBE Block-Erase 25 ms TSCE Chip-Erase 50 ms TES Erase-Suspend Latency 10 s TBY1,2 RY/BY# Delay Time 90 ns TBR1 Bus Recovery Time 0 s T16.1 1270 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. 2. This parameter applies to Sector-Erase, Block-Erase, and Program operations. This parameter does not apply to Chip-Erase operations. (c)2009 Silicon Storage Technology, Inc. S71270-04-000 18 11/09 32 Mbit Concurrent SuperFlash SST36VF3203 / SST36VF3204 Data Sheet TAA TRC ADDRESSES TCE CE# TOE OE# TOHZ TOLZ VIH WE# TCLZ TOH HIGH-Z DQ15-0 DATA VALID TCHZ DATA VALID HIGH-Z 1270 F03.0 FIGURE 4: Read Cycle Timing Diagram 555 ADDRESSES 2AA 555 ADDR TAH TWP WE# TAS TWPH OE# TCH CE# TBY TCS TBR RY/BY# TDS TDH DQ15-0 XXAA XX55 XXA0 DATA WORD (ADDR/DATA) VALID 1270 F04.0 Note: X can be VIL or VIH, but no other value. FIGURE 5: WE# Controlled Program Cycle Timing Diagram (c)2009 Silicon Storage Technology, Inc. S71270-04-000 19 11/09 32 Mbit Concurrent SuperFlash SST36VF3203 / SST36VF3204 Data Sheet TBP 555 TAH ADDRESSES 2AA 555 ADDR TCP CE# TAS TCPH OE# TCH WE# TBY TCS TBR RY/BY# TDS TDH XXAA DQ15-0 XX55 XXA0 VALID DATA WORD (ADDR/DATA) 1270 F05.0 Note: X can be VIL or VIH, but no other value. FIGURE 6: CE# Controlled Program Cycle Timing Diagram ADDRESS TCE CE# TOEH TOES OE# TOE WE# TBY RY/BY# DQ7 DATA DATA# DATA# DATA 1270 F06.0 FIGURE 7: Data# Polling Timing Diagram (c)2009 Silicon Storage Technology, Inc. S71270-04-000 20 11/09 32 Mbit Concurrent SuperFlash SST36VF3203 / SST36VF3204 Data Sheet ADDRESSES TCE CE# TOEH TOE OE# WE# TBR DQ6 VALID DATA TWO READ CYCLES WITH SAME OUTPUTS 1270 F07.0 FIGURE 8: Toggle Bit Timing Diagram TSCE SIX-BYTE CODE FOR CHIP-ERASE ADDRESSES 555 2AA 555 555 2AA 555 CE# OE# TWP WE# TBY TBR RY/BY# DQ15-0 XXAA XX55 XX80 XXAA XX55 XX10 VALID 1270 F08.0 Note: This device also supports CE# controlled Chip-Erase operation. The WE# and CE# signals are interchageable as long as minimum timings are met. (See Table 16) X can be VIL or VIH, but no other value. FIGURE 9: WE# Controlled Chip-Erase Timing Diagram (c)2009 Silicon Storage Technology, Inc. S71270-04-000 21 11/09 32 Mbit Concurrent SuperFlash SST36VF3203 / SST36VF3204 Data Sheet TBE SIX-BYTE CODE FOR BLOCK-ERASE ADDRESSES 555 2AA 555 555 2AA BAX CE# OE# TWP WE# TBR TBY RY/BY# DQ15-0 XXAA XX55 XX80 XXAA XX55 VALID XX30 1270 F09.0 Note: This device also supports CE# controlled Block-Erase operation. The WE# and CE# signals are interchageable as long as minimum timings are met. (See Table 16) BAX = Block Address X can be VIL or VIH, but no other value. FIGURE 10: WE# Controlled Block-Erase Timing Diagram TSE SIX-BYTE CODE FOR SECTOR-ERASE ADDRESSES 555 2AA 555 555 2AA SAX CE# OE# TWP WE# TBY TBR RY/BY# DQ15-0 XXAA XX55 XX80 XXAA XX55 XX50 VALID 1270 F10.0 Note: This device also supports CE# controlled Sector-Erase operation. The WE# and CE# signals are interchageable as long as minimum timings are met. (See Table 16) SAX = Sector Address X can be VIL or VIH, but no other value. FIGURE 11: WE# Controlled Sector-Erase Timing Diagram (c)2009 Silicon Storage Technology, Inc. S71270-04-000 22 11/09 32 Mbit Concurrent SuperFlash SST36VF3203 / SST36VF3204 Data Sheet THREE-BYTE SEQUENCE FOR SOFTWARE ID ENTRY 555 ADDRESSES 2AA 555 0000 0001 CE# OE# TIDA TWP WE# TWPH DQ15-0 XXAA XX55 TAA XX90 00BF Device ID 1270 F11.1 Device ID = 7354H for SST36VF3203 and 7353H for SST36VF3204 Note: X can be VIL or VIH, but no other value. FIGURE 12: Software ID Entry and Read THREE-BYTE SEQUENCE FOR CFI QUERY ENTRY 555 ADDRESSES 2AA 555 CE# OE# TWP TIDA WE# TWPH DQ15-0 XXAA XX55 TAA XX98 1270 F12.0 Note: X can be VIL or VIH, but no other value. FIGURE 13: CFI Entry and Read (c)2009 Silicon Storage Technology, Inc. S71270-04-000 23 11/09 32 Mbit Concurrent SuperFlash SST36VF3203 / SST36VF3204 Data Sheet THREE-BYTE SEQUENCE FOR SOFTWARE ID EXIT AND RESET 555 ADDRESSES 2AA XXAA DQ15-0 555 XX55 XXF0 TIDA CE# OE# TWP WE# TWPH 1270 F13.0 Note: X can be VIL or VIH, but no other value. FIGURE 14: Software ID Exit/CFI Exit THREE-BYTE SEQUENCE FOR CFI QUERY ENTRY 555 ADDRESS AMS-0 2AA 555 CE# OE# TIDA TWP WE# TWPH DQ15-0 TAA XXAA XX55 XX88 SW0 SW1 SW2 1270 F14.1 Note: AMS = Most significant address AMS = A20 for SST39VF3203/3204 WP# must be held in proper logic state (VIL or VIH) 1 s prior to and 1 s after the command sequence X can be VIL or VIH, but no other value. FIGURE 15: Sec ID Entry (c)2009 Silicon Storage Technology, Inc. S71270-04-000 24 11/09 32 Mbit Concurrent SuperFlash SST36VF3203 / SST36VF3204 Data Sheet RY/BY# 0V TRP RST# CE#/OE# TRHR 1270 F15.0 FIGURE 16: RST# Timing Diagram (When no internal operation is in progress) TRY RY/BY# RST# TRP CE# TBR OE# 1270 F16.0 FIGURE 17: RST# Timing Diagram (During Sector- or Block-Erase operation) (c)2009 Silicon Storage Technology, Inc. S71270-04-000 25 11/09 32 Mbit Concurrent SuperFlash SST36VF3203 / SST36VF3204 Data Sheet VIHT INPUT VIT REFERENCE POINTS VOT OUTPUT VILT 1270 F17.0 AC test inputs are driven at VIHT (0.9 VDD) for a logic "1" and VILT (0.1 VDD) for a logic "0". Measurement reference points for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10% 90%) are <5 ns. Note: VIT - VINPUT Test VOT - VOUTPUT Test VIHT - VINPUT HIGH Test VILT - VINPUT LOW Test FIGURE 18: AC Input/Output Reference Waveforms TO TESTER TO DUT CL 1270 F18.0 FIGURE 19: A Test Load Example (c)2009 Silicon Storage Technology, Inc. S71270-04-000 26 11/09 32 Mbit Concurrent SuperFlash SST36VF3203 / SST36VF3204 Data Sheet Start Load data: XXAAH Address: 555H Load data: XX55H Address: 2AAH Load data: XXA0H Address: 555H Load Address/Data Wait for end of Program (TBP, Data# Polling bit, or Toggle bit operation) Program Completed 1270 F19.0 Note: X can be VIL or VIH, but no other value. FIGURE 20: Word-Program Algorithm (c)2009 Silicon Storage Technology, Inc. S71270-04-000 27 11/09 32 Mbit Concurrent SuperFlash SST36VF3203 / SST36VF3204 Data Sheet Internal Timer Toggle Bit Data# Polling Program/Erase Initiated Program/Erase Initiated Program/Erase Initiated Read byte/word Read DQ7 Wait TBP, TSCE, TSE or TBE Read same byte/word Program/Erase Completed No Is DQ7 = true data? Yes No Does DQ6 match? Program/Erase Completed Yes Program/Erase Completed 1270 F20.0 FIGURE 21: Wait Options (c)2009 Silicon Storage Technology, Inc. S71270-04-000 28 11/09 32 Mbit Concurrent SuperFlash SST36VF3203 / SST36VF3204 Data Sheet Software Product ID Entry Command Sequence CFI Query Entry Command Sequence Software ID Exit/ CFI Exit/Sec ID Command Sequence Load data: XXAAH Address: 555H Load data: XXAAH Address: 555H Load data: XXAAH Address: 555H Load data: XX55H Address: 2AAH Load data: XX55H Address: 2AAH Load data: XX55H Address: 2AAH Load data: XX90H Address: 555H Load data: XX98H Address: 555H Load data: XXF0H Address: 555H Wait TIDA Wait TIDA Wait TIDA Read Software ID Read CFI data Return to normal operation X can be VIL or VIH, but no other value 1270 F20.0 FIGURE 22: Software Product ID/CFI/Sec ID Entry Command Flowcharts (c)2009 Silicon Storage Technology, Inc. S71270-04-000 29 11/09 32 Mbit Concurrent SuperFlash SST36VF3203 / SST36VF3204 Data Sheet Chip-Erase Command Sequence Sector-Erase Command Sequence Block-Erase Command Sequence Load data: XXAAH Address: 555H Load data: XXAAH Address: 555H Load data: XXAAH Address: 555H Load data: XX55H Address: 2AAH Load data: XX55H Address: 2AAH Load data: XX55H Address: 2AAH Load data: XX80H Address: 555H Load data: XX80H Address: 555H Load data: XX80H Address: 555H Load data: XXAAH Address: 555H Load data: XXAAH Address: 555H Load data: XXAAH Address: 555H Load data: XX55H Address: 2AAH Load data: XX55H Address: 2AAH Load data: XX55H Address: 2AAH Load data: XX10H Address: 555H Load data: XX50H Address: SAX Load data: XX30H Address: BAX Wait TSCE Wait TSE Wait TBE Chip erased to FFFFH Sector erased to FFFFH Block erased to FFFFH 1270 F22.0 Note: X can be VIL or VIH, but no other value. FIGURE 23: Erase Command Sequence (c)2009 Silicon Storage Technology, Inc. S71270-04-000 30 11/09 32 Mbit Concurrent SuperFlash SST36VF3203 / SST36VF3204 Data Sheet PRODUCT ORDERING INFORMATION SST 36 XX VF XX 320x - 70 XXXX - XXX - 4E XX - B3K - XXX E X Environmental Attribute E1 = non-Pb Package Modifier K = 48 balls or leads Package Type B3 = TFBGA (6mm x 8mm) E =TSOP (type 1, die up, 12mm x 20mm) Temperature Range E = Extended = -20C to +85C I = Industrial = -40C to +85C Minimum Endurance 4 = 10,000 cycles Read Access Speed 70 = 70 ns Bank Split 3 = 8 Mbit + 24 Mbit 4 = 24 Mbit + 8 Mbit Device Density 320 = 2 Mbit x16 or 4 Mbit x8 Voltage V = 2.7-3.6V Product Series 36 = Concurrent SuperFlash 1. Environmental suffix "E" denotes non-Pb solder. SST non-Pb solder devices are "RoHS Compliant". Valid combinations for SST36VF3203 SST36VF3203-70-4E-B3KE SST36VF3203-70-4E-EKE SST36VF3203-70-4I-B3KE SST36VF3203-70-4I-EKE Valid combinations for SST36VF3204 SST36VF3204-70-4E-B3KE SST36VF3204-70-4E-EKE SST36VF3204-70-4I-B3KE SST36VF3204-70-4I-EKE Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations. (c)2009 Silicon Storage Technology, Inc. S71270-04-000 31 11/09 32 Mbit Concurrent SuperFlash SST36VF3203 / SST36VF3204 Data Sheet PACKAGING DIAGRAMS TOP VIEW BOTTOM VIEW 8.00 0.20 5.60 0.45 0.05 (48X) 0.80 6 6 5 5 4.00 4 4 6.00 0.20 3 3 2 2 1 1 0.80 A B C D E F G H A1 CORNER SIDE VIEW H G F E D C B A A1 CORNER 1.10 0.10 0.12 SEATING PLANE 1mm 0.35 0.05 Note: 1. Complies with JEDEC Publication 95, MO-210, variant 'AB-1', although some dimensions may be more stringent. 2. All linear dimensions are in millimeters. 3. Coplanarity: 0.12 mm 4. Ball opening size is 0.38 mm ( 0.05 mm) 48-tfbga-B3K-6x8-450mic-4 48-BALL THIN-PROFILE, FINE-PITCH BALL GRID ARRAY (TFBGA) 6MM X 8MM SST PACKAGE CODE: B3K (c)2009 Silicon Storage Technology, Inc. S71270-04-000 32 11/09 32 Mbit Concurrent SuperFlash SST36VF3203 / SST36VF3204 Data Sheet 1.05 0.95 Pin # 1 Identifier 0.50 BSC 0.27 0.17 12.20 11.80 0.15 0.05 18.50 18.30 DETAIL 1.20 max. 0.70 0.50 20.20 19.80 0- 5 Note: 1. Complies with JEDEC publication 95 MO-142 DD dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in millimeters (max/min). 3. Coplanarity: 0.1 mm 4. Maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads. 0.70 0.50 1mm 48-tsop-EK-8 48-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) 12MM X 20MM SST PACKAGE CODE: EK (c)2009 Silicon Storage Technology, Inc. S71270-04-000 33 11/09 32 Mbit Concurrent SuperFlash SST36VF3203 / SST36VF3204 Data Sheet TABLE 17: Revision History Number Description Date 00 * Initial release of data sheet 01 * * * * * * 02 * * * * * Removed Industrial Grade reference Changed to Data Sheet Removed non-Pb reference Updated Bank information Changes TOE from 30ns to 35ns, Table 15, page 18 May 2006 03 * Re-added Industrial Grade reference Jul 2006 04 * Edited Tby TY/BY# Delay Time in Table 15 on page 18 from 90ns Min to 90ns Max Nov 2009 Feb 2005 Updated "Erase-Suspend/Erase-Resume Operations" on page 3 Updated footnote 5 and added footnote 7 to Table 7 on page 13 Updated CFI Query Identification in Table 8 on page 14 Updated Device Geometry Information in Table 10 on page 15 Updated TES parameter from 20 s to 10 s in Table 16 on page 18 In "Product Ordering Information" on page 31 - Removed all MPNs for packages containing Pb (B3K/EK) - Removed all commercial temperature MPNs - Added extended temperature MPNs for all devices Sep 2005 Silicon Storage Technology, Inc. * 1171 Sonora Court * Sunnyvale, CA 94086 * Telephone 408-735-9110 * Fax 408-735-9036 www.SuperFlash.com or www.sst.com (c)2009 Silicon Storage Technology, Inc. S71270-04-000 34 11/09