1
8, 16, 32 Meg x 72 Buffered DRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice.
DM77_2.p65 – Rev. 3/00 ©2000, Micron Technology, Inc.
8, 16, 32 MEG x 72
BUFFERED DRAM DIMMs
FEATURES
• JEDEC-standard ECC pinout in a 168-pin, dual in-
line memory module (DIMM)
• 64MB (8 Meg x 72), 128MB (16 Meg x 72), and
256MB (32 Meg x 72)
• High-performance CMOS silicon-gate process
• Single +3.3V ±0.3V power supply
• All inputs, outputs, and clocks are LVTTL-compatible
• All inputs are buffered except RAS#
• 4,096-cycle CAS#-BEFORE-RAS# (CBR) refresh
distributed across 64ms
• Extended Data-Out (EDO) PAGE MODE access cycle
OPTIONS MARKING
• Components
SOJ D
TSOP DT
• Package
168-pin DIMM (gold) G
• Refresh Addressing
4,096 (4K) rows Blank
8,192 (8K) rows F
• Module Height
Low profile, 1.65" (256MB only) C
Low profile, 1.25" (128MB only) D
• Timing
50ns access -5
60ns access -6
• Access Cycle
EDO PAGE MODE X
DRAM
MODULE
PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL
1V
SS
43 V
SS
85 V
SS
127 V
SS
2DQ0 44 OE2# 86 DQ36 128 RFU
3DQ1 45 RAS2# 87 DQ37 129 NC/RAS3#*
4DQ2 46 CAS4# 88 DQ38 130 NC/CAS5#*
5DQ3 47 RFU 89 DQ39 131 RFU
6V
DD
48 WE2# 90 V
DD
132 PDE#
7 DQ4 49 V
DD
91 DQ40 133 V
DD
8 DQ5 50 NC 92 DQ41 134 NC
9 DQ6 51 NC 93 DQ42 135 NC
10 DQ7 52 DQ18 94 DQ43 136 DQ54
11 DQ8 53 DQ19 95 DQ44 137 DQ55
12 V
SS
54 V
SS
96 V
SS
138 V
SS
13 DQ9 55 DQ20 97 DQ45 139 DQ56
14 DQ10 56 DQ21 98 DQ46 140 DQ57
15 DQ11 57 DQ22 99 DQ47 141 DQ58
16 DQ12 58 DQ23 100 DQ48 142 DQ59
17 DQ13 59 V
DD
101 DQ49 143 V
DD
18 V
DD
60 DQ24 102 V
DD
144 DQ60
19 DQ14 61 RFU 103 DQ50 145 RFU
20 DQ15 62 RFU 104 DQ51 146 RFU
21 DQ16 63 RFU 105 DQ52 147 RFU
22 DQ17 64 RFU 106 DQ53 148 RFU
23 V
SS
65 DQ25 107 V
SS
149 DQ61
24 NC 66 DQ26 108 NC 150 DQ62
25 NC 67 DQ27 109 NC 151 DQ63
26 V
DD
68 V
SS
110 V
DD
152 V
SS
27 WE0# 69 DQ28 111 RFU 153 DQ64
28 CAS0# 70 DQ29 112 NC/CAS1#* 154 DQ65
29 RFU 71 DQ30 113 RFU 155 DQ66
30 RAS0# 72 DQ31 114 NC/RAS1#* 156 DQ67
31 OE0# 73 V
DD
115 RFU 157 V
DD
32 V
SS
74 DQ32 116 V
SS
158 DQ68
33 A0 75 DQ33 117 A1 159 DQ69
34 A2 76 DQ34 118 A3 160 DQ70
35 A4 77 DQ35 119 A5 161 DQ71
36 A6 78 V
SS
120 A7 162 V
SS
37 A8 79 PD1 121 A9 163 PD2
38 A10 80 PD3 122 A11 164 PD4
39 A12 81 PD5 123 NC (A13) 165 PD6
40 V
DD
82 PD7 124 V
DD
166 PD8
41 RFU 83 ID0 125 RFU 167 ID1
42 RFU 84 V
DD
126 B0 168 V
DD
*256MB version only
PIN ASSIGNMENT
KEY TIMING PARAMETERS
SPEED tRC tRAC tPC tAA tCAC tCAS
-5 84ns 50ns 20ns 30ns 18ns 8ns
-6 104ns 60ns 25ns 35ns 20ns 10ns
NOTE: Pin symbols in parentheses are not used on these
modules but may be used for other modules in this
product family. They are for reference only.
MT9LD(T)872(F)X, MT18LD(T)1672(F)(D)X,
MT36LD(T)3272(C)(F)X
For the latest data sheet, please refer to the Micron Web site:
www.micronsemi.com/datasheets/datasheet.html
Front View (128MB)
168-PIN DIMM
2
8, 16, 32 Meg x 72 Buffered DRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice.
DM77_2.p65 – Rev. 3/00 ©2000, Micron Technology, Inc.
8, 16, 32 MEG x 72
BUFFERED DRAM DIMMs
EDO PAGE MODE
EDO PAGE MODE is an accelerated FAST-PAGE-
MODE cycle. The primary advantage of EDO is the
availability of data-out even after CAS# goes back HIGH.
EDO provides for CAS# precharge time (tCP) to occur
without the output data going invalid. This elimina-
tion of CAS# output control provides for pipeline READs.
FAST-PAGE-MODE modules have traditionally
turned the output buffers off (High-Z) with the rising
edge of CAS#. EDO-PAGE-MODE DRAMs operate like
FAST-PAGE-MODE DRAMs, except data will remain
valid or become valid after CAS# goes HIGH during
READs, provided RAS# and OE# are held LOW. If OE# is
pulsed while RAS# and CAS# are LOW, data will toggle
from valid data to High-Z and back to the same valid
data. If OE# is toggled or pulsed after CAS# goes HIGH
while RAS# remains LOW, data will transition to and
remain High-Z.
During an application, if the DQ outputs are wire
OR’d, OE# must be used to disable idle banks of DRAMs.
Alternatively, pulsing WE# to the idle banks during
CAS# HIGH time will also tristate the outputs. Indepen-
dent of OE# control, the outputs will disable after tOFF,
which is referenced from the rising edge of RAS# or
CAS#, whichever occurs last. (Refer to the
MT4LC16M4H9 DRAM data sheet for additional infor-
mation on EDO functionality.)
REFRESH
Returning RAS# and CAS# HIGH terminates a
memory cycle and decreases chip current to a reduced
standby level. Also, the chip is preconditioned for the
next cycle during the RAS# HIGH time. Correct memory
cell data is preserved by maintaining power and execut-
ing any RAS# cycle (READ, WRITE) or RAS# REFRESH
cycle (RAS#-ONLY, CBR or HIDDEN) so that all 4,096
combinations of RAS# addresses (A0-A11) are executed
at least every 64ms, regardless of sequence. However,
with the RAS#-ONLY REFRESH method some compat-
ibility issues may become apparent (128MB and 256MB
versions only). For example, both 4K and 8K refresh
options require 4,096 CBR REFRESH cycles, yet require
a different number of RAS#-ONLY REFRESH cycles (4K
= 4,096 and 8K = 8,192). JEDEC strongly recommends
the use of CBR REFRESH for these devices. The CBR
REFRESH cycle will invoke the internal refresh counter
for automatic RAS# addressing.
GENERAL DESCRIPTION
The Micron® MT9LD(T)872(F)X, MT18LD(T)1672(F)X,
and MT36LD(T)3272(F)X are randomly accessed 64MB,
128MB, and 256MB memories organized in a x72 con-
figuration. They are specially processed to operate from
3V to 3.6V for low-voltage memory systems.
During READ or WRITE cycles, each bit is uniquely
addressed through the address bits. First, the row ad-
dress is latched by the RAS# signal, then the column
address by CAS#. Two copies of address 0 (A0 and B0)
are defined to allow maximum performance for 4-byte
applications which interleave between two 4-byte banks.
A0 is common to the DRAMs used for DQ0-DQ35, while
B0 is common to the DRAMs used for DQ36-DQ71.
READ and WRITE cycles are selected with the WE#
input. A logic HIGH on WE# dictates read mode, while
a logic LOW on WE# dictates write mode. During a
WRITE cycle, data-in (D) is latched by the falling edge
of WE# or CAS#, whichever occurs last. EARLY WRITE
occurs when WE# goes LOW prior to CAS# going LOW,
and the output pins remain open (High-Z) until the
next CAS# cycle.
PART NUMBERS
REFRESH
PART NUMBER CONFIGURATION ADDRESSING
MT9LD872G-x X 8 Meg x 72 ECC 4K
MT9LDT872G-x X 8 Meg x 72 ECC 4K
MT9LD872FG-x X 8 Meg x 72 ECC 8K
MT9LDT872FG-x X 8 Meg x 72 ECC 8K
MT18LD1672G-x X 16 Meg x 72 ECC 4K
MT18LDT1672G-x X 16 Meg x 72 ECC 4K
MT18LD1672FG-x X 16 Meg x 72 ECC 8K
MT18LDT1672FG-x X 16 Meg x 72 ECC 8K
MT18LDT1672FDG-x X 16 Meg x 72 ECC 8K
MT36LD3272G-x X 32 Meg x 72 ECC 4K
MT36LDT3272G-x X 32 Meg x 72 ECC 4K
MT36LD3272FG-x X 32 Meg x 72 ECC 8K
MT36LDT3272FG-x X 32 Meg x 72 ECC 8K
MT36LD3272CG-x X 32 Meg x 72 ECC 4K
MT36LD3272CFG-x X 32 Meg x 72 ECC 8K
x = speed
3
8, 16, 32 Meg x 72 Buffered DRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice.
DM77_2.p65 – Rev. 3/00 ©2000, Micron Technology, Inc.
8, 16, 32 MEG x 72
BUFFERED DRAM DIMMs
FUNCTIONAL BLOCK DIAGRAM
MT9LD(T)872(F)X (64MB)
NOTE: 1. All inputs with the exception of RAS# are redriven.
2. D = line buffers.
3. Reference designators in this diagram do not necessarily match the actual module.
D
D
D
A12-A1
D
D
D
OE0#
WE0#
CAS0#
RAS0#
D
D
A0
DQ0-DQ7
A1–A11
DQ0-DQ7 DQ0-DQ7
A1–A11
DQ0-DQ7
DQ0-DQ7
A1–A11
A1–A11
DQ0-DQ7
A1–A11
A11
D
A1
A1–A11
DQ0-DQ7
U0
A1–A11
DQ0-DQ7
A1–A11
DQ0-DQ7
DQ64-DQ71
DQ16-DQ23 DQ24-DQ31DQ8-DQ15
DQ48-DQ55 DQ56-DQ63
DQ0-DQ7 DQ32-DQ39
DQ40-DQ47
U5
U4
U3
U2
U7 U8
U1
U6
A1–A11
U0-U8 = MT4LC8M8C2DJ EDO PAGE MODE, SOJ, 4K REFRESH
PDE#
PD1-PD8
E#
PRESENCE
DETECT
GENERATOR
OE2#
WE2#
CAS4#
RAS2#
B0
A0
WE#
OE#
RAS#
CAS#
A0
WE#
OE#
RAS#
CAS#
A0
WE#
OE#
RAS#
CAS#
A0
WE#
OE#
RAS#
CAS#
A0
WE#
OE#
RAS#
CAS#
A0
WE#
OE#
RAS#
CAS#
A0
WE#
OE#
RAS#
CAS#
A0
WE#
OE#
RAS#
CAS#
A0
WE#
OE#
RAS#
CAS#
V
DD
V
SS
U0-U8, BUFFERS
U0-U8, BUFFERS
U0-U8 = MT4LC8M8C2TG EDO PAGE MODE, TSOP, 4K REFRESH
U0-U8 = MT4LC8M8P4DJ EDO PAGE MODE, SOJ, 8K REFRESH
U0-U8 = MT4LC8M8P4TG EDO PAGE MODE, TSOP, 8K REFRESH
4
8, 16, 32 Meg x 72 Buffered DRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice.
DM77_2.p65 – Rev. 3/00 ©2000, Micron Technology, Inc.
8, 16, 32 MEG x 72
BUFFERED DRAM DIMMs
FUNCTIONAL BLOCK DIAGRAM
MT18LD(T)1672(F)X (128MB)
NOTE: 1. All inputs with the exception of RAS# are redriven.
2. D = line buffers.
3. Reference designators in this diagram do not necessarily match the actual module.
D
D
D
D
OE0#
D
D
WE0#
CAS0#
OE2#
WE2#
CAS4#
A12-A1
RAS0#
RAS2#
D
A0
D
B0
A11
D
A1
PDE#
PD1-PD8
E#
PRESENCE-
DETECT
GENERATOR
A1–A11
A0
WE#
OE#
RAS#
CAS# A1–A11
A0
WE#
OE#
RAS#
CAS# A1–A11
A0
WE#
OE#
RAS#
CAS# A1–A11
A0
WE#
OE#
RAS#
CAS# A1–A11
A0
WE#
OE#
RAS#
CAS# A1–A11
A0
WE#
OE#
RAS#
CAS# A1–A11
A0
WE#
OE#
RAS#
CAS# A1–A11
A0
WE#
OE#
RAS#
CAS# A1–A11
A0
WE#
OE#
RAS#
CAS#
A1–A11
A0
WE#
OE#
RAS#
CAS# A1–A11
A0
WE#
OE#
RAS#
CAS# A1–A11
A0
WE#
OE#
RAS#
CAS# A1–A11
A0
WE#
OE#
RAS#
CAS# A1–A11
A0
WE#
OE#
RAS#
CAS# A1–A11
A0
WE#
OE#
RAS#
CAS# A1–A11
A0
WE#
OE#
RAS#
CAS#
DQ0-DQ3
U0
DQ0-DQ3 DQ0-DQ3 DQ0-DQ3 DQ0-DQ3 DQ0-DQ3 DQ0-DQ3
DQ0-DQ3
DQ0-DQ3
U9
DQ0-DQ3
A1–A11
A0
WE#
OE#
RAS#
CAS#
U1 U2 U4 U5 U7
U3 U6 U8
U10 U11 U13 U14 U16 U17
U12 U15
DQ0-DQ3 DQ0-DQ3 DQ0-DQ3 DQ0-DQ3 DQ0-DQ3 DQ0-DQ3
DQ0-DQ3
DQ0-DQ3
DQ0-DQ3 DQ4-DQ7 DQ8-DQ11 DQ12-DQ15 DQ16-DQ19 DQ24-DQ27 DQ32-DQ35
DQ28-DQ31
DQ20-DQ23
DQ36-DQ39 DQ40-DQ43 DQ44-DQ47 DQ48-DQ51 DQ52-DQ55 DQ60-DQ63 DQ68-DQ71
DQ64-DQ67
DQ56-DQ59
A1–A11
A0
WE#
OE#
RAS#
CAS#
V
DD
V
SS
U0-U17, BUFFERS
U0-U17, BUFFERS
U0-U17 = MT4LC16M4H9DJ EDO PAGE MODE, SOJ, 4K REFRESH
U0-U17 = MT4LC16M4H9TG EDO PAGE MODE, TSOP, 4K REFRESH
U0-U17 = MT4LC16M4G3DJ EDO PAGE MODE, SOJ, 8K REFRESH
U0-U17 = MT4LC16M4G3TG EDO PAGE MODE, TSOP, 8K REFRESH
5
8, 16, 32 Meg x 72 Buffered DRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice.
DM77_2.p65 – Rev. 3/00 ©2000, Micron Technology, Inc.
8, 16, 32 MEG x 72
BUFFERED DRAM DIMMs
FUNCTIONAL BLOCK DIAGRAM
MT36LD(T)3272(C)(F)X (256MB)
NOTE: 1. All inputs with the exception of RAS# are redriven.
2. D = line buffers.
3. Reference designators in this diagram do not necessarily match the actual module.
D
D
CAS1#
CAS5#
RAS1#
RAS3#
11 11 11 11 11 11 11 11 11
11 11 11 11 11 11 11 11 11
11 11 11 11 11 11 11 11 11
11 11 11 11 11 11 11 11 11
D
D
D
D
OE0#
D
D
WE0#
CAS0#
OE2#
WE2#
CAS4#
A11-A1
RAS0#
RAS2#
D
A0
D
B0
A11
D
A1
PDE#
PD1-PD8
E#
PRESENCE-
DETECT
GENERATOR
A1–A11
A0
WE#
OE#
RAS#
CAS# A1–A11
A0
WE#
OE#
RAS#
CAS# A1–A11
A0
WE#
OE#
RAS#
CAS# A1–A11
A0
WE#
OE#
RAS#
CAS# A1–A11
A0
WE#
OE#
RAS#
CAS# A1–A11
A0
WE#
OE#
RAS#
CAS# A1–A11
A0
WE#
OE#
RAS#
CAS# A1–A11
A0
WE#
OE#
RAS#
CAS# A1–A11
A0
WE#
OE#
RAS#
CAS#
A1–A11
A0
WE#
OE#
RAS#
CAS# A1–A11
A0
WE#
OE#
RAS#
CAS# A1–A11
A0
WE#
OE#
RAS#
CAS# A1–A11
A0
WE#
OE#
RAS#
CAS# A1–A11
A0
WE#
OE#
RAS#
CAS# A1–A11
A0
WE#
OE#
RAS#
CAS# A1–A11
A0
WE#
OE#
RAS#
CAS# A1–A11
A0
WE#
OE#
RAS#
CAS# A1–A11
A0
WE#
OE#
RAS#
CAS#
A1–A11
A0
WE#
OE#
RAS#
CAS# A1–A11
A0
WE#
OE#
RAS#
CAS# A1–A11
A0
WE#
OE#
RAS#
CAS# A1–A11
A0
WE#
OE#
RAS#
CAS# A1–A11
A0
WE#
OE#
RAS#
CAS# A1–A11
A0
WE#
OE#
RAS#
CAS# A1–A11
A0
WE#
OE#
RAS#
CAS# A1–A11
A0
WE#
OE#
RAS#
CAS# A1–A11
A0
WE#
OE#
RAS#
CAS#
A1–A11
A0
WE#
OE#
RAS#
CAS# A1–A11
A0
WE#
OE#
RAS#
CAS# A1–A11
A0
WE#
OE#
RAS#
CAS# A1–A11
A0
WE#
OE#
RAS#
CAS# A1–A11
A0
WE#
OE#
RAS#
CAS# A1–A11
A0
WE#
OE#
RAS#
CAS# A1–A11
A0
WE#
OE#
RAS#
CAS# A1–A11
A0
WE#
OE#
RAS#
CAS# A1–A11
A0
WE#
OE#
RAS#
CAS#
U18
U27
U9
DQ0-DQ3
U0
DQ0-DQ3 DQ0-DQ3 DQ0-DQ3 DQ0-DQ3 DQ0-DQ3 DQ0-DQ3
DQ0-DQ3
U19 U20 U22 U23 U25
U28 U29 U31 U32 U34 U35
U21
U30
U24
U33
U26
U10 U11 U13 U14 U16 U17
U12 U15
U1 U2 U4 U5 U7
U3 U6 U8
DQ0-DQ3
DQ0-DQ3 DQ0-DQ3 DQ0-DQ3 DQ0-DQ3 DQ0-DQ3 DQ0-DQ3 DQ0-DQ3
DQ0-DQ3
DQ0-DQ3
DQ0-DQ3 DQ0-DQ3 DQ0-DQ3 DQ0-DQ3 DQ0-DQ3 DQ0-DQ3 DQ0-DQ3
DQ0-DQ3
DQ0-DQ3
DQ0-DQ3 DQ0-DQ3 DQ0-DQ3 DQ0-DQ3 DQ0-DQ3 DQ0-DQ3 DQ0-DQ3
DQ0-DQ3
DQ0-DQ3
VDD
VSS
U0-U35, BUFFERS
U0-U35, BUFFERS
DQ0-DQ3 DQ4-DQ7 DQ8-DQ11 DQ12-DQ15 DQ16-DQ19 DQ24-DQ27 DQ32-DQ35
DQ28-DQ31
DQ20-DQ23
DQ36-DQ39 DQ40-DQ43 DQ44-DQ47 DQ48-DQ51 DQ52-DQ55 DQ60-DQ63 DQ68-DQ71
DQ64-DQ67
DQ56-DQ59
DQ0-DQ3 DQ4-DQ7 DQ8-DQ11 DQ12-DQ15 DQ16-DQ19 DQ24-DQ27 DQ32-DQ35
DQ28-DQ31
DQ20-DQ23
DQ36-DQ39 DQ40-DQ43 DQ44-DQ47 DQ48-DQ51 DQ52-DQ55 DQ60-DQ63 DQ68-DQ71
DQ64-DQ67
DQ56-DQ59
U0-U35 = MT4LC16M4T8DJ EDO PAGE MODE, SOJ, 4K REFRESH
U0-U35 = MT4LC16M4T8TG EDO PAGE MODE, TSOP, 4K REFRESH
U0-U35 = MT4LC16M4A7DJ EDO PAGE MODE, SOJ, 8K REFRESH
U0-U35 = MT4LC16M4A7TG EDO PAGE MODE, TSOP, 8K REFRESH
6
8, 16, 32 Meg x 72 Buffered DRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice.
DM77_2.p65 – Rev. 3/00 ©2000, Micron Technology, Inc.
8, 16, 32 MEG x 72
BUFFERED DRAM DIMMs
PIN DESCRIPTIONS
PIN NUMBERS SYMBOL TYPE DESCRIPTION
30, 45, 114, 129 RAS0#-RAS3# Input Row-Address Strobe: RAS# is used to clock in the row-
address bits. Two RAS# inputs allow for one x72 bank or
two x36 banks.
28, 46, 112, 130 CAS0#, CAS1#, Buffered Input Column-Address Strobe: CAS# is used to clock in the
CAS4#, CAS5# column-address bits, enable the DRAM output buffers
and strobe the data inputs on WRITE cycles.
27, 48 WE0#, WE2# Buffered Input Write Enable: WE# is the READ/WRITE control for the DQ
pins. WE0# controls DQ0-DQ35. WE2# controls DQ36-
DQ71. If WE# is LOW prior to CAS# going LOW, the
access is an EARLY WRITE cycle. If WE# is HIGH while
CAS# is LOW, the access is a READ cycle, provided OE# is
also LOW. If WE goes LOW after CAS# goes LOW, then
the cycle is a LATE WRITE cycle. A LATE WRITE cycle is
generally used in conjunction with a READ cycle to form
a READ-MODIFY-WRITE cycle.
31, 44 OE0#, OE2# Buffered Input Output Enable: OE# is the input/output control for the
DQ pins. OE0# controls DQ0-DQ35. OE2# controls DQ36-
DQ71. These signals may be driven, allowing LATE
WRITE cycles.
33-39, 117-122, 126 A0-A12, B0 Buffered Input Address Inputs: These inputs are multiplexed and
clocked by RAS# and CAS#. A0 is common to the DRAMs
used for DQ0-DQ35, while B0 is common to the DRAMs
used for DQ36-DQ71.
2-5, 7-11, 13-17, 19-22, DQ0-DQ71 Input/ Data I/Os: For WRITE cycles, DQ0-DQ71 act as inputs to
52-53, 55-58, 60, 65-67, Output the addressed DRAM location. For READ access cycles,
69-72, 74-77, 86-89, DQ0-DQ71 act as outputs for the addressed DRAM
91-95, 97-101, 103-106, location.
136-137, 139-142, 144,
149-151, 153-156,
158-161
79-82, 163-166 PD1-PD8 Buffered Presence-Detect: These pins are read by the host system
Output and tell the system the DIMM’s personality. They will be
either no connect (1), or they will be driven to V
OL
(0).
29, 41-42, 47, 61-64, RFU –Reserved for Future Use: These pins should be left
111, 113, 115, 125, unconnected.
128, 131, 145-148
6, 18, 26, 40, 49, 59, 73, V
DD
Supply Power Supply: +3.3V ±0.3V.
84, 90, 102, 110, 124,
133, 143, 157, 168
1, 12, 23, 32, 43, 54, V
SS
Supply Ground.
68, 78, 85, 96, 107, 116,
127, 138, 152, 162
83, 167 ID0, ID1 Output ID Bits: ID0 = DIMM type. ID1 = Refresh Mode. These
pins will be either left floating (NC) or they will be
grounded (V
SS
).
132 PDE# Input Presence Detect-Enable: PDE# is the READ control for
the buffered presence-detect pins.
7
8, 16, 32 Meg x 72 Buffered DRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice.
DM77_2.p65 – Rev. 3/00 ©2000, Micron Technology, Inc.
8, 16, 32 MEG x 72
BUFFERED DRAM DIMMs
NOTE: VSS = Ground; VOL = 0; NC = 1.
* This addressing includes a redundant address to allow mixing of 12/10 and 11/11 DRAMs with the same presence-detect
setting.
PRESENCE-DETECT TRUTH TABLE
CHARACTERISTICS PRESENCE-DETECT PIN (PDx)
Module Module Row/Column ID0 ID1
Density Organization Addresses 12345678
0MB No module installed X 1111
8MB 1 Meg x 64/72 10/9 1100
8MB 1 Meg x 64/72 10/10 0010
16MB 2 Meg x 64/72 10/10 1010
16MB 2 Meg x 64/72 11/10 1001
32MB 4 Meg x 64/72 11/10 0101
32MB 4 Meg x 64/72 12*/11* 1101
•64MB 8 Meg x 64/72 12/11 1011
128MB 16 Meg x 64/72 12/11 0111
•128MB 16 Meg x 64/72 12/13/11/12 1111
•256MB 32 Meg x 64/72 12/13/11/12 1000
Operating Mode Fast Page Mode 0
EDO Page Mode 1
Access Timing 80ns 1 0
70ns 0 1
60ns 1 1
50ns 0 0
Refresh Control Standard Vss
Self NC
Data Width, Parity x64, No Parity Vss 1
x72, Parity NC 1
x72, ECC Vss 0
x80, ECC NC 0
8
8, 16, 32 Meg x 72 Buffered DRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice.
DM77_2.p65 – Rev. 3/00 ©2000, Micron Technology, Inc.
8, 16, 32 MEG x 72
BUFFERED DRAM DIMMs
ABSOLUTE MAXIMUM RATINGS*
Voltage on VDD Pin Relative to VSS ......... -1V to +4.6V
Voltage on Inputs or I/O Pins
Relative to VSS ....................................... -1V to +4.6V
Operating Temperature, TA (ambient) ... 0°C to +70°C
Storage Temperature (plastic) ............ -55°C to +125°C
Power Dissipation ................................................. 18W
DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS
(Note: 1) (VDD = +3.3V ±0.3V)
PARAMETER/CONDITION SYMBOL SIZE MIN MAX UNITS NOTES
SUPPLY VOLTAGE VDD ALL 3 3.6 V
INPUT HIGH VOLTAGE: Logic 1; All inputs VIH ALL 2 VDD + 0.3 V 2
INPUT LOW VOLTAGE: Logic 0; All inputs VIL ALL -0.5 0.8 V 2
INPUT LEAKAGE CURRENT: CAS0#, CAS1#, CAS4#,
Any input 0V ≤ VIN ≤ VDD + 0.3V CAS5#, A0-A12, B0, II1ALL -2 2 µA
(All other pins not under test = 0V) WE0#, WE2#,
OE0#, OE2#, PDE#
64MB -9 9
RAS0#-RAS3# II2128MB -18 18 µA
256MB -18 18
OUTPUT LEAKAGE CURRENT: 64MB -5 5
DQ is disabled; DQ0-DQ71 IOZ 128MB -5 5 µA
0V ≤ VOUT ≤ VDD + 0.3V 256MB -10 10
OUTPUT LEVELS: VOH ALL 2.4 –V
Output High Voltage (IOUT = -2mA)
Output Low Voltage (IOUT = 2mA) VOL ALL –0.4 V
*Stresses greater than those listed under “Absolute
Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only, and functional
operation of the device at these or any other conditions
above those indicated in the operational sections of
this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect reliability.
NOTE: 1. All voltages referenced to VSS.
2. VIH overshoot: VIH (MAX) = VDD + 2V for a pulse width ≤ 10ns, and the pulse width cannot be greater than one third of
the cycle rate. VIL undershoot: VIL (MIN) = -2V for a pulse width ≤ 10ns, and the pulse width cannot be greater than
one third of the cycle rate.
9
8, 16, 32 Meg x 72 Buffered DRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice.
DM77_2.p65 – Rev. 3/00 ©2000, Micron Technology, Inc.
8, 16, 32 MEG x 72
BUFFERED DRAM DIMMs
IDD OPERATING CONDITIONS AND MAXIMUM LIMITS
(Notes: 1-3) (VDD = +3.3V ±0.3V)
PARAMETER/CONDITION SYMBOLREFRESH SIZE -5 -6 UNITS NOTES
STANDBY CURRENT: TTL 64MB 66 66
(RAS# = CAS# = VIH)IDD1All 128MB 75 75 mA
256MB 99 99
STANDBY CURRENT: CMOS 64MB 4.5 4.5
(RAS# = CAS# = VDD - 0.2V) IDD2All 128MB 9 9 mA
256MB 18 18
OPERATING CURRENT: Random READ/WRITE 64MB 1,575 1,485
Average power supply current 4K 128MB 3,060 2,880
(RAS#, CAS#, address cycling: tRC = tRC [MIN]) IDD3256MB 3,135 2,955 mA 4, 5
64MB 1,215 1,125
8K 128MB 2,340 2,160
256MB 2,415 2,235
OPERATING CURRENT: EDO PAGE MODE 64MB 1,395 1,125
Average power supply current IDD4All 128MB 2,700 2,160 mA 4, 5
(RAS# = VIL, CAS#, address cycling: tPC = tPC [MIN]) 256MB 2,775 2,235
REFRESH CURRENT: RAS#-ONLY 64MB 1,575 1,485
Average power supply current 4K 128MB 3,060 2,880
(RAS# cycling, CAS# = VIH: tRC = tRC [MIN]) IDD5256MB 3,135 2,955 mA 4, 6
64MB 1,215 1,125
8K 128MB 2,340 2,160
256MB 2,415 2,235
REFRESH CURRENT: CBR 64MB 1,485 1,395
Average power supply current 4K 128MB 2,880 2,700
(RAS#, CAS#, address cycling: tRC = tRC [MIN]) IDD6256MB 2,955 2,778 mA 4, 7
64MB 1,485 1,395
8K 128MB 2,880 2,700
256MB 2,955 2,778
MAX
NOTE: 1. All voltages referenced to VSS.
2. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature
range is ensured.
3. An initial pause of 100µs is required after power-up, followed by eight RAS# REFRESH cycles (RAS#-ONLY or CBR with
WE# HIGH), before proper device operation is ensured. The eight RAS# cycle wake-ups should be repeated any time
the tREF refresh requirement is exceeded.
4. IDD is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time and the
outputs open.
5. Column address changed once each cycle.
6. RAS#-ONLY REFRESH requires that all rows be refreshed at least once every 64ms (4,096 rows for the 4K version and
8,192 rows for the 8K version). CBR REFRESH requires that at least 4,096 cycles be completed every 64ms.
7. Enables on-chip refresh and address counters.
10
8, 16, 32 Meg x 72 Buffered DRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice.
DM77_2.p65 – Rev. 3/00 ©2000, Micron Technology, Inc.
8, 16, 32 MEG x 72
BUFFERED DRAM DIMMs
CAPACITANCE
PARAMETER SYMBOL 64MB 128MB 256MB UNITS
Input Capacitance: A0-A12, B0, WE0#, WE2#, OE0#, OE2# CI1999pF
Input Capacitance: CAS0#, CAS1#, CAS4#, CAS5#, PDE# CI2999pF
Input Capacitance: RAS0#-RAS3# CI339 67 67 pF
Input/Output Capacitance: DQ0-DQ71 CIO 12 12 22 pF
Output Capacitance: PD1-PD8 CO10 10 10 pF
MAX
NOTE: This parameter is sampled. VDD = +3.3V; f = 1 MHz.
11
8, 16, 32 Meg x 72 Buffered DRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice.
DM77_2.p65 – Rev. 3/00 ©2000, Micron Technology, Inc.
8, 16, 32 MEG x 72
BUFFERED DRAM DIMMs
EDO PAGE MODE
AC ELECTRICAL CHARACTERISTICS
(Notes: 5, 6, 7, 8, 9, 10, 11, 12, 31; notes appear on next page and page 13) (VDD = +3.3V ±0.3V)
AC CHARACTERISTICS -5 -6
PARAMETER SYMBOL MIN MAX MIN MAX UNITS NOTES
Access time from column address tAA 30 35 ns 10
Column-address setup to CAS# tACH 12 15 ns
going HIGH during WRITE
Column-address hold time (referenced to RAS#) tAR 36 43 ns 11
Column-address setup time tASC 2 2 ns 12
Row-address setup time tASR 5 5 ns 10
Column address to WE# delay time tAWD 44 51 ns 12, 13
Access time from CAS# tCAC 18 20 ns 10, 14
Column-address hold time tCAH 13 15 ns 10
CAS# pulse width tCAS 8 10,000 10 10,000 ns
CAS# hold time (CBR Refresh) tCHR 6 8 ns 11, 16
CAS# to output in Low-Z tCLZ 2 2 ns 12, 18
Data output hold after CAS# LOW tCOH 3 3 ns
CAS# precharge time tCP 8 10 ns 15
Access time from CAS# precharge tCPA 33 40 ns 10
CAS# to RAS# precharge time tCRP 10 10 ns 10
CAS# hold time tCSH 36 43 ns 11
CAS# setup time (CBR Refresh) tCSR 7 7 ns 12, 16
CAS# to WE# delay time tCWD 30 37 ns 12, 13
WRITE command to CAS# lead time tCWL 8 10 ns
Data-in hold time tDH 13 15 ns 10, 17
Data-in setup time tDS -2 -2 ns 11, 17
Output disable tOD 0 12 0 15 ns 18
Output enable tOE 12 15 ns
OE# hold time from WE# during tOEH 6 8 ns 11
READ-MODIFY-WRITE cycle
OE# HIGH hold time from CAS# HIGH tOEHC 5 10 ns
OE# HIGH pulse width tOEP 5 5 ns
OE# LOW to CAS# HIGH setup time tOES 4 5 ns
Output buffer turn-off delay tOFF 2 17 2 20 ns 19, 20
OE# setup prior to RAS# tORD 0 0 ns
during HIDDEN REFRESH cycle
EDO-PAGE-MODE READ or WRITE cycle time tPC 20 25 ns
PDE# to valid presence-detect data tPD 10 10 ns 21
PDE# inactive to presence-detects inactive tPDOFF 2 2 ns 21
EDO-PAGE-MODE READ-WRITE cycle time tPRWC 49 58 ns 12
Access time from RAS# tRAC 50 60 ns 22
RAS# to column-address delay time tRAD 7 10 ns 23, 24
Row-address hold time tRAH 7 8 ns 11
RAS# pulse width tRAS 50 10,000 60 10,000 ns
RAS# pulse width (EDO PAGE MODE) tRASP 50 125,000 60 125,000 ns
Random READ or WRITE cycle time tRC 84 104 ns
RAS# to CAS# delay time tRCD 9 12 ns 24, 25
12
8, 16, 32 Meg x 72 Buffered DRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice.
DM77_2.p65 – Rev. 3/00 ©2000, Micron Technology, Inc.
8, 16, 32 MEG x 72
BUFFERED DRAM DIMMs
NOTE: 1. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature
range is ensured.
2. An initial pause of 100µs is required after power-up, followed by eight RAS# REFRESH cycles (RAS#-ONLY or CBR with
WE# HIGH), before proper device operation is ensured. The eight RAS# cycle wake-ups should be repeated any time
the tREF refresh requirement is exceeded.
3. AC characteristics assume tT = 2ns for -5 and 2.5ns for -6.
4. VIH (MIN) and VIL (MAX) are reference levels for measuring timing of input signals. Transition times are measured
between VIH and VIL (or between VIL and VIH).
5. In addition to meeting the transition rate specification, all input signals must transit between VIH and VIL (or between
VIL and VIH) in a monotonic manner.
6. If CAS# and RAS# = VIH, data output is High-Z.
7. If CAS# = VIL, data output may contain data from the last valid READ cycle.
8. Measured with a load equivalent to two TTL gates and 100pF and VOL = 0.8V and VOH = 2V.
9. If OE# is tied permanently LOW, LATE WRITE, or READ-MODIFY-WRITE operations are not possible.
10. A +5ns timing skew from the DRAM to the module resulted from the addition of line drivers.
11. A -2ns timing skew from the DRAM to the module resulted from the addition of line drivers.
12. A +2ns timing skew from the DRAM to the module resulted from the addition of line drivers.
13. tWCS, tRWD, tAWD and tCWD are not restrictive operating parameters. tWCS applies to EARLY WRITE cycles. If tWCS > tWCS
(MIN), the cycle is an EARLY WRITE cycle and the data output will remain an open circuit throughout the entire cycle. tRWD,
tAWD and tCWD define READ-MODIFY-WRITE cycles. Meeting these limits allows for reading and disabling output data
and then applying input data. OE# held HIGH and WE# taken LOW after CAS# goes LOW result in a LATE WRITE (OE#-
controlled) cycle. tWCS, tRWD, tCWD and tAWD are not applicable in a LATE WRITE cycle.
14. Requires that tAA and tRAC are not violated.
15. If CAS# is LOW at the falling edge of RAS#, output data will be maintained from the previous cycle. To initiate a new
cycle and clear the data-out buffer, CAS# must be pulsed HIGH for tCP.
16. Enables on-chip refresh and address counters.
17. These parameters are referenced to CAS# leading edge in EARLY WRITE cycles and WE# leading edge in LATE WRITE
or READ-MODIFY-WRITE cycles.
18. The 3ns minimum is a parameter guaranteed by design.
EDO PAGE MODE
AC ELECTRICAL CHARACTERISTICS
(Notes: 1-8; notes appear below and on next page) (VDD = +3.3V ±0.3V)
AC CHARACTERISTICS -5 -6
PARAMETER SYMBOL MIN MAX MIN MAX UNITS NOTES
READ command hold time (referenced to CAS#) tRCH 2 2 ns 27
READ command setup time tRCS 2 2 ns
Refresh period tREF 64 64 ms 28
RAS# precharge time tRP 30 40 ns
RAS# to CAS# precharge time tRPC 5 5 ns
READ command hold time (referenced to RAS#) tRRH 0 0 ns 27
RAS# hold time tRSH 18 20 ns 10
READ-WRITE cycle time tRWC 121 145 ns 10
RAS# to WE# delay time tRWD 69 81 ns 26
WRITE command to RAS# lead time tRWL 18 20 ns 10
Transition time (rise or fall) tT250250ns
WRITE command hold time tWCH 13 15 ns 10
WRITE command hold time (referenced to RAS#) tWCR 36 43 ns 11
WE# command setup time tWCS 2 2 ns 16
WE# to outputs in High-Z tWHZ 17 20ns10
WRITE command pulse width tWP 5 5 ns
WE# pulse width to disable outputs tWPZ 10 10 ns
WE# hold time (CBR Refresh) tWRH 6 8 ns 10
WE# setup time (CBR Refresh) tWRP 10 12 ns 12
13
8, 16, 32 Meg x 72 Buffered DRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice.
DM77_2.p65 – Rev. 3/00 ©2000, Micron Technology, Inc.
8, 16, 32 MEG x 72
BUFFERED DRAM DIMMs
NOTES: (continued)
19. tOFF (MAX) defines the time at which the output achieves the open circuit condition and is not referenced to VOH or
VOL.
20. A +2ns (MIN) and a +5ns (MAX) timing skew from the DRAM to the module resulted from the addition of line drivers.
21. tPDOFF (MAX) is determined by the pullup resistor value. Care must be taken to ensure adequate recovery time prior
to reading valid up-level on subsequent DIMM position.
22. Requires that tAA and tCAC are not violated.
23. The tRAD (MAX) limit is no longer specified. tRAD (MAX) was specified as a reference point only. If tRAD was greater
than the specified tRAD (MAX) limit, then access time was controlled exclusively by tAA (tRAC and tCAC no longer
applied). With or without the tRAD (MAX) limit, tAA, tRAC and tCAC must always be met.
24. A -2ns (MIN) and a -5ns (MAX) timing skew from the DRAM to the module resulted from the addition of line drivers.
25. The tRCD (MAX) limit is no longer specified. tRCD (MAX) was specified as a reference point only. If tRCD was greater
than the specified tRCD (MAX) limit, then access time was controlled exclusively by tCAC (tRAC [MIN] no longer
applied). With or without the tRCD (MAX) limit, tAA and tCAC must always be met.
26. Column address changed once each cycle.
27. Either tRCH or tRRH must be satisfied for a READ cycle.
28. RAS#-ONLY REFRESH requires that all rows be refreshed at least once every 64ms (4,096 rows for the 4K version and
8,192 rows for the 8K version). CBR REFRESH requires that at least 4,096 cycles be completed every 64ms.
14
8, 16, 32 Meg x 72 Buffered DRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice.
DM77_2.p65 – Rev. 3/00 ©2000, Micron Technology, Inc.
8, 16, 32 MEG x 72
BUFFERED DRAM DIMMs
tOFF 2 17 2 20 ns
tRAC 50 60 ns
tRAD 7 10 ns
tRAH 7 8 ns
tRAS 50 10,000 60 10,000 ns
tRC 84 104 ns
tRCD 9 12 ns
tRCH 2 2 ns
tRCS 2 2 ns
tRP 30 40 ns
tRRH 0 0 ns
tRSH 18 20 ns
TIMING PARAMETERS
-5 -6
SYMBOL MIN MAX MIN MAX UNITS
tAA 30 35 ns
tACH 12 15 ns
tAR 36 43 ns
tASC 2 2 ns
tASR 5 5 ns
tCAC 18 20 ns
tCAH 13 15 ns
tCAS 8 10,000 10 10,000 ns
tCLZ 2 2 ns
tCRP 10 10 ns
tCSH 36 43 ns
tOD 0 12 0 15 ns
tOE 12 15 ns
READ CYCLE
tRRH
tCLZ
tCAC
tRAC
tAA
VALID DATA OPEN
tOFF
tRCH
ROW
tRCS
tASC
tRAH
tRAD
tAR
tCAH
tRCD tCAS
tRSH
tCSH
tRP
tRC
tRAS
tCRP
tASR
ROW
OPEN
RAS#
V
VIH
IL
V
VIH
IL
ADDR
V
VIH
IL
DQ V
VOH
OL
V
VIH
IL
tOD
tOE
OE#
V
VIH
IL
COLUMN
CAS#
WE#
NOTE 1
tACH
DON’T CARE
UNDEFINED
NOTE: 1. tOFF is referenced from rising edge of RAS# or CAS#, whichever occurs last.
-5 -6
SYMBOL MIN MAX MIN MAX UNITS
15
8, 16, 32 Meg x 72 Buffered DRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice.
DM77_2.p65 – Rev. 3/00 ©2000, Micron Technology, Inc.
8, 16, 32 MEG x 72
BUFFERED DRAM DIMMs
tRAH 7 8 ns
tRAS 50 10,000 60 10,000 ns
tRC 84 104 ns
tRCD 9 12 ns
tRP 30 40 ns
tRSH 18 20 ns
tRWL 18 20 ns
tWCH 13 15 ns
tWCR 36 43 ns
tWCS 2 2 ns
tWP 5 5 ns
TIMING PARAMETERS
-5 -6
SYMBOL MIN MAX MIN MAX UNITS
tACH 12 15 ns
tAR 36 43 ns
tASC 2 2 ns
tASR 5 5 ns
tCAH 13 15 ns
tCAS 8 10,000 10 10,000 ns
tCRP 10 10 ns
tCSH 36 43 ns
tCWL 8 10 ns
tDH 13 15 ns
tDS -2 -2 ns
tRAD 7 10 ns
EARLY WRITE CYCLE
DON’T CARE
UNDEFINED
V
VIH
IL
VALID DATA
ROW
COLUMNROW
tDS
tWP
tWCH
tWCS
tWCR
tRWL
tCWL
tCAH
tASC
tRAH
tASR
tRAD
tAR
tCAS
tRSH
tCSH
tRCD
tCRP
tRAS
tRC
tRP
V
VIH
IL
ADDR V
VIH
IL
V
VIH
IL
DQ V
VIOH
IOL
V
VIH
IL
RAS#
OE#
tDH
WE#
CAS#
tACH
-5 -6
SYMBOL MIN MAX MIN MAX UNITS
16
8, 16, 32 Meg x 72 Buffered DRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice.
DM77_2.p65 – Rev. 3/00 ©2000, Micron Technology, Inc.
8, 16, 32 MEG x 72
BUFFERED DRAM DIMMs
tOEHC 5 10 ns
tOEP 5 5 ns
tOES 4 5 ns
tOFF 2 17 2 20 ns
tPC 20 25 ns
tRAC 50 60 ns
tRAD 7 10 ns
tRAH 7 8 ns
tRASP 50 125,000 60 125,000 ns
tRCD 9 12 ns
tRCH 2 2 ns
tRCS 2 2 ns
tRP 30 40 ns
tRRH 0 0 ns
tRSH 18 20 ns
TIMING PARAMETERS
-5 -6
SYMBOL MIN MAX MIN MAX UNITS
tAA 30 35 ns
tACH 12 15 ns
tAR 36 43 ns
tASC 2 2 ns
tASR 5 5 ns
tCAC 18 20 ns
tCAH 13 15 ns
tCAS 8 10,000 10 10,000 ns
tCLZ 2 2 ns
tCOH 3 3 ns
tCP 8 10 ns
tCPA 33 40 ns
tCRP 10 10 ns
tCSH 36 43 ns
tOD 0 12 0 15 ns
tOE 12 15 ns
VALID
DATA VALID
DATA
VALID
DATA
COLUMNCOLUMNCOLUMNROW ROW
DON’T CARE
UNDEFINED
tOD
tCAH
tASC
tCP
tRSH
tCP
tCP
tCAS
tRCD
tCRP
tPC
tCSH
tRASP tRP
tCAH
tASC
tCAH
tASC
tAR
tRAH
tRAD
tASR
tRCS
tRRH
tRCH
tOFF
tCAC
tCPA
tAA
tCLZ
tCAC
tCPA
tAA
tCAC
tRAC
tAA
tCLZ
tOE tOD tOE tOD
OPENOPEN
V
VIH
IL
V
VIH
IL
ADDR V
VIH
IL
V
VIH
IL
DQ V
VOH
OL
V
VIH
IL
RAS#
OE#
tCAS tCAS
CAS#
WE#
tCOH
tOEP
tOEHC
tOES
tOES
tACH
tACH tACH
EDO-PAGE-MODE READ CYCLE
-5 -6
SYMBOL MIN MAX MIN MAX UNITS
17
8, 16, 32 Meg x 72 Buffered DRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice.
DM77_2.p65 – Rev. 3/00 ©2000, Micron Technology, Inc.
8, 16, 32 MEG x 72
BUFFERED DRAM DIMMs
-5 -6
SYMBOL MIN MAX MIN MAX UNITS
TIMING PARAMETERS
-5 -6
SYMBOL MIN MAX MIN MAX UNITS
tACH 12 15 ns
tAR 36 43 ns
tASC 2 2 ns
tASR 5 5 ns
tCAH 13 15 ns
tCAS 8 10,000 10 10,000 ns
tCP 8 10 ns
tCRP 10 10 ns
tCSH 36 43 ns
tCWL 8 10 ns
tDH 13 15 ns
tDS -2 -2 ns
EDO-PAGE-MODE EARLY WRITE CYCLE
tDS tDH tDS tDH tDS tDH
tWCR
VALID DATA VALID DATA VALID DATA
tRWL
tWP
tCWL
tWCH
tWCS
tWP
tCWL
tWCH
tWCS
tWP
tCWL
tWCH
tWCS
tCAH
tASC
tCAH
tASC
tCAH
tASC
tRAH
tASR
tRAD tACH tACH
tACH
tAR
COLUMNCOLUMNCOLUMNROW ROW
tCP
tCAS
tRSH
tCP
tCAS
tCP
tCAS
tRCD
tCRP
tPC
tCSH
tRASP tRP
V
VIH
IL
CAS# V
VIH
IL
ADDR V
VIH
IL
WE# V
VIH
IL
DQ V
VIOH
IOL
RAS#
OE# V
VIH
IL
DON’T CARE
UNDEFINED
tPC 20 25 ns
tRAD 7 10 ns
tRAH 7 8 ns
tRASP 50 125,000 60 125,000 ns
tRCD 9 12 ns
tRP 30 40 ns
tRSH 18 20 ns
tRWL 18 20 ns
tWCH 13 15 ns
tWCR 36 43 ns
tWCS 2 2 ns
tWP 5 5 ns
18
8, 16, 32 Meg x 72 Buffered DRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice.
DM77_2.p65 – Rev. 3/00 ©2000, Micron Technology, Inc.
8, 16, 32 MEG x 72
BUFFERED DRAM DIMMs
tOD 0 12 0 15 ns
tOE 12 15 ns
tOEH 6 8 ns
tRAC 50 60 ns
tRAD 7 10 ns
tRAH 7 8 ns
tRAS 50 10,000 60 10,000 ns
tRCD 9 12 ns
tRCS 2 2 ns
tRP 30 40 ns
tRSH 18 20 ns
tRWC 121 145 ns
tRWD 69 81 ns
tRWL 18 20 ns
tWP 5 5 ns
TIMING PARAMETERS
-5 -6
SYMBOL MIN MAX MIN MAX UNITS
tAA 30 35 ns
tACH 12 15 ns
tAR 36 43 ns
tASC 2 2 ns
tASR 5 5 ns
tAWD 44 51 ns
tCAC 18 20 ns
tCAH 13 15 ns
tCAS 8 10,000 10 10,000 ns
tCLZ 2 2 ns
tCRP 10 10 ns
tCSH 36 43 ns
tCWD 30 37 ns
tCWL 8 10 ns
tDH 13 15 ns
tDS -2 -2 ns
READ-WRITE CYCLE
(LATE WRITE and READ-MODIFY-WRITE cycles)
VALID D OUT VALID D IN
ROW COLUMN ROW
V
VIH
IL
V
VIH
IL
ADDR V
VIH
IL
V
VIH
IL
DQ V
VIOH
IOL
V
VIH
IL
RAS#
OPENOPEN
tOE tOD
tCAC
tRAC
tAA
tCLZ
tDS tDH
tAWD tWP
tRWL
tCWL
tCWD
tRWD
tRCS
tASC tCAH
tAR
tASR
tRAD
tCRP tRCD tCAS
tRSH
tCSH
tRAS
tRWC
tRP
tRAH
OE#
tOEH
WE#
tACH
CAS#
DON’T CARE
UNDEFINED
-5 -6
SYMBOL MIN MAX MIN MAX UNITS
19
8, 16, 32 Meg x 72 Buffered DRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice.
DM77_2.p65 – Rev. 3/00 ©2000, Micron Technology, Inc.
8, 16, 32 MEG x 72
BUFFERED DRAM DIMMs
tOD 0 12 0 15 ns
tOE 12 15 ns
tOEH 6 8 ns
tPC 20 25 ns
tPRWC 49 58 ns
tRAC 50 60 ns
tRAD 7 10 ns
tRAH 7 8 ns
tRASP 50 125,000 60 125,000 ns
tRCD 9 12 ns
tRCS 2 2 ns
tRP 30 40 ns
tRSH 18 20 ns
tRWD 69 81 ns
tRWL 18 20 ns
tWP 5 5 ns
TIMING PARAMETERS
-5 -6
SYMBOL MIN MAX MIN MAX UNITS
tAA 30 35 ns
tAR 36 43 ns
tASC 2 2 ns
tASR 5 5 ns
tAWD 44 51 ns
tCAC 18 20 ns
tCAH 13 15 ns
tCAS 8 10,000 10 10,000 ns
tCLZ 2 2 ns
tCP 8 10 ns
tCPA 33 40 ns
tCRP 10 10 ns
tCSH 36 43 ns
tCWD 30 37 ns
tCWL 8 10 ns
tDH 13 15 ns
tDS -2 -2 ns
DON’T CARE
UNDEFINED
tOE
tOE
tOE
OPEN
DOUT
VALID
DIN
VALID
DOUT
VALID
DIN
VALID
DOUT
VALID
DIN
VALID
OPEN
tDH
tDS
tAA
tCPA
tCLZ
tCAC
tDH
tDS
tAA
tCPA
tCLZ
tCAC
tDH
tDS
tAA
tCLZ
tCAC
tRAC
tWP
tCWL
tRWL
tCWD
tAWD
tWP
tCWL
tCWD
tAWD
tWP
tCWL
tCWD
tAWD
tRCS
tRWD
tASR tRAH tASC
tRAD
tAR
tCAH tASC tCAH tASC tCAH
tCP tCAS
tRSH
tCP
tRP
tRASP
tCAS
tCP
tCAS
tRCD
tCSH tPC
tCRP
ROW COLUMN COLUMN COLUMN ROW
V
VIH
IL
CAS# V
VIH
IL
ADDR V
VIH
IL
V
VIH
IL
DQ V
VIOH
IOL
V
VIH
IL
RAS#
OE#
WE#
tPRWC
tOEH
tOD tOD tOD
NOTE 1
EDO-PAGE-MODE READ-WRITE CYCLE
(LATE WRITE and READ-MODIFY-WRITE cycles)
NOTE: 1. tPC is for LATE WRITE cycles only.
-5 -6
SYMBOL MIN MAX MIN MAX UNITS
20
8, 16, 32 Meg x 72 Buffered DRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice.
DM77_2.p65 – Rev. 3/00 ©2000, Micron Technology, Inc.
8, 16, 32 MEG x 72
BUFFERED DRAM DIMMs
tOE 12 15 ns
tPC 20 25 ns
tRAC 50 60 ns
tRAD 7 10 ns
tRAH 7 8 ns
tRASP 50 125,000 60 125,000 ns
tRCD 9 12 ns
tRCH 2 2 ns
tRCS 2 2 ns
tRP 30 40 ns
tRSH 18 20 ns
tWCH 13 15 ns
tWCS 2 2 ns
tWHZ 17 20 ns
TIMING PARAMETERS
-5 -6
SYMBOL MIN MAX MIN MAX UNITS
tAA 30 35 ns
tACH 12 15 ns
tAR 36 43 ns
tASC 2 2 ns
tASR 5 5 ns
tCAC 18 20 ns
tCAH 13 15 ns
tCAS 8 10,000 10 10,000 ns
tCOH 3 3 ns
tCP 8 10 ns
tCPA 33 40 ns
tCRP 10 10 ns
tCSH 36 43 ns
tDH 13 15 ns
tDS -2 -2 ns
EDO-PAGE-MODE READ EARLY WRITE CYCLE
(Pseudo READ-MODIFY-WRITE)
V
VIH
IL
V
VIH
IL
RAS#
V
VIH
IL
ADDR
V
VIH
IL
WE#
tRASP tRP
ROW COLUMN (A) COLUMN (N) ROW
V
VIH
IL
OE#
V
VIOH
IOL
tCRP
tCSH
tCAS
tRCD
t
ASR tRAH
tRAD
tASC
tAR
tCAH tASC tCAH tASC tCAH
tCP
tRSH
VALID DATA
IN
tRCS tRCH tWCS
tOE
VALID
DATA (B)
VALID DATA (A)
tWHZ
tCAC
tCPA
tAA
tCAC
tAA
OPEN
DQ
tPC
RAC
t
tCOH
tWCH
tDS tDH
tPC
COLUMN (B)
tACH
CAS#
tCAS
tCAS
tCP tCP
DON’T CARE
UNDEFINED
-5 -6
SYMBOL MIN MAX MIN MAX UNITS
21
8, 16, 32 Meg x 72 Buffered DRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice.
DM77_2.p65 – Rev. 3/00 ©2000, Micron Technology, Inc.
8, 16, 32 MEG x 72
BUFFERED DRAM DIMMs
tOD 0 12 0 15 ns
tOE 12 15 ns
tRAC 50 60 ns
tRAD 7 10 ns
tRAH 7 8 ns
tRCD 9 12 ns
tRCH 2 2 ns
tRCS 2 2 ns
tWHZ 17 20 ns
tWPZ 10 10 ns
TIMING PARAMETERS
-5 -6
SYMBOL MIN MAX MIN MAX UNITS
tAA 30 35 ns
tAR 36 43 ns
tASC 2 2 ns
tASR 5 5 ns
tCAC 18 20 ns
tCAH 13 15 ns
tCAS 8 10,000 10 10,000 ns
tCLZ 2 2 ns
tCP 8 10 ns
tCRP 10 10 ns
tCSH 36 43 ns
EDO READ CYCLE
(with WE#-controlled disable)
tCLZ
tCAC
tRAC
tAA
VALID DATA OPEN
tRCH
tRCS
tASC
tRAH
tRAD
tAR
tCAH
tRCD tCAS
tCSH
tCRP
tASR
ROW
OPEN
RAS#
V
VIH
IL
V
VIH
IL
ADDR
V
VIH
IL
DQ V
VOH
OL
V
VIH
IL
tOD
tOE
OE#
V
VIH
IL
COLUMN
WE#
tWHZ
tWPZ
tCP
tASC
tRCS
COLUMN
tCLZ
DON’T CARE
UNDEFINED
CAS#
-5 -6
SYMBOL MIN MAX MIN MAX UNITS
22
8, 16, 32 Meg x 72 Buffered DRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice.
DM77_2.p65 – Rev. 3/00 ©2000, Micron Technology, Inc.
8, 16, 32 MEG x 72
BUFFERED DRAM DIMMs
TIMING PARAMETERS
-5 -6
SYMBOL MIN MAX MIN MAX UNITS
tASR 5 5 ns
tCHR 6 8 ns
tCP 8 10 ns
tCRP 10 10 ns
tCSR 7 7 ns
tRAH 7 8 ns
RAS#-ONLY REFRESH CYCLE
ROW
V
VIH
IL
CAS# V
VIH
IL
ADDR V
VIH
IL
RAS#
tRC
tRAS tRP
tCRP
tASR tRAH
ROW
OPEN
DQ V
VOH
OL
tRPC
WE# V
VIH
IL
CBR REFRESH CYCLE
(Addresses, OE# = DON’T CARE)
tRP
V
VIH
IL
RAS#
tRAS
OPEN
tCHR
tCSR
V
VIH
IL
V
VOH
OL
CAS#
DQ
tRP tRAS
tRPC
tCSR
tRPC tCHR
tCP
V
VIH
IL
tWRP tWRH tWRP tWRH
WE#
DON’T CARE
UNDEFINED
NOTE 1
-5 -6
SYMBOL MIN MAX MIN MAX UNITS
tRAS 50 10,000 60 10,000 ns
tRC 84 104 ns
tRP 30 40 ns
tRPC 5 5 ns
tWRH 6 8 ns
tWRP 10 12 ns
23
8, 16, 32 Meg x 72 Buffered DRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice.
DM77_2.p65 – Rev. 3/00 ©2000, Micron Technology, Inc.
8, 16, 32 MEG x 72
BUFFERED DRAM DIMMs
TIMING PARAMETERS
-5 -6
SYMBOL MIN MAX MIN MAX UNITS
tAA 30 35 ns
tAR 36 43 ns
tASC 2 2 ns
tASR 5 5 ns
tCAC 18 20 ns
tCAH 13 15 ns
tCHR 6 8 ns
tCLZ 2 2 ns
tCRP 10 10 ns
tOD 0 12 0 15 ns
tOE 12 15 ns
HIDDEN REFRESH CYCLE
(WE# = HIGH; OE# = LOW)
DON’T CARE
UNDEFINED
tCLZ
tOFF
OPENVALID DATAOPEN
COLUMNROW
tCAC
tRAC
tAA
tCAH
tASC
tRAH
tASR
tRAD
tAR
tCRP tRCD tRSH
tRAS
tRC
tRP
tCHR
tRAS
DQ V
VIOH
IOL
V
VIH
IL
ADDR
V
VIH
IL
CAS#
V
VIH
IL
RAS#
-5 -6
SYMBOL MIN MAX MIN MAX UNITS
tOFF 2 17 2 20 ns
tORD 0 0 ns
tRAC 50 60 ns
tRAD 7 10 ns
tRAH 7 8 ns
tRAS 50 10,000 60 10,000 ns
tRC 84 104 ns
tRCD 9 12 ns
tRP 30 40 ns
tRSH 18 20 ns
NOTE: A HIDDEN REFRESH may also be performed after a WRITE cycle. In this case, WE# = LOW and OE# = HIGH.
24
8, 16, 32 Meg x 72 Buffered DRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice.
DM77_2.p65 – Rev. 3/00 ©2000, Micron Technology, Inc.
8, 16, 32 MEG x 72
BUFFERED DRAM DIMMs
NOTE: All dimensions in inches (millimeters) MAX or typical where noted.
MIN
168-PIN DIMM
(64MB SOJ)
168-PIN DIMM
64MB TSOP
.200 (5.08)
MAX
.054 (1.37)
.046 (1.17)
1.255 (31.88)
1.245 (31.62)
PIN 1 (PIN 85 ON BACKSIDE)
.700 (17.78)
TYP
.118 (3.00)
(2X)
.118 (3.00) TYP
4.550 (115.57)
.050 (1.27)
TYP
.118 (3.00)
TYP .039 (1.00)
TYP
.079 (2.00) R
(2X)
.039 (1.00)R (2X)
FRONT VIEW
.128 (3.25)
.118 (3.00)
PIN 84 (PIN 168 ON BACKSIDE)
(2X)
.250 (6.35) TYP
1.700 (43.18)
2.625 (66.68)
5.256 (133.50)
5.244 (133.20)
.054 (1.37)
.046 (1.17)
1.355 (34.42)
1.345 (34.16)
PIN 1 (PIN 85 ON BACKSIDE)
.700 (17.78)
TYP
.118 (3.00)
(2X)
.118 (3.00) TYP
4.550 (115.57)
.050 (1.27)
TYP
.118 (3.00)
TYP .039 (1.00)
TYP
.079 (2.00) R
(2X)
.039 (1.00)R (2X)
FRONT VIEW
.128 (3.25)
.118 (3.00)
PIN 84 (PIN 168 ON BACKSIDE)
(2X)
.250 (6.35) TYP
1.700 (43.18)
2.625 (66.68)
5.256 (133.50)
5.244 (133.20)
.125 (3.18)
MAX
25
8, 16, 32 Meg x 72 Buffered DRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice.
DM77_2.p65 – Rev. 3/00 ©2000, Micron Technology, Inc.
8, 16, 32 MEG x 72
BUFFERED DRAM DIMMs
.054 (1.37)
.046 (1.17)
2.005 (50.93)
1.995 (50.67)
PIN 1 (PIN 85 ON BACKSIDE)
.700 (17.78)
TYP
.118 (3.00)
(2X)
.118 (3.00) TYP
4.550 (115.57)
.050 (1.27)
TYP
.118 (3.00)
TYP .039 (1.00)
TYP
.079 (2.00) R
(2X)
.039 (1.00)R (2X)
FRONT VIEW
.128 (3.25)
.118 (3.00)
PIN 84 (PIN 168 ON BACKSIDE)
(2X)
.250 (6.35) TYP
1.700 (43.18)
2.625 (66.68)
5.256 (133.50)
5.244 (133.20)
.125 (3.18)
MAX
168-PIN DIMM
(128MB TSOP)
168-PIN DIMM
(128MB SOJ)
.350 (8.89)
MAX
.054 (1.37)
.046 (1.17)
1.105 (28.07)
1.095 (27.81)
PIN 1 (PIN 85 ON BACKSIDE)
.700 (17.78)
TYP
.118 (3.00)
(2X)
.118 (3.00) TYP
4.550 (115.57)
.050 (1.27)
TYP
.118 (3.00)
TYP .039 (1.00)
TYP
.079 (2.00) R
(2X)
.039 (1.00)R (2X)
FRONT VIEW
.128 (3.25)
.118 (3.00)
PIN 84 (PIN 168 ON BACKSIDE)
(2X)
.250 (6.35) TYP
1.700 (43.18)
2.625 (66.68)
5.256 (133.50)
5.244 (133.20)
NOTE: All dimensions in inches (millimeters) MAX or typical where noted.
MIN
26
8, 16, 32 Meg x 72 Buffered DRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice.
DM77_2.p65 – Rev. 3/00 ©2000, Micron Technology, Inc.
8, 16, 32 MEG x 72
BUFFERED DRAM DIMMs
168-PIN DIMM
(128MB TSOP)
.054 (1.37)
.046 (1.17)
1.255 (31.88)
1.245 (31.62)
.700 (17.78)
TYP
.118 (3.00)
(2X)
.079 (2.00) R
(2X)
FRONT VIEW
5.256 (133.50)
5.244 (133.20)
.157 (4.00)
MAX
PIN 1 (PIN 85 ON BACKSIDE)
4.550 (115.57)
.050 (1.27)
TYP
.118 (3.00)
TYP .039 (1.00)
TYP
.039 (1.00)R (2X)
.128 (3.25)
.118 (3.00)
PIN 84 (PIN 168 ON BACKSIDE)
(2X)
.250 (6.35) TYP
1.700 (43.18)
2.625 (66.68)
.118 (3.00) TYP
NOTE: All dimensions in inches (millimeters) MAX or typical where noted.
MIN
27
8, 16, 32 Meg x 72 Buffered DRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice.
DM77_2.p65 – Rev. 3/00 ©2000, Micron Technology, Inc.
8, 16, 32 MEG x 72
BUFFERED DRAM DIMMs
.054 (1.37)
.046 (1.17)
2.005 (50.93)
1.995 (50.67)
PIN 1 (PIN 85 ON BACKSIDE)
.700 (17.78)
TYP
.118 (3.00)
(2X)
.118 (3.00) TYP
4.550 (115.57)
.050 (1.27)
TYP
.118 (3.00)
TYP .039 (1.00)
TYP
.079 (2.00) R
(2X)
.039 (1.00)R (2X)
FRONT VIEW
.128 (3.25)
.118 (3.00)
PIN 84 (PIN 168 ON BACKSIDE)
(2X)
.250 (6.35) TYP
1.700 (43.18)
2.625 (66.68)
5.256 (133.50)
5.244 (133.20)
.157 (4.00)
MAX
168-PIN DIMM
(256MB TSOP)
168-PIN DIMM
(256MB SOJ)
.350 (8.89)
MAX
.054 (1.37)
.046 (1.17)
2.005 (50.93)
1.995 (50.67)
PIN 1 (PIN 85 ON BACKSIDE)
.700 (17.78)
TYP
.118 (3.00)
(2X)
.118 (3.00) TYP
4.550 (115.57)
.050 (1.27)
TYP
.118 (3.00)
TYP .039 (1.00)
TYP
.079 (2.00) R
(2X)
.039 (1.00)R (2X)
FRONT VIEW
.128 (3.25)
.118 (3.00)
PIN 84 (PIN 168 ON BACKSIDE)
(2X)
.250 (6.35) TYP
1.700 (43.18)
2.625 (66.68)
5.256 (133.50)
5.244 (133.20)
NOTE: All dimensions in inches (millimeters) MAX or typical where noted.
MIN
28
8, 16, 32 Meg x 72 Buffered DRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice.
DM77_2.p65 – Rev. 3/00 ©2000, Micron Technology, Inc.
8, 16, 32 MEG x 72
BUFFERED DRAM DIMMs
168-PIN DIMM
(256MB SOJ)
.054 (1.37)
.046 (1.17)
1.655 (42.04)
1.645 (41.78)
PIN 1 (PIN 85 ON BACKSIDE)
.700 (17.78)
TYP
.118 (3.00)
(2X)
.118 (3.00) TYP
4.550 (115.57)
.050 (1.27)
TYP
.118 (3.00)
TYP .039 (1.00)
TYP
.079 (2.00) R
(2X)
.039 (1.00)R (2X)
FRONT VIEW
.128 (3.25)
.118 (3.00)
PIN 84 (PIN 168 ON BACKSIDE)
(2X)
.250 (6.35) TYP
1.700 (43.18)
2.625 (66.68)
6.955 (176.66)
6.945 (176.40)
.350 (8.89)
MAX
.870 (22.10) MIN
NOTE: All dimensions in inches (millimeters) MAX or typical where noted.
MIN
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
E-mail: prodmktg@micronsemi.com, Internet: http://www.micronsemi.com, Customer Comment Line: 800-932-4992
Micron is a registered trademark of Micron Technology, Inc.
