Order Number: 252636, Revi sion: 004
26 Aug 2005
Intel® Advanced+ Boot Block Flash
Memory (C3)
SCSP Family
Datasheet
Product Featu res
The I nte l® Advanced+ Boot Block Flas h Mem ory (C3) Stacked Chip Scale Package (SCSP)
devi ce del ivers a fe ature- rich s olution f or low-p ower appl icati ons. The C3 SCSP memo ry devic e
incorporate s flash memory and sta tic RAM in one package with low voltage capability to
achieve the smallest system memory solution form-factor together with high-speed, low-power
operations. T he C3 SCS P memory device offers a protection register and flexible block locking
to enable next generation security capability. Combined with the Intel® Flash Data Integrator
(Intel® FDI) soft ware, the C 3 SCSP memory devi ce provi des a cost-e f fecti ve, fl exible, c ode plus
data storage solution.
■Flash Memory Plus SRAM
—R ed u ces M emory Board Space
Required, Simplifying PCB Design
Complexity
■SCSP Technology
—Smal lest Memory Subs ystem Footprint
—Area : 8 x 10 mm for 16 Mbit (0.13 µm)
Fl as h + 2 Mbit or 4 Mbit SRAM
—Area : 8 x 12 mm for 32 Mbit (0.13 µm)
Fl as h + 4 Mbit or 8 Mbit SRAM
—Heigh t : 1.20 mm for 16 Mbit (0.13 µm)
Fl ash + 2 Mbit or 4 Mbit SRAM, and 32
Mbit (0.13um) Flash + 8 Mbit SRAM
—Heigh t : 1.40 mm for 32 Mbit (0.13 µm)
Fl as h + 4 Mbit SRAM
—This F amily also inc lude s 0.25 µm, 0.18
µm, and 0.13 µm technologies
■Advanced SRAM Te chnology
—7 0 ns Access Time
—Low Power Operation
—Low Voltage D ata Ret ention Mode
■Intel® Flash Data Integrator (FDI)
Software
—Real-Time Data Storage and Code
Exe cution in the Same Memory Device
—Full F lash File Manager Capability
■Advance d+ Boot Blo ck Flash Memory
—70 ns Access Time
—Instant, Individual Block Locking
—128 bit Protection Regist er
—12 V Production Programming
—Fast Progra m and Erase Suspend
—Extended Temperature –25 °C to +85 °C
■Blocking Architecture
—Block Sizes for Code + Data Storage
—4-Kword Paramet er Blocks
—64-Kbyte Main Blocks
—100,000 Erase Cycles per Block
■Low Power Operation
—Asynchronous Read Current: 9 mA
(Flash)
—Standby Current: 7 µA (Flash)
—Automatic Power Saving Mode
■Flash Technologies
—0.25 µm ET OX™ VI, 0.1 8 µm ET OX™
VII and 0.13 µm ETOX™ VIII Flash
Technologies
26 Aug 2005 Intel® Advanced+ Boot Block Flash Memory (C3) SCSP Family Datasheet
2 Order Numbe r: 252636 , Revision: 004
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The Intel® Advanced+ Boot Block Flash Memory (C3) may contain design defects or errors known as errata which may cause the product to deviate
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Copyright © 2005, Intel Corporation. All rights reserved.
C3 SCSP Flash Memory
Datasheet Intel® Advan ce d+ Bo ot Block Flash Memory (C 3) SCSP Family 26 Aug 2005
Order Number: 252636, Revisio n: 004 3
Contents
1.0 Introduction....................................................................................................................................6
1.1 Docu men t Co nv e nt ions ..... ..... .......... .... ..... .......... .... .......... .... .......... ..... ......... ..... ..... ......... ....6
1.2 Pro duct Overview .................................................................................................................6
1.3 Package Ballo u t...... .... .......... .... .......... ..... .... .......... ..... ......... ..... ..... ......... ..... ......... ..... ...........8
1.4 Signal Definitions.................................. ....... .......... ......... ....... .......... ....... ......... .......... ...........9
2.0 Principles of Operation...............................................................................................................11
2.1 Bus Opera tion...... .......... .... ..... .......... .... .......... ..... .... .......... .... .......... ..... .... .......... ..... ..... ......11
2.1.1 Read ......................................................................................................................12
2.1.2 Outp u t Disab le.... ......... ..... .......... .... ..... .......... .... .......... ..... ......... ..... ......... ..... ..... ....12
2.1.3 Standby..................................................................................................................13
2.1.4 Fl as h Rese t....... ......... ..... ..... ......... ..... ......... ..... ......... ..... .......... .... ..... .......... .... .......13
2.1.5 Write ......................................................................................................................13
3.0 Flash Memory Modes of Operation............................................................................................14
3.1 Read Array (FFh)................. ............................................. ................... .............. .................14
3.2 Read Identifier (90h)........................ .......................... .............. .......................... .................14
3.3 Read Status Register (70h) .................... ....................... ............................. ................... .....15
3.3.1 Clear Status Register (50h) ... ....... ............ ....... ....... ............ ....... ....... ....... ............ ..16
3.4 CFI Que ry ( 9 8h)...... .... .......... .... ..... .......... .... .......... ..... .... .......... ..... ......... ..... .... .......... .........16
3.5 Word Program (40h/10h)..... ................... .......................... ................... .......................... .....16
3.5.1 Suspending and Resuming Program (B0h/D0h)................... ....... ....... .......... ....... ..17
3.6 Blo ck Era se ( 20h )................. .... ..... .......... .... .......... ..... .... .......... ..... ......... ..... .... .......... ..... ....18
3.6.1 Suspending and Resuming Erase (B0h/D0h)..................... ....... ....... ....... ............ ..18
3.7 Block L o cking..... ......... ..... ......... ..... ..... ......... ..... .......... .... .......... ..... ......... ..... .... .......... .........20
3.7.1 Block L o cking Operati o n Summar y.... ......... ..... ......... ..... .......... .... .......... ..... ......... ..21
3.7.2 Locked State..........................................................................................................21
3.7.3 Unlocked State ......................................................................................................21
3.7.4 Lock-Down State ...................................................................................................21
3.7.5 Readi ng Lock Status for a Block............................................. ...............................22
3.7.6 Locking Ope ratio n During Erase Suspend ................. ...................................... .....22
3.7.7 Sta tu s Regi ster Error Ch ec king ........... .......... .... .......... ..... ......... ..... ......... .......... ....22
3.8 128 Bit Protection Register............................ .......................... ...................................... .....23
3.8.1 Readi ng the Protection Register....... ...................................... .............................. .23
3.8.2 Pro gramming the Pro tection Register (C0h) ..........................................................24
3.8.3 Locki n g the Pro te c tion Register.. ......... ..... ......... ..... .......... .... .......... .... .......... ..... ....24
4.0 Power and Reset Considera tions ..............................................................................................25
4.1 Power -U p /Down Characteristics........... ..... ..... ......... ..... ......... ..... .......... .... ..... .......... .... .......25
4.2 Additional Flash Features......... ............ ................... ....... ............ .............. ....... ................. ..25
4.2.1 Improved 12 Volt Production Programmin g................................... ........................25
4.2.2 F-VPP £ VPPLK for Complete Protection..............................................................25
5.0 Electrical Specifications .............................................................................................................26
5.1 Absolute Maxi mu m Ratings................ ..... ......... ..... ......... ..... .......... .... ..... ......... ..... .......... ....26
5.2 Ope r at ing Conditi o n s......... ..... ..... ......... ..... .......... .... .......... .... ..... .......... .... .......... ..... ......... ..27
5.3 Capacitance........................................................................................................................27
C3 SCSP Flash Memory
26 Aug 2005 Intel® Advanced+ Boot Block Flash Memory (C3) SCSP Family Datasheet
4 Order Numbe r: 252636 , Revision: 004
5.4 DC Characte ristics....... ......... ..... .......... .... .......... ..... ......... ..... ......... ..... ......... ..... .......... .... ....28
5.5 Flash AC Characteristics....................................................................................................32
5.6 Flash AC Characteristics—Write Operations......................................................................33
5.7 Flash Erase and Progra m Timi n g s( 1 ).... ......... ..... .......... .... ..... .......... .... .......... .... ..... .......... .34
5.8 Flash Reset O perations......................................................................................................36
5.9 S RA M AC Characteristics—Read Ope rations........................................ .............. ............ ..37
5.10 SRAM AC Chara cte r i stics—Wr i te Ope r a ti o n s.......... ..... ......... ..... ......... ..... ......... ..... .......... .38
5.11 SRAM Data Retention Characte ristics—Extended Tem perature........... .............. ..............40
6. 0 Mig r ation Guide Informati on......................................................................................................41
7.0 System Design Considerations ..................................................................................................41
7.1 Background.........................................................................................................................41
7.1.1 Flash + SRAM Footprint Integration......................................................................41
7.1.2 C3 Flash Memory Features...................................................................................42
7.2 Flash Control Considerations.............................................................................................42
7.2.1 F-RP# Connected to System Reset............... ....... ..... .. .......... .. ..... .. ....... ..... ..... ......42
7.2.2 F-VCC, F-VPP and F-RP# Tran sition....................................................................42
7.3 Noise Reduction .......................... ................... ................. ......... ................... ................... ....43
7.4 Simultaneous Ope r a ti o n... .... .......... ..... ......... ..... ..... ......... ..... ......... ..... ..... ......... ..... ......... ....44
7.4.1 SRAM Operati o n during Flash “ Busy”....... ......... ..... ......... ..... ......... ..... .......... .... ....45
7.4.2 Simultaneous Bu s Ope r a ti o ns.. ..... .... .......... ..... ......... ..... ..... ......... ..... ......... ..... ..... .45
7.5 Printed Circuit Board Notes................................................................................................45
7.6 System Design Notes Summary.........................................................................................45
A Program/Erase Flowcharts............................................................................................................46
B CFI Query St r u ctu r e.......... ..... ......... ..... .......... .... ..... .......... .... .......... .... .......... ..... .... .......... .............52
B.1 Query Stru cture Outpu t.. ..... ......... ..... .......... .... ..... .......... .... .......... ..... ......... ..... .... .......... ......52
B.2 Query Stru cture Overview......... ..... ..... ......... ..... ......... ..... ......... ..... .......... .... ..... .......... .... ....53
B.3 Block Lock Status Register.................................................................................................54
B.4 CFI Query Identification String................. ....... .......... ....... ....... ....... ....... ....... ....... ............ ....54
B.5 System Interface Information ..............................................................................................55
B.6 Device Geo metry Definitio n.. .......... ..... ......... ..... ..... ......... ..... ......... ..... ......... ..... .......... .... ....56
B.7 Intel-Spec ific Extended Query Table................................... ................................. ..............57
C Word-Wide Memory Map Diag r a ms..... ..... ..... .... .......... ..... ......... ..... ......... ..... ......... ..... ..... ......... ....59
D Device ID Tab le. ......... ..... ......... ..... ..... ......... ..... ......... ..... ..... ......... ..... .......... .... ..... ......... ................66
E Protection Register Add re ssing....... ..... ..... ......... ..... .......... .... .......... .... .......... ..... .... .......... ..... ........67
F Mechanical and Shippin g Media Details...................... ................................... ...............................68
F.8 Mechan ical Specifica tio n....................................................................................................68
F.9 Media In fo rmati on............... ..... .... .......... ..... ......... ..... ..... ......... ..... ......... ..... ..... ......... ..... ......71
G Add itional Information............................... ................... .......................... ................... .....................73
H Ordering Information......................................................................................................................74
C3 SCSP Flash Memory
Datasheet Intel® Advan ce d+ Bo ot Block Flash Memory (C 3) SCSP Family 26 Aug 2005
Order Number: 252636, Revisio n: 004 5
Revision History
Date of
Revision Version Description
02/11/03 -001 Initial release, Stacked Chip Scale Package
01/29/04 -002 Minor text edits.
03/05 -003 Updated Ordering Information figures and table in Appendix H.
26 Aug 2005 -004 Updated Ordering Information to add PF28F1602C3TD70.
C3 SCSP Flash Memory
26 Aug 2005 Intel® Advanced+ Boot Block Flash Memory (C3) SCSP Family Datasheet
6 Order Numbe r: 252636 , Revision: 004
1.0 Introduction
This docume nt conta i ns the specific ations for th e I ntel® Advanced+ Boot Block Fla sh Memor y
(C3) Stacked Chi p Sc ale Package (SCS P) device. C3 SCSP memo ry solutions ar e o ffered in the
following combinations:
•32- Mbit flash + 8-Mbit SRAM
•32- Mbit flash + 4-Mbit SRAM
•16- Mbit flash + 4-Mbit SRAM
•16- Mbit flash memory + 2-Mbit SRAM
1.1 Document Convent ions
Throughout this document, the fol lowing conventions have be en adopted.
•Voltages:
— 2.7 V refer s to the full voltage range, 2.7 V–3.3V
— 12 V refers to 1 1.4 V to 12.6 V
•Main block(s): 32-Kword block
•Pa ra meter block(s): 4-Kword block
1.2 Product Overview
The C3 SCSP device combines flash memory and SRAM into a single package, which provides
secure low-voltage memory solutions for port able applications.
The flash memory provides the following features:
•Enhanced security.
•Instant locking/unlocking of any flash blo ck with zero-latency
•A 128-bit protection register that enables unique device identification, to meet the needs of
next generati on portable applications.
•Improved 12 V production programming for increased factory throughput.
Table 1. Block Organ ization (x16)
Memory Device Kwords
32-Mbit Flash 2048
16-Mbit Flash 1024
2-Mbit SRAM 128
4-Mbit SRAM 256
8-Mbit SRAM 512
Note: All words are 16 bits each.
C3 SCSP Fla s h Me mor y
Datasheet Intel® Advan ce d+ Bo ot Block Flash Memory (C 3) SCSP Family 26 Aug 2005
Order Number: 252636, Revisio n: 004 7
The flash memory is asymmetri call y-block ed to enab le syste m inte gration of code and da ta sto rage
in a s ingle device. Each flash blo ck can be eras ed independently of the others up to 100,000 tim es.
The flash memory has eight 8-KB pa rameter blocks lo ca ted at ei ther the top (denoted by -T suffix)
or the bottom (-B suffix) of the address map, to accommodate different micr oprocessor prot ocols
for kernel co de loca tion.
The remaining flash m emory is grouped into 32-Kword main blocks.
Any individual flash memory b lock can be locked or unlocked ins tantly to provide complete
pr otection for code or data (s ee Sectio n 5.7, “Flash Erase and Program Timi ngs(1)” on pa ge 34 for
details).
Th e flas h memor y co ntains b o th a Co mmand User I n terface (CUI) and a Write S tate Mach ine
(WSM).
•The CUI is th e interface bet ween the mic r ocontroller and the internal operation of the flash
memo ry.
•The internal WSM automaticall y exe cutes the algorithms and tim ings necessa r y for program
and era se operations, including verificatio n, thereby unburdening the mi croproces sor or
micr ocontroller. To in dicate the st atus of the WSM, the flash memo ry status regi ster signifies
block erase or word program completion and status.
Fl as h program and eras e aut om ation enabl es executin g pr ogram and erase operations using an
indus try-sta ndard two-write command sequence to the CUI.
•Program operations are performed in word increments.
•Erase operations erase all locations with in a block simult aneousl y.
The system software can suspend both program and erase operations to read from any other flash
block. In addit ion, data can be prog rammed to another fla sh block during an erase suspe nd.
The C3 SCSP memo ry device offer s two low-powe r s avings features to significantly reduce power
consumption:
•Automatic Power Savings (APS) for flash memory. The C3 SCSP mem ory device
au tomatically enters APS mode after a r ead cycle co mpl etes f rom the f lash memo ry.
•Standby mode for flash and SRAM. This mode is initiated when the system deselects the
device by driving F-CE# and S-CS1# or S-CS2 inactive.
To reset the flash m emory, lo wer the F-RP # sig nal to GND. Setting F-RP# to GND provides CPU
mem ory reset synchronization and additional protection against bus noise that can occur during
system reset and power-up/power-down sequences.
C3 SCSP Flash Memory
26 Aug 2005 Intel® Advanced+ Boot Block Flash Memory (C3) SCSP Family Datasheet
8 Order Numbe r: 252636 , Revision: 004
1.3 Package Ballout
72-
Notes:
1. Flash memor y upgrade ball s are shown up to A21 (64-Mbi t flash) and A22 (128-Mbit flash). In all flash
memory and SRAM combinations, 66 balls are populated on lower density devices. (Upper address
ball s are not popula ted). Bal l location A10 is NC on 16/2 device s onl y.
2. To maintain compatibility with all JEDEC Variation B options for the C6 ball location, connect this C6
land pad directly to the land pad for the G4 (A17) ball.
Figure 1. 66-Ball SCSP Package Ballo ut
1 2 3 4 5 6 7 8
A
B
C
D
E
F
G
H
NC A
20
A
11
A
15
A
14
A
13
A
12
A
16
A
8
A
10
A
9
DQ
15
S-WE#
F-WE# NC A
21
DQ
13
DQ
6
S-V
SS
F-WP# A
19
DQ
11
DQ
10
S-LB# S-UB# S-OE# DQ
9
DQ
8
A
18
A
17
A
7
A
6
A
3
A
2
NC NC A
5
A
4
A
0
F-CE# F-V
SS
F-RP# A
22
DQ
12
S-CS
2
910 11 12
F-V
SS
NC
DQ
14
DQ
7
DQ
4
DQ
5
DQ
2
DQ
3
DQ
0
DQ
1
A
1
S-CS
1
#
F-OE# NC NC
S-V
CC
F-V
CC
Top View, Balls Down
F-V
CCQ
F-V
PP
C3 SCSP Fla s h Me mor y
Datasheet Intel® Advan ce d+ Bo ot Block Flash Memory (C 3) SCSP Family 26 Aug 2005
Order Number: 252636, Revisio n: 004 9
1.4 Signal Definitions
Table 2 defines the signals sho wn in Fi gure 1 “66-Ball SCSP Pack age Ballout” on page 8.
Table 2. Intel® Advanced+ Boot Block SCSP Ball Descriptions (Sheet 1 of 2)
Symbo l Type Name an d Func tion
A[20:0] INPUT
ADDRESS INPUTS for memory add resses. Addresses are internally latche d during a program or
erase cycle.
• 2-Mb it : A[16:0]
• 4-Mb it : A[18:0]
• 16-Mbit : A[19:0]
• 32-Mbit A[20:0]
DQ[15:0] INPUT /
OUTPUT
DATA INPUTS/OUTPUTS:
• Inputs array data for SRAM write operations and on the second F-CE# and F-WE# cycle
during a flash program comm and.
• Inputs comma nds to the flash memory Command User I nterface w hen F-CE# and F-WE# a re
asserted.
• Data is internally latched.
• O utputs array, configuration, and statu s register data.
The data balls float to tristate when the chip is deselected or the outputs are disabled.
F-CE# INPUT
FLASH CHIP E NABLE: Activa tes the flash internal contr ol lo gic, inpu t buffers, decoder s, an d
sense amp lifiers.
• F-CE# is active low.
• F-CE# high deselects the flash memory device an d reduces power consump tion to standby
levels.
S-CS1# INPUT
SRAM CHIP S ELECT1: Activates the SRAM internal control logic, input buffers, decoders, and
sense amp lifiers.
• S-CS1# is active low.
• S-CS1# high deselects the SRAM memory device and reduces power consumption to standby
levels.
S-CS2INPUT
SRAM CHIP S ELECT2: Activates the SRAM internal control logic, input buffers, decoders, and
sense amp lifiers.
• S-CS2 is active high.
• S-CS2 low desel ect s the SRAM memory device and r educ es power consumptio n to standby
levels.
F-OE# INPUT FLASH OUTPUT ENABLE: Enables flash memory outputs through the data buffers during a read
operation. F- OE# i s active low.
S-OE# INPUT SRAM OUTPUT ENABLE: Enables SRAM outputs through the data buffers during a read
operation. S- OE# i s acti ve lo w.
F-WE# INPUT FLASH WRIT E ENABLE: Controls writes to the flash memory command register and memory
array. F-WE# is active low. Addresses and data are latched on the rising edge of the second
F-WE# pulse.
S-WE# INPUT SRAM WRIT E ENABLE: Controls writes to the SRAM memory array. S-WE# is active low.
S-UB# INPUT SRAM UPPER BYTE ENABL E: Enables the upper byte for SRAM (DQ8–DQ15).
S-UB# is active low.
S-LB# INPUT SRAM LOWER BYTE ENABLE: Enables the lower byte for SRAM (DQ0–DQ7).
S-L B# is active low.
C3 SCSP Flash Memory
26 Aug 2005 Intel® Advanced+ Boot Block Flash Memory (C3) SCSP Family Datasheet
10 Order Numbe r: 252636 , Revision: 004
F-RP# INPUT
FLASH RESET/DEEP POWER-DOWN: Uses two voltage l evels (VIL, VIH) to control reset/deep
pow e r -dow n mo de.
•When F-RP# is at logic low, the device is in reset/deep power-down mode, which drives
the outputs to High-Z, resets the Write State Machine, and minimizes current levels (ICCD).
•When F-RP# is at logic high, the device is in standard operation.
• When F-RP # transitions from logic-low to logi c-high, the device resets all bl ocks t o locked and
defaults to the read array mode.
F-WP# INPUT
FLASH WRITE PROTECT: Controls the lock-down function of the flexible Locking feature.
•When F-WP# is a logic low, the lock-down mechanism is enabled and blocks marked
lock-dow n ca nnot be u nloc k ed through s oftw are. After F-WP# go es low, any b locks pre viou s ly
marked lock-down revert to that state.
•When F-WP# is logic high, the lock-down mechanism is disabled. Blocks previous ly
locked-down are now locke d, and can be unlo cked or loc k ed through s oftware .
See Section 7.0, “System Design Considerations” on page 41 for details on block locking.
F-VCC SUPPLY FLASH POWER SUPPLY: [2.7 V–3.3 V] Supplies power fo r device core oper ations.
F-VCCQ SUPPLY FLASH I/O POWER SUPPLY: [2.7 V–3.3 V] Supplies power for device I/O operations.
S-VCC SUPPLY SRAM POWER SUPPLY: [2.7 V–3.3 V] Supplies power for device operati ons.
See Section 7.2.2, “F-VCC, F-VPP and F-RP# Transition” on page 42 f or deta il s of po w er
connections.
F-VPP INPUT /
SUPPLY
FLA SH PROGRAM /E R ASE POWER SUPPLY: [1.65 V–3.3 V or 11.4 V–12.6 V] O perates as an
input at logic le vels to control complete flash me mory protection. Supplies power for ac cel erated
flash memory program and erase operations in 12 V ± 5% range. This ball cannot be left floating.
Lower F-VPP ≤ VPPLK, to protect all contents against Program and Erase commands.
Set F-VPP =F-V
CC for in-system read, program and erase operations. In this configuration,
F-VPP can drop as low as 1.65 V to allow for r esistor or diode drop from the syst em supply.
Note: If F-V PP i s driven by a logic signal, th en VIH = 1.65 V. That is , F-V PP must remain above
1.65 V to mo di fy in-sys te m fla sh me mo ry.
Raise F-VPP to 12 V ± 5% for fast er prog r am and era se in a prod uct ion enviro nm en t. 12 V ±
5% to F-VPP can be applied for a maximum of 1000 cycles on the main blocks and 2500 cycles on
the parameter blocks. F-VPP can be connec ted to 12 V for a total of 80 hours maximum.
F-VSS SUPPLY FLASH GROUND: For all internal circuitry. All ground inputs must be connected.
S-VSS SUPPLY SRAM GROUND: For all internal circuitry. All ground inputs must be connected.
NC NOT CONNECTED: Inter nal ly disconnected within the device.
Table 2. Intel® Advanced+ Boo t Block SCSP Ball Descriptions (Sheet 2 of 2 )
Symbol Type Name and Function
C3 SCSP Fla s h Me mor y
Datasheet Intel® Advan ce d+ Bo ot Block Flash Memory (C 3) SCSP Family 26 Aug 2005
Order Number: 252636, Revisio n: 004 11
2.0 Principles of Op eration
The flash memory uses a CUI and automated algorithms to simplify progra m and er ase operat ions .
To automa te pr ogram and erase operations, the WSM handles data and address lat che s, WE#, and
system status requests.
.
2.1 Bus Operati on
All bus cycl es to or from the SCSP confo r m to standard microcontroller bus cy cle s. Four control
signals dictate the data f low in and out of the flash component:
•F-CE#
•F-OE#
•F-WE#
•F-RP#
Four sepa rate control signals handle the da ta flow in and out of the SRAM component:
•S-CS1#
•S-CS2
•S-OE#
•S-WE#
Table 2 on page 9 and Table 3 on page 12 summarize the s e bus operations .
Figure 2. Intel® Advanced+ Boot Block SCSP Block Diagram
F-VCC
F-OE#
F-CE#
A[Max:0]
2-, 4- or 8-M bit
SRAM
28F160C3
or
28F320C3
Flash
S-VCC
F-VCCQ
S-CS1
S-CS2
S-OE#
S-WE#
S-UB#
S-LB#
F-VPP
F-WE#
F-VSS
S-VSS
D[15:0]
F-WP#
F-RP#
C3 SCSP Flash Memory
26 Aug 2005 Intel® Advanced+ Boot Block Flash Memory (C3) SCSP Family Datasheet
12 Order Numbe r: 252636 , Revision: 004
2.1.1 Read
The flash mem ory device provides four read modes:
•Re ad arr ay
•Re ad id en t ifier
•Re ad sta tu s
•CF I q ue r y
The se flas h memory re ad modes do not dep end on the F-VPP voltag e. Upon i nit ial de vic e power -up
or after exit from reset, the fla sh memory device automatically defaults to read a rray mode. F-CE#
and F- OE# mus t be ass erted to obta in data from the flash memory device.
The SRAM provides only one read mode. S-C S 1#, S- CS 2, and S-OE# must be asserted to obtain
data from the SRAM device. See Table 3 for a summary of operations.
2.1.2 Output Disable
When F- OE# and S-OE# are deass erted, the SCSP out put signal s ar e pla ced in a high-impedance
state.
Table 3. Intel Advanced+ Boo t Block Flash Memo ry SC SP Bus Operati on s
Modes
Flash Signals SRAM Signals Memory Output
Notes
F-RP#
F-CE#
F-OE1#
F-WE#
S-CS1#
S-CS2
S-OE1#
S-WE#
S-UB#,S-LB#(1)
Memory Bus Control
D0–
D15
FLASH
Read H L L H SRAM must be in High Z Flash DOUT 2,3,4
Write H L H L Flash DIN 2,4
Standby H H X X
Any SRAM mode is allowable
Other High Z 5,6
Output Disable H L H H Other High Z 5,6
Reset L X X X Other High Z 5,6
SRAM
Read FLASH must be in High Z LHLHLSRAMD
OUT 2,4
Write L H H L L SRAM DIN 2,4
Standby
Any FLASH mode is allowable
HXXXX
Other High Z 4,5,6
XLXXX
Output Disable L H H H X Other High Z 4,5,6
Data Retention same as a standby Ot her High Z 4,5,7
Notes:
1. Two devices cannot dr ive the mem ory bus at the same t ime.
2. To place the SRAM into data retention mode, lower the S-VCC signal to the VDR ra nge, as specified.
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2.1.3 Standby
When F-CE# and S-CS1# or S-CS2 are deasserted, the SCSP enters a sta ndby mode, which
substantially reduces device power consumption. In standby mode, outputs are placed in a high-
impe dance st ate indep endent of F-OE# a nd S-OE#. If t he flash m emory devi ce is dese lecte d during
a program or era se operation, the flash mem ory continues to consume active power unt il the
program or erase operation is complete.
2.1.4 Flash Reset
The flash memory device ente rs a reset mode when RP# is dr iven low. In reset mode, internal
circ uitry is turned off and outputs are pla ced in a high -impedance state.
After returning from reset, a time tPHQV is requ ir ed unti l outputs ar e valid. A delay (tPHWL or
tPHEL) is required before a write sequenc e can be initiated. After this wake-up inter val, normal
operation is restored.
•The flas h memory device default s to read array mode.
•The status register is set to 80h.
•The read con f iguration register defaults to asynchronous reads.
If RP# is taken low during a block erase or program operation, the operation aborts and the
memory contents at the aborted loc ation are no longer valid .
2.1.5 Write
•W rite s to flash memory occur when both F- CE# and F-WE# ar e ass erted and F-OE# is
deasserted.
•W rite s to S RAM occ ur when both S - CS 1# and S-WE# are ass erted and S-OE # and S- CS 2 are
deasserted.
Commands are writ ten to the flash memory Command User Interface (CUI), using standard
micr oprocessor writ e timings to con trol flash memory ope rations. The CUI does not occupy an
addressable memory location within the flash memory device. The address and data buses are
latched on the risi ng edge of the second F-WE# or F-CE# puls e, whiche ver oc curs first. (See
Fig ure 6 on page 33 and Figure 7 on page 35 for read and write waveforms.)
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3.0 Flash Memory Modes of Operation
The flash memory has four read modes:
•Re ad arr ay
•Read configuration
•Re ad sta tu s
•CF I q ue r y
The w r it e mo d es are :
•Program
•Erase
Thre e additiona l modes are available only during suspended operations:
•Erase suspend to program
•Erase suspend to read
•Progra m suspend to read
Thes e modes are reached using the commands summarized in Table 5 “Flash Memory Command
Definitions” on page 19.
3.1 Read Array (FFh)
When F-RP# transitions from VIL (r es e t) to VIH, the flash memory device defaults to read array
mode and re sponds to the read control inputs without additiona l CUI commands.
In addition, the address of the desired location must be applied to the address balls. If the flash
me mory device is not in read array mode, such as after a progra m or er ase operation, the Read
Array command (FFh) must be written to the CU I before array reads can take place.
3.2 Read Identifier (90h)
The Read Configuration mode outputs three types of information:
•Manufacturer/device id entifier
•Block locking status
•Protection register
1. To switch the flash mem ory device to t his mode, wr ite the read configuration command (90h).
In this mode, rea d cycle s from add resse s show n in Table 4 “Read Configuration Table” on
page 15 retrieve the specified information.
2. To return to read array mode, write the Read Array command (FFh).
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Order Number: 252636, Revisio n: 004 15
Intel reserves other locations within the conf iguration add r ess space for future use.
3.3 Read Status Register (70h)
The status register indicates the status of device ope rations, and the success /failure of that
operation.
1. After you issue the Read Status Regi s ter (70h) command, sub sequent reads output data from
the status register until another command is issued.
2. To return to reading from the array, issue a Read Array (FFh) command.
The sta tus register bits are output on DQ[7:0]. The upper byte, DQ[15:8], outputs 00h during a
Read Status Register command.
The contents of the status register are latched on the falling edge of F-OE# or F-CE#, whichever
occurs last. Lat ching on the fal ling edge preve nts possible bus errors that might occur if sta tus
register contents change while being read. F-CE# or F-OE# must be toggled with each subsequent
status read, or the status regis ter does not indicate completion of a program or erase operation.
When th e W SM is acti ve, SR7 indicates the st atus of the W SM. The remaining bits in the st atus
regis ter ind icate whether the WSM was succe ssfu l in performing the des ired oper ation (see Table 6
“Flas h Memory Status Register Definition” on page 19).
Table 4. Read Configuration Table
Item Address Data Notes
M anufactu rer Code (x16) 0x00000 0x0089
Device ID (See Appendix D) 0x00001 ID
Block Lock Configuration 0xXX002 LOCK 1, 2
•Block Is Unlocked DQ0=0
•Block Is Locked DQ0=1
•Block Is Locked-Down DQ1=1
Prote c tion Register Lock 0x 80 PR -LK 3
Protection Register (x16) 0x81-0x88 PR
Notes:
1. See Sec t io n 3.7 for valid lock status outputs.
2. “XX” specifies the block address of lock configuration being
read.
3. See Sec t io n 3.8 for protection register infor m ation.
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3.3.1 Clear Status Register (50h)
The WSM sets status b its 1 through 7 to a 1 value, an d clears bits 2, 6 and 7 to a 0 value . However,
WSM cannot clear stat us bits 1 or 3 through 5 to a 0 value . Beca use bits 1, 3, 4, and 5 indicate
various error conditions , only the Clear S tatus Regis ter (50h) comman d can cle ar these bits .
I f the system software c ontrols resetting the se bits, seve ral operations (such as cumulative ly
pr ogramming several addresses or eras ing multiple blocks in sequence) can be performed before
r ea ding the status regi ster to determine wheth er an error oc curre d during that series.
•Clear the status register before beginning another command or sequence.
•A Read Array command must be issued before data can be read from the memory arra y.
•Resetting the flash memory device also clears the status register.
3.4 CFI Query (98h)
The CF I quer y m ode outputs Commo n Flash Interfac e (CFI) data when the fl as h memory device is
read.
The CFI data struct ure contains inf orm ation such as:
•block size
•density
•command set
•electr i cal s p ec if i cati o ns
1. To access this mode, writ e the CFI Query Com mand (98h).
In this mode, rea d cycle s from add resse s show n in Appendix B, “CFI Query Structure”
r etrieve the speci f ied info r ma tion.
2. To return to read array mode, write the Read Array command (FFh).
3.5 W ord Progr am (40h/10h)
Programming uses a two-write sequence.
1. The Program Setup command (40h) is written to the CUI.
2. A second write specifi es the address and data to program.
3. The WSM executes a sequence of internally timed events to program desired bits of the
addressed location
4. The WSM then verifies that the bits are sufficiently programmed.
Programming th e memory changes the val ue of specific bi ts within an address to 0.
Note: If you attempt to program a 1 value, the memory cell contents do not change and no error occurs .
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The sta tus register indicates programming stat us :
•While the program sequence execute s, status bit 7 has a 0 value.
•To poll the status register, toggle either F-CE# or F-OE#.
While programming, the onl y valid commands ar e:
•Read Status Regi ster
•Program Suspend
•Program Resume
1. When programming is complete, check the program status bits.
— If the program ming ope ratio n was un success ful, status regi ster but SR .4 is s et to i ndic ate a
program failure.
— I f SR .3 is s et , th e n F - V PP was not within accept able limits, and the WSM did not execute
the program command.
— If SR.1 is set, a program ope ration was attempt ed on a locked bloc k and the operation
aborted.
2. Clea r the status register before attempting the ne xt operation.
Any CUI instruction can fol low after programm ing is completed.
3. To prevent inadvertent status register reads, reset the CUI to read array mode.
3.5.1 Suspending and Resuming Program (B0h/D0h)
The Program Suspend comma nd halts an in-progress program operation, so that data can be read
from other location s of memory.
1. After the programming process starts, write the Program Suspend command to the CUI.
— This command requests th at the WSM suspend the program sequence (at predetermined
points in the program algorithm).
— The flash memory device continues to output status register data after the Program
Suspend command is written.
2. Pol l st atus regist er bits SR.7 and SR.2 to determine when the prog ram operation has be en
suspended (both are set to 1).
Note: tWHRH1/tEHRH1 specifies the program suspend laten cy.
A Read Array comman d can be written to the CUI to read da ta from any block othe r than the
suspended block. The only other valid commands, while program is suspended, are:
•Read Status Regi ster
•Read Configurat ion
•CFI Q u ery
•Program Resume.
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After the Program Resume command is written to the flash memory:
•WSM continues the programming process.
•Status register bits SR.2 and SR.7 are automatically cleared.
•The flash mem o r y d ev ice au toma tica lly ou tp uts statu s regis ter data when read (se e Appendix
A, “Pr o g r am/ Er ase F l owch ar t s”).
Note: F-VPP must remain at the same F-VPP level used for program while in program suspend mode.
F-RP# must also remai n at VIH.
3.6 B lo ck Era se (20 h)
To erase a block, write the Erase Set-up and Erase Confi rm c ommands to the CUI, along with an
address ident ifying the block to be erased. This address is latc hed internally when the Era se
Confi rm comma nd is iss ued. Block er asure resul ts in all bit s withi n th e block being s et to “ 1.” Only
o n e b l ock can be erased at a time. The WSM will exe cute a sequence of intern ally timed ev ents to
pr ogram all bits within the block to “0,” era se all bit s within the block to “1,” then verify that al l
bits within the block are sufficiently erased. While the erase executes, status bit 7 is a “0.”
When the status register indicates that erasure is complete, check the erase status bit to verify that
the erase operation was successful. If the Erase operation was unsuccessful, SR.5 of the status
reg ister wi ll be set to a “ 1 ,” in d i ca tin g an er ase fa il u r e. If F- VPP w a s no t w it hin ac c ep tab le lim i ts
aft er th e Erase Conf ir m comm a nd w as iss u ed , th e WS M wi ll no t ex e cu t e th e er a s e seq u e nce;
instead, SR.5 of the status register is set to indicate an erase error , and SR.3 is set to a “1” to
iden t if y th at F -VPP supply voltage was not within acceptable limits.
After an erase operation, clear the status regis ter (50h) before attempting the next operation. Any
CUI ins truction ca n follow after era sure is completed; however, to prevent inadverte nt status
reg iste r rea d s, it is ad vi s a b le to p la ce th e fl as h in r ead ar ra y mo d e af t er th e erase is comp l et e.
3.6.1 Suspending and Resuming Erase (B0h/D0h)
An eras e operation can take seve ral seco nds to comple te, the ref ore, the Erase Suspe nd command is
provided to allow erase-seque nce interr uption in order to rea d data from, or program data to,
anot her bloc k in memory. Once a n erase s equence ha s start ed, writ ing t he Erase Suspe nd comman d
to the CUI causes the device to suspend the erase sequence at a predetermined point in the erase
algorithm. Block eras e is suspended when Status Registe r bits SR[7,6] are set. Suspend latency is
spe cified in S ec tion 5.7, “Flash Erase and Program Timings” on page 31.
When an erase ope ration has been sus pende d, a Word Pro gram or Re ad oper ation c an be pe rformed
within any block, exc ept the bloc k that is in an erase suspend state. An erase ope ration cannot be
nes ted within another erase suspend operation.
A suspended erase operation cannot resume until the nested program operation has completed.
Read Array, Read Status Register, Clear Status Register, Read Identifier, CFI Query, Erase
Resume, are all valid comm ands during Erase Suspend. Additionally, Program, Program Suspend,
Program Resume, Lock Block, Unlock Block and Lock-Down Block are valid commands during
Eras e S us p en d .
To resume an erase suspend opera tion, issue the Resum e command. The Res um e command can be
written to any dev ice address. When a program operation is nes ted within an Erase Suspend
operation and the Program Suspend command is issued, the device will suspend the program
C3 SCSP Fla s h Me mor y
Datasheet Intel® Advan ce d+ Bo ot Block Flash Memory (C 3) SCSP Family 26 Aug 2005
Order Number: 252636, Revisio n: 004 19
operation. When the resume command is issued, the de vice will resume the program operation
first. Once the ne sted program operation is completed, an additional Resume command is required
to complete the block operation.
Table 5. Flash Memory Command Definitions
Command Note First Bus Cycle Second Bus Cycle
Operation Address Data Operation Address Data
Read Array 1 W r ite X FFh
Read Identifier 1, 2 Write X 90h Read IA ID
CFI Query 1, 2 Wr ite X 98h Read QA QD
Read Status Register 1 Write X 70h Read X SRD
Clear Status R egister 1 Write X 50h
Word Program 1, 3 Write X 40h/10h Write PA PD
Bl oc k E ras e / Confir m 1 Wri te X 20h Writ e BA D0h
Progr am/Er ase Suspen d 1 Write X B0h
Pr ogram/Er ase Resume 1 Write X D0h
Lock Block 1 Write X 60h Write BA 01h
Unlock Block 1, 4 Write X 60h Write BA D0h
Lock-Down Block 1 Write X 60h Write BA 2Fh
Protection Register Program 1 Write X C0h Write PA PD
Lock Protection Register 1 Write X C0h Write PA FFFD
X = Don’t Care PA = Program Address BA = Block Address IA = Identifier Address QA = Query Address
SRD = St atus Register Data PD = Program Data ID = Identifier Data QD = Query Data
Notes:
1. Wh en writ in g co m ma nd s, th e up pe r data bu s [ DQ 8–DQ15] should be either VIL or VIH, to mi nim iz e cur ren t draw.
2. Following the R ead Configuration or CFI Query commands, read o perations out put device configuration or CFI que ry
information, respectively.
3. Either 40h or 10h command is valid, but the Intel standard is 40h.
4. When unlocking a b lock, WP # must be held for thr ee clock cycles (1 clock cycle after the second c ommand bus cycle) .
Table 6. Flash Memo ry Status Register Definition
WSMS ESS ES PS VPPS PSS BLS R
76543210
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3.7 B lo ck Lo ck ing
The instant, individual block locking featur e tha t allows any flas h block to be lock ed or unlocked
with no latency, which enable s instant code and da ta protection.
This locking offers two levels of prote ction. The firs t level allows soft ware -only control of block
locking (useful for data bloc ks th at chan ge frequently), while the second level requires hardware
interaction before locking ca n be changed (useful for code blocks tha t cha nge infrequently).
The following sec tions will di sc us s the ope ration of the locking syst em . T he te rm “state [XYZ] ”
will be used to specify locking states; e.g., “state [001],” where X = value of WP#, Y = bit DQ1 of
the Block Lock status register, and Z = bit DQ0 of the Block Lock stat us register. Table 8 “Bl ock
Lock i n g Stat e Tran si ti o n s” on p ag e 23 def ines al l of th ese possibl e lo ck i ng s t at es .
Bit Number NOTES:
SR.7 WRITE STATE MACHINE STATUS
1 = Ready (WSMS)
0=Busy
Check Write St ate M achin e bit first to deter mine Word P rogram or
Bl oc k Eras e com pl eti on , be for e che ck ing Pr ogr am or Erase Status
bits.
SR.6 = ERASE-SUSPEND STATUS (ESS)
1 = Erase Suspended
0 = Erase In Progress/Completed
When Er ase Suspen d is issued, WSM h alts execution and sets
both WSMS and ESS bits to 1. ESS bit remains set to 1 until an
Er ase Resume command is issued .
S R.5 = ERASE STATUS (ES)
1 = Error In Block Erase
0 = Successful Block E rase
When this bit is s et to 1, WS M has ap plie d the max. n umber of
erase pulses and is still un able to verify successful block erasure.
SR.4 = PROGRAM STATUS (PS)
1 = Error in Programming
0 = Successful Pr ogramming
When this bit is set to 1, WSM has attempted but failed to program
a word/byte.
SR.3 = F-VPP STATUS (VPPS)
1=F-V
PP Low Detect, Opera tio n Abort
0=F-V
PP OK
The F-VPP status bit does n ot provide c ontinuou s ind icat ion of VPP
level. The WSM interrogates F-VPP l evel only after the Program or
Er ase command sequences have been entered, and informs the
system if F-VPP has not been switched on. The F-VPP is also
c hecke d before the operation is v erified by the WS M. The F-VPP
status bit is not guaranteed to report accurate feedback between
VPPLK and VPP1 min.
SR.2 = PROGRAM SUSPEND STATUS (PSS)
1 = Program Suspended
0 = Pr ogram in Pr ogress/Co mple ted
When Program Suspend is issued, WSM halts execution and sets
both WSMS and PSS bits to 1. PSS bit remains set to 1 until a
Pr ogram Resume command is issued .
SR.1 = B LOCK LOCK STATUS
1 = Pr og/Er ase a ttempted on a locked b lock; O peration
aborted.
0 = No oper atio n to locked blocks
If a program or erase oper at ion is att empted to one of the locked
blocks, this bit is set by the WSM. The operation specified is
aborted and the device is returned to read status mode.
SR.0 = RESERVED FOR FUTURE ENHANCEMENTS (R) This bit is reserved for future use and should be masked out when
polling the status register.
Note: A Command Sequence Error is indicated when SR.4, SR.5 and SR.7 are set.
C3 SCSP Fla s h Me mor y
Datasheet Intel® Advan ce d+ Bo ot Block Flash Memory (C 3) SCSP Family 26 Aug 2005
Order Number: 252636, Revisio n: 004 21
3.7.1 Block Locking Operation Summary
The fol lowing concisely summar izes the locki ng functionality.
All blocks are locked when powered-up, and c an be unlocked or locked with t he Unlock and Lock
commands.
•The Lock-Down command locks a block and prevents it from being unlocked when WP# = 0.
•When WP# = 1, Lock-Down is overridden and commands can unlock/lock locked-down
blocks.
•When WP# returns to 0, lock ed-down blocks return to Lock-Down.
•Lock-Down is cleared only when the device is reset or powered-down.
The lockin g s tatus of each block can set to Locked, Unlocked, and Lock-Down, each of which will
be described in the following sections. A comprehensive state t able for the locking functions is
shown in Table 8 on page 23, and a flowchart for locking operations is shown in Figure 19 on
page 50.
3.7.2 Locked State
The default status of all blocks upon power-up or reset is lo cke d (s tates [001] or [101]). Lock ed
blocks are fully protected from alteration. Any program or erase operations attempted on a locked
block will return an error on bit SR.1 of the status regi st er. The stat us of a loc ked block can be
changed to Unlocked or Lock-Down us ing the appropriate software comma nds . Unlocked blocks
can be locke d issuing the “Lock” command sequence, 60h followed by 01h.
3.7.3 Unlocked State
Unlocke d blocks (states [000], [100], [110]) can be progr ammed or erased. All unlocked blocks
return to the Locked state when the device is reset or powered down. The st atus of an unlocked
block can be chan ged to Locked or Lo cke d-Down using the appropriate softwa re c ommands. A
Locked block can be unlocked by writing the Unlock command sequence, 60h followed by D0h.
3.7.4 Lock-Down State
Blocks that are Locked-Down (state [011]) are protected from pr ogram and erase opera tions (just
like Locked blocks), bu t the ir prote ction s tatu s cannot be change d using s oftware commands al one.
A Locked or Unlock ed block ca n be Locked-down by writing the L ock-Down command se quence,
60h followed by 2Fh. Locked-Down blocks revert to the Locked state when the devi ce is reset or
powered down.
The Lock-Down funct ion is dependent on the WP# input ball . When WP# = 0, blo cks in Lock-
Down [011] are protected from p rogram, erase, and lock status changes. When WP# = 1, the Lock-
Down function is disabled ([111]) and locked-down blocks can be individually unlocked by
soft ware command to the [110] state, where they can be erased a nd program med. These blocks can
then be re-locked [111] and unlocked [110 ] as des ired while WP# remains high. When WP# goes
low, blocks that were previously locked-down return to the Lock-Down state [011] regardless of
any changes made while WP# was high. Device res et or power-down res ets all blocks, including
th o se in Lock-Down, to Locked state.
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3.7.5 Reading Lock Status for a Block
The lock status of every block can be read in the configuration read mode of the devi ce. To enter
this mode , write 90 h to th e devic e. Subs equent reads at Bl ock Ad dress + 00 002 will out put the lock
status of that block. The lock status is represe nted by the least significant outputs, DQ0 and DQ1.
DQ0 indicates the Block Lock/Unlock status and is set by the Lock command and cleared by the
Unl o ck co mmand. I t is al so au to m a ti cal ly s et when en t er in g Lo ck - D o wn . D Q 1 in d i cates Lo ck -
Down status and is set by the Lock-Down comm and. It cannot be cleared by software, only by
device reset or power-down.
3.7.6 Locking Operation During Erase Suspend
Changes to block lock status can be performed during an erase suspend by using the standard
locking com m and sequences to unlock, lock, or lock-down a block. This is u se f ul in the case when
another block needs to be updated while an erase operation is in progress.
To change bloc k locking during an erase operation, fi rs t wr ite the erase suspe nd com m and (B0h),
then check the status register until it indicates that the erase operation has been suspended. Next
write the desired lock command sequence to a block and the lock status will be changed. After
completing any desired lock, read, or program operations, resume the erase operation with the
Erase Re s u me comm a n d (D 0 h) .
I f a bloc k is locke d or locked-down during a suspended erase of the s ame block, the locking status
bits wil l be cha nged imme diate ly, but when the e rase is resum ed, the erase ope ratio n will compl ete.
Locking operations cannot be performed during a program sus pend.
3.7.7 Status Register Error Checking
Using nested locking or pr ogram command sequences during erase suspend can introduce
am biguity in to s tatus register results.
Si nce loc king changes are performed usi ng a two cycle command seq uence, e.g., 60h followed by
01h to lock a block, following th e Configuration Setup command (60h) with an invalid command
will produce a lock command error (SR.4 and SR.5 will be set to 1) in the status regist er. If a lock
com mand error oc curs duri ng an era se suspend , SR.4 and SR. 5 will be set to 1, and will remain at 1
after the erase is resumed. When erase is complete, any possible error during the erase cannot be
detected via the status register because of the pr evious locking command error.
A similar situation happen s if an error occurs during a program operation error nested within an
erase su s p en d .
Table 7. Block Lock Status
Item Address Data
Block Lock Configuration XX002 LOCK
• Block Is Unlocked DQ0=0
• Block Is L o cked DQ 0=1
• Block Is Locked -Down DQ1=1
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Order Number: 252636, Revisio n: 004 23
3.8 128 Bit Protecti on Register
The C3 SCSP architecture includes a 128-bit protection register than can be used to increase the
security of a syste m design. For example , the number conta ined in the prote ction register can be
use d to “mate” the flash com ponent with other system components such as the CPU or ASIC,
preventing device substitution.
3.8.1 Reading the Protection Register
The protection register is read in the configurati on read mode. The device is switched to this mode
by wr iting the Read Conf iguration command (90h ). Once in t his mode, read cycles from addresses
shown in Appendix E retrieve the spec ified information. To return to re ad array mode, write the
Read Array command (FFh).
Table 8. Block Locking State Transitions
Current State Erase/
Program
Allowed?
Next State after Command I nput
WP# DQ1DQ0Name Lock Unlock Lock-Down
0 0 0 Unlocked Yes Go To [001] – Go To [011]
1 0 0 Unlocked Yes Go To [101] – Go To [111]
001Locked (Default) No – Go To [000] Go To [01 1]
1 0 1 Loc ked No – G o To [100] G o To [111 ]
0 1 1 Locked-Down No – – –
110 Lock-Down
Disabled Ye s Go To [111] – Go To [111]
1 1 1 No - Go To [110 ] –
Notes:
1. “–” indicates no change in the current state.
2. In this table, the nota tion [XYZ] denotes the locking state of a block, where X = WP#, Y = DQ1, and Z = D Q 0. The
current locking state of a block is defined by the state of WP# and the two bits of the block lock status (DQ0, DQ1). DQ0
indicates if a bloc k is locked (1) or unlo cked (0). DQ1 indicat es if a block has been locked-do wn (1) or not (0) .
3. At pow er-up or d evice reset, all blocks default to Locked state [001] (if WP# = 0). holdi ng WP# = 0 is the recommended
default.
4. The “Erase/Program Allowed?” column shows whethe r erase and program operations are enabled (Yes) or disabled
(No) in that block’s current locking state.
5. The “Lock Command Input Result [Next State]” c olumn shows the re sult of wr iting the three locking commands (Lock,
Unlock, Lock-D own) in t he current locking state. For example, “Goes To [0 01]” would mean that writing the command to
a block in the current locking state would change it to [001].
6. The 128 bit s of the protection register are divid ed into two 64-bit segments . O ne of the s egments is programmed at the
Intel factory with a unique 64 bit number, which is unch angeable. The other segment is left blank for customer desig ns
to progr am as desired. O nce the customer segment is programmed, it can be locked to prevent reprogramming.
C3 SCSP Flash Memory
26 Aug 2005 Intel® Advanced+ Boot Block Flash Memory (C3) SCSP Family Datasheet
24 Order Numbe r: 252636 , Revision: 004
3.8.2 Programming the Protection Register (C0h)
The pr otection re gister bit s a r e programmed using the two-cycle Protection Program command.
The 64-bit number is programmed 16 bits at a time for word-wide parts. Firs t write the Protection
Program Setup com mand, C0h. The next write to the device will latch in address and data and
pr ogram the specified location. The allowable addres se s are shown in Appendix E. See F igure 20
“Protection Register Programming Flowch art” on page 51.
Any attempt to address Protection Program commands outside the defined protection register
addre ss space will resu lt in a status regis te r error (program error bit SR.4 will be set to 1).
Attempting to program or to a previous ly locked protection register segmen t will result in a status
r egi st er e rror (program error bit SR.4 and lock error bit SR.1 will be set to 1).
3.8.3 Locking the Protection Register
The user-programma ble segme nt of the pr otection register is lockable by programming Bit 1 of the
PR-LOCK location to 0. Bit 0 of this location is programmed t o 0 at the Intel factory to protect the
unique device number. This bit is set using the Protection Program command to program FFFDh to
the PR-LOCK locat ion. Afte r these bit s have been programmed, no furt her chang es can be made to
the values stored in the protection register. A Protection Program command to locked words will
re sult in a status register error (program error bit SR.4 and Lock Error bit SR.1 will be set to 1).
The pr otection re gister loc kout state is not reversib le.
Figure 3. Protection Register Memory Map
4 Words
F actory Pr ogram m ed
4 Words
User Progr ammed
PR-LOCK
88H
85H
84H
81H
80H
C3 SCSP Fla s h Me mor y
Datasheet Intel® Advan ce d+ Bo ot Block Flash Memory (C 3) SCSP Family 26 Aug 2005
Order Number: 252636, Revisio n: 004 25
4.0 Power and Reset Considerations
4.1 Power-Up/Down Characteristics
In order to prevent any condition that may res ult in a spurious write or eras e ope ration, it is
recomm ende d to power-up F - VCC, F-V CCQ and S-VCC to gether. Conversely, F-VCC, F-VCCQ and
S-VCC must power -d own togethe r . It is also re commende d to power- up F- VPP with or slightly af ter
F-VCC. Conversely, F-VPP must power down with or slightl y before F-VCC.
If F-VCCQ and/or F-VPP are not connected to the F-VCC supply, then F-VCC should attain F-
VCCMin before applying F-VCCQ and F-VPP. Devic e inputs should not be driven before supply
voltage = F-VCCMin. Power supply transitions should only occur when F-RP# is low.
4.2 Additional Flash Features
C3 SCSP products provi de in-system progra mming and erase in the 1.65 V–3.3 V range. For fast
production programming, it also includes a low-cost, backward-compatible 12 V programming
feature.
4.2.1 Improved 12 Volt Production Programming
When F-VPP is between 1.65 V and 3.3 V, all program and erase current is drawn through th e
F-VCC signal. Note that if F-VPP is driven by a logic signal, VIH min = 1.65 V. T hat is, F - VPP must
remain a bove 1. 65 V to perform in -system fl ash modif ica tions . When F-VPP is c onnect ed to a 12 V
power su pply, the device draws program and erase current directly from the F-VPP signal. This
eliminates the need for an external switching transistor to control the voltage F-V PP. Figure 12
“Example Power Supply Configurations” on page 43 shows examples of how the flash power
supplies can be configured for various usage models.
The 12 V F-VPP mode enhances programming performance during the sho rt period of time
typic ally fou nd in manu facturi ng pro cesse s; however, it is not intende d for exte nded us e. 12 V may
be applied to F-VPP during program and era s e operations for a maximu m of 1000 cycles on the
main blocks and 2500 cycles on the parameter blocks. F -VPP may be connected to 12 V for a total
of 80 hour s maxi mum. S tressing the device beyond these lim its may cause permanent damage.
4.2.2 F-VPP ≤ VPPLK for Complete Protect ion
In addition to the fle x ible block locking, the F-VPP programmi ng voltage can be held low for
abs olute hardware wr ite protect ion of all blocks in the flas h device. When F-VPP is below VPPLK,
any prog ram or e rase ope ration will resu lt in a err or , pro mpting the co rrespon ding status regis ter bi t
(SR. 3) to be se t.
C3 SCSP Flash Memory
26 Aug 2005 Intel® Advanced+ Boot Block Flash Memory (C3) SCSP Family Datasheet
26 Order Numbe r: 252636 , Revision: 004
5.0 Electrical Specifications
5.1 Absolute Maximum Ratings
Warning: Str es sing the dev ice beyond the Absolute Maxi mum Ratings in Table 9 might cause permanent
damage. These are stress ratings only. Do not operate the flash memory device beyond the
Operating Conditions in Table 10. Extended exposure beyond these Operating Conditions might
affect device reliability.
NOTICE: This datasheet contains information on products in full production. The specifications are subject to
change without notice. Verify with your local Intel Sales office that you have the latest datasheet before finalizing a
design.
Table 9. Absolute Maximum Rating s
Parameter Maximum Rating Notes
Extended Operating Temperature
–25°C to +85°C
Dur ing Read
Dur ing Flas h Block Erase and Program
Temperature under Bias
Storag e Te mp erat u re –65°C to +1 25 °C
Voltage on Any Ball (except F-VCC /F-VCCQ / S-VCC and F-VPP) with
Re spec t to GN D –0.5 V to +3.3 V 1
F-VPP Vol tag e ( for Blo c k E ras e and P rogr a m) w ith Re sp ec t to G N D –0 .5 V to +13 . 5 V 1,2 ,4
F-VCC / F-VCCQ / S-VCC Supply V o ltage with Respect to GND –0.2V to +3.3 V
Out put Short Circuit C urrent 100 mA 3
Notes:
1. Minimu m DC vol tage is –0.5 V on inpu t/output balls . During transitions, this level may undershoot
to –2 .0 V for pe ri ods < 20 ns. Maxim um D C vol t age o n in pu t/o ut put ba l ls i s F-V CC / F-VCCQ / S-VCC
+ 0.5 V which, during transitions, may overshoot to
F-VCC / F-VCCQ / S-VCC + 2.0 V for periods < 20 ns.
2. Maximum DC voltage on F-V PP may ov ershoot to +14.0 V for periods < 20 ns.
3. F-VPP voltage is normall y 1.65 V–3.3 V. C onnection to supply of 11.4 V–12.6 V c an onl y be done
for 1000 cycles on the main blocks and 2500 cycles on the parameter blo c ks during program/
erase. F-VPP may be connected to 12 V for a total of 80 hours maximum. See Section 4.2.1 for
details
4. Output shorted for no more than one second. No more than one output shorted at a time.
C3 SCSP Fla s h Me mor y
Datasheet Intel® Advan ce d+ Bo ot Block Flash Memory (C 3) SCSP Family 26 Aug 2005
Order Number: 252636, Revisio n: 004 27
5.2 Operating Conditions
5.3 Capacitance
TCASE = +25°C, f = 1 MHz
Tabl e 10. Maximum Operating Con ditions
Symbol Parameter Notes Min Max Units
TCASE Operating Temperatur e –25 +85 °C
VCC / VCCQ F-VCC /F-VCCQ /S-VCC Supply
Voltage 1 2.7 3.3 Volts
VPP1 Sup pl y Vol tage 1 1. 65 3 .3 Vo lts
VPP2 1, 2 11. 4 12.6 Vol ts
Cycling Block Erase Cycling 2 100,000 Cycles
Notes:
1. F-VCC/F-VCCQ must s hare the same supply. F-VCC/S-VCC must sh are the same supp ly when not in
data retention.
2. Applying F-VPP = 11.4 V–12.6 V during a pr ogram/erase can only be do ne for a maximu m of 1000
c ycles on th e m ain bl o cks and 2500 cyc le s o n the p aram et er b lo cks . F- VPP ma y b e co nnec te d to 1 2 V
for a total of 80 hours maximum. See Se ction 4.2 .1 fo r details.
Table 11. Capacitance
Sym Parameter Notes Typ Max Units Conditions
CIN Input Capacitance 1 16 18 pF VIN =0V
COUT Ou tp ut C apa cit an ce 1 2 0 22 pF V OUT =0V
Note: Sampled, not 100% tested.
C3 SCSP Flash Memory
26 Aug 2005 Intel® Advanced+ Boot Block Flash Memory (C3) SCSP Family Datasheet
28 Order Numbe r: 252636 , Revision: 004
5.4 DC Characteristics
Table 12. DC Characteristics (Sheet 1 of 2)
Symbol Parameter Device Note 2.7 V – 3.3 V Unit Test Conditions
Typ Max
ILI Input Load Current Flash/
SRAM 1 ± 2µA
F-VCC/S-VCC =V
CC Max
VIN =V
CCMax or GND
ILO Output Leakage Current Flash/
SRAM 10.2 ± 10 µA F-VCC/S-VCC =V
CC Max
VIN =V
CC Max or G ND
ICCS VCC Standby Current
0.25µm
Flash 11025
µA
F-VCC =V
CC Max
F-CE# = F-RP# = VCC
F-WP# = VCC or GND
VIN =V
CC Max or G ND
0.13µm
and
0.18µm
Flash
1715
2-Mb
SRAM 1 - 10 µA S-VCC=V
CC Max
S-CS1# = VCC, S-C S2 = VCC
or S-CS2 = GND
VIN =V
CC Max or G ND
4-Mb
SRAM 1 - 15 µA
8-Mb
SRAM 1 - 25 µA
ICCD VCC Deep Power-Down Current
0.25µm
Flash 1725
µA F-VCC =V
CCMax
VIN =V
CC Max or G ND
F-RP# = GND ± 0.2 V
0.13µm
and
0.18µm
Flash
1715
ICC Operating Power Supply Current
(cycle time = 1 µs)
2-Mb
SRAM 1-7mA
IIO =0 mA, S-CS1#=V
IL
S-CS2 = S-WE# = VIH
VIN =V
IL or VIH
4-Mb
SRAM 1-10mA
8-Mb
SRAM 1-10mA
ICC2 Operating Power Supply Current
(min cycle time)
2-Mb
SRAM 1-40mA
Cycle time = Min, 100% duty,
IIO = 0 mA, S-CS1# = VIL,
S-CS2 = VIH, VIN =V
IL or VIH
4-Mb
SRAM 1-45mA
8-Mb
SRAM 1-50mA
ICCR VCC Read Current
0.25µm
Flash 1,2 10 18 mA F-VCC =V
CCMax
F-OE# = VIH, F-CE# = VIL
f=5 MHz, I
OUT =0 mA
VIN =V
IL or VIH
0.13µm
and
0.18µm
Flash
1,2 9 18 mA
C3 SCSP Fla s h Me mor y
Datasheet Intel® Advan ce d+ Bo ot Block Flash Memory (C 3) SCSP Family 26 Aug 2005
Order Number: 252636, Revisio n: 004 29
ICCW VCC Program Current Flash 1,3
18 55 mA F-VPP =V
PP1
Program in Progress
822mA
F-VPP =V
PP2 (12 V)
Program in Progress
ICCE VCC Erase Cur rent Flash 1,3
16 45 mA F-VPP =V
PP1
Erase in Progress
815mA
F-VPP =V
PP2 (12 V)
Erase in Progress
ICCES VCC Er ase Suspend Cu rrent Fla sh 1,3,4 7 15 µA F-CE# = VCC, Erase Su sp en d
in Progress
ICCWS VCC Program Suspend Current
0.25µm
Flash 1,3,4 10 25
µA F-CE# = VCC, Progra m
Suspend in Progress
0.13µm
and
0.18µm
Flash
1,3,4 7 15
IPPD F-VPP Deep Power-Down Current Flash 1 0.2 5 µA F-RP# = GND ± 0.2 V
F-VPP ≤ VCC
IPPS F-VPP Standby Current Flash 1 0.2 5 µA F-VPP ≤ VCC
IPPR F-VPP Read Current Flash 12±15 µA F-VPP ≤ VCC
1,2 50 200 µA F-VPP ≥ VCC
IPPW F-VPP Program Current Flash 1,2
0.05 0.1 mA F-VPP =VPP1
Program in Progress
822mA
F-VPP =V
PP2 (12 V)
Program in Progress
IPPE F-VPP Erase Current Flash 1,2 0.05 0.1 ma F-VPP =V
PP1
Erase in Progress
IPPES F-VPP Erase Suspend Current Flash 1,2
0.2 5 µA F-VPP =V
PP1
Er ase Suspend in Progre ss
50 200 µA F-VPP =V
PP2 (12 V)
Er ase Suspend in Progre ss
IPPWS F-VPP Progra m Suspend Current Flash 1,2 0.2 5 µA F-VPP =V
PP1
Pr ogram Suspend in P rogress
50 200 µA F-VPP =V
PP2 (12 V)
Pr ogram Suspend in P rogress
Notes:
1. All currents are in RMS unless otherwise noted. Typical values at nominal F-VCC/S-VCC, TCASE =+25 °C.
2. Automatic Power Savings (APS) reduces ICCR to approximately standby levels in static operation (CMOS inp uts).
3. Sampled, not 100% tested.
4. ICCES an d ICCWS are specified with device de-selected. If device is read while in era s e suspend, current draw is su m of
ICCES and ICCR. If the device is read while in program suspend, current draw is the sum of ICCWS and ICCR.
Table 12. DC Characteristics (Sheet 2 of 2)
Symbol Parameter Device Note 2.7 V – 3.3 V Unit Test Conditions
Typ Max
C3 SCSP Flash Memory
26 Aug 2005 Intel® Advanced+ Boot Block Flash Memory (C3) SCSP Family Datasheet
30 Order Numbe r: 252636 , Revision: 004
Note: CL includes jig capacitance.
Table 13. DC Characteristics
Symbol Parameter Device Note 2.7 V – 3.3 V Units Test Conditions
Min Max
VIL Input Low Voltage Flash/
SRAM –0.2 0.6 V
VIH Input High Voltage Flash/
SRAM 2.3 VCC
+0.2 V
VOL Ou tput Lo w Volt a ge Flash/
SRAM –0.10 0.10 V F-VCC/S-VCC =V
CC Min
IOL =100 µA
VOH Output High Voltage Flash/
SRAM VCC –
0.1 V
F-VCC/S-VCC =V
CC Min
IOH = – 100 µA
VPPLK F-VPP Lock-Out Voltage Flash 1 1.0 V Complete Write Protection
VPP1 F-VPP during Prog ra m / Erase Flash 1 1.65 3.3 V
VPP2 Operations 1,2 11.4 12.6
VLKO VCC Prog/ Erase Lock Voltage Flash 1.5 V
VLKO2 VCCQ Prog/Erase Lock Voltage Flash 1.2 V
Notes:
1. Erase and Program are inhibited when F-Vpp < VPPLK and not guaranteed outside the valid F-Vpp ranges of VPP1 and
VPP2.
2. Applying F-Vpp = 11.4V–1 2.6V durin g program/era se can only be done for a maximum of 1000 cycl es on t he mai n
bloc ks an d 25 00 cycl es on the p ara met e r bloc ks. F-V pp may be co nn ec te d to 12 V for a tot a l of 80 ho ur s maximum . S ee
Se c tio n 4.2. 1 for details.
Figure 4. In put/Ou tpu t Reference Waveform
Note: AC test inputs are driven at VCCQ fo r a lo gi c “1” an d 0.0V for a l og ic “0 .” I np ut ti mi ng beg in s, an d outp ut
timin g ends, at V CCQ/2. Input rise and fall times (10%–90%) <10 ns. Worst case speed conditions are
when VCCQ = VCCQMin.
Figure 5. Test Con figuration
INPUT
OUTPUT
TEST POI NTS
V
CC
0.0
V
CC
2
V
CC
2
Device
Under Test Ou
t
CL
C3 SCSP Fla s h Me mor y
Datasheet Intel® Advan ce d+ Bo ot Block Flash Memory (C 3) SCSP Family 26 Aug 2005
Order Number: 252636, Revisio n: 004 31
Flash Test Configuration Compone nt Values Table
Tes t Config uratio n CL (pF)
2.7 V–3.3 V Standard Test 50
C3 SCSP Flash Memory
26 Aug 2005 Intel® Advanced+ Boot Block Flash Memory (C3) SCSP Family Datasheet
32 Order Numbe r: 252636 , Revision: 004
5.5 Flash AC Characteristics.
Table 14. Flash AC Characteristics—Rea d Ope rations
#Sym Parameter
Density 16-Mbit 32-Mbit
Uni
t
Product -70 -90 -110 -70 -90
Voltage
Range 2 .7 V - 3.3 V
Note Mi
nMa
xMi
nMa
xMi
nMa
xMin Ma
xMin Ma
x
R1 tAVAV Read Cycle Time 70 90 110 70 90 ns
R2 tAVQ
VAd dres s t o Out p ut De lay 7 0 90 110 70 9 0 ns
R3 tELQ
VF- C E# to O utput De lay 1 70 90 110 70 9 0 ns
R4 tGLQ
VF- O E# t o Out p ut Del ay 1 2 0 30 30 2 0 20 ns
R5 tPHQ
VF- R P# to O utput De lay 150 150 150 15 0 150 n s
R6 tELQ
XF- CE# to O utp ut in Low Z 2 0 0 0 0 0 n s
R7 tGLQ
XF-OE# to Output in Low Z 2 0 0 0 0 0 ns
R8 tEHQ
ZF-CE# to Output in High Z 2 20 25 25 20 20 ns
R9 tGHQ
ZF-OE# to Output in High Z 2 20 20 20 20 20 ns
R1
0tOH
Output Hold from Address
F-CE#, or F-OE# Change,
Whi chever Occu rs First 20 0 0 0 0 ns
Notes:
1. F-OE# may be delaye d up to tELQV–tGLQV after the falling edge of CE# without impact on tELQV
2. Sampled, but not 100% tested.
3. See Figure 6 “AC Waveform: Flash Read Operations” on page 33.
4. See Figure 4, “ Input/Ou tput R eference Waveform” on p age 28 for timing measuremen ts a nd maximum allow able inpu t
slew rate.
C3 SCSP Fla s h Me mor y
Datasheet Intel® Advan ce d+ Bo ot Block Flash Memory (C 3) SCSP Family 26 Aug 2005
Order Number: 252636, Revisio n: 004 33
5.6 Flash AC Characteri sti cs—Write Operations
Figure 6. AC Waveform: Flash Read Ope rations
Table 15. Flash AC Characteristics—Write Operations (Sheet 1 of 2)
#Sym Parameter
Density 16-Mbit 32-Mbit
Uni
t
Product -70 -90 -
110 -70 -90
Voltage
Range 2.7 V - 3.3 V
Note Mi
nMi
nMin Min Min
W1 tPHWL tPHEL F-RP# High Recovery to F-WE# (F-CE#) Going Low 150 150 150 150 150 ns
W2 tELWL tWLEL F-CE# (F-WE#) Setup to F-WE# (F-CE#) Going Low 0 0 0 0 0 ns
W3 tELEH tWLWH F-WE# (F-CE#) Pulse Width 1 45 60 70 45 60 ns
W4 tDVWH tDVEH Data Setup to F-WE# (F-CE#) Going High 2 40 50 60 40 40 ns
W5 tAVWH tAVEH Address Setup to F-WE# (F-CE#) Going High 2 50 60 70 50 60 ns
W6 tWHEH tEHWH F-CE# (F-WE#) Hold Time from F-WE# (F-CE#) High 0 0 0 0 0 ns
W7 tWHDX tEHDX Data Hold Time from F-WE# (F-CE#) High 2 0 0 0 0 0 ns
W8 tWHAX tEHAX Add ress Hold Time from F-WE# (F-CE#) High 2 0 0 0 0 0 ns
W9 tWHWL tEHEL F-WE# (F-CE#) Pulse Width High 1 25 30 30 25 30 ns
Address Stable
Device and
Address Selection
I
H
V
I
L
V
A
DDRESSES (A)
I
H
V
I
L
V
I
H
V
I
L
V
I
H
V
I
L
V
C
E# (E)
O
E# (G)
W
E# (W)
D
ATA (D/Q)
I
H
V
I
L
V
R
P#(P)
O
L
V
O
H
VHigh Z Valid Output
Data
Valid Standby
High Z
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
C3 SCSP Flash Memory
26 Aug 2005 Intel® Advanced+ Boot Block Flash Memory (C3) SCSP Family Datasheet
34 Order Numbe r: 252636 , Revision: 004
See Figure 4 “Input/Output Reference Waveform” on page 30 for timing measurements and
maximum allowable input slew r ate.
See Figure 7 “AC Waveform: Flash Program and Eras e Operatio ns” on page 35.
5.7 Flash Erase and Program Timings(1)
W1
0tVPWH tVPEH F-VPP Setup to F-WE# (F-CE#) Going High 3 200 200 200 200 200 ns
W11 tQVVL F-VPP Hold from Valid SRD 3 0 0 0 0 0 ns
Notes:
1. Write pulse width (tWP) is defined from F-CE# or F-WE# going low (whichever goes low last) to F-CE# or
F-W E# going h igh (whichever goes high first). Henc e, tWP=t
WLWH =t
ELEH =t
WLEH =t
ELWH. Similarly, write pulse width
high (tWPH) is defined from F-CE# or F-WE# going hi gh (whichever goes high first) to F-CE# or
F-W E# going l ow (whichever goes l ow firs t). Hence, tWPH =t
WHWL=t
EHEL =t
WHEL=t
EHWL.
2. Refer to Table 5 “Flash Memory Command D efinitions” on p age 19 for valid AIN or DIN.
3. Sampled, but not 100% tested.
Table 15. Flash AC Characteristics—Write Opera tions (Sh eet 2 of 2)
#Sym Parameter
Density 16-Mbit 32-Mbit
Uni
t
Product -70 -90 -
110 -70 -90
Voltage
Range 2.7 V - 3.3 V
Note Mi
nMi
nMin Min Min
Table 16. Flash Erase and Progr am Timings
Symbol Parameter F-VPP 1.65 V– 3.3 V 11.4 V– 12.6 V Unit
Note Typ(1) Max Typ(1) Max
tBWPB 4-KW Parame ter Bl ock P rogram Time (Word) 2, 3 0.10 0.30 0.03 0.12 s
tBWMB 32-KW Main Block Progra m Time (Word) 2, 3 0.8 2.4 0.24 1 s
tWHQV1 / tEHQV1 0.25 µm Word Program Time 2, 3 22 200 8 185 µs
0.13 µm and 0.18 µm Word P rogram Time 2, 3 12 200 8 185
tWHQV2 / tEHQV2 4-KW Parameter Block Erase Time (Word) 2, 3 0.5 4 0. 4 4 s
tWHQV3 / tEHQV3 32-KW Main Block Erase Time (Word) 2, 3 1 5 0.6 5 s
tWHRH1 / tEHRH1 Pr ogram Suspend Latency 3 5 10 5 10 µs
tWHRH2 / tEHRH2 Er ase Suspend Lat ency 3 5 20 5 20 µs
Notes:
1. Typ ical values measured at TCASE = +25 °C and nominal voltages.
2. Excludes external s ystem-level ov erhead.
3. Sampled, but not 100% tested.
C3 SCSP Fla s h Me mor y
Datasheet Intel® Advan ce d+ Bo ot Block Flash Memory (C 3) SCSP Family 26 Aug 2005
Order Number: 252636, Revisio n: 004 35
Notes:
1. F-CE# must be toggled l ow whe n reading Status Register Data. F-WE# must be inactive (high) when
reading Status Register Data.
2. F-VCC Power-Up and Standby.
3. Write Program or Erase Setup Command.
4. Write Valid Address and Data (for Program) or Erase Confirm Command.
5. Automated Program or Erase Delay.
6. Read Status Regi ste r Data (SRD): reflects compl eted program/erase operation.
7. Write Read Array Command.
Figure 7. AC Wa veform: Fl ash Program an d Erase Operations
ADDRESSES [A]
C
E#(WE#) [E(W)]
OE# [G]
W
E#(CE#) [W(E)]
D ATA [D/Q]
RP# [P]
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IL
V
IL
V
IN
D
IN
AIN
A
Valid
SRD
IN
D
IH
V
High Z
IH
V
IL
V
V [V]
PP
PPH
V
PPLK
VPPH
V1
2
WP# IL
V
IH
V
IN
D
AB C D E F
W8
W6
W9
W3
W4
W7
W1
W5
W2
W10 W11
(Note 1)
(Note 1)
ADDRESSES [A]
C
E#(WE#) [E(W)]
OE# [G]
W
E#(CE#) [W(E)]
D ATA [D/Q]
RP# [P]
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IL
V
IL
V
IN
D
IN
AIN
A
Valid
SRD
IN
D
IH
V
High Z
IH
V
IL
V
V [V]
PP
PPH
V
PPLK
VPPH
V1
2
WP# IL
V
IH
V
IN
D
AB C D E F
W8
W6
W9
W3
W4
W7
W1
W5
W2
W10 W11
(Note 1)
(Note 1)
C3 SCSP Flash Memory
26 Aug 2005 Intel® Advanced+ Boot Block Flash Memory (C3) SCSP Family Datasheet
36 Order Numbe r: 252636 , Revision: 004
5.8 Flash Reset Operations
Figure 8. AC Waveform: Reset Operation
Table 17. Reset Specifications(1)
Symbol Parameter Note F-VCC 2.7 V – 3.3 V Unit
Min Max
tPLPH F-RP# Low to Reset during Read (If F-RP# is tied
to VCC, this specification is not applicable) 2,4 100 ns
tPLRH1 F-RP# Low to Reset during Block Erase 3,4 22 µs
tPLRH2 F-RP# Low to Re set during Program 3,4 12 µs
Notes:
1. See Section 2.1.4, “Flash Reset” on page 13 for a f ul l des c rip t io n of the se co nd it i on s.
2. If tPLPH is < 100 ns the devi ce may still r es et but t hi s is not gu ar a nte ed.
3. If F-RP# is asserted while a block erase or word program operation is not executing, the reset will
complete within 100 ns.
4. Sampled, but not 100% teste d.
IH
V
IL
V
RP# (P )
PLPH
t
IH
V
IL
V
RP# (P)
PLPH
t
(A) Reset during Read Mode
Abort
Complete PHQV
tPHWL
tPHEL
t
PHQV
tPHWL
tPHEL
t
(B) Reset during Program or Block Erase, <
PLPH
tPLR
H
t
PLRH
t
IH
V
IL
V
RP # (P )
PLPH
t
Abort
Complete PHQV
tPHWL
tPHEL
t
PLRH
t
Deep
Power-
Down
(C) Reset Program or Block Erase, >
PLPH
tPLRH
t
C3 SCSP Fla s h Me mor y
Datasheet Intel® Advance d+ Bo ot Block Flash Memory (C 3) SCSP Family 26 Aug 2005
Order Number: 252636, Revisio n: 004 37
5.9 SRAM AC Characteristics—Read Operations
Table 18. SRAM AC Characteristics—Read Operations(1)
#Sym Parameter
Density 2/4/8-Mbit
UnitVoltage Range 2.7 V– 3.3 V
Note Min Max
R1 tRC Read Cycle Time 70 – ns
R2 tAA Address to Output Delay – 70 ns
R3 tCO1, tCO2 S-CS1#, S-CS2 to Output Delay – 70 ns
R4 tOE S - OE# to O utput Delay – 35 n s
R5 tBA S-UB#, LB# to Output Delay – 70 ns
R6 tLZ1, tLZ2 S-CS1#, S-CS2 to Output in Low Z 2,3 5 – ns
R7 tOLZ S-OE# to Output in Low Z 3 0 – ns
R8 tHZ1, tHZ2 S-CS1#, S-CS2 to Output in High Z 2,3,4 0 25 ns
R9 tOHZ S-OE# to Output in High Z 3,4 0 25 ns
R10 tOH Output Hold from Address, S-CS1#,
S-CS2, or S-OE# Change, Whichever Occurs
First 0–ns
R11 tBLZ S-UB #, S-LB# t o Output in Low Z 3 0 – ns
R12 tBHZ S-UB#, S-LB# to Output in High Z 3 0 25 ns
Note:
1. See Figure 9 “AC Waveform: SRAM Read Operations” on page 38.
2. At any given temperature and voltage cond ition, tHZ (Max) is less th an and tLZ (Max) both for a given
device and from device to device interconnection.
3. Sam p le d, bu t not 10 0% te s ted .
4. Timings of tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit
c ondi tions and are not refer enced to output voltage levels.
C3 SCSP Flash Memory
26 Aug 2005 Intel® Advanced+ Boot Block Flash Memory (C3) SCSP Family Datasheet
38 Order Numbe r: 252636 , Revision: 004
5.10 SRAM AC Characteristics—Write Operations
Figure 9. AC Wave form : SRAM Read Operations
Table 19. SRA M AC Chara cteris tics—Write Op eration s(1,2)
#Sym Parameter
Density 2/4/8-Mbit
UnitVolt 2.7 V – 3.3 V
Note Min Max
W1 tWC Write Cycle Time 70 – ns
W2 tAS Address Setup to S-WE# (S-CS1#) and S-UB#,
S-LB# Going Low 30–ns
W3 tWP S-W E# (S-CS 1#) Pulse Width 4 55 – ns
W4 tDW Data to Write Time Overlap 3 0 – ns
W5 tAW Address Setup to S-WE# (S-CS1#) Going High 60 – ns
W6 tCW S-CE# (S-WE#) Setup to S-WE# (S-CS1#) Going
High 60 – ns
W7 tDH Data Hold Time from S-WE# (S-CS1#) High 0 – ns
High Z
Valid Output
Address St able
Data Valid
Device
Address Selection
Standby
ADDRESSES (A)
V
IH
V
IL
V
IH
V
IL
CS
1
# (E
1
)
V
IH
V
IL
V
OH
V
OL
V
IH
OE# (G)
WE# (W)
DATA (D/Q)
UB#, LB#
High Z
V
IH
V
IL
R1
R2
R4
R3
R6
R7
R8
R9
R10
CS
2
(E
2
)
V
IH
V
IL
V
IH
R5
R11 R12
C3 SCSP Fla s h Me mor y
Datasheet Intel® Advance d+ Bo ot Block Flash Memory (C 3) SCSP Family 26 Aug 2005
Order Number: 252636, Revisio n: 004 39
W8 tWR Write Recovery 5 0 – ns
W9 tBW S-UB#, S-LB# Setu p to S-WE # (S-C S1# ) Goi ng High 60 – ns
Notes:
1. See Figure 10 “AC Waveform: SRAM Write Operations” on page 39.
2. A write occurs during the overlap (tWP) of low S-CS1# and low S-WE#. A write begins when S-CS1#
goes low an d S-WE# goes low with asserting S-UB# or S-LB# for single byte operation or
simultaneously asserting
S- UB # an d S- LB# for d ou bl e by te oper at ion . A wri te en ds at the ea r li es t tr an siti on whe n S -CS1# goe s
high and S-WE# goes high. The tWP is measured from the begi nnin g of write to the end of wr ite .
3. tAS is measured from the address valid to the beginning of write.
4. tWP is measured from S-CS1# going low to end of write.
5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as S-
CS1# or S-W E# going h igh.
Figure 10. AC Waveform: S RAM Write Operation s
Table 19. SRAM AC Characteristics—Write Operations(1,2)
#Sym Parameter
Density 2/4/8-Mbit
UnitVolt 2.7 V – 3.3 V
Note Min Max
High Z
Data In
Address St able
Device
Address Selection
Standby
ADDRESSES (A)
V
IH
V
IL
V
IH
V
IL
CS
1
# (E
1
)
V
IH
V
IL
V
OH
V
OL
V
IH
OE# (G)
WE# (W)
DATA (D/Q)
UB#, LB#
High Z
V
IH
V
IL
W1
W8
CS
2
(E
2
)
V
IH
V
IL
V
IH
W9
W6
W5
W2
W3
W4 W7
C3 SCSP Flash Memory
26 Aug 2005 Intel® Advanced+ Boot Block Flash Memory (C3) SCSP Family Datasheet
40 Order Numbe r: 252636 , Revision: 004
5.11 SRAM Data Retention Characteristics—Extended
Temperature
Table 20. SRA M Data R etention Characteri sti cs(1)— Extend ed Temp eratu re
Sym Parameter Note Min Typ Max Unit Test Conditions
VDR S-VCC for Data Retention
2
1.5–3.3VCS
1# ≥VCC – 0.2 V
IDR
Deep Retention Current -
8-Mbit ––6µA
S-VCC = 1.5 V
CS1# ≥VCC – 0.2 V
Deep Retention Current -
4-Mbit ––5µA
Deep Retention Current -
2-Mbit ––4µA
tSDR Data Retention Set-up Time 0 – – ns See Data Retention Waveform
tRDR Recovery Time tRC ––ns
Notes:
1. Typical values at nominal S-VCC, TCASE =+25 °C.
2. S-CS1# ≥ VCC – 0.2 V, S-CS2 ≥ VCC – 0.2 V ( S-CS1# controlled) or S- CS2 ≤ 0.2 V (S-CS2 controlled).
Figure 11. SRAM Data R etention Waveform
V
CC
3.0/2.7V
CS
1
# (E
1
)
2.2V
V
DR
CS
2
(E
2
)
GND
V
CC
3.0/2.7V
0.4V
V
DR
GND
CS
1
# Cont r oll ed
CS
2
Cont r oll ed
Dat a Ret ention M odet
SDR
t
RDR
Dat a Ret ention M ode
t
SDR
t
RDR
C3 SCSP Fla s h Me mor y
Datasheet Intel® Advance d+ Bo ot Block Flash Memory (C 3) SCSP Family 26 Aug 2005
Order Number: 252636, Revisio n: 004 41
6.0 Migration Guide Information
Typically, it is important to discuss footprint migration compatibility between a new product and
exis ting products. In this spec ific case, the SCSP allows the sys tem designer to remove two
sep ara te memory foot prints for individual flash and SRAM and replace them with a single
footprint, thus resulting in an overall reduction in board space required. This implies that a new
printed circuit board would be used to take advantage of this feat ure.
Since t h e f l ash in SCSP shares th e same fe atur es as the C3 features, conversi o n s from t h e C3 are
des cribed in AP-658 Designing for Upgrade to the Advanc ed+ Boo t Bl ock Flash Memory, order
number 292216.
Please contact your local Intel representation for detailed information about specific Flash +
SR AM system mi gration s .
7.0 System Design Considerations
This section contains in form ation that would have been contained in a product design guide in
earlier generations. In an effort to s implify the amount of documentation, relevant system design
cons iderations have been combined into this document.
7.1 Background
The C3 SCSP combines the features of the C3 flash memory architecture with a low-power SRAM
to achieve an overall reduction in system board space. This enables applications to integrate
security with si mple s oftware and hardware configurations, while al s o combining the system
SRAM and flash into one common footprint. This s ection dis cusses how to take full advantage of
the C3 SCSP.
7.1. 1 Flash + SRAM Foo tp rint Integ ratio n
The SCSP memory solution can be used to replace a subset of the memory subsystem within a
design. Where a previous design may have used two separate footprints for SRAM and Flash, you
can now re place with the indus try -stan dard I-bal lout of the SCSP devic e. This allows f or an overall
reduction in board space, which allows the design to integrate both the flash and the SRAM into
one component.
C3 SCSP Flash Memory
26 Aug 2005 Intel® Advanced+ Boot Block Flash Memory (C3) SCSP Family Datasheet
42 Order Numbe r: 252636 , Revision: 004
7.1.2 C3 Flash Memory Features
C3 adds the following new features to Intel Advanced Boot Block architecture:
•I nstant, individual block locking provides s oftware/hardware controlled, independe nt locking/
unlockin g of any block with zero latency to protect code and data.
•A 128- bit Protec tion Regis ter enables system sec urity implementations.
•I mpro ved 12 V production programmi ng si mp lifies the system configuration required to
imp lement 12 V fas t programming.
•C ommon F la sh Int er fac e (C FI) provi d es co mpo nent in form at io n on t he chi p to al low sof twa re-
independent device upgrades.
For more inform ation on spe cific advan tages of the C3, ple ase see AP-658 Designing with the
Adv ance d+ Boot Block Flash Memory Archite ctur e.
7.2 Flash Control Considerations
The flash device is protected agai nst acciden tal block erasure or programming during power
transiti ons. Power supp ly s equencing is not required, si nce the device is indifferent as to which
power supply, F-VPP or F-VCC, powers-up first. Example flash power suppl y configurati ons are
sh own in Figure 12 “Example Power Supply Configurations” on page 43.
7.2.1 F-RP# Connected to System Reset
The use of F-RP# during syst em reset is import ant with au tomat ed program/e rase devi ces sinc e the
system ex p ects to read from the flash memory wh en it comes out of reset. If a CPU re set occurs
without a flash me mory reset, proper CPU initialization will not occur because the flash memory
may be providing status information instead of array data. Intel recommends connecting F-RP# to
the system CPU RESET# signal to allow proper CP U/flash initialization following system reset.
System designers must guard aga inst spurious writes when F-V CC voltages are above VLKO. Since
both F - WE# and F-CE# mus t be low for a command write, driving either signal to VIH will inhibit
writes to the device. The CUI architecture provides additional protection since alteration of
mem ory contents can only occur after successful completion of the two-step command sequences.
The device is also disabled until F-RP# is brought to VIH, rega rdless of the state of its contro l
inputs.
By holding the device in reset (F -RP# connected to system PowerGood) during power-up/down,
invalid bus conditions during power-up can be masked, providin g yet another level of memory
protection.
7.2.2 F-VCC, F-VPP and F-R P# Transit ion
The C U I la t ch es comm a nds as iss u ed by system software and is not altered by F-VPP or F-CE#
transitions or WSM action s. Its default st ate upon power -up, after exit from reset mode or after
F-VCC transitions above VLKO (Lockou t voltage), is read array mode.
After any program or block er ase operation is comp lete (even after F-VPP transitions down to
VPPLK), the CUI must be reset to read array mode via the Read Array command if access to the
f lash m em ory array is desi red.
C3 SCSP Fla s h Me mor y
Datasheet Intel® Advance d+ Bo ot Block Flash Memory (C 3) SCSP Family 26 Aug 2005
Order Number: 252636, Revisio n: 004 43
Note: 1. A resistor can be used if the F-VCC supply can sink adequate current based on resistor value.
7.3 Noise Reductio n
SCSP memory’s power swit ching characteristics require careful device dec oupling. Sy st em
des igners should co ns ider three supply current issue s for bot h the flash and SRAM:
•S tandby current levels (ICCS)
•Read curre nt le vel s (ICCR)
•Trans ient peaks produced by fall ing and rising edge s of F-CE#, S-CS1#, and S- CS 2.
Trans ient current magnitudes depend on the device o utputs’ capacitive and in ductive loading. Two-
line control and proper decoupling capacitor selection will suppress these transient voltage peaks .
Each device should have a capa citors between individual power (F-VCC, F-VCC Q, F-VPP,
S-VCC) and ground (GND) signals. High-frequency, inherently low-inductance capacitors should
be pl a ced as cl o se as po s si bl e to th e pack ag e lead s.
Noise issues within a system can cause devices to operate erratically if it is not adequately filtered.
In order to avoid any noise interaction issues within a system, it is recommended that the de sign
contain the appr opriate number of de coupling cap acitors in the syste m. Noise issue s can also be
reduced if leads to the de vice are kept very short, in order to reduce inductance.
Decoupling cap acitors between VCC and VSS reduce volt age spikes by supplying the extra curre nt
neede d during switc hing. Placing these capacito rs as close to the de vice as possible reduces line
induc tan ce. The capacit ors s hould be low inducta nc e capaci tor s; surfa ce mount ca pacit ors typ icall y
exhibit lo wer inductance.
It is hi ghly recommended tha t s ystems use a 0.1 µf capacitor for ea ch of the D9, D10, A10 and E4
grid ballout locations (see Figure 1 “66-Ball SCSP Packa ge Ballout” on page 8 for ballout). These
capa citors are nec es s ary to avoid undesired conditions crea ted by excess nois e. Smaller ca pacitors
can be used to dec ouple higher fre quencies.
Figure 12. E xam ple P owe r Supply Con fig uration s
V
CC
V
PP
12 V Fast Program m ing
Absolu te Write Protection With V
PP
≤
V
PPLK
System Supply
12 V Supply
10
≤
K
Ω
V
CC
V
PP
System Supply
12 V Supply
Low Volta ge a nd 12 V Fast Program m ing
V
CC
V
PP
System Supply
Prot#
(Lo g ic Signal)
V
CC
V
PP
System Supply
Low-Voltage Programming
Low-Voltage Programming
Absolute Write Protection via Logic Signal
(Note 1)
C3 SCSP Flash Memory
26 Aug 2005 Intel® Advanced+ Boot Block Flash Memory (C3) SCSP Family Datasheet
44 Order Numbe r: 252636 , Revision: 004
Notes:
1. Substrate connections refer to ballout locations shown in Figure 1 “66-Ball SCSP Pack age Ballo ut” on
page 8.
2. 0.1µf capacitors should be used with D9, D10, A10and E4.
3. Some SRAM devices do not have a S-VSSQ; in this case, this pad is a S-VSS.
4. Some SR AM devices do not have a S-VSSQ ; in this case, this pad is a VCC.
7.4 Simultaneous Operation
The term simultaneous ope r ation in used to describe the abilit y to re ad or writ e to the SRAM while
als o progra mmin g or era sing f lash. In additi on, F-CE#, S-CS 1# and S- CS2 should not be enable d a t
the same time. (See Table 2 “Intel® Advance d+ Boot Blo ck SCSP Ba ll Descript ion s” on page 9 for
a summary of re commended operat ing m odes .) Simulta neous operation of the can be summarized
by the fo llo win g:
•SRA M r ead/write are dur i ng a Flash P rogram or Erase O p eration are allowed.
•Simult aneous Bus Op erations b etween the Flash and SRAM are not allowed (because of bus
contention).
Figure 13. Typical Flash + S RAM Sub strate Power and Gro und Con nec tions
S-V
SSQ
D10
SRAM DIE
FLASH DIE
SUBSTRATE
XX
S-X
F-X
Substrate connection to package ball
SR AM die bond pad connection
Flash di e bond pad connection
S-V
CCQ
S-V
CC
S-V
SS
F-V
PP
F-V
SSQ
F-V
CC
F-V
CCQ
F-V
SS
H8
A9
D9
E4
D3
A10
C3 SCSP Fla s h Me mor y
Datasheet Intel® Advance d+ Bo ot Block Flash Memory (C 3) SCSP Family 26 Aug 2005
Order Number: 252636, Revisio n: 004 45
7.4.1 SRAM Operation during Flash “Busy”
This functionality provides the ability to use both the flash and the SRAM “at the s ame time”
within a sys tem, s imilar t o the ope ration of two de vice s with se parate footprin ts . This o perati on can
be achieved by following the appropriate timing constraints within a system.
7.4.2 Simultaneous Bus Operations
Operat ion s that requir e bot h the SRAM and Flash to be in active mode are disal lowed. An examp le
of thes e cases would incl ude simultan eous reads on both the fla s h and SRAM, which would result
in contention for th e data bus. Final ly, a read of one devi ce while attempting to write to the other
(similar to the conditions of direct memory access (DMA) opera tion) are also not within the
recomm ended operating conditions. Basi cally, only one memory can drive the out puts out the
device at one given point in tim e.
7.5 Printed Circuit Board Notes
The Int el SCSP will sa ve significant space on your PCB by combining two chips into one BGA
styl e package . Int el SCSP has a 0.8 mm pit ch th at can be route d on your Printe d Circuit Boar d with
conve nti onal de sign rules . T race widths of 0.127 m m (0.005 i nches ) ar e typi cal. Unused balls i n the
center of the packag e are not populated to further increase the routi ng options. S tandard sur f ac e
mount process and equipment can be used for the Intel SCSP.
Note: Top View
7.6 System Design Notes Summary
The C3 SCSP allows higher levels of memory component integration. Different power supply
co nfig urat ion s ca n be used wi thi n t he s yste m to ach ie ve d ifferent ob j ectiv es . At le ast thr ee dif fe ren t
0.1 µf capacitors should be used to dec ouple the devi ces within a syste m. SRAM reads or writes
dur ing a fla sh prog ram or er ase are support ed oper ations . S tand ard print ed circ ui t board t echnol ogy
can be used.
Figure 14. Standard PCB Design Rules Can be Used with SC SP Device
Land Pad Diameter: 0.35 mm (0.0138 in)
Solder Mask Opening: 0.50 mm (0.0198 in)
Trace Width: 0.127 mm (0.005 in)
Trace Spaces: 0.160 mm (0.00625 in)
Via Capture Pad: 0.51 mm (0.020 in)
Via Dr ill Siz e: 0.25 m m ( 0.0 10 in)
C3 SCSP Flash Memory
26 Aug 2005 Intel® Advanced+ Boot Block Flash Memory (C3) SCSP Family Datasheet
46 Order Numbe r: 252636 , Revision: 004
Appendix A Prog ram/Erase Flowcharts
Figu re 15 . Aut om ate d Word P r og ra m ming Flo w chart
Start
Write 40H
Program A ddress/Data
Read S tatus Register
SR.7 = 1?
Full Status
Check if Desired
Program Complete
Read S tatus Register
Data (S ee Above)
V
PP
Range Error
Programming Error
Attempted Program to
Locked Block - Aborted
Program Successful
SR.3 =
SR.4 =
SR.1 =
FULL ST ATUS CHECK PROCEDURE
Bus Operation
Write
Write
Standby
Repeat for subsequent programming operations.
SR Full Status Check can be done after each program or after a sequence of
program operations.
Write FFH after the last program operation to reset device to read array mode.
Bus Operation
Standby
Standby
SR.3 MUST be cleared, if set during a program attempt, before further
attempts are allowed by the Write State Machine.
SR.1, SR.3 and SR.4 are only cleared by the Clear Staus Register Command,
in cases where multiple bytes are programmed before full status is checked.
If an error is detected, clear the status register before attempting retry or other
error rec ove ry.
No
Yes
1
0
1
0
1
0
Command
Program Setup
Program
Comments
Data = 40H
Data = Data to Program
Addr = Location to Program
Check S R.7
1 = WSM Ready
0 = WSM Busy
Command Comments
Check S R.3
1 = V
PP
Low Detect
Check S R.1
1 = Attempted Program to
Locked Block - Program
Aborted
Read Status Register Data Toggle
CE# or OE# to Update Status
Register Data
Standby Check S R.4
1 = V
PP
Program E rror
C3 SCSP Fla s h Me mor y
Datasheet Intel® Advance d+ Bo ot Block Flash Memory (C 3) SCSP Family 26 Aug 2005
Order Number: 252636, Revisio n: 004 47
0645_13
Figure 16. P rog ram S usp end /Resume Flow char t
Start
Wr ite B0H
Read Status Regi ster
No
Comments
Data = B0H
Addr = X
Data = F FH
Addr = X
SR.7 =
SR.2 =
1
Write FF H
Read Array Data
Program Completed
Done
Reading
Yes
Wr it e FF HWrite D0H
Program Resum ed Read Array Data
0
1
Read array data from block
other than the one being
programmed.
Status Register Data Toggle
CE# or OE# to Update Status
Register Data
Addr = X
Check SR.7
1 = WSM Ready
0 = WSM Busy
Check SR.2
1 = Program Suspended
0 = Program Completed
Data = D0H
Addr = X
Bus
Operation Command
0
Wr i t e 70 H
Status Register Data Toggle
CE# or OE# to Update Status
Register Data
Addr = X
Write
Write
Write
Read
Read
Standby
Standby
Write
Data = 70H
Addr = X
Command
Program
Suspend
Read St atus
Read Array
Program
Resume
C3 SCSP Flash Memory
26 Aug 2005 Intel® Advanced+ Boot Block Flash Memory (C3) SCSP Family Datasheet
48 Order Numbe r: 252636 , Revision: 004
0645_14
Figure 17. Automated Block Erase Flow chart
Start
Write 20H
Write D0H and
Block Address
Read S tatus Register
SR.7 =
Full Status
Check if Desired
Block Erase Complete
FULL ST ATUS CHECK PROCEDURE
Bus Operation
Write
Write
Standby
Repeat for subsequent block erasures.
Full Status Check can be done after each block erase or after a sequence of
block erasures.
Write FFH after the last write operation to reset device to read array mode.
Bus Operation
Standby
SR. 1 and 3 MUST be cleared, if set during an erase attempt, before further
attempts are allowed by the Write State Machine.
SR.1, 3, 4, 5 are only cleared by the Clear Staus Register Command, in cases
where multiple bytes are erased before full status is checked.
If an error is detected, clear the status register before attempting retry or other
error rec ove ry.
No Yes
Suspen d Erase
Suspend
Erase Loop
1
0
Standby
Command
Erase Setup
Erase Confirm
Comments
Data = 20H
Addr = Within Block to Be
Erased
Data = D0H
Addr = Within Block to Be
Erased
Check S R.7
1 = WSM Ready
0 = WSM Busy
Command Comments
Check S R.3
1 = V
PP
Low Detect
Check SR.4,5
Both 1 = Command Sequence
Error
Read S tatus Register
Data (See Above)
V
PP
Range Error
Command Sequence
Error
Block Erase
Successful
SR.3 =
SR.4,5 =
1
0
1
0
Block Erase ErrorSR.5 = 1
0
Attempted Erase of
Locked Block - Aborted
SR.1 = 1
0
Read Status Register Data Toggle
CE# or OE# to Update Status
Register Data
Standby Check S R.5
1 = Block Erase Error
Standby Check S R.1
1 = Attempted Erase of
Locked Block - Erase Aborted
C3 SCSP Fla s h Me mor y
Datasheet Intel® Advance d+ Bo ot Block Flash Memory (C 3) SCSP Family 26 Aug 2005
Order Number: 252636, Revisio n: 004 49
0645_15
Figure 18. Erase Susp end /Re sume Flow cha rt
Start
Write B0H
Read Status Register
No
Comments
Data = B0H
Addr = X
Data = F FH
Addr = X
SR.7 =
SR.6 =
1
Write FFH
Read Arra y Data
Erase Completed
Done
Reading
Yes
Write FFHWrite D0H
Erase Resumed Read Array Data
0
1
Read array data from block
other than the one being
erased.
Status Register Data Toggle
CE# or O E# to Update Status
Register Data
Addr = X
Ch eck SR.7
1 = WSM Ready
0 = WSM Busy
Ch eck SR.6
1 = Erase Suspended
0 = Erase Completed
Data = D0H
Addr = X
Bus
Operation
Write
Standby
Write
Read
Standby
Read
Command
0
Write 70H
Status Register Data Toggle
CE# or O E# to Update Status
Register Data
Addr = X
Write
Write
Data = 70H
Addr = X
Command
Erase Suspend
Read Status
Read Array
Erase Resume
C3 SCSP Flash Memory
26 Aug 2005 Intel® Advanced+ Boot Block Flash Memory (C3) SCSP Family Datasheet
50 Order Numbe r: 252636 , Revision: 004
0645_16
Figure 19. Lockin g Op erati ons Flowchart
Start
Wr ite 60 H
(C onfi guration Setup)
No
Comments
Data = 60H
Addr = X
Wr ite 90 H
(Re ad Configuration)
Read Block Lo ck Sta tus
Locking
Change
Confirmed?
Locking Change
Complete
Bus
Operation
Write
Command
Write
01H, D0H, or 2FH
Write
Write
Data= 01H (Lock Block)
D0H (Unlock Block)
2FH (Lockdown Block)
Addr=Within block to lock
Command
Config. Setup
Lock, Unlock,
or Lockdown
Data = 90H
Addr = X
Write
(Optional) Read
Configuration
Bloc k Lock Status Data
Addr = Second addr of block
Read
(Optional) Block Lock
Status
Confirm Locking Change on
DQ
1
, D Q
0
. (See Block Locking
State T able for valid
combinations.)
Standby
(Optional)
Optional
Write FFh
(Rea d A rr a y )
C3 SCSP Fla s h Me mor y
Datasheet Intel® Advance d+ Bo ot Block Flash Memory (C 3) SCSP Family 26 Aug 2005
Order Number: 252636, Revisio n: 004 51
0645_17
Fig ure 20 . Prot ection R egi s t er Pr ogra m m i ng Fl owchart
Start
Write C0H
(Protection Reg.
Program S etup)
Write Protect. Register
Address/Data
Read S tatus Register
SR.7 = 1?
Full Status
Check if Desired
Program Complete
Read S tatus Register
Data (S ee Above)
V
PP
Range Error
Protection Register
Programming Error
Attempted Program to
Locked Register -
Aborted
Program Successful
SR.3, SR.4 =
SR.1, SR.4 =
SR.1, SR.4 =
FULL ST ATUS CHECK PROCEDURE
Bus Operation
Write
Write
Standby
Protection Program operations can only be addressed within the protection
register a ddre s s space . Addres s es outside the def ined space will retu rn an
error.
Repeat for subsequent programming operations.
SR Full Status Check can be done after each program or after a sequence of
program operations.
Write FFH after the last program operation to reset device to read array mode.
Bus Operation
Standby
Standby
SR.3 MUST be cleared, if set during a program attempt, before further
attempts are allowed by the Write State Machine.
SR.1, SR.3 and SR.4 are only cleared by the Clear Staus Register Command,
in cases of multiple protection register program operations before full status is
checked.
If an error is detected, clear the status register before attempting retry or other
error rec ove ry.
No
Yes
1, 1
0,1
1,1
Command
Protection Program
Setup
Protection Program
Comments
Data = C0H
Data = Data to Program
Addr = Location to Program
Check S R.7
1 = WSM Ready
0 = WSM Busy
Command Comments
SR.1 SR.3 SR.4
0 1 1 V
PP
Low
0 0 1 Prot. Reg.
Prog. Error
1 0 1 Register
Locked:
Aborted
Read Status Register Data Toggle
CE# or OE# to Update Status
Register Data
Standby
C3 SCSP Flash Memory
26 Aug 2005 Intel® Advanced+ Boot Block Flash Memory (C3) SCSP Family Datasheet
52 Order Numbe r: 252636 , Revision: 004
Appendix B CFI Query Structure
This appendix define s the data structure or “d ata base” return ed by the Common Flash Interface
( CFI) Query command. System software should parse this st ructure to gain critical information
suc h as block size, de nsity, x8/x 16, and electrical specificat ions. Once this informa tion has been
obtained, the software will know which com m and s ets to use to enable f lash writes, block erases,
and otherwise cont rol the flash component. The Query is part of an overall specification for
multiple command set and control interface descriptions called Common Flash Interface, or CFI.
B.1 Query Structure Output
The Query “database” allows system software to gain information for controlling the flash
com ponent. This sectio n desc ribes the dev ice’s CFI-c ompli ant int erf ace th at allo ws the hos t sys tem
t o acce ss Quer y d ata.
Query data are always pre se nted on the lowest -order data out puts (DQ0-7) onl y. The numerical
offset value is the address relative to the maximum bus width supported by the device. On this
f amily of devices, the Que ry table device s tarting address is a 10h, which is a word address for x16
devices.
For a word-wide (x16) device, the first two bytes of the Query structure, “Q” and “R” in ASCII,
appe ar on the l ow byte at word addr esses 10h a nd 1 1 h. This CFI-c ompli ant device outp uts 00h data
on upper bytes. Thus, the device outputs ASCII “Q” in the low byte (DQ0-7) and 00h in the high
byte ( D Q 8-15).
At Query addresses co ntaining two or mor e bytes of informat ion, the least significant data byte is
pr es ented a t the lower address, and the most signi ficant da ta byte is presented at the higher add r ess.
In all of the following tables, addresses and data are represented in hexadecimal notation, so the
“h” suffix has bee n dropped. In addition, sinc e the upper byte of word-wide devices is always
“00h,” the leading “00” has be en dropped from the tabl e notation an d only the lower byte value is
shown. Any x16 device outputs can be assumed to have 00h on the upper byte in this mode.
Table 21. Su mm ary of Qu ery Struc ture Ou tput as a Function of Devi ce and Mod e
Device Hex Offset Code ASCII Value
Devi ce Addr ess
10: 51 “Q”
11: 52 “R”
12: 59 “Y”
C3 SCSP Fla s h Me mor y
Datasheet Intel® Advance d+ Bo ot Block Flash Memory (C 3) SCSP Family 26 Aug 2005
Order Number: 252636, Revisio n: 004 53
B.2 Quer y Struc tu re Over vi ew
The Query com mand ca uses the flash co mponent to display the Common Flash Interface (CFI)
Query structure or “database.” The structure sub-sections and address locations are su mmarized
below.
Ta ble 22. Exam ple of Qu ery Structure Outp ut of x16 and x8 Devices
Word Addressing Byte Addressing
Offset Hex Code Value Offset Hex Code Value
A15–A0D15–D0A7–A0D7–D0
0010h 0051 “Q” 10h 51 “Q”
0011h 0052 “R” 11h 52 “R”
0012h 0059 “Y” 12h 59 “Y”
0013h P_IDLO PrVendor 13h P_IDLO PrVendor
0014h P_I D HI I D # 14h P_ I DLO ID #
0015h P L O Pr Ve nd or 15h P_I DH I ID #
0016h PHI TblAdr 16h ... ...
0017h A_IDLO AltVendor 17h
0018h A_I D HI I D # 18h
... ... ... ...
Table 23. Query Structure
Offset Sub-Section Na me Description Note s
00h Man ufacturer Code 1
01h Device Code 1
(BA+2)h Block Status Register Block-specific information 1,2
04-0Fh Reserved Reserved for vendor-specific information 1
10h CFI Qu ery Identification String Command set ID and vendor data of fset 1
1Bh System Interface Inf ormation Device timing & voltage in formation 1
27h Devi c e Geometr y Definition Flash de vice layou t 1
PPrimary Intel-Specific Extended
Query Ta ble Vendor-define d additional information spec ifi c to the
Pri m ary Vendor Algori thm 1,3
Notes:
1. Refer to the Query Structure Output section and offset 28h for the detailed definition of offset address
as a function of device bus width and mode.
2. BA = The beginning loc ation of a Block Address (e.g., 0800 0h is the beginning l ocation of block 1
when the block size is 32 Kword).
3. Offset 15 defines “P” which points to the Primary Intel-specific Extended Query Table.
C3 SCSP Flash Memory
26 Aug 2005 Intel® Advanced+ Boot Block Flash Memory (C3) SCSP Family Datasheet
54 Order Numbe r: 252636 , Revision: 004
B.3 Blo ck Lock Status R eg ist er
The Block Status Register indicate s whether an erase opera tion compl eted succe ssfull y or whether
a give n block is locked or can be acce ssed for flash program/erase ope rations.
B lock Erase St atu s (BS R.1 ) al lows syst em so ft war e to de ter min e the su cc ess of th e last bloc k era se
operation. BSR .1 can be us ed jus t after power-up to verify that the VCC supply was not
acc idental ly removed during an erase operation. This bit is only res et by issuing another erase
operation to the block. The Bl ock Status Register is acces sed from word address 02h within each
block.
B.4 CFI Query Identification String
The Identifica tion String provides verifica tion that the component supports the Common F lash
I nterface spe cification. It also indicat es the specification ve rsion and supported vendor-spe cified
command set(s).
Table 24. Block Status Register
Offset Length Description Address Value Notes
(BA+2)h 1 Block Lock Status Register BA+2: --00 or --01 1
BSR.0 Block Lock Status
0 = Unlocked
1 = Locked BA+2: (bit 0): 0 or 1
BSR.1 Block Lock-Do wn Status
0 = Not locked down
1 = Locked down BA+2: (bit 1): 0 or 1
BSR 2–7: Reserved for future use BA+2: (bit 2–7): 0
Note: 1. BA = The beginning location of a Block Address (i.e., 008000h is the beginning location of block 1
in word mode.)
Table 25. CFI Identification
Offset Length Description Addr. Hex
Code Value
10h 3 Query-unique ASCII string “QRY“ 10 --51 “Q”
11: --52 “R”
12: --59 “Y”
13h 2 Primary vendor command set and control interface ID code. 13: --03
16-bit ID code for vendor-specified algorithms 14: --00
15h 2 Extended Query Table primary algorithm address 15: --35
16: --00
17h 2 Alternate vendor comma nd set and co ntrol interfac e ID code 17: --00
0000h mea ns no se cond vendor-specified algorith m exist s 18: --00
19h 2 Secondary algori thm Extended Query Ta ble address. 19: --00
0000h means none exists 1A: --00
C3 SCSP Fla s h Me mor y
Datasheet Intel® Advance d+ Bo ot Block Flash Memory (C 3) SCSP Family 26 Aug 2005
Order Number: 252636, Revisio n: 004 55
B.5 System Interface Information
Tabl e 26. System Interface In forma tion
Offset Length Description Addr. Hex
Code Value
1Bh 1 VCC logic su pply minimu m program/erase voltage
bits 0– 3 BCD 100 mV
bits 4–7 BCD volts 1B: --27 2.7 V
1Ch 1 VCC logic supply maximum program/erase voltage
bits 0– 3 BCD 100 mV
bits 4–7 BCD volts 1C: --36 3.3 V
1Dh 1 VPP [programming] supply minimum program/erase voltage
bits 0– 3 BCD 100 mV
bits 4–7 HEX volts 1D: --B4 11. 4 V
1Eh 1 VPP [programming] supply maximum program/erase voltage
bits 0– 3 BCD 100 mV
bits 4–7 HEX volts 1E: --C 6 12.6 V
1Fh 1 “n” such that typical single word program time-out = 2n µs 1F: --05 32 µ s
1Bh 1 VCC logic su pply minimu m program/erase voltage
bits 0– 3 BCD 100 mV
bits 4–7 BCD volts 1B: --27 2.7 V
1Ch 1 VCC logic supply maximum program/erase voltage
bits 0– 3 BCD 100 mV
bits 4–7 BCD volts 1C: --36 3.3 V
1Dh 1 VPP [programming] supply minimum program/erase voltage
bits 0– 3 BCD 100 mV
bits 4–7 HEX volts 1D: --B4 11. 4 V
1Eh 1 VPP [programming] supply maximum program/erase voltage
bits 0– 3 BCD 100 mV
bits 4–7 HEX volts 1E: --C 6 12.6 V
1Fh 1 “n” such that typical single word program time-out = 2n µs 1F: --05 32 µ s
1Bh 1 VCC logic su pply minimu m program/erase voltage
bits 0– 3 BCD 100 mV
bits 4–7 BCD volts 1B: --27 2.7 V
1Ch 1 VCC logic supply maximum program/erase voltage
bits 0– 3 BCD 100 mV
bits 4–7 BCD volts 1C: --36 3.3 V
1Dh 1 VPP [programming] supply minimum program/erase voltage
bits 0– 3 BCD 100 mV
bits 4–7 HEX volts 1D: --B4 11. 4 V
20h 1 “n” such that typical max. buffer write time-out = 2n µs 20: --00 n/a
21h 1 “n” such that typical block erase time-out = 2n ms 21: --0A 1 s
22h 1 “n” such that typical full chip erase time-out = 2n ms 22: --00 n/a
23h 1 “n” such that maximum word program time-out = 2n time s typical 23: --04 512 µs
24h 1 “n” such that maximum buffer write time-out = 2n times typical 24: --00 n/a
25h 1 “n” such that maximum block erase time-out = 2n times typical 25: --03 8 s
26h 1 “n” such that maximum chip erase time-out = 2n times typical 26: --00 NA
C3 SCSP Flash Memory
26 Aug 2005 Intel® Advanced+ Boot Block Flash Memory (C3) SCSP Family Datasheet
56 Order Numbe r: 252636 , Revision: 004
B.6 Device Geometry Definition
n
Table 27. Device Geometry Definition
Offset Length Description Code
See Ta ble Below
27h 1 “n” such tha t device size = 2n in number of bytes 27:
28h 2 Flash device interface: x8 async x16 async x8/x16 async 28: --01 x16
28:00,29:00 28:01,29:00 28:02,29:00 2 9: --00
2Ah 2 “n” such that maximum number of bytes in write buffer = 2n2A: --00 0
2B: --00
2Ch 1
Number of erase block regions within device:
1. x = 0 mean s no erase blocki ng; the device erases in “bulk”
2. x specifies the number of device or partition regions with one or
more contiguous s ame-size e rase block s.
3. Symmetrically blocked partitio ns have one bl ocking re gion
4. Partition size = (total blocks) x (individual block size)
2C: --02 2
2Dh 4 Erase Block Region 1 Information 2D:
bits 0–15 = y, y+1 = number of identical-size erase blocks 2E:
bits 16–31 = z, region erase bloc k(s) size ar e z x 256 bytes 2F:
30:
31h 4 Erase Block Region 2 Information 31:
bits 0–15 = y, y+1 = number of identical-size erase blocks 32:
bits 16–31 = z, region erase bloc k(s) size ar e z x 256 by tes 33:
34:
C3 SCSP Fla s h Me mor y
Datasheet Intel® Advance d+ Bo ot Block Flash Memory (C 3) SCSP Family 26 Aug 2005
Order Number: 252636, Revisio n: 004 57
B.7 Intel-Specific Extended Query Table
Certain flash features and commands are optiona l. The Intel-Specific Extended Query table
specifies this and other sim ilar types of in f or mation.
Device Geometry Definition
Address 16-Mbit 32-Mbit
–B –T –B –T
27: --15 --15 --16 --16
28: --01 --01 --01 --01
29: --00 --00 --00 --00
2A: --00 --00 --00 --00
2B: --00 --00 --00 --00
2C: --02 --02 --02 --02
2D: --07 --1E --07 --3E
2E: --00 --00 --00 --00
2F: --20 --00 --20 --00
30: --00 --01 --00 --01
31: --1E --07 --3E --07
32: --00 --00 --00 --00
33: --00 --20 --00 --20
34: --01 --00 --01 --00
Table 28. Primary-Vendor Specific Extended Query (Sheet 1 of 2)
Offset(1)
P = 35h Length Description
(Optional Flash Features and Commands) Addr. Hex
Code Value
(P+0)h 3 Primary extended query table 35: --50 “P”
(P+1)h Unique ASCII string “PRI” 36: --52 “R”
(P+2)h 37: --49 “I”
(P+ 3)h 1 Major version number, ASCII 38: --31 “ 1”
(P+4)h 1 Minor version number, ASCII 39: --30 “0”
(P+ 5)h 4 O ptional feat ure and command support (1 =yes, 0=no) 3A: --66
(P+6)h bits 9–31 are reserved; undefined bits are “0.” If bit 31 is “1” then
anot her 31 bit field of op tio nal feat ures foll ows at the en d of the bit-30
field.
3B: --00
(P+7)h 3C: --00
(P+8)h 3D: --00
bit 0 Chip erase supported bit 0 = 0 No
bit 1 Suspend erase suppor ted bit 1 = 1 Yes
bit 2 Suspend program supported bit 2 = 1 Yes
bit 3 Legacy lock/unlock supported bit 3 = 0 No
C3 SCSP Flash Memory
26 Aug 2005 Intel® Advanced+ Boot Block Flash Memory (C3) SCSP Family Datasheet
58 Order Numbe r: 252636 , Revision: 004
bit 4 Queued erase supported bit 4 = 0 No
bit 5 Instant individual block locking supported bit 5 = 1 Yes
bit 6 Protection bits supported bit 6 = 1 Yes
bit 7 Page mod e read supported bit 7 = 0 No
bit 8 Synchronous read supported bit 8 = 0 No
(P+9)h 1 Supported functions after suspend: read array, status, query
Ot her s upported operations are:
bits 1–7 reserved; undefined bits are “0” 3E: --01
bit 0 Program supported after erase suspend bit 0 = 1 Yes
(P +A)h 2 Block status register ma sk 3F: --03
(P+B)h bits 2–15 are Reserved; undefined bits are “0” 40: --00
bit 0 Block Lock-Bit St atus register active bit 0 = 1 Yes
bit 1 Block Lock-Do wn Bit Status ac tiv e bit 1 = 1 Yes
(P+C)h 1 VCC logic su pply highest perfo rmance program/er ase vol tage
bits 0 –3 BCD value in 10 0 mV
bits 4–7 BCD value in volts 41: --33 3.3 V
(P+D)h 1 VPP optimum program/erase supply voltage
bits 0 –3 BCD value in 10 0 mV
bits 4–7 HEX value in volts 42: --C 0 12.0 V
Table 29. Protection Register Information
Offset(1)
P = 35h Length Description
(Optional Flash Features and Commands) Addr. Hex
Code Value
(P+E)h 1 Number of Protection register fields in JEDEC ID space.
“00h,” indi cates that 256 protection bytes are available 43: --01 01
(P+F)h
4
Protect ion Field 1: P rotection Description 44: --80 80h
(P+10)h
This field describes user-available One Time Programmable (OTP)
Protection register bytes. Some are pre-programmed with device-
uniq ue ser ial nu mbe rs. Oth ers ar e u ser p ro gra mma bl e. B its 0– 15 poi nt
to the Protection register Lock byte, the section’s first byte. The
following bytes are factor y pre-programmed and user-prog rammable .
45: --00 00h
(P+11)h
bits 0 –7 = Lock/by tes JEDEC-plane physical low address
bits 8 –15 = L ock/b ytes JEDEC -pla ne physical hi gh add ress
bits 16–23 = “n” such that 2n = fa ctory pre- programmed bytes
bits 24–31 = “n” such that 2n = user pr ogrammable bytes
46: --03 8 byte
(P+12)h 47: --03 8 byte
(P+13) h Reserved for f uture us e 48:
Note: 1. The var iable P is a pointer which is defined at CFI offset 15h.
Table 28. Primar y-Vendo r Sp eci fic Extended Qu ery (Sheet 2 of 2)
Offset(1)
P = 35h Length Description
(Optional Flash Features and Commands) Addr. Hex
Code Value
C3 SCSP Fla s h Me mor y
Datasheet Intel® Advance d+ Bo ot Block Flash Memory (C 3) SCSP Family 26 Aug 2005
Order Number: 252636, Revisio n: 004 59
Appendix C Word-Wide Memory Map Diagrams
Table 30. 16, 32, and 64 Mbit Memory Addressing (Sheet 1 of 3)
16-Mbit, 32-Mbit 64-Mbit Word-Wide Memory Addressing
Top Boot Bo ttom Bo ot
Size
(KW) 16-Mbit 32-Mbit 64-Mbit Size
(KW) 16-Mbit 32-Mbit 64-Mbit
4 FF000-FFFFF 1FF000-
1FFFFF 3FF000-3FFFFF 32 3F8000-
3FFFFF
4FE000-FEFFF 1FE000-
1FEFFF 3FE000-
3FEFFF 32 3F0000-
3F7FFF
4 FD000-FDFFF 1FD000-
1FDFFF 3FD000-
3FDFFF 32 3E8000-
3EFFFF
4 FC000-FCFFF 1FC000-
1FCFFF 3FC000-
3FCFFF 32 3E0000-
3E7FFF
4FB000-FBFFF 1FB000-
1FBFFF 3FB000-
3FBFFF 32 3D8000-
3DFFFF
4FA000-FAFFF 1FA000-
1FAFFF 3FA000-3FAFFF 32 3D0000-
3D7FFF
4 F9000-F9FFF 1F9000-
1F9FFF 3F9000-3F9FFF 32 3C8000-
3CFFFF
4 F8000-F8FFF 1F8000-
1F8FFF 3F8000-3F8FFF 32 3C0000-
3C7FFF
32 F0000-F7FFF 1F0000-
1F7FFF 3F0000-3F7FFF 32 3B8000-
3BFFFF
32 E8000-EFFFF 1E8000-
1EFFFF 3E8000-
3EFFFF 32 3B0000-
3B7FFF
32 E0000-E7FFF 1E0000-
1E7FFF 3E0000-3E7FFF 32 3A8000-
3AFFFF
32 D8000-DFFFF 1D8000-
1DFFFF 3D8000-
3DFFFF 32 3A0000-
3A7FFF
32 D0000-D7FFF 1D0000-
1D7FFF 3D0000-
3D7FFF 32 398000-
39FFFF
32 C8000-CFFFF 1C8000-
1CFFFF 3C8000-
3CFFFF 32 390000-
397FFF
32 C0000-C7FFF 1C0000-
1C7FFF 3C0000-
3C7FFF 32 388000-
38FFFF
32 B8000-BFFFF 1B8000-
1BFFFF 3B8000-
3BFFFF 32 380000-
387FFF
32 B0000-B7FFF 1B0000-
1B7FFF 3B0000-3B7FFF 32 378000-
37FFFF
C3 SCSP Flash Memory
26 Aug 2005 Intel® Advanced+ Boot Block Flash Memory (C3) SCSP Family Datasheet
60 Order Numbe r: 252636 , Revision: 004
32 A8000-AFFFF 1A8000-
1AFFFF 3A8000-
3AFFFF 32 370000-
377FFF
32 A0000-A7FFF 1A0000-
1A7FFF 3A0000-3A7FFF 32 368000-
36FFFF
32 98000-9FFFF 198000-
19FFFF 398000-39FFFF 32 360000-
367FFF
32 90000-97FFF 190000-
197FFF 390000-397FFF 32 358000-
35FFFF
32 88000-8FFFF 188000-
18FFFF 388000-38FFFF 32 350000-
357FFF
32 80000-87FFF 180000-
187FFF 380000-387FFF 32 348000-
34FFFF
32 78000-7FFFF 178000-
17FFFF 378000-37FFFF 32 340000-
347FFF
32 70000-77FFF 170000-
177FFF 370000-377FFF 32 338000-
33FFFF
32 68000-6FFFF 168000-
16FFFF 368000-36FFFF 32 330000-
337FFF
32 60000-67FFF 160000-
167FFF 360000-367FFF 32 328000-
32FFFF
32 58000-5FFFF 158000-
15FFFF 358000-35FFFF 32 320000-
327FFF
32 50000-57FFF 150000-
157FFF 350000-357FFF 32 318000-
31FFFF
32 48000-4FFFF 148000-
14FFFF 348000-34FFFF 32 310000-
317FFF
32 40000-47FFF 140000-
147FFF 340000-347FFF 32 308000-
30FFFF
32 38000-3FFFF 138000-
13FFFF 338000-33FFFF 32 300000-
307FFF
32 30000-37FFF 130000-
137FFF 330000-337FFF 32 2F8000-
2FFFFF
32 28000-2FFFF 128000-
12FFFF 328000-32FFFF 32 2F0000-
2F7FFF
32 20000-27FFF 120000-
127FFF 320000-327FFF 32 2E8000-
2EFFFF
32 18000-1FFFF 118000-
11FFFF 318000-31FFFF 32 2E0000-
2E7FFF
Table 30. 16, 32, and 64 Mbit Memo ry Addressi ng (Sheet 2 of 3)
16-Mbit, 32-Mbit 64-Mbit Word-Wide Memory Addressing
Top Boot Bottom Boot
Size
(KW) 16-Mbit 32-Mbit 64-Mbit Size
(KW) 16-Mbit 32-Mbit 64-Mbit
C3 SCSP Fla s h Me mor y
Datasheet Intel® Advance d+ Bo ot Block Flash Memory (C 3) SCSP Family 26 Aug 2005
Order Number: 252636, Revisio n: 004 61
32 10000-17FFF 110000-
117FFF 310000-317FFF 32 2D8000-
2DFFFF
32 08000-0FFFF 108000-
10FFFF 308000-30FFFF 32 2D0000-
2D7FFF
32 00000-07FFF 100000-
107FFF 300000-307FFF 32 2C8000-
2CFFFF
32 0F8000-
0FFFFF 2F8000-2FFFFF 32 2C0000-
2C7FFF
32 0F0000-
0F7FFF 2F0000-2F7FFF 32 2B8000-
2BFFFF
32 0E8000-
0EFFFF 2E8000-
2EFFFF 32 2B0000-
2B7FFF
32 0E0000-
0E7FFF 2E0000-2E7FFF 32 2A8000-
2AFFFF
32 0D8000-
0DFFFF 2D8000-
2DFFFF 32 2A0000-
2A7FFF
32 0D0000-
0D7FFF 2D0000-
2D7FFF 32 298000-
29FFFF
32 0C8000-
0CFFFF 2C8000-
2CFFFF 32 290000-
297FFF
32 0C0000-
0C7FFF 2C0000-
2C7FFF 32 288000-
28FFFF
32 0B8000-
0BFFFF 2B8000-
2BFFFF 32 280000-
287FFF
32 0B0000-
0B7FFF 2B0000-2B7FFF 32 278000-
27FFFF
32 0A8000-
0AFFFF 2A8000-
2AFFFF 32 270000-
277FFF
This column continues on next page This column continues on next page
Table 30. 16, 32, and 64 Mbit Memory Addressing (Sheet 3 of 3)
16-Mbit, 32-Mbit 64-Mbit Word-Wide Memory Addressing
Top Boot Bo ttom Bo ot
Size
(KW) 16-Mbit 32-Mbit 64-Mbit Size
(KW) 16-Mbit 32-Mbit 64-Mbit
C3 SCSP Flash Memory
26 Aug 2005 Intel® Advanced+ Boot Block Flash Memory (C3) SCSP Family Datasheet
62 Order Numbe r: 252636 , Revision: 004
Table 31. 16, 32, and 64 Mbit Memo ry Addressi ng (Sheet 1 of 3)
16-Mbit, 32-Mbit 64-Mbit Word-Wide Memory Addressing
Top Boot Bottom Boot
Size
(KW) 16-Mbit 32-Mbit 64-Mbit Size
(KW) 16-Mbit 32-Mbit 64-Mbit
32 0A0000-
0A7FFF 2A0000-2A7FFF 32 268000-
26FFFF
32 098000-
09FFFF 298000-29FFFF 32 260000-
267FFF
32 090000-
097FFF 290000-297FFF 32 258000-
25FFFF
32 088000-
08FFFF 288000-28FFFF 32 250000-
257FFF
32 080000-
087FFF 280000-287FFF 32 248000-
24FFFF
32 078000-
07FFFF 278000-27FFFF 32 240000-
247FFF
32 070000-
077FFF 270000-277FFF 32 238000-
23FFFF
32 068000-
06FFFF 268000-26FFFF 32 230000-
237FFF
32 060000-
067FFF 260000-267FFF 32 228000-
22FFFF
32 058000-
05FFFF 258000-25FFFF 32 220000-
227FFF
32 050000-
057FFF 250000-257FFF 32 218000-
21FFFF
32 048000-
04FFFF 248000-24FFFF 32 210000-
217FFF
32 040000-
047FFF 240000-247FFF 32 208000-
20FFFF
32 038000-
03FFFF 238000-23FFFF 32 200000-
207FFF
32 030000-
037FFF 230000-237FFF 32 1F8000-
1FFFFF 1F8000-
1FFFFF
32 028000-
02FFFF 228000-22FFFF 32 1F0000-
1F7FFF 1F0000-
1F7FFF
32 020000-
027FFF 220000-227FFF 32 1E8000-
1EFFFF 1E8000-
1EFFFF
32 018000-
01FFFF 218000-21FFFF 32 1E0000-
1E7FFF 1E0000-
1E7FFF
32 010000-
017FFF 210000-217FFF 32 1D8000-
1DFFFF 1D8000-
1DFFFF
C3 SCSP Fla s h Me mor y
Datasheet Intel® Advance d+ Bo ot Block Flash Memory (C 3) SCSP Family 26 Aug 2005
Order Number: 252636, Revisio n: 004 63
32 008000-
00FFFF 208000-21FFFF 32 1D0000-
1D7FFF 1D0000-
1D7FFF
32 000000-
007FFF 200000-207FFF 32 1C8000-
1CFFFF 1C8000-
1CFFFF
32 1F8000-1FFFFF 32 1C0000-
1C7FFF 1C0000-
1C7FFF
32 1F0000-1F7FFF 32 1B8000-
1BFFFF 1B8000-
1BFFFF
32 1E8000-
1EFFFF 32 1B0000-
1B7FFF 1B0000-
1B7FFF
32 1E0000-1E7FFF 32 1A8000-
1AFFFF 1A8000-
1AFFFF
32 1D8000-
1DFFFF 32 1A0000-
1A7FFF 1A0000-
1A7FFF
32 1D0000-
1D7FFF 32 198000-
19FFFF 198000-
19FFFF
32 1C8000-
1CFFFF 32 190000-
197FFF 190000-
197FFF
32 1C0000-
1C7FFF 32 188000-
18FFFF 188000-
18FFFF
32 1B8000-
1BFFFF 32 180000-
187FFF 180000-
187FFF
32 1B0000-1B7FFF 32 178000-
17FFFF 178000-
17FFFF
32 1A8000-
1AFFFF 32 170000-
177FFF 170000-
177FFF
32 1A0000-1A7FFF 32 168000-
16FFFF 168000-
16FFFF
32 198000-19FFFF 32 160000-
167FFF 160000-
167FFF
32 190000-197FFF 32 158000-
15FFFF 158000-
15FFFF
32 188000-18FFFF 32 150000-
157FFF 150000-
157FFF
32 180000-187FFF 32 148000-
14FFFF 148000-
14FFFF
32 178000-17FFFF 32 140000-
147FFF 140000-
147FFF
Table 31. 16, 32, and 64 Mbit Memory Addressing (Sheet 2 of 3)
16-Mbit, 32-Mbit 64-Mbit Word-Wide Memory Addressing
Top Boot Bo ttom Bo ot
Size
(KW) 16-Mbit 32-Mbit 64-Mbit Size
(KW) 16-Mbit 32-Mbit 64-Mbit
C3 SCSP Flash Memory
26 Aug 2005 Intel® Advanced+ Boot Block Flash Memory (C3) SCSP Family Datasheet
64 Order Numbe r: 252636 , Revision: 004
32 170000-177FFF 32 138000-
13FFFF 138000-
13FFFF
32 168000-16FFFF 32 130000-
137FFF 130000-
137FFF
32 160000-167FFF 32 128000-
12FFFF 128000-
12FFFF
32 158000-15FFFF 32 120000-
127FFF 120000-
127FFF
32 150000-157FFF 32 118000-
11FFFF 118000-
11FFFF
32 148000-14FFFF 32 110000-
117FFF 110000-
117FFF
32 140000-147FFF 32 108000-
10FFFF 108000-
10FFFF
32 138000-13FFFF 32 100000-
107FFF 100000-
107FFF
32 130000-137FFF 32 F8000-FFFFF F8000-FFFFF F8000-FFFFF
32 128000-12FFFF 32 F0000-F7FFF F0000-F7FFF F0000-F7FFF
32 120000-127FFF 32 E8000-EFFFF E8000-EFFFF E8000-EFFFF
32 118000-11FFFF 32 E0000-E7FFF E0000-E7FFF E0000-E7FFF
32 110000-117FFF 32 D8000-DFFFF D8000-
DFFFF D8000-DFFFF
32 108000-10FFFF 32 D0000-D7FFF D0000-D7FFF D0000-D7FFF
32 100000-107FFF 32 C8000-CFFFF C8000-
CFFFF C8000-CFFFF
32 0F8000-0FFFFF 32 C0000-C7FFF C0000-C7FFF C0000-C7FFF
This column continues on next page This column continues on next page
Table 31. 16, 32, and 64 Mbit Memo ry Addressi ng (Sheet 3 of 3)
16-Mbit, 32-Mbit 64-Mbit Word-Wide Memory Addressing
Top Boot Bottom Boot
Size
(KW) 16-Mbit 32-Mbit 64-Mbit Size
(KW) 16-Mbit 32-Mbit 64-Mbit
C3 SCSP Fla s h Me mor y
Datasheet Intel® Advance d+ Bo ot Block Flash Memory (C 3) SCSP Family 26 Aug 2005
Order Number: 252636, Revisio n: 004 65
Table 32. 16, 32, and 64 Mbit Memory Addressing (Sheet 1 of 2)
16-Mbit, 32-Mbit 64-Mbit Word-Wide Memory Addressing
Top Boot Bottom Boot
Size
(KW) 16-Mbit 32-Mbit 64-Mbit Size
(KW) 16-Mbit 32-Mbit 64-Mbit
32 0F0000-0F7FFF 32 B8000-BFFFF B8000-BFFFF B8000-BFFFF
32 0E8000-
0EFFFF 32 B0000-B7FFF B0000-B7FFF B0000-B7FFF
32 0E0000-0E7FFF 32 A8000-AFFFF A8000-AFFFF A8000-AFFFF
32 0D8000-
0DFFFF 32 A0000-A7FFF A0000-A7FFF A0000-A7FFF
32 0D0000-
0D7FFF 32 98000-9FFFF 98000-9FFFF 98000-9FFFF
32 0C8000-
0CFFFF 32 90000-97FFF 90000-97FFF 90000-97FFF
32 0C0000-
0C7FFF 32 88000-8FFFF 88000-8FFFF 88000-8FFFF
32 0B8000-
0BFFFF 32 80000-87FFF 80000-87FFF 80000-87FFF
32 0B0000-0B7FFF 32 78000-7FFFF 78000-7FFFF 78000-7FFFF
32 0A8000-
0AFFFF 32 70000-77FFF 70000-77FFF 70000-77FFF
32 0A0000-0A7FFF 32 68000-6FFFF 68000-6FFFF 68000-6FFFF
32 098000-09FFFF 32 60000-67FFF 60000-67FFF 60000-67FFF
32 090000-097FFF 32 58000-5FFFF 58000-5FFFF 58000-5FFFF
32 088000-08FFFF 32 50000-57FFF 50000-57FFF 50000-57FFF
32 080000-087FFF 32 48000-4FFFF 48000-4FFFF 48000-4FFFF
32 078000-07FFFF 32 40000-47FFF 40000-47FFF 40000-47FFF
32 070000-077FFF 32 38000-3FFFF 38000-3FFFF 38000-3FFFF
32 068000-06FFFF 32 30000-37FFF 30000-37FFF 30000-37FFF
32 060000-067FFF 32 28000-2FFFF 28000-2FFFF 28000-2FFFF
32 058000-05FFFF 32 20000-27FFF 20000-27FFF 20000-27FFF
32 050000-057FFF 32 18000-1FFFF 18000-1FFFF 18000-1FFFF
32 048000-04FFFF 32 10000-17FFF 10000-17FFF 10000-17FFF
32 040000-047FFF 32 08000-0FFFF 08000-0FFFF 08000-0FFFF
32 038000-03FFFF 4 07000-07FFF 07000-07FFF 07000-07FFF
C3 SCSP Flash Memory
26 Aug 2005 Intel® Advanced+ Boot Block Flash Memory (C3) SCSP Family Datasheet
66 Order Numbe r: 252636 , Revision: 004
Appendix D Device ID Tab le
32 030000-037FFF 4 06000-06FFF 06000-06FFF 06000-06FFF
32 028000-02FFFF 4 05000-05FFF 05000-05FFF 05000-05FFF
32 020000-027FFF 4 04000-04FFF 04000-04FFF 04000-04FFF
32 018000-01FFFF 4 03000-03FFF 03000-03FFF 03000-03FFF
32 010000-017FFF 4 02000-02FFF 02000-02FFF 02000-02FFF
32 008000-00FFFF 4 01000-01FFF 01000-01FFF 01000-01FFF
32 000000-007FFF 4 00000-00FFF 00000-00FFF 00000-00FFF
Table 33. Devi ce ID
Read Configuration Address and Data
Item Address Data
Manufacturer Code x16 00000 0089
Device Cod e
16 -M b it x 16 -T x16 00001 8 8C 2
16 -M b it x 16 -B x16 0 0001 8 8C 3
32 -M b it x 16 -T x16 00001 8 8C 4
32 -M b it x 16 -B x16 0 0001 8 8C 5
Note: Other lo cati o ns wit hi n the conf igu r atio n ad dres s sp ac e ar e rese r ved by In t el for fut ur e use.
Table 32. 16, 32, and 64 Mbit Memo ry Addressi ng (Sheet 2 of 2)
16-Mbit, 32-Mbit 64-Mbit Word-Wide Memory Addressing
Top Boot Bot to m Boot
Size
(KW) 16-Mbit 32-Mbit 64-Mbit Size
(KW) 16-Mbit 32-Mbit 64-Mbit
C3 SCSP Fla s h Me mor y
Datasheet Intel® Advance d+ Bo ot Block Flash Memory (C 3) SCSP Family 26 Aug 2005
Order Number: 252636, Revisio n: 004 67
Appendi x E Protection Register Addressing
Table 34. Protection Register Addressing
Word-Wide Protection Register Addressing
WordUseA7A6A5A4A3A2A1A0
LOCKBoth10000000
0Factory10000001
1Factory10000010
2Factory10000011
3Factory10000100
4User10000101
5User10000110
6User10000111
7User10001000
Note: All address lines not specified in the above table must be 0 when accessing the Protection Register—for example,
A21–A8 = 0.
C3 SCSP Flash Memory
26 Aug 2005 Intel® Advanced+ Boot Block Flash Memory (C3) SCSP Family Datasheet
68 Order Numbe r: 252636 , Revision: 004
Appendix F Mechanical and Shipping Media Details
F.8 Mechanical Specification
Note: Shaded pins i ndica te upper address balls for 64-Mbit and 12 8-Mbit devices . In all Flash an d SRAM
c ombi nat i ons, 66 ba ll s are po pula t ed on l owe r de ns it y devi ce s. (U pper ad dre ss b al ls are no t pop ul ated ) .
E
1 2 3 4 5 6 7 8
A
B
C
D
E
F
G
H
910 11 12
A1
Index
D
12345678 A
B
C
D
E
F
G
H
9101112
S2
S
1
b
e
Bottom View - Ball UpTop View - Ball Down
A
A2
Y
A1
Table 35. Pa ckaging Specifications (0.18µm an d 0.25µm) (Sheet 1 of 2)
Millimeters Inches
Sym Min Nom Max Min Nom Max
Package H eigh t A 1. 400 0.0551
Ball Height A1 0.250 0.0098
Package Body Thickness A2 0.960 0.0378
Ball Lead Diameter b 0.350 0.400 0.450 0.0138 0.0157 0.0177
P ac k ag e B od y Le ng th – 16 - Mb it /2- M b it
D
9.900 10.00 10.100 0.3898 0.3937 0.3976
Package Body Length –
32-Mbit/4-Mbit, 16-Mbit/4-Mbit 11.900 12.000 12.100 0.4685 0.4724 0.4764
Package Body Length –
32-Mbit/8-Mbit 13.900 14.000 14.100 0.5472 0.5512 0.5551
Package Body Width –
16-Mbit/2-Mbit, 16-Mbit/4-Mbit,
32-Mbit/4-Mbit, 32-Mbit/8-Mbit E 7.900 8.000 8.100 0.3110 0.3150 0.3189
C3 SCSP Fla s h Me mor y
Datasheet Intel® Advance d+ Bo ot Block Flash Memory (C 3) SCSP Family 26 Aug 2005
Order Number: 252636, Revisio n: 004 69
Pitch e 0.800 0.0315
Ball (Lead) Count N 66 66
Seating Plane Coplanarity Y 0.100 0.0039
Corner to Ball A1 Distance Along E
16-Mbit/2-Mbit, 16-Mbit/4-Mbit,
32-Mbit/4-Mbit, 32-Mbit/8-Mbit S1 1.100 1.200 1.300 0.0433 0.0472 0.0512
Corner to Ball A1 Distance Along D
16-Mbit/2-Mbit
S2
0.500 0.600 0.700 0.0197 0.0236 0.0276
Corner to Ball A1 Distance Along D
32-Mbit/4-Mbit, 16-Mbit/4-Mbit 1.500 1.600 1.700 0.0591 0.0630 0.0669
Corner to Ball A1 Distance Along D
32-Mbit/8-Mbit 2.500 2.600 2.700 0.0984 0.1024 0.1063
Tabl e 35. Packag ing Specifications (0.18µm and 0.25µm) (Sheet 2 of 2)
Millimeters Inches
Sym Min Nom Max Min Nom Max
C3 SCSP Flash Memory
26 Aug 2005 Intel® Advanced+ Boot Block Flash Memory (C3) SCSP Family Datasheet
70 Order Numbe r: 252636 , Revision: 004
Table 36. Packaging Specifications (0.13µm)
Millimeters Inches
Sym Min Nom Max Min Nom Max
Package Height
16/02-Mb, 16/04-Mb, 32/08-Mb A
1. 200 0.047 2
Package Height
32/04-Mb 1. 400 0.0551
Ball Height
16/02-Mb, 16/04-Mb, 32/08-Mb A1
0.200 0.0079
Ball Height
32/04-Mb 0.250 0.0098
Package Body Thickness
16/02-Mb, 16/04-Mb, 32/08-Mb A2
0.860 0.0339
Package Body Thickness
32/04-Mb 0.960 0.0378
Ball (Lead) Width
16/02-Mb, 16/04-Mb, 32/08-Mb b
0.325 0.375 0.425 0.0128 0.0148 0.0167
Ball (Lead) Width
32/04-Mb 0.350 0.40 0.450 0.0138 0.0157 0.0177
Packag e Body Leng th
16/02-Mb, 16/04-Mb D
9.900 10.000 10.100 0.3898 0.3937 0.3976
Packag e Body Leng th
32/04-Mb, 32/08-Mb 11.900 12.000 12.100 0.4685 0.4724 0.4764
Packag e Body Width
16/02-Mb, 16/04-Mb, 32/04-Mb, 32/08-Mb E 7.900 8.000 8.100 0.3110 0.3150 0.3189
Pitch e 0.800 0.0315
Ball (Lead) Count N 66 66
Seating Plane Coplana rity Y 0. 100 0.0039
Corner to Ball A1 Distance Along E
16/02-Mb, 16/04-Mb, 32/04-Mb, 32/08-Mb S1 1.100 1.200 1.300 0.0433 0.0472 0.0512
Corner to Ball A1 Distance Along D
16/02-Mb, 16/04-Mb S2 0.500 0.600 0.700 0.0197 0.0236 0.0276
Corner to Ball A1 Distance Along D
32/04-Mb, 32/08-Mb S2 1.500 1.600 1.700 0.0591 0.0630 0.0669
C3 SCSP Fla s h Me mor y
Datasheet Intel® Advance d+ Bo ot Block Flash Memory (C 3) SCSP Family 26 Aug 2005
Order Number: 252636, Revisio n: 004 71
F.9 Media Information
Note: Top view, ball side down. Drawing is not to scale and is only designed to show orientation of devices.
Tray Chamfer
Device Pin 1
C3 SCSP Flash Memory
26 Aug 2005 Intel® Advanced+ Boot Block Flash Memory (C3) SCSP Family Datasheet
72 Order Numbe r: 252636 , Revision: 004
Note: Top view, ball side down.
Figure 21. SCSP Devi ce in 24 mm Tap e (10 mm x 8 mm and 12 mm x 8 mm )
Device Pin 1
C3 SCSP Fla s h Me mor y
Datasheet Intel® Advance d+ Bo ot Block Flash Memory (C 3) SCSP Family 26 Aug 2005
Order Number: 252636, Revisio n: 004 73
Appen dix G Additional Infor mation
Table 37. Related Documents
Order Number Document/Tool
292216 AP-658 Designing for Upgrade to the Advanced+ Boot Block Flash Memory
292215 AP-657 Designing with the Advanced+ Boot Block Flash Memory Architecture
Contact Your In tel
Representative Fl ash D ata I nt eg r at or (FD I) Sof twar e De ve lo per’s Kit
297874 FDI Interactive: Play with Intel’s Flash Data Integrator on Your PC
Notes:
1. Please call the Intel Lit erature Center at (800) 548-4725 to reques t Intel documen tation .
International customers should contact their local Intel or distribution sales office.
2. Visit Intel’s World Wide Web home page at http://www .Intel.com or http://developer.intel.com for
techn ical documenta tion and tools.
C3 SCSP Flash Memory
26 Aug 2005 Intel® Advanced+ Boot Block Flash Memory (C3) SCSP Family Datasheet
74 Order Numbe r: 252636 , Revision: 004
Appendix H Orde ring Information
.
Table 38. Ord eri ng Informatio n for Product Combin ations with 0.25 µm to 0.13 µm Flash
Table 39. Ord eri ng Informatio n for Combinations sp ecific to 32M 0.13 µm Flash
R D 2 8 F 1 6 0 2 C 3 T D 7 0
P
ackage
R D = Leaded Ball St ac k ed-C SP
P
roduct Line D esignator
16 Mbi t = 70, 90 , or 110 ns
32 Mbi t = 70 or 90 ns
Acce ss Spe ed (ns
)
28F or 38F = Intel
®
Flash Memory
F
lash Density
320 = x16 (32 Mbi t)
160 = x16 (16 Mbi t)
S
RAM Device Density
8 = x16 ( 8 M bit)
4 = x16 ( 4 M bit)
2 = x16 ( 2 M bit)
Parameter Location
T = T op Bloc k ing
B = Bot t om Blo c kin g
D = 0. 13µm
< blank > = 0. 25µm or
0 .18 µm (ref er t o ac ces s
s peed f or dif f erient at ion)
Technology
Differentiator
C = Adv anc ed+ Boot Bloc k
Flash Memory
Product Fami l y
PF = L ead -F ree Ball St ac k ed-C SP
P arameter Locatio n
R D 3 8 F 1 0 1 0 C 0 Z T L 0
P
ackage
R D = Leaded Ba ll S t a cked- CSP
P
roduct Line Designator
D
ensity
F las h #1 = 1 = 32 M bit
F las h #2 = 0 = N o Di e
F las h #3 = 1 = 4 M bit SR AM
= 2 = 8 Mb it SR AM
F las h #4 = 0 = N o Di e
P
roduct Family
0 = Or iginal V ersion of
t his produc t:
F las h Speed = 7 0 n s
F las h Proc es s = 0. 13 µm
Vc c q = 2.7 V to 3.3 V
D evi ce D etails
L = 72 ball "I "-b allout
Pi nout Indi cator
T = Top Block ing
B = Bot t om Blo c k ing
Voltage
Z = 3.0 V I/ O
C = Adv anc ed + Boot Bloc k F las h M em ory
38F = I nt el Flas h St ac k ed M em ory
®
PF = Lea d -F ree Bal l St ac k ed-C SP
C3 SCSP Fla s h Me mor y
Datasheet Intel® Advance d+ Bo ot Block Flash Memory (C 3) SCSP Family 26 Aug 2005
Order Number: 252636, Revisio n: 004 75
Table 40. Ordering Information Val id Combinations
0. 25 µm C3 SC SP 0.18 µm C3 SC SP 0.13µm C3 SC SP
32-Mb it No longer availa ble.
RD28F3208C3T70
RD28F3208C3B70
RD28F3208C3T90
RD28F3208C3B90
RD28F3204C3T70
RD28F3204C3B70
RD38F1010C0ZTL0
RD38F1010C0ZBL0
PF38F1010C0ZTL0
PF38F1010C0ZBL0
RD38F1020C0ZTL0
RD38F1020C0ZBL0
16-Mbit
RD28F1604C3T90
RD28F1604C3B90
RD28F1604C3T110
RD28F1604C3B110
RD28F1602C3T90
RD28F1602C3B90
RD28F1602C3T110
RD28F1602C3B110
RD28F1602C3T70
RD28F1602C3B70
PF28F1602C3TD70
RD28F1602C3TD70
RD28F1602C3BD70
RD28F1604C3TD70
RD28F1604C3BD70
