Product Specification
21328-DSH-001-E Mindspeed Technologies®9
Mindspeed Proprietary and Confidential
Table 1-6. C able Driver Output Electrical Specifications (SD/HD/2 xHD)
Symbol Parameter Notes Minimum Typical Maximum Units
DROUT Output Bit Rates 1, 5 0 — 2970 Mbps
tr/tfSD Rise/Fall Time (20–80%) 1, 3, 5 400 600 800 ps
HD/2xHD Rise/Fall Time (20–80%) 1, 3, 5 — 100 135 ps
tr/tfMM Rise/fall mismatch (HD/2xHD Rate) 1, 2, 5 — 10 30 ps
Rise/fall mismatch (SD Rate) 1, 2, 5 — 40 100 ps
VOSingle-ended voltage swing range p–p 1, 2, 4, 5 500 800 1600 mV
VOTOL Swing Level output variation at 800 mVpp
[RSET = 750ohm ±1%] (Single-Ended) 1, 2, 3, 5 -7 — +7 %
VOS Overshoot/Undershoot 1, 2, 5 -10 — +10 %
JAOPP Additive Output Jitter (HD/2xHD rate) 1, 5, 8 — 20 30 ps
Additive Output Jitter (SD rate) 1, 5, 8 — 40 60 ps
DCDODuty Cycle Distortion (HD/2xHD Rate) 1, 2, 5, 6, 8 — 15 30 ps
Duty Cycle Distortion (SD Rate) 1, 2, 5, 6, 8 — 20 70 ps
S22 Output Return Loss (5 MHz to 1.5 GHz) 1, 2, 5, 7 15 — — dB
S22 Output Return Loss (5 MHz to 3.0 GHz) 1, 2, 5, 7 10 — — dB
NOTES:
1. Entire table specified at recommended operating condition with 400 mVP–P differential input—see Table 1-2.
2. Specification verified at 800 mVpp output with 1m cable on MSPD test board. System results may vary.
3. Rated at nominal SMPTE 800 mV output swing level (using a 750Ω ±1% resistor at RSET).
4. Output stage is an open collector differential pair, actual swing dependant on IC supply voltage and external termination voltage.
5. Into 75Ω back termination and 75Ω load and appropriate external termination voltage, see Table 2-1, Figure 2-3.
6. Duty Cycle Distortion (DCD) is defined as the difference in the intrinsic jitter at the 50% voltage level and the intrinsic jitter at the rising/falling
edge crossing point. If the rising/falling edge crossing point is at the 50% voltage level, then DCD = 0.
7. Measured under DC conditions that simulate AC coupling, VT = 3.3V.
8. Measured using a “1010” data pattern.