LTC4291-1/LTC4292
1
Rev 0
For more information www.analog.comDocument Feedback
n PoE PSE Switches/Routers
n PoE PSE Midspans
APPLICATIONS
FEATURES DESCRIPTION
4-Port IEEE 802.3bt
PoE PSE Controller
The LTC
®
4291-1/LTC4292 chipset is a 4-port power
sourcing equipment (PSE) controller designed for use in
IEEE 802.3bt Type 3 and 4 compliant Power over Ethernet
(PoE) systems. The LTC4291-1/LTC4292 is designed to
power compliant 802.3af, 802.3at, and 802.3bt PDs. The
LTC4291-1/LTC4292 chipset delivers lowest-in-indus-
try heat dissipation by utilizing low RDS(ON) external
MOSFETs and 0.15Ω sense resistance per power channel.
Atransformer-isolated communication protocol replaces
expensive opto-couplers and complex isolated 3.3V sup-
ply, resulting in significant BOM cost savings.
Advanced power management features include per-port
14-bit current monitoring, programmable current limit,
and versatile fast shutdown of preselected ports. Advanced
power management host software is available under a no-
cost license. PD detection uses a proprietary multipoint
detection mechanism ensuring excellent immunity from
false PD identification. Autoclass and 5-event physical
classification are supported. The LTC4291-1/LTC4292
includes an I2C serial interface operable up to 1MHz. The
LTC4291-1/LTC4292 is pin or I2C programmable to nego-
tiate PD delivered power up to 71.3W.
n Four PSE Ports
n Two Power Channels per Port
n Fully Compliant IEEE 802.3bt Type 3 and 4 PSE
n Compliant Support for Type 1, 2, 3, and 4 PDs
n Low Power Path Dissipation per Channel
n 150mΩ Sense Resistance
n 30mΩ or Lower MOSFET RDS(ON)
n Chipset Provides Electrical Isolation
n Eliminates Optos and Isolated 3.3V Supply
n Very High Reliability Multipoint PD Detection
n Connection Check Distinguishes Single-
Signature and Dual-Signature PDs
n Continuous, Dedicated Per-Port Power and Current
Monitoring
n Per-Port Power Policing
n 1MHz I2C Compatible Serial Control Interface
n Pin or I2C Programmable PD Power Up to 71.3W
n Available in a 40-Lead 6mm × 6mm (LTC4292) and
24-Lead 4mm × 4mm (LTC4291-1) QFN Packages
All registered trademarks and trademarks are the property of their respective owners.
TYPICAL APPLICATION
VSSKn
VSSKn
V
EE
V
EE
100Ω
100Ω
100Ω
100Ω
100Ω
100Ω
100Ω
100Ω
S1B
10Ω
0.15Ω
>47µF
0.22µF
100V
S1B
S1B
0.15Ω
0.22µF
100V
S1B
2nF
0.1µF
1µF
100V
0.22µF
1µF
3.3V
V
EE
3.3V
CPA
CNA
DPA
DNA
V
EE
VSSKn
SENSEnA
GATEnA
AGNDP
LTC4292
1000BASE-T
V
EE
OUTnA
AGNDP
SENSEnB
GATEnB
OUTnB
AGNDP
TX1
TX2
TX3
TX4
RJ45
1
2
6
4
3
5
7
8
PWRMD0
PWRMD1
V
EE
MSD
SCL
SDAIN
AD0
DGND
DPD
CND
V
DD
LTC4291-1
CPD
DND
GP0
GP1
ISOLATION
AD1
AD2
AD3
SDAOUT
4PVALID
RESET
INT
AUTO
CAP1
3.3V
(NO I
2
C
ISOLATION
REQUIRED)
V
EE
AGNDP
(1 OF 4 PORTS)
CAP2
2kV
VSSKn
AGNDP
0.22μF, 100V
0.15Ω
42911 TA01a
LTC4291-1/LTC4292
2
Rev 0
For more information www.analog.com
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS
LTC4292
Supply Voltages
AGNDP – VEE ......................................... –0.3V to 80V
VSSK12, VSSK34 (Note 7) ... VEE – 0.3V to VEE + 0.3V
Digital Pins
PWRMD0, PWRMD1 ........ VEE – 0.3V to CAP2 + 0.3V
Analog Pins
SENSEnM, GATEnM, OUTnM VEE – 0.3V to VEE + 80V
CAP2 (Note 13) ...................... VEE – 0.3V to VEE + 5V
CPA, CNA, DPA, DNA .............. VEE – 0.3V to VEE + 0.3
Operating Ambient Temperature Range
LTC4292I .............................................–40°C to 85°C
Junction Temperature (Note 2) ............................ 125°C
Storage Temperature Range .................. –65°C to 150°C
(Notes 1, 4)
LTC4291-1
Supply Voltages
VDD – DGND ......................................... –0.3V to 3.6V
Digital Pins
SCL, SDAIN, SDAOUT, INT, RESET, MSD, ADn, AUTO,
4PVALID, GPn .................DGND – 0.3V to VDD + 0.3V
Analog Pins
CAP1 (Note 13) ...........................–0.3V to DGND + 2V
CPD, CND, DPD, DND ......DGND – 0.3V to VDD + 0.3V
Operating Ambient Temperature Range
LTC4291I-1 ..........................................–40°C to 85°C
Junction Temperature (Note 2) ............................ 125°C
Storage Temperature Range .................. –65°C to 150°C
(Note 1)
LTC4292 LTC4291-1
1211 13 14 15
TOP VIEW
41
VEE
UJ PACKAGE
40-LEAD (6mm × 6mm) PLASTIC QFN
TJMAX = 125°C, θJC = 2°C/W, θJA = 33°C/W
EXPOSED PAD (PIN 41) IS V
EE
, MUST BE SOLDERED TO PCB
16 17 18 19 20
3940 38 37 36 35 34 33 32 31
23
24
25
26
27
28
29
30
8
7
6
5
4
3
2
1GATE1A
OUT1A
GATE1B
OUT1B
VSSK12
CAP2
GATE2A
OUT2A
GATE2B
OUT2B
GATE4B
OUT4B
GATE4A
OUT4A
VSSK34
AGNDP
GATE3B
OUT3B
GATE3A
OUT3A
VEE
CPA
CNA
DPA
DNA
NC
NC
VEE
NC
VEE
PWRMD0
SENSE1A
SENSE1B
SENSE2A
SENSE2B
SENSE3A
SENSE3B
SENSE4A
SENSE4B
PWRMD1
22
21
9
10
24 23 22 21 20 19
789
TOP VIEW
UF PACKAGE
24-LEAD (4mm × 4mm) PLASTIC QFN
TJMAX = 125°C, θJC = 4°C/W, θJA = 47°C/W
EXPOSED PAD (PIN 25) IS DGND, MUST BE SOLDERED TO PCB
10 11 12
6
5
4
3
2
1
13
14
15
16
17
18
AD0
AD1
AD2
AD3
DGND
4PVALID
SCL
SDAIN
SDAOUT
INT
RESET
DNC
MSD
GP0
GP1
AUTO
VDD
CAP1
NC
CPD
CND
DPD
DND
VDD
25
DGND
LTC4291-1/LTC4292
3
Rev 0
For more information www.analog.com
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC4291IUF-1#PBF LTC4291IUF-1#TRPBF 42911 24-Lead (4mm × 4mm) Plastic QFN –40°C to 85°C
LTC4292IUJ#PBF LTC4292IUJ#TRPBF LTC4292UJ 40-Lead (6mm × 6mm) Plastic QFN –40°C to 85°C
Contact the factory for parts specified with wider operating temperature ranges.
Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. AGNDP – VEE = 54V and VDD – DGND = 3.3V unless otherwise noted.
(Notes 3 and 4)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Main PoE Supply Voltage AGNDP – VEE
For IEEE Type 3 Compliant Output
For IEEE Type 4 Compliant Output
l
l
51
53
57
57
V
V
Undervoltage Lock-Out AGNDP – VEE l20 25 30 V
VDD VDD Supply Voltage VDD – DGND l3.0 3.3 3.6 V
Undervoltage Lock-Out VDD – DGND 2.7 V
VCAP1 Internal Regulator Supply Voltage VCAP1 – DGND 1.84 V
VCAP2 Internal Regulator Supply Voltage VCAP2 – VEE 4.3 V
IEE VEE Supply Current (AGNDP – VEE) = 55V l9 15 mA
REE VEE Supply Resistance (AGNDP – VEE) < 15V l12 kΩ
IDD VDD Supply Current (VDD – DGND) = 3.3V l10 15 mA
Detection/Connection Check
Forced Current First Point, AGNDP – VOUTnM = 9V
Second Point, AGNDP – VOUTnM = 3.5V
l
l
220
143
240
160
260
180
µA
µA
Forced Voltage AGNDP – VOUTnM, 5µA ≤ IOUTnM ≤ 500µA
First Point
Second Point
l
l
7
3
8
4
9
5
V
V
Detection/Connection Check Current
Compliance
AGNDP – VOUTnM = 0V l0.8 0.9 mA
VOC Detection/Connection Check Voltage
Compliance
AGNDP – VOUTnM, Open Port l10.4 12 V
Detection/Connection Check Voltage
Slew Rate
AGNDP – VOUTnM, CPORT = 0.15µF (Note 7) l0.01 V/µs
Min. Valid Signature Resistance l15.5 17 18.5 kΩ
Max. Valid Signature Resistance l27.5 29.7 32 kΩ
LTC4291-1/LTC4292
4
Rev 0
For more information www.analog.com
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. AGNDP – VEE = 54V and VDD – DGND = 3.3V unless otherwise noted.
(Notes 3 and 4)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Classification
VCLASS Classification Voltage AGNDP – VOUTnM, 0mA ≤ IOUTnM ≤ 50mA l16.0 20.5 V
Classification Current Compliance VOUTnM = AGNDP l53 61 67 mA
Classification Threshold Current Class Signature 0 – 1
Class Signature 1 – 2
Class Signature 2 – 3
Class Signature 3 – 4
Class Signature 4 – Overcurrent
l
l
l
l
l
5.5
13.5
21.5
31.5
45.2
6.5
14.5
23
33
48
7.5
15.5
24.5
34.9
50.8
mA
mA
mA
mA
mA
VMARK Classification Mark State Voltage AGNDP – VOUTnM, 0.1mA ≤ ICLASS ≤ 5mA l7.5 9 10 V
Mark State Current Compliance VOUTnM = AGNDP l53 61 67 mA
Gate Driver
GATE Pin Pull-Down Current Port Off, VGATEnM = VEE + 5V
Port Off, VGATEnM = VEE + 1V
l
l
0.4
0.08
0.12
mA
mA
GATE Pin Fast Pull-Down Current VGATEnM = VEE + 5V 30 mA
GATE Pin On Voltage VGATEnM – VEE, IGATEnM = 1µA l8 12 14 V
Output Voltage Sense
VPG Power Good Threshold Voltage VOUTnM – VEE l2 2.4 2.8 V
OUT Pin Pull-Up Resistance to AGNDP 0V ≤ (AGNDP – VOUTnM) ≤ 5V l300 500 700 kΩ
Current Sense
VCUT-2P Overcurrent Sense Voltage,
Single-Signature PD
VSENSEnM – VSSKn
Class 1, CUTn[6:0] = 45h
Class 2, CUTn[6:0] = 48h
Class 3, CUTn[6:0] = 52h
Class 4, CUTn[6:0] = 62h
Class 5, CUTn[6:0] = 5Fh
Class 6, CUTn[6:0] = 67h
Class 7, CUTn[6:0] = 6Ch
Class 8, CUTn[6:0] = 74h (Note 12)
l
l
l
l
l
l
l
l
13.5
21.6
47.5
92.0
84.0
105
119
140
14.1
22.5
50.5
96.0
87.0
110
124
146
14.6
23.4
53.5
100.0
91.0
114
129
152
mV
mV
mV
mV
mV
mV
mV
mV
Overcurrent Sense Voltage,
Dual-Signature PD
VSENSEnM – VSSKn
Class 1, CUTn[6:0] = 45h
Class 2, CUTn[6:0] = 48h
Class 3, CUTn[6:0] = 52h
Class 4, CUTn[6:0] = 62h
Class 5, CUTn[6:0] = 74h (Note 12)
l
l
l
l
l
13.5
21.6
47.5
92.0
140
14.1
22.5
50.5
96.0
146
14.6
23.4
53.5
100.0
152
mV
mV
mV
mV
mV
VLIM-2P Active Current Limit,
Single-Signature PD
VOUTnM – VEE < 10V
Class 1 – Class 3, LIMn = 80h
Class 4 – Class 6, LIMn = C0h
Class 7, LIMn = D0h
Class 8, LIMn = E9h (Note 12)
l
l
l
l
61.2
122
153
168
63.6
128
159
175
67.3
135
169
185
mV
mV
mV
mV
Active Current Limit,
Dual-Signature PD
VOUTnM – VEE < 10V
Class 1 – Class 3, LIMn = 80h
Class 4, LIMn = C0h
Class 5, LIMn = E9h (Note 12)
l
l
l
61.2
122
168
63.6
128
175
67.3
135
185
mV
mV
mV
VINRUSH-2P Active Current Limit, Inrush AGNDP – VOUTnM > 30V (Note 17)
LIMn = 80h
LIMn = 08h
l
l
61.2
30.6
63.6
31.8
67.3
33.7
mV
mV
VHOLD-2P DC Disconnect Sense Voltage VSENSEnM – VSSKn
CUTn[7] (Dis) Bit = 0
CUTn[7] (Dis) Bit = 1 (Note 12)
l
l
0.31
0.76
0.53
1.13
0.74
1.49
mV
mV
LTC4291-1/LTC4292
5
Rev 0
For more information www.analog.com
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. AGNDP – VEE = 54V and VDD – DGND = 3.3V unless otherwise noted.
(Notes 3 and 4)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VSC Short-Circuit Sense VSENSEnM – VEE – VLIM l20 50 80 mV
Port Current Readback
Full-Scale Range (Notes 7, 15, 16) 1.018 V
LSB Weight VSENSEnM – VSSKn, VSSKn = VEE (Note 15) l61.0 62.1 63.5 µV/LSB
Averaging Period FILTER_TYPE Bit = 1
FILTER_TYPE Bit = 0 (Note 7)
100
1000
ms
ms
Update Interval (Note 7) 100 ms
Port Power Readback
Full-Scale Range (Notes 7, 15, 16) 83.8 V2
LSB Weight (VSENSEnM – VSSKn) × (AGNDP – VEE)
VSSKn = VEE (Note 15)
l4.992 5.115 5.235 mV2/LSB
Averaging Period FILTER_TYPE Bit = 1
FILTER_TYPE Bit = 0 (Note 7)
100
1000
ms
ms
Update Interval (Note 7) 100 ms
System Voltage Readback
Full-Scale Range (Note 7) 82 V
LSB Weight AGNDP – VEE l9.8 10.1 10.3 mV/LSB
Averaging Period FILTER_TYPE Bit = 1
FILTER_TYPE Bit = 0 (Note 7)
100
1000
ms
ms
Update Interval (Note 7) 100 ms
Digital Interface
VILD Digital Input Low Voltage ADn, RESET, MSD, GPn, AUTO, 4PVALID (Note 6) l0.8 V
I2C Input Low Voltage SCL, SDAIN (Note 6) l1.0 V
VIHD Digital Input High Voltage (Note 6) l2.2 V
Digital Output Voltage Low ISDAOUT = 3mA, IINT = 3mA
ISDAOUT = 5mA, IINT = 5mA
l
l
0.4
0.7
V
V
Internal Pull-Up to VDD ADn, RESET, MSD, GPn50 kΩ
Internal Pull-Down to DGND AUTO, 4PVALID 50 kΩ
PWRMD
PWRMD Digital Input Low Voltage VPWRMDn – VEE l0.8 V
PWRMD Digital Input High Voltage VPWRMDn – VEE l3.4 V
Internal Pull Up to CAP2 PWRMD0, PWRMD1 50 kΩ
PSE Timing Characteristics (Note 7)
tDET Detection Time Beginning to End of Detection l320 500 ms
tCLASS_RESET Classification Reset Duration l15 ms
tCEV Class Event Duration l6 12 20 ms
tCEVON Class Event Turn On Duration CPORT = 0.6µF l0.1 ms
tLCE Long Class Event Duration l88 105 ms
tCLASS Class Event ICLASS Measurement Timing l6 ms
tCLASS_LCE Long Class Event ICLASS Measurement
Timing
l6 75 ms
tCLASS_ACS Autoclass ICLASS Measurement Timing l88 ms
LTC4291-1/LTC4292
6
Rev 0
For more information www.analog.com
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
tME1 Mark Event Duration (Except Last Mark
Event)
(Note 11) l6 8.6 12 ms
tME2 Last Mark Event Duration (Note 11) l6 20 ms
tPON Power On Delay, Auto Mode From End of Valid Detect to End of Valid Inrush
(Note 14)
l400 ms
tAUTO_PSE1 Autoclass Power Measurement Start From End of Inrush to Beginning of Autoclass
Power Measurement
l1.4 1.6 s
tAUTO_PSE2 Autoclass Power Measurement End From End of Inrush to End of Autoclass Power
Measurement
l3.1 3.5 s
tAUTO_WINDOW Autoclass Average Power Sliding
Window
l0.15 0.2 0.3 s
tED Fault Delay From Power On Fault to Next Detect l1.0 1.3 1.5 s
tSTART Maximum Current Limit Duration
During Inrush
l52 59 66 ms
tCUT Maximum Overcurrent Duration After
Inrush
l52 59 66 ms
Maximum Overcurrent Duty Cycle l5.8 6.3 6.7 %
tLIM Maximum Current Limit Duration After
Inrush
(Note 12)
Type 3, tLIMn = 8h
Type 4, tLIMn = 5h
l
l
10
6
12
8
14
10
ms
ms
tMPS Maintain Power Signature (MPS) Pulse
Width Sensitivity
Current Pulse Width to Reset Disconnect Timer
(Note 8)
l1.6 3.6 ms
tDIS Maintain Power Signature (MPS)
Dropout Time
(Note 5) l320 350 380 ms
tMSD Masked Shut Down Delay 6.5 µs
I2C Watchdog Timer Duration l1.5 2 3 s
Minimum Pulse Width for Masked Shut
Down
l3 µs
Minimum Pulse Width for RESET l4.5 µs
I2C Timing (Note 7)
fSCLK Clock Frequency l1 MHz
t1Bus Free Time Figure5 (Note 9) l480 ns
t2Start Hold Time Figure5 (Note 9) l240 ns
t3SCL Low Time Figure5 (Note 9) l480 ns
t4SCL High Time Figure5 (Note 9) l240 ns
t5SDAIN Data Hold Time Figure5 (Note 9) l60 ns
t5Data Clock to SDAOUT Valid Figure5 (Note 9) l130 ns
t6Data Set-Up Time Figure5 (Note 9) l80 ns
t7Start Set-Up Time Figure5 (Note 9) l240 ns
t8Stop Set-Up Time Figure5 (Note 9) l240 ns
trSCL, SDAIN Rise Time Figure5 (Note 9) l120 ns
tfSCL, SDAIN Fall Time Figure5 (Note 9) l60 ns
Fault Present to INT Pin Low (Notes 9, 10) l150 ns
Stop Condition to INT Pin Low (Notes 9, 10) l1.5 µs
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. AGNDP – VEE = 54V and VDD – DGND = 3.3V unless otherwise noted.
(Notes 3 and 4)
LTC4291-1/LTC4292
7
Rev 0
For more information www.analog.com
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
ARA to INT Pin High Time (Note 9) l1.5 µs
SCL Fall to ACK Low (Note 9) l130 ns
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. AGNDP – VEE = 54V and VDD – DGND = 3.3V unless otherwise noted.
(Notes 3 and 4)
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. With the exception of (VDD –
DGND), exposure to any Absolute Maximum Rating condition for extended
periods may affect device reliability and lifetime.
Note 2: This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 140ºC when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
Note 3: All currents into device pins are positive; all currents out of device
pins are negative.
Note 4: The LTC4292 operates with a negative supply voltage (with
respect to AGNDP). To avoid confusion, voltages in this data sheet are
referred to in terms of absolute magnitude.
Note 5: tDIS is the same as tMPDO defined by IEEE 802.3.
Note 6: The LTC4291-1 digital interface operates with respect to DGND. All
logic levels are measured with respect to DGND.
Note 7: Guaranteed by design, not subject to test.
Note 8: The IEEE 802.3 specification allows a PD to present its
Maintain Power Signature (MPS) on an intermittent basis without being
disconnected. In order to stay powered, the PD must present the MPS for
tMPS within any tMPDO time window.
Note 9: Values Measured at VILD and VIHD.
Note 10: If a fault condition occurs during an I2C transaction, the INT pin
will not be pulled down until a stop condition is present on the I2C bus.
Note 11: Load characteristics of the LTC4292 during Mark: 7V <
(AGNDP – VOUTnM) < 10V or IOUTnM < 50µA.
Note 12: See the LTC4291 Software Programming documentation for
information on serial bus usage and device configuration and status
registers.
Note 13: Do not source or sink current from CAP1 and CAP2.
Note 14: For single-signature PDs, tPON is measured from end of valid
detect on either power channel. For dual-signature PDs, tPON is measured
from the end of valid detect on the same power channel.
Note 15: Port current and port power measurements depend on sense
resistor value (0.15Ω typical). See External Component Selection for
details.
Note 16: The full-scale range for each power channel is half of the port
full-scale range.
Note 17: See Inrush Control for details on inrush threshold selection.
LTC4291-1/LTC4292
8
Rev 0
For more information www.analog.com
Open Circuit Detection
TYPICAL PERFORMANCE CHARACTERISTICS
802.3bt Single–Signature
Class Probe and Demotion Classification Current Compliance
Power On Current Limits
Single–Signature
Power On Current Limits
Dual–Signature Inrush Current Limits (Note 17)
802.3bt Single–Signature
Power On Sequence
802.3bt Single–Signature
Classification and Power On
802.3bt Dual–Signature
Power On Sequence
V
EE
DETECTION /
CONNECTION
CHECK
CLASSIFICATION
POWER
ON
OUT1A
OUT1B
200ms/DIV
–60
–50
–40
–30
–20
–10
0
CHANNEL VOLTAGE (V)
Power On Sequence
42911 G01
V
EE
CLASSIFICATION
POWER
ON
CLASS 8
OUT1A
OUT1B
40ms/DIV
–60
–50
–40
–30
–20
–10
0
CHANNEL VOLTAGE (V)
Classification and Power On
42911 G02
V
EE
DETECTION /
CONNECTION
CHECK
CLASSIFICATION
POWER
ON
OUT1A
OUT1B
200ms/DIV
–60
–50
–40
–30
–20
–10
0
CHANNEL VOLTAGE (V)
Power On Sequence
42911 G03
V
EE
PROBE
CLASS 8
POWER
ON
CLASS 8
CLASS
RESET
CLASS 3
DEMOTION
OUT1A
OUT1B
30ms/DIV
–60
–50
–40
–30
–20
–10
0
CHANNEL VOLTAGE (V)
Class Probe and Demotion
42911 G04
AGND
AGND
50ms/DIV
OUT1A
5V/DIV
OUT1B
5V/DIV
42911 G05
CLASSIFICATION CURRENT (mA)
0
10
20
30
40
50
60
70
–20
–16
–12
–8
–4
0
CLASSIFICATION VOLTAGE (V)
42911 G06
R
SENSE
= 0.15Ω
CLASS 1 TO 3
CLASS 4 TO 6
CLASS 7
CLASS 8
OUTnM – V
EE
(V)
0
11
22
33
44
55
0
25
50
75
100
125
150
175
200
0
167
333
500
667
833
1000
1167
1333
V
LIM–2P
(mV)
I
LIM–2P
(mA)
42911 G07
R
SENSE
= 0.15Ω
CLASS 1 TO 3
CLASS 4
CLASS 5
OUTnM – V
EE
(V)
0
11
22
33
44
55
0
25
50
75
100
125
150
175
200
0
167
333
500
667
833
1000
1167
1333
V
LIM-2P
(mV)
I
LIM-2P
(mA)
Dual–Signature
42911 G08
R
SENSE
= 0.15Ω
LIMn = 80h
LIMn = 08h
OUTnM – V
EE
(V)
0
11
22
33
44
55
0
25
50
75
100
125
150
175
200
0
167
333
500
667
833
1000
1167
1333
V
INRUSH–2P
(mV)
I
INRUSH–2P
(mA)
Inrush Current Limits (Note 17)
42911 G09
LTC4291-1/LTC4292
9
Rev 0
For more information www.analog.com
TYPICAL PERFORMANCE CHARACTERISTICS
ILIM-2P vs Temperature ICUT-2P vs Temperature
Current Readback ADC vs
Temperature
Voltage Readback ADC vs
Temperature
Power Readback ADC vs
Temperature
Powering Up into 180µF Load
LIMn = E9h
R
SENSE
= 0.15Ω
OUTnM = V
EE
TEMPERATURE (°C)
–40
–20
0
20
40
60
80
100
171
172
173
174
175
176
177
1140
1150
1160
1170
1180
V
LIM–2P
(mV)
I
LIM–2P
(mA)
LIM–2P
42911 G10
CUTn = 74h
R
SENSE
= 0.15Ω
TEMPERATURE (°C)
–40
–20
0
20
40
60
80
100
140
142
144
146
148
150
152
933
953
973
993
1013
V
CUT–2P
(mV)
I
CUT–2P
(mA)
CUT–2P
42911 G11
SENSEnM – VSSKn = 151mV
TEMPERATURE (°C)
–40
–20
0
20
40
60
80
100
2406
2411
2416
2421
2426
2431
2436
2441
2446
2451
2456
ADC CODE
42911 G12
AGNDP – VEE = 55V
TEMPERATURE (°C)
–40
–20
0
20
40
60
80
100
5430
5441
5452
5463
5474
5485
5496
5507
5518
5529
5540
ADC CODE
42911 G13
AGNDP – VEE = 55V
SENSEnM – VSSKn = 151mV
TEMPERATURE (°C)
–40
–20
0
20
40
60
80
100
1614
1618
1622
1626
1630
1634
1638
1642
1646
ADC CODE
vs Temperature
42911 G14
FET ON
FOLDBACK
CURRENT
LIMIT
VEE
LOAD FULLY CHARGED
5ms/DIV
OUT1A
20V/DIV
GATE1A
10V/DIV
CHANNEL
CURRENT
200mA/DIV
42911 G15
Temporary Short Circuit on
Channel 1B
AGND
VEE
VEE
100µs/DIV
OUT1B
50V/DIV
OUT1A
50V/DIV
GATE1B
10V/DIV
CHAN 1B
CURRENT
2A/DIV
42911 G16
LTC4291-1/LTC4292
10
Rev 0
For more information www.analog.com
TEST TIMING DIAGRAMS
Figure1. Detect, Class and Turn-On Timing in Auto or Semi-Auto Modes
VOUTnM
PD
CONNECTED
CLASSIFICATIONDETECTION
tDET
FORCED-CURRENT
FORCED-
VOLTAGE
CONNECTION
CHECK
VOC
INT
VEE
42911 F01
tSTART
TURN ON
20.5V
VMARK
VCLASS
tCEV
tCEV
tLCE
tME1 tME1 tME2
tCLASS_RESET
0V
2.8V
15.5V
tPON
tLCE
tCEVON
TYPICAL PERFORMANCE CHARACTERISTICS
VEE Supply Current vs Voltage
VDD Supply Current vs
Temperature
85°C
25°C
–40°C
AGNDP – V
EE
(V)
30
33
36
39
42
45
48
51
54
57
60
5.0
5.5
6.0
6.5
7.0
7.5
8.0
8.5
9.0
9.5
10.0
I
EE
SUPPLY CURRENT (mA)
EE
42911 G017
85°C
25°C
–40°C
V
DD
SUPPLY VOLTAGE (V)
2.9
3
3.1
3.2
3.3
3.4
3.5
3.6
10
11
12
13
14
15
16
17
18
I
DD
SUPPLY CURRENT (mA)
42911 G18
LTC4291-1/LTC4292
11
Rev 0
For more information www.analog.com
TEST TIMING DIAGRAMS
Figure2. Current Limit Timing
Figure3. DC Disconnect Timing
Figure4. Shut Down Delay Timing
Figure5. I2C Interface Timing
VLIM-2P VCUT-2P
0V
VSENSEnM TO VEE
INT
42911 F02
tSTART, tCUT
VMIN
VSENSEnM
TO VEE
INT
tDIS
tMPS 42911 F03
VGATEnM
VEE
MSD
tMSD
42911 F04
SCL
SDA
t1
t2
t3tr
tf
t5t6t7t8
t4
42911 F05
LTC4291-1/LTC4292
12
Rev 0
For more information www.analog.com
I2C TIMING DIAGRAMS
Figure6. Writing to a Register
Figure7. Reading from a Register
Figure8. Reading the Interrupt Register (Short Form)
Figure9. Reading from Alert Response Address
SCL
SDA
42911 F06
0 01 AD3 AD2 AD1 AD0 A7 A6 A5 A4 A3 A2 A1 A0
R/W ACK D7 D6 D5 D4 D3 D2 D1 D0
ACK ACK
START BY
MASTER
ACK BY
SLAVE
ACK BY
SLAVE
ACK BY
SLAVE
FRAME 1
SERIAL BUS ADDRESS BYTE
FRAME 2
REGISTER ADDRESS BYTE
FRAME 3
DATA BYTE
STOP BY
MASTER
SCL
SDA 0 01 AD3 AD2 AD1 AD0 A7 A6 A5 A4 A3 A2 A1 A0
R/W ACK ACK 01 AD3 AD2 AD1 AD0 D7 D6 D5 D4 D3 D2 D1 D0
R/W ACK ACK
START BY
MASTER
ACK BY
SLAVE
ACK BY
SLAVE
42911 F07
STOP BY
MASTER
REPEATED
START BY MASTER
ACK BY
SLAVE
NO ACK BY
MASTER
FRAME 1
SERIAL BUS ADDRESS BYTE
FRAME 2
REGISTER ADDRESS BYTE
FRAME 1
SERIAL BUS ADDRESS BYTE
FRAME 2
DATA BYTE
0
SCL
SDA
42911 F08
0 1 0AD3 AD2 AD1 AD0 D7 D6 D5 D4 D3 D2 D1 D0
R/W ACK ACK
START BY
MASTER
ACK BY
SLAVE
NO ACK BY
MASTER
FRAME 1
SERIAL BUS ADDRESS BYTE
FRAME 2
DATA BYTE
STOP BY
MASTER
SCL
SDA
42911 F09
0 0 110AD30000 1 AD2 AD1 AD0
R/W ACK ACK1
START BY
MASTER
ACK BY
SLAVE
NO ACK BY
MASTER
FRAME 1
ALERT RESPONSE ADDRESS BYTE
FRAME 2
SERIAL BUS ADDRESS BYTE
STOP BY
MASTER
LTC4291-1/LTC4292
13
Rev 0
For more information www.analog.com
PIN FUNCTIONS
LTC4292
VEE (Pins 31, 33, 40, Exposed Pad Pin 41): Main PoE
Supply Input. Connect to a –51V to –57V supply, relative
to AGNDP. Voltage depends on PSE Type (Type 3 or 4).
GATEnM (Pins 1, 3, 7, 9, 22, 24, 28, 30): Gate Drive,
Port n, Channel M. Connect GATEnM to the gate of
the external MOSFET for port n, channel M. When the
MOSFET is turned on, the gate voltage is driven to
12V(typ) above VEE. During a current limit condition, the
voltage at GATEnM will be reduced to maintain constant
current through the external MOSFET. If the fault timer
expires, GATEnM is pulled down, turning the MOSFET off
and raising a port n fault event. If the channel is unused,
the GATEnM pin must be floated.
OUTnM (Pins 2, 4, 8, 10, 21, 23, 27, 29): Output Voltage
Monitor, Port n, Channel M. Connect OUTnM to the output
channel. A current limit foldback circuit limits the power
dissipation in the external MOSFET by reducing the cur-
rent limit threshold when the drain-to-source voltage
exceeds 10V. The port n power good event is raised when
the voltage from OUTnM to VEE drops below 2.4V (typ).
A 500k resistor is connected internally from OUTnM to
AGNDP when the channel is idle. If the channel is unused,
the OUTnM pin must be floated.
CAP2 (Pin 6): Analog Internal 4.3V Power Supply Bypass
Capacitor. Connect a 0.22µF ceramic cap to VEE.
PWRMDn (Pins 11, 20): Maximum Power Mode Input.
Logic input signals between V
EE
and V
EE
+ 4.3V for config-
uration of maximum output power per-port in auto mode.
See Auto Mode Maximum PSE Power section. Internally
pulled up to CAP2.
SENSEnM (Pins 12, 13, 14, 15, 16, 17, 18, 19): Current
Sense Input, Port n, Channel M. SENSEnM monitors
the external MOSFET current via a 0.15Ω sense resistor
between SENSEnM and VSSKn. Whenever the voltage
across the sense resistor exceeds the overcurrent detection
threshold VCUT-2P, the current limit fault timer counts up. If
the voltage across the sense resistor reaches the current
limit threshold VLIM-2P, the GATEnM pin voltage is lowered
to maintain constant current in the external MOSFET. See
Applications Information for further details. If the channel
is unused, the SENSEnM pin must be tied to VEE.
AGNDP (Pin 25): Analog Ground. Connect AGNDP to the
return for the VEE supply through a 10Ω resistor.
DNA (Pin 36): Data Transceiver Negative Input Output
(Analog). Connect to DND through a data transformer.
DPA (Pin 37): Data Transceiver Positive Input Output
(Analog). Connect to DPD through a data transformer.
CNA (Pin 38): Clock Transceiver Negative Input Output
(Analog). Connect to CND through a data transformer.
CPA (Pin 39): Clock Transceiver Positive Input Output
(Analog). Connect to CPD through a data transformer.
VSSK12 (Pin 5): Kelvin Sense to VEE. Connect to sense
resistor common node for ports 1 and 2 through a 0.15Ω
resistor. Connect to AGNDP through a 0.22μF, 100V
capacitor. Do not connect directly to VEE plane. See Layout
Requirements.
VSSK34 (Pin 26): Kelvin Sense to VEE. Connect to sense
resistor common node for ports 3 and 4 through a 0.15Ω
resistor. Connect to AGNDP through a 0.22μF, 100V
capacitor. Do not connect directly to VEE plane. See Layout
Requirements.
Common Pins
NC, DNC (LTC4291-1 Pins 7, 13; LTC4292 Pins 32, 34,
35): All pins identified with “NC” or “DNC” must be left
unconnected.
LTC4291-1
AD0 (Pin 1): Address Bit 0. Tie the address pins high or
low to set the I2C serial address to which the LTC4291-1
responds. The address will be (010A3A2A1A0)b. Internally
pulled up to VDD.
AD1 (Pin 2): Address Bit 1. See AD0.
AD2 (Pin 3): Address Bit 2. See AD0.
AD3 (Pin 4): Address Bit 3. See AD0.
4PVALID (Pin 6): 4-Pair Valid Input, Active Low. When
low, the LTC4291-1/LTC4292 will not apply power to a
port unless both pairsets present a valid signature. When
high, the LTC4291-1/LTC4292 will power any pairset pre-
senting a valid signature, regardless of the other pairset.
Internally pulled down to DGND.
LTC4291-1/LTC4292
14
Rev 0
For more information www.analog.com
CPD (Pin 8): Clock Transceiver Positive Input Output
(Digital). Connect to CPA through a data transformer.
CND (Pin 9): Clock Transceiver Negative Input Output
(Digital). Connect to CNA through a data transformer.
DPD (Pin 10): Data Transceiver Positive Input Output
(Digital). Connect to DPA through a data transformer.
DND (Pin 11): Data Transceiver Negative Input Output
(Digital). Connect to DNA through a data transformer.
VDD (Pins 12, 20): VDD IO Power Supply. Connect to
a 3.3V power supply relative to DGND. VDD must be
bypassed to DGND near the LTC4291-1 with at least a
0.1μF capacitor.
RESET (Pin 14): Reset Input, Active Low. When RESET is
low, the LTC4291-1/LTC4292 is held inactive with all ports
off and all internal registers reset. When RESET is pulled
high, the LTC4291-1/LTC4292 begins normal operation.
RESET can be connected to an external capacitor or RC
network to provide a power turn-on delay. Internal filtering
of RESET prevents glitches less than 1μs wide from reset-
ting the LTC4291-1/LTC4292. Internally pulled up to V
DD
.
INT (Pin 15): Interrupt Output, Open Drain. INT will pull
low when any one of several events occur in the LTC4291-
1. It will return to a high impedance state when bits 6 or
7 are set in the Reset PB register (1Ah). The INT signal
can be used to generate an interrupt to the host proces-
sor, eliminating the need for continuous software polling.
Individual INT events can be disabled using the INT Mask
register (01h). See LTC4291 Software Programming
documentation for more information. INT is only updated
between I2C transactions.
SDAOUT (Pin 16): Serial Data Output, Open Drain Data
Output for the I2C Serial Interface Bus. The LTC4291-1
uses two pins to implement the bidirectional SDA func-
tion to simplify opto isolation of the I2C bus. To imple-
ment a standard bidirectional SDA pin, tie SDAOUT and
SDAIN together. See Applications Information for more
information.
SDAIN (Pin 17): Serial Data Input. High impedance data
input for the I2C serial interface bus. The LTC4291-1
uses two pins to implement the bidirectional SDA func-
tion to simplify opto isolation of the I2C bus. To imple-
ment a standard bidirectional SDA pin, tie SDAOUT and
SDAIN together. See Applications Information for more
information.
SCL (Pin 18): Serial Clock Input. High impedance clock
input for the I2C serial interface bus. The SCL pin should
be connected directly to the I2C SCL bus line. SCL must
be tied high if the I2C serial interface bus is not used.
CAP1 (Pin 19): Core Power Supply Bypass Capacitor.
Connect a 1µF capacitance to DGND for the internal 1.8V
regulator bypass. Do not use other capacitor values.
AUTO (Pin 21): Auto Mode Input, Active High. When high,
the LTC4291-1 detects, classifies and powers up valid
PDs without host interaction. AUTO determines the state
of the internal registers when the LTC4291-1 is reset or
comes out of UVLO (see LTC4291 Software Programming
documentation). The state of these register bits can sub-
sequently be changed via the I2C interface. Internally
pulled down to DGND.
GP1 (Pin 22): General Purpose Digital Input Output for
customer applications. Referenced to DGND.
GP0 (Pin 23): General Purpose Digital Input Output for
customer applications. Referenced to DGND.
MSD (Pin 24): Maskable Shutdown Input, Active Low.
When pulled low, all ports that have their corresponding
mask bit set in the mconf register (17h) will be reset.
Internal filtering of the MSD pin prevents glitches less
than 1μs wide from resetting ports. The MSD Pin Mode
register can configure the MSD pin polarity. Internally
pulled up to VDD.
DGND (Pin 5, Exposed Pad Pin 25): Digital Ground. DGND
should be connected to the return from the VDDsupply.
PIN FUNCTIONS
LTC4291-1/LTC4292
15
Rev 0
For more information www.analog.com
OVERVIEW
Power over Ethernet, or PoE, is a standard protocol for
sending DC power over copper Ethernet data wiring.
The IEEE group that administers the 802.3 Ethernet data
standards added PoE powering capability in 2003. This
original PoE standard, known as 802.3af, allowed for 48V
DC power at up to 13W. 802.3af was widely popular, but
13W was not adequate for some applications. In 2009,
the IEEE released a new standard, known as 802.3at or
PoE+, increasing the voltage and current requirements to
provide 25.5W of delivered power.
The IEEE standard also defines PoE terminology. A device
that provides power to the network is known as a PSE,
or power sourcing equipment, while a device that draws
power from the network is known as a PD, or powered
device. PSEs come in two types: Endpoints (typically net-
work switches or routers), which provide data and power;
and Midspans, which provide power but pass through
data. Midspans are typically used to add PoE capabil-
ity to existing non-PoE networks. PDs are typically IP
phones, wireless access points, security cameras, and
similar devices.
PoE++ Evolution
Even during the development of the IEEE 802.3at (PoE+)
25.5W standard, it became clear there was a significant
and increasing need for more than 25.5W of delivered
power. In 2013, the 802.3bt task force was formed to
develop a standard capable of increasing delivered PD
power.
The primary objective of the task force is to use all four
pairs of the Ethernet cable as opposed to the two pair
power utilized by 802.3at. Using all four pairs allows for
at least twice the delivered power over existing Ethernet
cables. Further, the amount of current per two pairs
(known as a pairset) has been increased while maintain-
ing the Ethernet data signal integrity. 802.3bt increases
APPLICATIONS INFORMATION
PD delivered power from 25.5W to 71.3W, enabling IEEE-
compliant high power PD applications.
The LTC4291-1/LTC4292 delivers power over two power
channels. Each pairset is driven by a dedicated power
channel. In this data sheet, the term “channel” refers to
the PSE circuitry assigned to a corresponding pairset. For
the purposes of this document, the terms channel and
pairset may be considered interchangeable.
In addition, IEEE 802.3bt enables substantially lower
Maintain Power Signature (MPS) currents, resulting in
significantly lower standby power consumption. This
allows new and emerging government or industry standby
regulations to be met using standard PoE components.
LTC4291-1/LTC4292 Product Overview
The LTC4291-1/LTC4292 is a fifth generation PSE control-
ler that implements four PSE ports in either an Endpoint
or Midspan application. Virtually all necessary circuitry
is included to implement an IEEE 802.3bt compliant PSE
design, requiring a pair of external power MOSFETs and
sense resistors per port; these minimize power loss com-
pared to alternative designs with onboard MOSFETs, and
increase system reliability.
The LTC4291-1/LTC4292 chipset implements a propri-
etary isolation scheme for inter-chip communication. This
architecture substantially reduces BOM cost by replacing
expensive opto-isolators and isolated power supplies with
a single low-cost transformer.
The LTC4291-1/LTC4292 offers advanced fifth genera-
tion PSE features including a configurable interrupt sig-
nal triggered by per-port events, per-channel power on
control and fault telemetry, per-port current monitoring,
VEE monitoring, one second rolling current, voltage, and
port power averaging, and two general purpose input/
outputpins.
LTC4291-1/LTC4292
16
Rev 0
For more information www.analog.com
V
EE
and port current measurements are performed simul-
taneously, providing fully coherent port power calcula-
tions. The reported port power calculations enable coher-
ent and precise per-port power monitoring.
PoE BASICS
Common Ethernet data connections consist of two or
four twisted pairs of copper wire (commonly known
as Ethernet cable), transformer-coupled at each end to
avoid ground loops. PoE systems take advantage of this
coupling arrangement by applying voltage between the
center-taps of the data transformers to transmit power
from the PSE to the PD without affecting data transmis-
sion. Figures 10 and 11 show high level PoE system
schematics.
To avoid damaging legacy data equipment that does not
expect to see DC voltage, the PoE standard defines a
protocol that determines when the PSE may apply and
remove power. Valid PDs are required to have a specific
25k common-mode resistance at their input. When such
a PD is connected to the cable, the PSE detects this sig-
nature resistance and applies power. When the PD is
later disconnected, the PSE senses the open circuit and
removes power. The PSE also removes power in the event
of a current fault or short circuit.
When a PD is detected, the PSE looks for a classification
signature that tells the PSE the maximum power the PD
will draw. The PSE can use this information to allocate
power among several ports, to police the current con-
sumption of the PD, or to reject a PD that will draw more
power than the PSE has available.
New in 802.3bt
The 802.3bt draft introduces several new features:
n Type 3 and Type 4 PSEs may provide power over all
four pairs (both pairsets), depending on connected
PD characteristics.
n Type 3 and Type 4 PDs are required to be capable of
receiving power over all four pairs (both pairsets).
n Type 3 and 4 PDs can be formed as either a single-
signature PD or dual-signature PD. A single-signature
APPLICATIONS INFORMATION
PD presents the same valid signature resistor to both
pairsets simultaneously. A dual-signature PD pres-
ents two fully independent valid detection signatures,
one to each pairset.
n Type 3 single-signature PDs request exactly one of six
possible power levels: 3.84W, 6.49W, 13W, 25.5W,
40W, or 51W.
n
Type 3 dual-signature PDs request exactly one of four
possible power levels on each pairset: 3.84W, 6.49W,
13W, or 25.5W. The total PD requested power is the
sum of the requested power on both pairsets.
n Type 3 PD Classes overlap with Type 1 and 2 Classes
in order to provide additional Type 3 feature sets at
lower power levels.
n
Type 4 single-signature PDs request exactly one of
two possible power levels: 62W or 71.3W.
n Type 4 dual-signature PDs request exactly 35.6W on
at least one pairset and one of five possible power lev-
els on the other pairset: 3.84W, 6.49W, 13W, 25.5W,
or 35.6W. The total PD requested power is the sum
of the requested power on both pairsets.
n
Classification is extended to a possible maximum
of five class events. The additional events allow for
unique identification of existing and new PD Classes.
n Type 3 and 4 PSEs issue a long first class event to
advertise Type 3 and 4 feature support to attachedPDs.
n Lower standby power is enabled by shortening the
length of the maintain power signature pulse (short
MPS). The PD duty cycle drops from ~23% to ~2%. A
PD is allowed to present short MPS if the PSE issues
a long first class event.
n Power management is augmented by Autoclass, an
optional feature for 802.3bt PSEs and PDs. In an
Autoclass system the maximum PD power is mea-
sured and reported to the PSE host, enabling the PSE
to reclaim output power not used by the PD appli-
cation and losses in the Ethernet cabling (Table1).
See Autoclass section and LTC4291 Software
Programming documentation for details.
LTC4291-1/LTC4292
17
Rev 0
For more information www.analog.com
Figure10. Power over Ethernet Single-Signature PD System Diagram
Figure11. Power over Ethernet Dual-Signature PD System Diagram
1000BASE-T
TX1
TX2
TX3
TX4
RJ45
RJ45
1
2
6
4
3
5
7
8
1
2
6
4
3
5
7
8
1000BASE-T
TX1
TX2
TX3
TX4
V
EE
GATEnA
AGNDP
1/4
LTC4291-1/LTC4292
GATEnB
I2C
–54V
–54V
–54V
PD
42911 F10
+
–
VOUT
DATA PAIRS
DATA PAIRS
1000BASE-T
TX1
TX2
TX3
TX4
RJ45
RJ45
1
2
6
4
3
5
7
8
1
2
6
4
3
5
7
8
1000BASE-T
TX1
TX2
TX3
TX4
V
EE
GATEnA
AGNDP
1/4
LTC4291-1/LTC4292
GATEnB
I2C
–54V
–54V
–54V
42911 F11
PD1
+
–
VOUT
PD2
+
–
VOUT
DATA PAIRS
DATA PAIRS
APPLICATIONS INFORMATION
LTC4291-1/LTC4292
18
Rev 0
For more information www.analog.com
Table1. IEEE-Specified Power Allocations, Single-Signature PD
PD CLASS
PSE OUTPUT
POWER
ALLOCATED
CABLING LOSS
PD INPUT
POWER
1 4W 0.16W 3.84W
2 6.7W 0.21W 6.49W
3 14W 1W 13W
4 30W 4.5W 25.5W
5 45W 5W 40W
6 60W 9W 51W
7 75W 13W 62W
8 90W 18.7W 71.3W
BACKWARD COMPATIBILITY
The LTC4291-1/LTC4292 may be configured as an
802.3bt-compliant PSE, either Type 3 or Type 4. While
802.3bt PSEs cannot identify as an 802.3at Type 1 or
Type 2 PSE, there is no loss in PSE functionality; all
802.3bt-compliant PSEs are fully backwards compatible
with existing 802.3at Type1 and Type 2 PDs as shown
in Table2. In addition to full compatibility, 802.3bt PSEs
extend support for lower standby power, enhanced cur-
rent limit timing, and dynamic power management to all
PD Types (as supported by the PD application).
Table2. PSE Maximum Delivered Power, Per-Port
DEVICE PSE
STANDARD 802.3at 802.3bt
TYPE 1 2 3 4
PD
802.3at 113W 13W 13W 13W
213W* 25.5W 25.5W 25.5W
802.3bt 313W* 25.5W* 51W 51W
413W* 25.5W* 51W* 71.3W
*Indicates PD allocated less power than requested.
Software register map compatibility with LTC4266 and
LTC4271-based PSEs has been maintained to the extent
possible. LTC4291-based PSEs utilize two channels to
control a single PSE port. This multiplicity of channel
status and control requires extensions to the existing
registermap.
For register map details please contact Analog Devices
to request the LTC4291 Software Programming
documentation.
Special Compatibility Mode Notes
n As with prior generations, each I2C address provides
status and control for four PoE ports. Each port reg-
ister slice provides port control and status as well as
channel A vs B control and status.
n Certain status registers, e.g. Port Status and Power
Status, relate to a channel state, as opposed to port
state and are split into three copies; a generalized port
state, channel A state and channel B state.
n
Certain command registers, e.g., Power-on pushbutton,
likewise are bifurcated to allow per-channel control.
OPERATING MODES
The LTC4291-1/LTC4292 includes four independent
ports, each of which can operate in one of three modes:
manual, semi-auto, or auto. A fourth mode, shutdown,
disables the port (see Table3).
Table3. Operating Modes
MODE
AUTO
PIN OPMD
DETECT/
CLASS POWER-UP
AUTOMATIC
THRESHOLD
ASSIGNMENT
Auto
1 11b Enabled
at Reset Automatically Yes
0 11b Host
Enabled Automatically Yes
Semi-auto 0 10b Host
Enabled Upon Request No
Manual 0 01b
Once
Upon
Request
Upon Request No
Shutdown 0 00b Disabled Disabled No
In manual mode, the port waits for instructions from the
host system before taking any action. It runs a single
detection, or detection and classification cycle when com-
manded to by the host, and reports the result in its Port
Status register. The host system can command the port
to apply or remove power at any time.
In semi-auto mode, the port repeatedly attempts to detect
and classify any PD attached to it. It reports the status of
these attempts back to the host, and waits for a command
from the host before applying power to the port. The host
must enable detection and classification.
APPLICATIONS INFORMATION
LTC4291-1/LTC4292
19
Rev 0
For more information www.analog.com
Auto mode operates the same as semi-auto mode except
it will automatically apply power to the port if detec-
tion and classification are successful. Auto mode will
autonomously set the ICUT-2P, ILIM-2P, and PCUT-4P values
based on the Class result. This operational mode may
be entered by setting AUTO high at reset or by changing
the OPMD state to Auto. See Auto Mode Maximum PSE
Powersection.
In shutdown mode the port is disabled and will not detect
or power a PD.
Regardless of which mode it is in, the LTC4291-1/
LTC4292 will remove power automatically from any port
and/or channel, as appropriate, that generates a fault. It
will also automatically remove power from any port/chan-
nel that generates a disconnect event if disconnect detec-
tion is enabled. The host controller may also command
the port to remove power at any time.
Reset and the AUTO Pin
The initial LTC4291-1/LTC4292 configuration depends on
the state of AUTO during reset. Reset occurs at power-up,
whenever RESET is pulled low, or when the global Reset
All bit is set. Changing the state of AUTO after power-
up will not change the port behavior of the LTC4291-1/
LTC4292 until a reset occurs.
Although typically actively managed by a host controller,
the LTC4291-1/LTC4292 may alternatively be configured
for autonomous operation by setting AUTO high. With
AUTO high, each port will detect and classify repeatedly
until a PD is discovered, set ICUT-2P, ILIM-2P, and PCUT-4P
according to the PSE assigned Class, apply power to valid
PDs, and remove power when a PD is disconnected.
Tables 4 and 5 show the ICUT-2P, ILIM-2P, and PCUT-4P val-
ues that will be automatically set in auto mode, based on
the PD requested Class.
Table4. Typical Auto Mode Power On Thresholds,
Single-Signature PD
CLASS
PER-CHANNEL PER-PORT
ICUT-2P ILIM-2P PCUT-4P
1 94mA 425mA 5.43W
2 150mA 425mA 8.69W
3 338mA 425mA 19.5W
4 638mA 850mA 36.4W
5 581mA 850mA 52.7W
6 731mA 850mA 70.0W
7 825mA 1063mA 87.4W
8 975mA 1167mA 96.6W
Table5. Typical Auto Mode Power On Thresholds,
Dual-Signature PD
CLASS
PER-CHANNEL
ICUT-2P ILIM-2P PCUT-2P*
1 94mA 425mA 5.43W
2 150mA 425mA 8.69W
3 338mA 425mA 19.5W
4 638mA 850mA 36.4W
5 975mA 1167mA 48.3W
*A per-port PCUT-4P threshold holds the sum of PCUT-2P for each
poweredchannel.
CONNECTION CHECK
Connection Check Overview
IEEE 802.3bt introduces a new detection subroutine known
as connection check. A connection check is required to
determine whether the attached PD is a single-signature
PD, a dual-signature PD or an invalid result.
In 802.3at, only one PD configuration was described;
this is known as a single-signature PD and is shown in
Figure10. A single-signature PD presents the same 25k
detection resistor to both the pairsets in parallel.
New in 802.3bt is the dual-signature PD as shown in
Figure11. A dual-signature PD presents two fully indepen-
dent 25k detection signature resistors, one to each pairset.
APPLICATIONS INFORMATION
LTC4291-1/LTC4292
20
Rev 0
For more information www.analog.com
APPLICATIONS INFORMATION
Multipoint Detection
The LTC4291-1/LTC4292 uses a multipoint method to
detect PDs. False-positive detections are minimized by
checking for signature resistance with both forced current
and forced voltage measurements.
Initially, two test currents are forced onto the channel (via
the OUTnM pin) and the resulting voltages are measured.
The detection circuitry subtracts the two V-I points to
determine the resistive slope while removing offset caused
by series diodes or leakage at the port (see Figure13). If
the forced current detection yields a valid signature resis-
tance, two test voltages are then forced onto the channel
and the resulting currents are measured and subtracted.
Both methods must report valid resistances to report a
valid detection. PD signature resistances between 17k
and 29k (typically) are detected as valid and reported as
Detect Good in the corresponding Port Status register or
Channel Status register, as appropriate. Values outside
this range, including open and short circuits, are also
reported. If the channel measures less than 1V during
any forced current test, the detection cycle will abort and
Short Circuit will be reported. Tables 6 and 7 show the
possible detection results.
The PD configuration (single or dual) determines how the
PD is managed during subsequent detection, classifica-
tion and power on procedures. Throughout the remainder
of this data sheet attention will be called to the different
treatment of single-signature and dual-signature PDs.
Connection check is performed with two current measure-
ments, at the same forced voltage, on the first channel.
The second channel is tested for aggressor behavior by
introducing a forced current on the second channel during
the second measurement. Comparison of the two result-
ing current measurements on the first channel allows
for the connected device to be categorized as a single-
signature PD, a dual-signature PD, or an invalid result.
An invalid connection check result is reported when a
device is added or removed during connection check.
DETECTION
Detection Overview
To avoid damaging network devices that were not designed
to tolerate DC voltage, a PSE must determine whether the
connected device is a valid PD before applying power.
The IEEE specification requires that a valid PD have a
common-mode resistance of 25k ±5% at any channel
voltage below 10V. The PSE must accept resistances that
fall between 19k and 26.5k, and it must reject resistances
above 33k or below 15k (shaded regions in Figure12).
The PSE may choose to accept or reject resistances in
the undefined areas between the must-accept and must-
reject ranges. In particular, the PSE must reject standard
computer Network Interface Cards (NICs), many of which
have 150Ω common-mode termination resistors that will
be damaged if power is applied to them (the black region
at the left of Figure12).
Figure12. IEEE 802.3 Signature Resistance Ranges
RESISTANCE
PD
PSE
0Ω 10k
15k
42911 F12
19k 26.5k
26.25k23.75k
150Ω (NIC)
20k 30k
33k
Figure13. PD Detection
FIRST
DETECTION
POINT
SECOND
DETECTION
POINT
VALID PD
25kΩ SLOPE
240
160
CURRENT (µA)
0V-2V
OFFSET VOLTAGE
42911 F13
LTC4291-1/LTC4292
21
Rev 0
For more information www.analog.com
APPLICATIONS INFORMATION
Table6. Port Detection Status
MEASURED PD SIGNATURE
(TYPICAL) PORT DETECTION RESULT
Incomplete or Not Yet Tested Detect Status Unknown
VPD < 1V Short Circuit
RPD < 17k RSIG Too Low
17k < RPD < 29k Detect Good, Single-Signature PD
RPD > 29k RSIG Too High
RPD > 50k Open Circuit
VPD > 10V Port Voltage Outside Detect Range
Connection Check = INVALID Connection Check Invalid
Connection Check = DUAL or
Channel Detection Results Differ
Refer to Channel Detect Results
Table7. Channel Detection Status
MEASURED PD SIGNATURE
(TYPICAL) CHANNEL DETECTION RESULT
Incomplete or Not Yet Tested Detect Status Unknown
VPD < 1V Short Circuit
CPD > 2.7μF CPD Too High
RPD < 17k RSIG Too Low
17k < RPD < 29k Detect Good, Dual-Signature PD
RPD > 29k RSIG Too High
RPD > 50k Open Circuit
VPD > 10V Channel Voltage Outside Detect Range
Connection Check = INVALID Connection Check Invalid
Connection Check = SINGLE or
Channel Detection Results Match
Refer to Port Detect Result
More on Operating Modes
The port’s operating mode determines when the
LTC4291-1/LTC4292 runs a detection cycle. In manual
mode, the port will idle until the host orders a detect cycle.
It will then run detection, report the result, and return to
idle to wait for another command.
In semi-auto mode the LTC4291-1/LTC4292 autono-
mously polls a port for PDs, but it will not apply power
until commanded to do so by the host. The Port Status
and Channel Status registers are updated at the end of
each detection/classification cycle.
In semi-auto mode, if a valid signature resistance is
detected and classification is enabled, the port will classify
the PD and report that result as well. The port will then
wait for at least 100ms, and will repeat the detection cycle
to refresh the data in the Port Status registers.
The port will not turn on in response to a power-on com-
mand unless the current detect result is Detect Good. Any
other detect result will generate a tSTART fault if a power-on
command is received.
Behavior in auto mode is similar to semi-auto; however,
after Detect Good is reported and the port is classified, it
is automatically powered on without host intervention. In
auto mode the I
CUT-2P
, I
LIM-2P
, and P
CUT-4P
thresholds are
automatically set; see the Reset and the AUTO Pin section
for more information.
Detection is disabled for a port when the LTC4291-1/
LTC4292 is initially powered up with AUTO low, when
the port is in shutdown mode, or when the corresponding
Detect Enable bit is cleared.
Detection of Legacy PDs
Proprietary PDs that predate the original IEEE 802.3af
standard are commonly referred to today as legacy PDs.
One type of legacy PD uses a large common-mode capaci-
tance (>10μF) as the detection signature. Note that PDs in
this range of capacitance are defined as invalid, so a PSE
that powers legacy PDs is noncompliant with the IEEE
standard. The LTC4291-1/LTC4292 can be configured to
detect this type of legacy PD. Legacy detection is disabled
by default, but can be manually enabled on a per-port
basis. When enabled, the port will report Detect Good
when it sees either a valid IEEE PD or a high-capacitance
legacy PD. With legacy mode disabled, only valid IEEE
PDs will be recognized.
If a nonstandard PD presents an invalid detection signa-
ture not included by legacy detection, the LTC4291-1/
LTC4292 may be configured to perform classification and/
or apply power regardless of detection result. To accom-
plish this, the LTC4291-1/LTC4292 introduces per-port
Force Power and Class Event overrides. These overrides
intentionally defeat compliance checks. See the LTC4291
Software Programming documentation for details.
LTC4291-1/LTC4292
22
Rev 0
For more information www.analog.com
APPLICATIONS INFORMATION
Table8. Type 1 and Type 2 PD Classification Values
CLASS RESULT
Class 0 No Class Signature Present; Treat Like Class 3
Class 1 3.84W
Class 2 6.49W
Class 3 13W
Class 4 25.5W (Type 2)
If classification is enabled, the PSE will classify the PD
immediately after a successful detection cycle. The PSE
measures the PD classification signature by applying
VCLASS to the port via OUTnM and measuring the result-
ing current; it then reports the discovered class in the Port
Status or Channel Status register, as appropriate. If the
LTC4291-1/LTC4292 is in auto mode, it will additionally
use the classification result to set the I
CUT-2P
, I
LIM-2P
, and
PCUT-4P thresholds.
Classification is disabled for a port when the LTC4291-1/
LTC4292 is initially powered up with the AUTO pin low,
when the port is in shutdown mode, or when the corre-
sponding Class Enable bit is cleared.
LLDP Classification
Introduced in 802.3at and extended by 802.3bt, the PoE
specification defines a Link Layer Discovery Protocol
(LLDP) method of classification. The LLDP method adds
extra fields to the Ethernet LLDP data protocol.
Although the LTC4291-1/LTC4292 is compatible with this
classification method, it cannot perform LLDP classifica-
tion directly since it does not have access to the data path.
LLDP classification allows the host to perform LLDP com-
munication with the PD and update the PD’s power allo-
cation. The LTC4291-1/LTC4292 supports changing the
ILIM-2P, ICUT-2P, and PCUT-4P levels dynamically, enabling
system-level LLDP support.
802.3at 2-Event Classification
In 802.3at, 802.3af classification is named Type 1 clas-
sification. The 802.3at standard introduces an extension
of Type 1 classification: Type 2 (2-event) classification.
Type 2 PSEs are required to perform classification.
Classification
802.3af Classification
A PD may optionally present a classification signature
to the PSE to indicate the maximum power it will draw
while operating. The IEEE specification defines this sig-
nature as a constant current draw when the PSE port
voltage is in the VCLASS range (between 15.5V and 20.5V)
as shown in Figure15, with the current level indicating
one of five possible PD signatures. Figure14 shows a
typical PD load line, starting with the slope of the 25k
signature resistor below 10V, then transitioning to the
classification signature current (in this case, Class 3)
in the VCLASS range. Table8 shows the possible clas-
sification values.
Figure14. PD Classification
VOLTAGE (VCLASS)
0
CURRENT (mA)
60
50
40
30
20
10
05 10 15 20
42911 F14
25
TYPICAL
CLASS 3
PD LOAD
LINE
48mA
33mA
PSE LOAD LINE
23mA
14.5mA
6.5mA
CLASS 4
CLASS 2
CLASS 1
CLASS 0
CLASS 3
OVER
CURRENT
Figure15. Type 1 PSE, 1-Event Class Sequence
42911 F15
V
OUTnM
VCLASSMIN
VMARKMAX
VSIGMIN
VRESET
DETECT
CLASS
POWER ON
LTC4291-1/LTC4292
23
Rev 0
For more information www.analog.com
APPLICATIONS INFORMATION
A Type 2 PD requesting 25.5W presents class signature4
during all class events. If a Type 2 PSE with 25.5W of
available power sees class signature 4 during the first
class event, it forces the PD to VMARK (9V typical), pauses
briefly, and issues a second class event as shown in
Figure16. The second class event informs the PD that
the PSE has allocated 25.5W.
Figure16. Type 2 PSE, 2-Event Class Sequence
42911 F16
V
OUTnM
VCLASSMIN
VMARKMAX
VSIGMIN
VRESET
DETECT
1ST
CLASS
1ST
MARK
2ND
MARK
2ND
CLASS
POWER ON
Note that the second classification event only runs if
required by the IEEE classification procedure. For exam-
ple, a single-signature Class 0 to 3 PD will only be issued
a single class event in all situations.
The concept of demotion is introduced in 802.3at. A
Type2 PD may be connected to a PSE only capable of
delivering 13W, perhaps due to power management limi-
tations. In this case, the PSE will perform a single classi-
fication event as shown in Figure15, and note that 25.5W
is requested. Due to the limited power availability, the
PSE will not issue a second event and proceeds directly
to power on the PD. The presence of a single class event
informs the Type 2 PD it has been demoted to 13W. If
demoted, the PD is subject to power limitations and may
operate in a reduced power mode.
802.3bt Multi-Event Classification
The LTC4291-1/LTC4292 implements Type 3 and Type 4
classification, as required by 802.3bt. Type 3 and Type 4
classification are backwards-compatible with Type 1 and
Type 2 PDs.
While Type 2 (802.3at) classification extends Type 1
(802.3af) classification, Type 3 and Type 4 (802.3bt)
classification supersede Type 1 and Type 2 classifica-
tion. Type 1 and Type 2 classification are described in
the preceding sections as a historical reference and to
define common terminology such as power demotion,
class events, mark events, and electrical parameters.
IEEE 802.3bt defines eight PD Classes for single-signature
PDs and five PD Classes for dual-signature PDs, as shown
in Table9.
Classification treatment of single-signature and dual-
signature PDs differs. The following sections explain the
Physical Layer classification of each PD configuration
separately.
Table9. Type 3 and Type 4 PD Classifications by PDConfiguration
SINGLE-SIGNATURE PDs DUAL-SIGNATURE PDs
CLASS
PD AVAILABLE
POWER CLASS
CHANNEL AVAILABLE
POWER*
Class 1 3.84W Class 1 3.84W
Class 2 6.49W Class 2 6.49W
Class 3 13W Class 3 13W
Class 4 25.5W Class 4 25.5W
Class 5 40W Class 5 35.6W
Class 6 51W
Class 7 62W
Class 8 71.3W
*Dual-signature PD total available power is the sum of both channels
available power. Class signatures may differ between channels of a port,
e.g., Class 3 + Class 4 = 13W + 25.5W = 38.5W.
802.3bt Classification of Single-Signature PDs
Type 3 and Type 4 PSEs issue a single classification event
(see Figure17) to Class 0 through 3 single-signature (SS)
PDs. A Class 0 through 3 SS PD presents its class signa-
ture to the PSE and is then powered on if sufficient power
is available. Power limited 802.3bt PSEs may also issue a
single classification event to Class 4 and higher SS PDs in
order to demote those PDs to 13W. See Figure17.
Type 3 and 4 PSEs present three classification events
to Class 4 SS PDs (see Figure18) if sufficient power is
available. Class 4 SS PDs present class signature 4 on
all events. The third event differentiates a Class 4 SS PD
from a higher Class SS PD. Power limited IEEE 802.3bt
LTC4291-1/LTC4292
24
Rev 0
For more information www.analog.com
APPLICATIONS INFORMATION
802.3bt Classification of Dual-Signature PDs
Classification and power allocations to each pairset of a
dual-signature (DS) PD are fully independent. For exam-
ple, a DS PD may request Class 1 (3.84W) on one pairset
and a Class 4 (25.5W) on the second pairset for a total
PD requested power of 29.3W. As such, all classification
is performed to the pairset entity as opposed to the PD.
The terms should be considered interchangeable for the
remainder of this section.
Type 3 and Type 4 PSEs issue three classification events
(see Figure18) to all Class 1 through 4 DS PDs.
Power limited Type 3 and Type 4 PSEs may issue a class
reset to Class 4 and 5 DS PDs in order to demote those
PDs to 13W (see Understanding 4PID section).
PSEs may issue three classification events to Class 5 and
higher SS PDs in order to demote those PDs to 25.5W.
Type 3 and 4 PSEs present four classification events (see
Figure19) to Class 5 and 6 SS PDs if sufficient power is
available. Class 5 and 6 SS PDs present class signature
4 on the first two events. Class 5 and 6 SS PDs present
class signature 0 or 1, respectively, on the subsequent
events. Power limited PSEs may issue four events to Class
7 and 8 SS PDs in order to demote those PDs to 51W.
Type 4 PSEs present five classification events (see
Figure20) to Class 7 and 8 SS PDs if sufficient power
is available. Class 7 and 8 PDs present class signature
4 on the first two events. Class 7 and 8 SS PDs present
classsignature 2 or 3, respectively, on the subsequent
events.
Figure17. Type 3 or 4 PSE, 1-Event Class Sequence
42911 F17
V
OUTnM
VCLASSMIN
VMARKMAX
VSIGMIN
VRESET
DETECT
1ST
CLASS
1ST
MARK
POWER ON
Figure18. Type 3 or 4 PSE, 3-Event Class Sequence
42911 F18
V
OUTnM
VCLASSMIN
VMARKMAX
VSIGMIN
VRESET
DETECT
1ST
CLASS
1ST
MARK
2ND
MARK
3RD
MARK
2ND
CLASS
3RD
CLASS
POWER ON
Figure19. Type 3 or 4 PSE, 4-Event Class Sequence
42911 F19
V
OUTnM
VCLASSMIN
VMARKMAX
VSIGMIN
VRESET
DETECT
1ST
CLASS
1ST
MARK
2ND
MARK
3RD
MARK
4TH
MARK
2ND
CLASS
3RD
CLASS
4TH
CLASS
POWER ON
42911 F20
V
OUTnM
VCLASSMIN
VMARKMAX
VSIGMIN
VRESET
DETECT
1ST
CLASS
1ST
MARK
2ND
MARK
3RD
MARK
4TH
MARK
5TH
MARK
2ND
CLASS
3RD
CLASS
4TH
CLASS
5TH
CLASS
POWER ON
Figure20. Type 4 PSE, 5-Event Class Sequence
LTC4291-1/LTC4292
25
Rev 0
For more information www.analog.com
APPLICATIONS INFORMATION
Power limited Type 3 and Type 4 PSEs may issue only
three events to Class 5 DS PDs in order to demote those
PDs to 25.5W.
Type 4 PSEs present four classification events (see
Figure19) to Class 5 DS PDs if sufficient power is avail-
able. Class 5 DS PDs present class signature 4 on the first
two events and class signature 3 on subsequent events.
Understanding 4PID
4-pair identification (4PID) refers to a set of conditions for
determining whether a PD is capable of receiving power
over both pairsets simultaneously.
The PSE may apply 4-pair power if the PD presents a valid
detection signature on both pairsets and one or more of
the following conditions are met:
• The PD is single-signature configuration.
• The PD is Type 3 or Type 4.
• The PD presents a valid detection signature on an
unpowered pairset when power is applied over the
other pairset.
Although PD signature configuration is not defined for
Type 1 and Type 2 PDs, a Type 3 or Type 4 PSE may
identify such a PD as single-signature or dual-signature.
Single-signature PDs may receive 4-pair power regardless
of PD Type. Certain pre-802.3bt “dual-signature” PDs may
be damaged by 4-pair power.
Type 3 and Type 4 dual-signature PDs are required to
present a unique classification response from pre-802.3bt
dual-signature PDs of the same Class. For dual-signature
PDs, the LTC4291-1/LTC4292 determines and reports
both PD Class and PD Type during classification.
Type 3, Type 4, and pre-802.3bt Class 1 through Class4
dual-signature PDs present class signature 1 through 4,
respectively, during the first and second class events.
Type 3 and Type 4 dual-signature PDs present class sig-
nature 0 for all subsequent class events. Thus, a PSE can
conclusively determine PD Type by the third class event
for all dual-signature PDs.
An issue arises when a Class 4 or Class 5 dual-signature
PD is connected. In order to determine PD Type, three
class events are issued. Based on the class event count,
the PD has been allocated 25.5W. If the PSE desires to
both determine PD Type (3 events) and demote to 13W
(1 event), a class reset event must be issued as shown
in Figure21.
Figure21. Class Reset Event Between Class Sequences
42911 F21
V
OUTnM
VCLASSMIN
VMARKMAX
VRESET
DETECT
1ST
CLASS
1ST
MARK
1ST
MARK
2ND
MARK
2ND
CLASS
3RD
CLASS
1ST
CLASS
POWER ON
CLASS
RESET
A class reset event is issued by maintaining the channel
voltage below 2.8V for at least tCLASS_RESET. The subse-
quent single event classification is used to demote the
PD to13W.
In auto mode the 4PID information and the state of
4PVALID are used to automatically determine the number
of powered channels.
LLDP signaling may, at some time later, determine the
pre-bt PD is actually four pair capable and the LTC4291-1/
LTC4292 may be instructed to deliver 4-pair power.
Invalid Multi-Event Classification Combinations
The 802.3bt specification defines a set of valid class sig-
nature combinations. All PDs return the same classifica-
tion signature on the first two class events. Type 3 and 4
PDs modify the classification signature on all subsequent
class events. For example, a single-signature Class 5 PD
will respond to the class events 1, 2, 3, and 4 with a class
signature of 4, 4, 0, and 0, respectively.
Any individual class signature that exceeds the class cur-
rent limit is flagged as an invalid classification result. Any
sequence of class signatures that does not represent a
legal sequence based on PD configuration will likewise
be flagged as an invalid classification result.
LTC4291-1/LTC4292
26
Rev 0
For more information www.analog.com
APPLICATIONS INFORMATION
Auto Mode Maximum PSE Power
In auto mode the LTC4291-1/LTC4292 automatically
detects, classifies and powers all connected valid PDs.
In order to do this, the PSE must be configured for its
maximum power allocation. The maximum power alloca-
tion is a reflection of the power supply and power path
capability. The PWRMD pins must be set appropriately
to reflect the PSE system’s power delivery capabilities.
These pins are sampled at reset.
Table10. Auto Mode Maximum Delivered Power Capabilities
PWRMD1 PWRMD0
MAX PORT POWER
(SINGLE-SIGNATURE)
MAX PAIRSET POWER
(DUAL-SIGNATURE)
0 0 40W 13W
0 1 51W 25.5W
1 0 62W 25.5W
1 1 71.3W 35.6W
POWER CONTROL
The primary function of the LTC4291-1/LTC4292 is to con-
trol power delivery to the PSE port. With the LTC4291-1/
LTC4292, a PSE port is composed of two power chan-
nels; each power channel controls power delivery over a
pairset. Within this section, power delivery and control
are defined per-channel.
The LTC4291-1/LTC4292 delivers power by controlling
the gate drive voltage of an external power MOSFET while
monitoring the current (through an external sense resis-
tor) and the output voltage (across the OUT pin).
The LTC4291-1/LTC4292 connects the V
EE
power sup
-
ply to the PSE port in a controlled manner, meeting the
power demands of the PD while minimizing power dis-
sipation in the external MOSFET and disturbances to the
VEE backplane.
Inrush Control
When commanded to apply power to a port, the
LTC4291-1/LTC4292 ramps up the GATE pin of one or
both channels (as commanded), raising the external
MOSFET gate voltage in a controlled manner.
During a typical inrush, the MOSFET gate voltage will rise
until the external MOSFET is fully enhanced or the channel
reaches the inrush current limit (IINRUSH-2P). IINRUSH-2P is
set automatically by the PSE. When the PSE is applying
4-pair power to a single-signature PD assigned Class0
to Class4, IINRUSH-2P is 212.5mA (typical) per channel
(LIMn = 08h). Otherwise, IINRUSH-2P is 425mA (typical)
per channel (LIMn = 80h).
The GATE pin will be servoed if channel current exceeds
IINRUSH-2P, actively limiting current to IINRUSH-2P. When
the GATE pin is not being servoed, the final VGS is 12V
(typical).
During inrush, each powered channel runs a timer (tSTART).
Each powered channel stays in inrush until t
START
expires.
When t
START
expires, the PSE inspects channel voltage
and current. When the PSE is applying power to a PD,
inrush is successful if the channel(s) are drawing current
below IINRUSH-2P, as appropriate per the PD configuration
and Class.
If inrush is not successful, power is removed and the
corresponding tSTART faults are set. Otherwise, the port
or channel, as appropriate, advances to power on and
the programmed current limiting thresholds are used as
described in the Current Limit section.
Port Power Policing
The power policing threshold (PCUT-4P) is monitored on a
per-port basis, up to 128W in 0.5W increments (typical).
When the total output power over a one second moving
average exceeds the specified threshold, power will be
removed from the port and the corresponding tCUT faults
are set.
In particular, the port policing feature may be used to
ensure delivery of PD Class power while staying below
100W Limited Power Source (LPS) requirements.
Current Cutoff and Limit
Each LTC4291-1/LTC4292 port includes two current lim-
iting thresholds (ICUT-2P and ILIM-2P), each with a cor-
responding timer (tCUT and tLIM). Setting the ICUT-2P and
ILIM-2P thresholds depends on several factors: the PD
LTC4291-1/LTC4292
27
Rev 0
For more information www.analog.com
APPLICATIONS INFORMATION
assigned Class, the main supply voltage (VEE), the PSE
Type (Type 3 or 4), and the MOSFET SOA.
A single set of programmable port ICUT-2P and ILIM-2P
thresholds is shared by both channels. The thresholds
should be set based on the classification result as shown
in Table4 and Table5. For a dual-signature PD assigned
unequal Classes, the highest Class is used to set the
thresholds. For example, a dual-signature PD assigned
Class 1 and Class 5 would enforce ICUT-2P and ILIM-2P
based on Class 5.
Per the IEEE specification, the LTC4291-1/LTC4292 will
allow the channel current to exceed ICUT-2P for a limited
period of time before removing power from the port, or
channel, as appropriate whereas it will actively control
the MOSFET gate drive to keep the channel current below
ILIM-2P. The channel does not take any action to limit the
current when only the ICUT-2P threshold is exceeded, but
does start the tCUT timer. If the current drops below the
ICUT-2P threshold before its timer expires, the tCUT timer
counts back down, but at 1/16 the rate that it counts up. If
the tCUT timer reaches 59ms (typical), the port or channel,
as appropriate, is turned off and the corresponding tCUT
faults are set. This allows the channel to tolerate intermit-
tent overload signals with duty cycles below about 6%;
longer duty cycle overloads will remove power from the
port or channel, as appropriate.
The ILIM-2P current limiting circuit is always enabled and
actively limiting channel current. The tLIM timer is enabled
only when the tLIM Timer Configuration field is set to a
non-zero value. This allows tLIM to be set to a shorter value
than tCUT to provide more aggressive MOSFET protection
and turn off a port before MOSFET damage can occur. The
tLIM timer starts when the ILIM-2P threshold is exceeded.
When the t
LIM
timer reaches 1.7ms (typical) times the
value in the tLIM Timer Configuration field, the port or
channel, as appropriate, is turned off and the appropriate
tLIM faults are set. When the tLIM Timer Configuration field
is set to 0, tLIM behaviors are tracked by the tCUT timer,
which counts up during both ILIM-2P and ICUT-2P events.
To maintain IEEE compliance, the programmed tLIM Timer
Configuration field should be set as shown in the LTC4291
Software Programming documentation.
ICUT-2P is typically set to a lower value than ILIM-2P,
allowing the port to tolerate minor faults without current
limiting.
To maintain IEEE compliance, the programmed I
LIM-2P
should be set as shown in Tables 4 and 5. The pro-
grammed ILIM-2P setting is automatically applied follow-
ing the completion of inrush.
The tCUT and tLIM timers are maintained on a per channel
basis. When a tCUT or tLIM fault occurs a determination is
made to turn off one or both channels. See the Port Fault
vs Channel Fault section for details.
ILIM-2P Foldback
The LTC4291-1/LTC4292 ILIM-2P threshold is imple-
mented as a two-stage foldback circuit that reduces the
channel current if the channel voltage falls below the nor-
mal operating voltage. This keeps MOSFET power dissipa-
tion at safe levels. Current limit and foldback behavior are
programmable on a per-port basis.
The LTC4291-1/LTC4292 supports current levels well
beyond the maximum values in the 802.3bt specifica-
tion. Large values of ILIM-2P may require larger external
MOSFETs, additional heat sinking, and setting the t
LIM
Timer Configuration field to a lower value.
MOSFET Fault Detection
LTC4291-1/LTC4292 PSE ports are designed to tolerate
significant levels of abuse, but in extreme cases it is pos-
sible for an external MOSFET to be damaged. A failed
MOSFET may short source to drain, which will make the
port appear to be on when it should be off; this condition
may also cause the sense resistor to fuse open, turning
off the port but causing SENSE to rise to an abnormally
high voltage. A failed MOSFET may also short from gate to
drain, causing GATE to rise to an abnormally high voltage.
OUT, SENSE and GATE are designed to tolerate up to 80V
faults without damage.
LTC4291-1/LTC4292
28
Rev 0
For more information www.analog.com
APPLICATIONS INFORMATION
If the LTC4291-1/LTC4292 sees a power good condition
on either channel of an unpowered port (neither channel
powered), it disables all port functionality, reduces the
gate drive pull-down current for the port and reports a FET
Bad fault. This is typically a permanent fault, but the host
can attempt to recover by resetting the port, or by reset-
ting the entire chip if a port reset fails to clear the fault.
If the MOSFET is in fact bad, the fault will quickly return,
and the port will disable itself again. The remaining ports
of the LTC4291-1/LTC4292 are unaffected.
An open or missing MOSFET will not trigger a FET Bad
fault, but will cause a tSTART fault if the LTC4291-1/
LTC4292 attempts to turn on the port.
Disconnect
The LTC4291-1/LTC4292 monitors powered channels to
ensure the PD continues to draw the minimum speci-
fied current. The I
HOLD-2P
threshold, monitored as the
VHOLD-2P threshold across the 0.15Ω sense resistor, is
used to determine if a PD has been disconnected.
The IHOLD-2P threshold is set automatically in auto mode
and is set by the user in semi-auto and manual modes.
When powering a single-signature PD assigned Class 0 to
Class 4 over a single channel, set the IHOLD-2P threshold
to 7.5mA (typ) via the Disconnect Configuration bit. In all
other cases, set the IHOLD-2P threshold to 3.5mA (typ).
A disconnect timer (tDIS) counts up whenever channel
current is below the IHOLD-2P threshold, indicating that the
PD has been disconnected. If the appropriate tDIS timer(s)
expire, the port or channel (Table11) will be turned off
and the corresponding tDIS faults are set. If the current
increases above IHOLD-2P before the tDIS timer expires, the
timer(s) reset. As long as the PD exceeds the minimum
current level before tDIS expires, it will remain powered.
Although not recommended, the DC disconnect fea-
ture can be disabled by clearing the corresponding DC
Disconnect Enable bits. Disabling the DC disconnect fea-
ture forces the LTC4291-1/LTC4292 out of compliance
with the IEEE standard. A powered port will stay powered
after the PD is removed; the still-powered port may be
subsequently connected to a non-PoE data device, poten-
tially causing damage.
The LTC4291-1/LTC4292 does not include AC discon-
nect circuitry. AC disconnect is not a supported feature
of 802.3bt.
Port Fault vs Channel Fault
The tCUT, tLIM and tDIS timers are maintained on a per-
channel basis. When any channel timer expires, a deter-
mination is made to remove power from both, one, or
neither channel of the port.
Optional behavior is allowed by the 802.3bt standard
when faults occur on single-signature PDs. This option
allows a single-signature PD to remain powered on pair-
setX, even if a fault occurs on pairset Y. The FAULT2Pn bit,
when set, enables this optional behavior. This behavior is
not recommended for normal operation, as a fault in the
PD or cabling is indicative of imminent PD or cable failure.
Table11. Channel Fault Effect on Port/Channel State
PD CON-
FIGURATION FAULT2Pn
FAULT RESULT:
TURN OFF PORT OR CHANNEL
tCUT** tLIM tDIS
Single 0 Port Port Port*
1 Channel Channel
Dual x Channel Channel Channel
*If tDIS Expires on Both Channels
**Port power policing (PCUT-4P) raises a tCUT event. When enabled, port
power policing removes power from the port regardless of FAULT2Pn
configuration.
Fault Telemetry
As discussed in the preceding sections, faults may occur
on one or both channels, resulting in power removal on
one or both channels. The fault event registers have tra-
ditionally been implemented at the port level. In order to
trace faults to the offending channel, a second layer of fault
registers have been added to the LTC4291-1/LTC4292:
the Fault Telemetry registers. See the LTC4291 Software
Programming documentation for additional information.
LTC4291-1/LTC4292
29
Rev 0
For more information www.analog.com
Autoclass
IEEE 802.3bt introduces a new optional feature, Autoclass.
Autoclass enables the PSE to reclaim power budget from
single-signature PDs requesting more power than needed
under worst-case operating conditions. 802.3bt does not
specify Autoclass for dual-signature PDs. The LTC4291-1/
LTC4292 fully supports Autoclass.
Prior versions of the 802.3 PoE standard specify mini-
mum PSE output power for worst-case IR drop across
the Ethernet cable and minimum PSE output voltage.
However, a method for the PSE to reclaim over-allocated
power is not specified. When a shorter Ethernet cable is
used, or when the guaranteed PSE output voltage is above
the specified minimum, the specified minimum PSE out-
put power substantially over-allocates power to the PD.
An example PoE system is shown in two versions.
Figure22 shows a 100W four port PSE servicing three
25.5W PDs over 100m cables. Such a system requires
the PSE to allocate 25.5W per PD and a further 4.5W for
each 100m cable’s IR drop.
The total power allocation is:
3 Ports • (4.5W + 25.5W) = 90W
If an additional 13W PD is plugged into the fourth PSE
port, only 10W is available and the PD cannot be powered.
APPLICATIONS INFORMATION
Figure22. 100W PoE System with 100m Cables
13W PD
25.5W PD
25.5W PD
25.5W PD
100m CABLE
4.5W IR DROP
100m CABLE
4.5W IR DROP
100m CABLE
4.5W IR DROP
100W PSE
42911 F22
Figure23 shows a 100W four port PSE servicing three
25.5W PDs over 10m cables. Such a system requires the
PSE to allocate 25.5W per PD and a further ~0.5W for
each 10m cable’s IR drop.
Without Autoclass, the total power allocation is:
3 ports • (4.5W + 25.5W) = 90W
If an additional 13W PD is plugged into the fourth PSE
port, only 10W is available and the PD cannot be powered
even though the IR drop is much less than in the prior
example.
Assuming the system in Figure23 is Autoclass-enabled,
the recovered power budget can be used to power addi-
tional ports. During classification, the PSE observes the
PD’s Autoclass request. After power on is completed, the
PD draws its maximum power while the PSE performs
an Autoclass measurement, as specified by 802.3bt. The
PSE in Figure23 will measure and report 26W of power
consumption for each of the three 25.5W PDs. This result
allows the host to revise the PSE available power budget.
With Autoclass, the total power allocation for Figure23 is:
3 Ports • 26W (Measured) = 78W
If an additional 13W PD is plugged into the fourth PSE
port, a full 22W is now available and the PD can be suc-
cessfully powered.
Figure23. 100W PoE System with 10m Cables
13W PD
25.5W PD
25.5W PD
25.5W PD
10m CABLE
~0.5W IR DROP
10m CABLE
~0.5W IR DROP
10m CABLE
~0.5W IR DROP
100W PSE
42911 F23
LTC4291-1/LTC4292
30
Rev 0
For more information www.analog.com
Autoclass Negotiation Procedure
A PSE may receive an Autoclass request from the PD by
Physical Layer classification or LLDP (by way of the PSE
host). For Physical Layer requests, the Autoclass negotia-
tion procedure listed below is shown in Figure24.
1. PSE begins issuing the long first class event. The PD
class signature is allowed to settle during this time.
2. The PD responds with a class signature correspond-
ing to its Class. The class signature during this time
period is unrelated to the Autoclass negotiation.
3. The PSE measures the PD class signature during this
time and uses the result for the normal Multi-event
Classification.
4. The PD continues presenting its class signature.
5. The PSE continues the long class event and does not
measure the class signature current at this time.
6. The PD, if requesting Autoclass, transitions to class
signature 0. If the PD is not requesting Autoclass it
continues presenting its class signature.
APPLICATIONS INFORMATION
7. The PSE measures the Autoclass response of the PD.
If class signature 0 is measured, the PD is requesting
Autoclass. When the measurement is complete the
first class event is ended.
8. The PD continues holding the class signature selected
in step 6 until the end of the first class event.
Following the Autoclass negotiation procedure, PSE and
PD continue Physical Layer classification and power up
as normal. Regardless of Autoclass, the PD is required
to operate below the negotiated power allocation corre-
sponding to PD assigned Class.
Autoclass Measurement Procedure
Autoclass measurements may be requested by the PD
through Physical Layer classification or, following power
on, through LLDP. Although the LTC4291-1/LTC4292 is
compatible with LLDP-based Autoclass requests, it can-
not receive LLDP Autoclass requests directly since it does
not have access to the data path.
If the PSE is commanded to perform an Autoclass mea-
surement following a Physical Layer request, the mea-
surement typically begins tAUTO_PSE1 (1.5s typical) after
port inrush is successfully completed. For LLDP-based
Autoclass requests, the measurement begins immediately.
The Autoclass measurement period is tAUTO_PSE2 – tAUTO_
PSE1 (1.8s typical) using a sliding window of tAUTO_WINDOW
(0.2s typical). During the Autoclass measurement period,
the PSE continuously monitors IPORT and VEE, calculat-
ing maximum average power. Following the Autoclass
measurement period, the Autoclass measurements are
reported in the Port Parametric registers.
See the LTC4291 Software Programming documen-
tation for details on enabling Autoclass, the status of
the Autoclass negotiation, reading Autoclass measure-
ment results and dynamically requesting an Autoclass
measurement.
Port Current Readback
The LTC4291-1/LTC4292 measures the current at each
power channel with per-channel A/D converters. The total
port current (sum of both channels) is reported. Port
Figure24. Autoclass Negotiation, Voltage and Current
3 5 71
4 6 82
tACS_MAX (87.5ms)
tACS_MIN (75.5ms)
tCLASS_ACS_MIN
tCLASS_PD_MAX (5ms)
tCLASS_MIN
tCLASS_LCE_MAX
tLCE_MIN
t
LCE_MAX
V
OUTnM
VCLASS
VMARK
IOUTnM
CLASS_SIG_4
CLASS_SIG_0
t
t
42911 F24
LTC4291-1/LTC4292
31
Rev 0
For more information www.analog.com
current is only valid when at least one power channel of a
port is on and reads zero at all other times. The converter
has two modes:
• 100ms mode: Samples are taken continuously and
the measured value is updated every 100ms
• 1s mode: Samples are taken continuously; a moving
1second average is updated every 100ms
VEE Readback
The LTC4291-1/LTC4292 continuously measures the
V
EE
voltage with a dedicated A/D converter. This global
VEE measurement is fully synchronized to all port current
measurements.
Port Power Readback
The LTC4291-1/LTC4292 provides fully continuous and
synchronized port power measurements. The LTC4291-1/
LTC4292 calculates the port power by multiplying the port
current and VEE measurements.
PPORT = IPORT × VEE
The Port Power measurements replace the Port Voltage
measurements provided in prior ADI PSEs. Port voltage
may be characterized and extrapolated from the VEE mea-
surement in a user-defined manner.
Masked Shutdown
The LTC4291-1/LTC4292 provides a low latency port
shedding feature to quickly reduce the system load when
required. By allowing a pre-determined set of ports to be
turned off, the current on an overloaded main power supply
can be reduced rapidly while keeping high priority devices
powered. Each port can be configured to high or low prior-
ity; all low-priority ports will shut down within 6.5μs after
MSD is pulled low, high priority ports will remain powered.
If a port is turned off via MSD, the corresponding Detection
and Classification Enable bits are cleared, so the port will
remain off until the host explicitly re-enables detection.
In the LTC4291-1/LTC4292 chipset, the active level of
MSD is register configurable as active high or low. The
default behavior is active low.
APPLICATIONS INFORMATION
General Purpose IO
Two general purpose IO pins, GP0 and GP1 are available
on the LTC4291-1. These fully bidirectional IO pins use
3.3V CMOS logic.
Code Download
The LT C4291-1 includes a default firmware image,
enabling 802.3bt-compliant operation with no user inter-
vention required. In addition, the LT C4291-1 firmware is
field-upgradable by downloading and executing firmware
images. Firmware images are volatile and must be re-
downloaded after each VDD power cycle, but will remain
valid during reset and VEE power events.
The LT C4291-1 is intended for use with Analog Devices
firmware images only. Contact Analog Devices for code
download procedures and firmware images.
SERIAL DIGITAL INTERFACE
Overview
The LTC4291-1 communicates with the host using a
standard SMBus/I2C 2-wire interface. The LTC4291-1
is a slave-only device, and communicates with the host
master using standard SMBus protocols. Interrupts
are signaled to the host via INT. The Timing Diagrams
(Figure5 through Figure9) show typical communication
waveforms and their timing relationships. More infor-
mation about the SMBus data protocols can be found at
www.smbus.org.
The LTC4291-1 requires both the V
DD
and V
EE
supply rails
to be present for the serial interface to function.
Bus Addressing
The LTC4291-1’s primary 7-bit serial bus address is
010A3A2A1A0b, with the lower four bits set by AD3 – AD0;
this allows up to 16 LTC4291-1s on a single bus. Sixteen
LTC4291-1s are equivalent to 64 ports. All LTC4291-1s
also respond to the broadcast address 0110000b, allow-
ing the host to write the same command (typically
configuration commands) to multiple LTC4291-1s in a
singletransaction.
LTC4291-1/LTC4292
32
Rev 0
For more information www.analog.com
If the LTC4291-1 is asserting INT, it will also respond to
the alert response address (0001100b) per the SMBus
specification.
Each LTC4291-1/LTC4292 is logically composed of a
single four port quad, packed into a single I2C address.
Interrupts and SMBAlert
Most port events can be configured to trigger an inter-
rupt, asserting INT and alerting the host to the event. This
removes the need for the host to poll the LTC4291-1,
minimizing serial bus traffic and conserving host CPU
cycles. Multiple LTC4291-1s can share a common INT
line, with the host using the SMBAlert protocol (ARA) to
determine which LTC4291-1 caused an interrupt.
Register Description
For information on serial bus usage and device con-
figuration and status, refer to the LTC4291 Software
Programming documentation. Contact Analog Devices
to request this document.
ISOLATION REQUIREMENTS
IEEE 802.3 Ethernet specifications require that network
segments (including PoE circuitry) be electrically isolated
from the chassis ground of each network interface device.
However, network segments are not required to be iso-
lated from each other, provided that the segments are
connected to devices residing within a single building on
a single power distribution system.
For simple devices, such as small PoE switches, the isola-
tion requirement can be met by using an isolated main
power supply for the entire device. This strategy can be
used if the device has no electrically conducting ports
other than twisted-pair Ethernet. In this case, the SDAIN
and SDAOUT pins can be tied together and will act as a
standard I2C/SMBus SDA pin.
If the device is part of a larger system, contains additional
external non-Ethernet ports, or must be referenced to pro-
tective ground for some other reason, the PoE subsystem
must be electrically isolated from the rest of the system.
The LTC4291-1/LTC4292 chipset simplifies PSE isolation
by allowing the LTC4291-1 chip to reside on the non-
isolated side. There it can receive power from the main
logic supply and connect directly to the I2C/SMBus bus.
Isolation between the LTC4291-1 and LTC4292 is imple-
mented using a proprietary transformer-based commu-
nication protocol. Additional details are provided in the
Serial Bus Isolation section of this data sheet.
EXTERNAL COMPONENT SELECTION
Power Supplies
The LTC4291-1/LTC4292 requires two supply voltages to
operate. VDD requires 3.3V (nominally) relative to DGND.
VEE requires a negative voltage of between –51V to –57V
for Type 3 PSEs, or –53V to –57V for Type 4 PSEs, rela-
tive to AGNDP.
Digital Power Supply
VDD provides digital power for the LTC4291-1 processor.
A ceramic decoupling cap of at least 0.1μF should be
placed from VDD to DGND, as close as practical to each
LTC4291-1. A 1.8V core voltage supply is generated inter-
nally and requires a 1µF ceramic decoupling cap between
the CAP1 pin and DGND.
In the LTC4291-1, VDD should be delivered by the host
controller’s non-isolated 3.3V supply. To maintain required
isolation, LTC4292 AGNDP and LTC4291-1 DGND must
not be connected in any way.
Main PoE Power Supply
VEE is the main isolated PoE supply that provides power
to the PDs. Because it supplies a relatively large amount
of power and is subject to significant current transients,
it requires more design care than a simple logic supply.
For minimum IR loss and best system efficiency, set VEE
near maximum amplitude (57V), leaving enough margin
to account for transient over or undershoot, temperature
drift, and the line regulation specifications of the particular
power supply used.
APPLICATIONS INFORMATION
LTC4291-1/LTC4292
33
Rev 0
For more information www.analog.com
Bypass capacitance between AGNDP and VEE is very
important for reliable operation. If a short circuit occurs
at one of the output ports it can take as long as 1μs for
the LTC4292 to begin regulating the current. During this
time the current is limited only by the small impedances
in the circuit; a high current spike typically occurs, caus-
ing a voltage transient on the VEE supply and possibly
causing the LTC4291-1/LTC4292 to reset due to a UVLO
fault. A 1μF, 100V X7R capacitor placed near the VEE and
AGNDP pins along with an electrolytic bulk capacitor of at
least 47µF across the supply is recommended to minimize
spurious resets.
Serial Bus Isolation
The LTC4291-1/LTC4292 chipset uses transformers to
isolate the LTC4291-1 from the LTC4292 (see Figure25).
In this case, the SDAIN and SDAOUT pins can be shorted
to each other and tied directly to the I2C/SMBus bus.
The transformers should be 10BASE-T or 10/100BASE-T
with a 1:1 turns ratio. It is optimal that the selected
APPLICATIONS INFORMATION
Figure25. LTC4291-1/LTC4292 Proprietary Isolation
••
3.3V
3.3V
VEE
100Ω
100Ω
100Ω
100Ω
••
3.3V VEE
100Ω
100Ω
100Ω
100Ω
GP0
GP1
4PVALID
RESET
MSD
INT
AUTO
SCL
AD0
AD1
AD2
AD3
DGND
DND
DPD
CND
CPD
DNA SENSEnA
GATEnA
OUTnA
LTC4292
DPA
CNA
CPA
AGNDP
42911 F25
SDAIN
SDAOUT
LTC4291-1
NO ISOLATION
REQUIRED ON
I2C INTERFACE
VDD
SENSEnB
GATEnB
OUTnB
PWRMD0
PWRMD1
AGNDP
10Ω
ISOLATION
PORTn
2nF 2kV
VEE
V
EE
transformers do not have common-mode chokes. These
transformers typically provide 1500V of isolation between
the LTC4291-1 and the LTC4292. For proper operation,
strict layout guidelines must be met.
External MOSFET
Careful selection of the power MOSFET is critical to sys-
tem reliability. Choosing a MOSFET requires extensive
analysis and testing of the MOSFET SOA curve against the
various PSE current limit conditions. ADI recommends
the PSMN075-100MSE for PSEs configured to deliver
up to 51W maximum port power (single-signature) or
25.5W maximum pairset power (dual-signature). For
PSEs configured to power up to 71.3W maximum port
power (single-signature) or 35.6W maximum pairset
power (dual-signature), ADI recommends the PSMN040-
100MSE. These MOSFETs are selected for their proven
reliability in PoE applications. Contact ADI Applications
before using a MOSFET other than one of these recom-
mended parts.
LTC4291-1/LTC4292
34
Rev 0
For more information www.analog.com
Sense Resistors
The LTC4291-1/LTC4292 is designed for a low 0.15Ω cur-
rent sense resistance per channel. Two parallel 0.3Ω resis-
tors must be laid out as shown in the Layout Requirements
section. In order to meet the IHOLD-2P, ICUT-2P, and ILIM-2P
accuracy required by the IEEE specification, the sense
resistors should have ±1% tolerance or better, and no
more than ±200ppm/°C temperature coefficient.
Port Output Cap
Each port requires a 0.22μF cap across OUTnM to AGNDP
(see Figure25) to keep the LTC4292 stable while in cur-
rent limit during startup or overload. Common ceramic
capacitors often have significant voltage coefficients; this
means the capacitance is reduced as the applied voltage
increases. To minimize this problem, X7R ceramic capaci-
tors rated for at least 100V are recommended and must
be located close to the LTC4292.
Surge Protection
Ethernet ports can be subject to significant cable surge
events. To keep PoE voltages below a safe level and pro-
tect the application against damage, protection compo-
nents, as shown in Figure26, are required at the main
supply, at the LTC4292 supply pins, and at each port.
Bulk transient voltage suppression (TVSBULK) and bulk
capacitance (C
BULK
) are required across the main PoE
supply and should be sized to accommodate system level
surge requirements.
Each LTC4292 requires a 10Ω, 0805 resistor (R1) in series
from supply AGND to the LTC4292 AGNDP pin. Across
Figure26. LTC4292 Surge Protection
42911 F26
AGNDP
VEE
SENSEnMVSSKn GATEnM OUTnM
OUTnM
TO
PORT
S1B
S1B
C1
1µF
100V LTC4292
D1
SMAJ58A
R1
10Ω
+
C
BULK
TVSBULK
VEE
VEE
Cn
0.22µF
X7R
100V
QnM
RSENSEnM
AGNDP
AGNDP
the LTC4292 AGNDP pin and VEE pin is a SMAJ58A 58V
TVS (D1) and a 1µF, 100V bypass capacitor (C1). These
components must be placed close to the LTC4292 pins.
Finally, each port requires a pair of S1B clamp diodes: one
from OUTnM to supply AGND and one from OUTnM to
supply VEE. The diodes at the ports steer harmful surges
into the supply rails where they are absorbed by the surge
suppressors and the VEE bypass capacitance. The layout
of these paths must be low impedance.
LAYOUT REQUIREMENTS
Strict adherence to board layout, parts placement and
routing requirements is critical for IEEE compliance, para-
metric measurement accuracy, system robustness and
thermal dissipation. Refer to the DC2685A demo kit for
example layout references.
Sense Resistor Block Layout Requirements
A channel sense resistor may be affected by currents
flowing in other channels. To ensure IEEE parametric
compliance, the sense resistor layout is strictly defined
and must be adhered to. In addition, the sense resistor
block’s common V
EE
plane connections and layout are
specified.
Figure33 shows the component names for ports 1 and 2
as referenced in the remainder of this section. The sense
resistors (RST1 to RST4 and RSU1 to RSU4) for channels
1A, 1B, 2A, and 2B must be grouped together in a sense
resistor block. The same requirements apply to channel
3A, 3B, 4A, and 4B sense resistors and VSSK34.
APPLICATIONS INFORMATION
LTC4291-1/LTC4292
35
Rev 0
For more information www.analog.com
APPLICATIONS INFORMATION
Figure27 shows the top layer PCB placement of sense
resistors RST1 to RST4. Each bottom layer sense resistor,
RSU1 to RSU4, is placed directly underneath its paired
top layer sense resistor. The VEE–facing side of the sense
resistors connect to a common VEE copper area on the
solder pad top edge with a 5mil to 10mil overlap.
Figure28 shows the top component layer common VEE
area copper requirements. On the top layer, the common
VEE area copper is extended at the bottom center down
to the length of the sense resistor pads to allow copper
to flow between the two center sense resistors and bot-
tom center power via. A 10mil keepout is placed around
the common VEE copper area and VEE pads of the sense
resistors. These instructions for the top component layer
are repeated for the bottom component layer.
Figure29 shows the inner layer 2 (VEE plane) common
VEE copper area requirements. A 10mil keepout is placed
around the common VEE copper area; the exception is the
bottom center where the common V
EE
area copper opens
up to the VEE plane. The common VEE copper area only
connects to VEE on layer 2.
Figure30 shows the inner layer 3 (AGND plane and rout-
ing) common VEE area copper requirements. A 10mil
keepout is placed around the common VEE copper area
to separate it from the surrounding AGND plane.
Figure31 shows the common VEE copper area power via
placement. There are 15 power vias in the common VEE
copper area and connect the common copper in this area
on all four layers. The power vias must be sized to a 17mil
drill and 30mil diameter annular ring.
Figure32 is the PCB layer structure defining the copper
thickness requirements for each layer.
Kelvin Sense
Proper Kelvin sensing must be implemented in the layout.
VSSK12 connects to a series resistor RK1 in Figure33.
From RK1 (Figure28), a Kelvin sense small signal trace
connects to VEE only on layer 3 at the centroid top of
the sense resistors (RST1 to RST4 and RSU1 to RSU4)
common VEE copper area (Figure30). A 10mil keepout
must be placed around the RK1 solder pad that leads to
VEE (Figure28); around the trace from RK1 to the cen-
troid (Figures 28 and 30); on all layers around any vias
that connect the trace to different layers (Figures 28, 29,
and30).
At each of the sense resistors, on the side facing
SENSEnM, a power via is placed as close to the respec-
tive solder pads as allowed by the layout DRC. This power
via connects the top and bottom sense resistor pair for
a channel. A Kelvin sense small signal trace connects
SENSEnM directly to the respective sense resistor pair
via shown in Figure30. A separate power path wide trace
connects from the sense resistor pair to the MOSFET.
SENSEnM must not connect to anywhere else on the
power path between the sense resistor and the MOSFET.
RST1 RST2 RST3 RST4
VSSK12 VIA
RK1
250Mil
110Mil
42911 F27
NOTES: DRAWING NOT TO SCALE.
VSSK12 VIA ISOLATED ON TOP AND BOTTOM LAYERS.
RST1 RST2 RST3 RST4
RK1
300Mil
90Mil
NOTES: DRAWING NOT TO SCALE.
RK1 ONLY ON TOP LAYER.
42911 F28
Figure27. Top Component Layer Sense Resistors Placement Figure28. Top and Bottom Layer Sense Resistor Block Layout
LTC4291-1/LTC4292
36
Rev 0
For more information www.analog.com
APPLICATIONS INFORMATION
Figure29. Inner Layer 2 Sense Resistor Block Layout
(VEE Plane)
300Mil
90Mil
(VEE PLANE)
130Mil
NOTES: DRAWING NOT TO SCALE.
VSSK12 VIA ISOLATED.
42911 F29
Figure30. Inner Layer 3 Sense Resistor Block Layout
(AGND/Signal Plane)
Figure31. Sense Resistor Block Via Specifications
Figure32. PCB Layer Structure
NOTES: DRAWING NOT TO SCALE.
VSSK12 VIA CONNECTS V
EE
.
42911 F30
(AGND PLANE)
SENSE2A
SENSE1B
SENSE2B
SENSE1A
300Mil
90Mil
NOTE: DRAWING NOT TO SCALE.
42911 F31
240Mil
40Mil
40Mil
25Mil
160Mil
80Mil
RK1
LTC4291-1/LTC4292
37
Rev 0
For more information www.analog.com
TYPICAL APPLICATION
Figure33. Alternative A (MDI-X) and Alternative B(S), 1000BASE-T, IEEE 802.3bt, Type 3 or Type 4 PSE, Ports 1 and 2 Shown
1
2
3
4
5
6
7
8
RJ45
1000pF
2kV
S1B
75Ω
CT8
75Ω
CT7
CT6
75Ω
75Ω
CT5
Q3
Q4
S1B
1
2
3
4
5
6
7
8
RJ45
1000pF
2kV
S1B
75Ω
CT4
75Ω
CT3
CT2
75Ω
75Ω
CT1
Q1
RSU1
0.3Ω
RST1
0.3Ω
Q2
S1B
0.22μF
100V
0.22μF
100V
0.22μF
100V
10Ω
0.22μF
100V
S1B
S1B
S1B
S1B
DATA SOURCE
PORT 2
DATA AND
POWER OUT
DATA SOURCE
PORT 1
DATA AND
POWER OUT
CPA
CNA
DPA
DNA
PWRMD0
PWRMD1
AGNDP
LTC4292
SENSE2B
GATE2B
OUT2B
SENSE2A
GATE2A
OUT2A
VSSK12
SENSE1B
GATE1B
OUT1B
SENSE1A
GATE1A
OUT1A
TO LTC4291-1 THROUGH ISOLATION INTERFACE
V
EE
AGNDP
AGNDP
AGNDP
AGNDP
AGNDP
V
EE
V
EE
V
EE
V
EE
V
EE
V
EE
T1, T2: WURTH 749022016
COILCRAFT ETH-460L
CT1-CT8: 0.01μF, 200V
V
EE
V
EE
V
EE
V
EE
T1
T2
RSU2
0.3Ω
RST2
0.3Ω
RSU3
0.3Ω
RST3
0.3Ω
RSU4
0.3Ω
RST4
0.3Ω
42911 F33
PWRMD0 PWRMD1 Q1 TO Q4
0 0
0 1
1 0
1 1
NEXPERIA
PSMN075-100MSE
NEXPERIA
PSMN040-100MSE
AGNDP
0.22μF
100V
0.15Ω
LTC4291-1/LTC4292
38
Rev 0
For more information www.analog.com
4.00 ±0.10
(4 SIDES)
NOTE:
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGD-X)—TO BE APPROVED
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE, IF PRESENT
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
PIN 1
TOP MARK
(NOTE 6)
0.40 ±0.10
2423
1
2
BOTTOM VIEW—EXPOSED PAD
2.45 ±0.10
(4-SIDES)
0.75 ±0.05 R = 0.115
TYP
0.25 ±0.05
0.50 BSC
0.200 REF
0.00 – 0.05
(UF24) QFN 0105 REV B
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
0.70 ±0.05
0.25 ±0.05
0.50 BSC
2.45 ±0.05
(4 SIDES)
3.10 ±0.05
4.50 ±0.05
PACKAGE OUTLINE
PIN 1 NOTCH
R = 0.20 TYP OR
0.35 × 45° CHAMFER
UF Package
24-Lead Plastic QFN (4mm × 4mm)
(Reference LTC DWG # 05-08-1697 Rev B)
PACKAGE DESCRIPTION
LTC4291-1/LTC4292
39
Rev 0
For more information www.analog.com
6.00 ±0.10
(4 SIDES)
NOTE:
1. DRAWING IS A JEDEC PACKAGE OUTLINE VARIATION OF (WJJD-2)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
PIN 1 TOP MARK
(SEE NOTE 6)
PIN 1 NOTCH
R = 0.45 OR
0.35 × 45°
CHAMFER
0.40 ±0.10
4039
1
2
BOTTOM VIEW—EXPOSED PAD
4.50 REF
(4-SIDES)
4.42 ±0.10
4.42 ±0.10
4.42 ±0.05
4.42 ±0.05
0.75 ±0.05 R = 0.115
TYP
0.25 ±0.05
0.50 BSC
0.200 REF
0.00 – 0.05
(UJ40) QFN REV Ø 0406
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
0.70 ±0.05
4.50 ±0.05
(4 SIDES)
5.10 ±0.05
6.50 ±0.05
0.25 ±0.05
0.50 BSC
PACKAGE OUTLINE
R = 0.10
TYP
UJ Package
40-Lead Plastic QFN (6mm × 6mm)
(Reference LTC DWG # 05-08-1728 Rev Ø)
PACKAGE DESCRIPTION
LTC4291-1/LTC4292
40
Rev 0
For more information www.analog.com
D17158-0-10/18(0)
www.analog.com
ANALOG DEVICES, INC. 2018
RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS
LT4294 LTPoE++/PoE+/PoE PD Controller External Switch, IEEE 802.3bt Support Configurable Class
LT4295 IEEE 802.3bt PD with Forward/Flyback
Switching Regulator Controller
External Switch, IEEE 802.3bt Support, Configurable Class, Forward or No-Opto Flyback
Operation, Frequency, PG/SG Delays, Soft-Start, and Aux Support as Low as 9V, Including
Housekeeping Buck, Slope Compensation
LTC4257-1 IEEE 802.3af PD Interface Controller Internal 100V, 400mA Switch, Dual Current Limit, Programmable Class
LTC4263 Single IEEE 802.3af PSE Controller Internal FET Switch
LTC4265 IEEE 802.3at PD Interface Controller Internal 100V, 1A Switch, 2-Event Classification Recognition
LTC4266 Quad IEEE 802.3at PoE PSE Controller With Programmable ICUT/ILIM, 2-Event Classification, and Port Current and Voltage Monitoring
LTC4267 IEEE 802.3af PD Interface with Integrated
Switching Regulator
Internal 100V, 400mA Switch, Dual Inrush Current, Programmable Class
LTC4269-1 IEEE 802.3at PD Interface with Integrated
Flyback Switching Regulator
2-Event Classification, Programmable Class, Synchronous No-Opto Flyback Controller,
50kHz to 250kHz, Aux Support
LTC4269-2 IEEE 802.3at PD Interface with Integrated
Forward Switching Regulator
2-Event Classification, Programmable Class, Synchronous Forward Controller, 100kHz to
500kHz, Aux Support
LTC4270/
LTC4271
12-Port PoE/PoE+/LTPoE++
®
PSE Controller Transformer Isolation, Supports Type 1, Type 2 and LTPoE++ PDs
LTC4278 IEEE 802.3at PD Interface with Integrated
Flyback Switching Regulator
2-Event Classification, Programmable Class, Synchronous No-Opto Flyback Controller,
50kHz to 250kHz, 12V Aux Support
LTC4279 Single PoE/PoE+/LTPoE++ PSE Controller Supports IEEE 802.3af, IEEE 802.3at, LTPoE++ and Proprietary PDs
LTC4290/
LTC4271
8-Port PoE/PoE+/LTPoE++ PSE Controller Transformer Isolation, Supports IEEE 802.3af, IEEE 802.3at and LTPoE++ PDs
TYPICAL APPLICATION
VSSKn
VSSKn
V
EE
V
EE
100Ω
100Ω
100Ω
100Ω
100Ω
100Ω
100Ω
100Ω
S1B
10Ω
0.15Ω
>47µF
0.22µF
100V
S1B
S1B
0.15Ω
0.22µF
100V
S1B
2nF
0.1µF
1µF
100V
0.22µF
1µF
3.3V
V
EE
3.3V
CPA
CNA
DPA
DNA
V
EE
VSSKn
SENSEnA
GATEnA
AGNDP
LTC4292
1000BASE-T
V
EE
OUTnA
AGNDP
SENSEnB
GATEnB
OUTnB
AGNDP
TX1
TX2
TX3
TX4
RJ45
1
2
6
4
3
5
7
8
PWRMD0
PWRMD1
V
EE
MSD
SCL
SDAIN
AD0
DGND
DPD
CND
V
DD
LTC4291-1
CPD
DND
GP0
GP1
ISOLATION
AD1
AD2
AD3
SDAOUT
4PVALID
RESET
INT
AUTO
CAP1
3.3V
(NO I
2
C
ISOLATION
REQUIRED)
V
EE
AGNDP
(1 OF 4 PORTS)
D1
D2
QnA, QnB: PSMN040-100MSE
D1: SMCJ58A
D2: SMAJ58A
CAP2
2kV
QnA
QnB
VSSKn
AGNDP
0.22μF, 100V
0.15Ω
42911 F34
Figure34. IEEE 802.3bt Type 3 or Type 4 PSE, Alternative A (MDI-X) and Alternative B(S), 1000BASE-T, 1 of 4 Ports Shown
