Preliminary W24B02 256K x 8 CMOS STATIC RAM GENERAL DESCRIPTION The W24B02 is a normal-speed, very low-power CMOS static RAM organized as 262144 x 8 bits that operates on a wide voltage range from 2.7V to 3.6V power supply. The W24B02, W24B02-LE and W24B02-LI, can meet the requirement of various operating temperature. This device is manufactured using Winbond's high performance CMOS technology. FEATURES * Low power consumption Access time: 55/70 nS * 2.7V to 3.6V supply voltage * Fully static operation * All inputs and outputs directly TTL compatible * * * PIN CONFIGURATIONS BLOCK DIAGRAM Three-state outputs Battery back-up operation capability * Data retention voltage: 1.5V (min.) * Available packages: TFBGA and 32-pin Type one TSOP (8 x 13.4 mm and 8 x 20 mm) CLK GEN. PRECHARGE CKT. R O W CORE CELL ARRAY A18 A11 A9 A8 A13 #WE NC A15 VDD A17 A16 A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32-pin TSOP A17 #OE A10 #CS I/O8 I/O7 I/O6 I/O5 I/O4 Vss I/O3 I/O2 I/O1 A0 A1 A2 A3 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 A16 A15 A14 A13 A12 A10 1024 ROWS D E C O D E R 256 X 8 COLUMNS A8 A7 I/O1 : I/O8 I/O CKT. COLUMN DECODER DATA CNTRL. CLK GEN. #WE TFBGA TOP VIEW A11 A9 A6 A5 A4 A3 A2 A1 A0 #CS #OE 1 2 3 4 5 6 A A0 A1 NC A3 A6 A8 B I/O5 A2 #WE A4 A7 I/O1 C I/O6 NC A5 D V SS V DD E VDD VSS SYMBOL I/O2 F I/O7 G I/O8 #OE #CS A16 A15 I/O4 H A9 A10 A11 A12 A13 A14 NC PIN DESCRIPTION A0 - A17 I/O1 - I/O8 #CS #WE #OE VDD VSS NC I/O3 A17 -1- DESCRIPTION Address Inputs Data Inputs/Outputs Chip Select Input Write Enable Input Output Enable Input Power Supply Ground No Connection Publication Release Date: May 6, 2002 Revision A1 Preliminary W24B02 TRUTH TABLE I/O1 - I/O8 #CS #OE #WE MODE VDD CURRENT H X X Not Selected High Z ISB, ISB1 L H H Output Disable High Z IDD L L H 2 Bytes Read DOUT IDD L L H Lower Byte Read DOUT IDD L L H Upper Byte Read High Z IDD L X L 2 Bytes Write DIN IDD L X L Lower Byte Write DIN IDD L X L Upper Byte Write High Z IDD X X X Not Selected High Z ISB, ISB1 DC CHARACTERISTICS Absolute Maximum Ratings PARAMETER RATING UNIT -0.5 to +4.6 V Input/Output to VSS Potential -0.5 to VDD +0.5 V Allowable Power Dissipation 1.0 W -65 to +150 C LE -20 to 85 C LI -40 to 85 C Supply Voltage to VSS Potential Storage Temperature Operating Temperature Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. Operating Characteristics (VSS = 0V; TA (C) = -20 to 85 for LE, -40 to 85 for LI) PARAMETER SYM. TEST W24B02 UNIT CONDITIONS MIN. MAX. VDD - 2.7 3.6 Input Low Voltage VIL - -0.2 +0.4 V Input High Voltage VIH - +2.2 VDD +0.3 V Input Leakage Current ILI VIN = VSS to VDD -1 +1 A Output Leakage Current ILO VI/O = VSS to VDD; #CS = VIH (min.) or #OE = VIH (min.) or #WE = VIL (max.) -1 +1 A Output Low Voltage VOL IOL = +0.1 mA - 0.4 V Operating Power Voltage -2- V Preliminary W24B02 Operating Characteristics, continued PARAMETER TEST SYM. W24B02 CONDITIONS UNIT MIN. MAX. 2.4 - V Output High Voltage VOH IOH = -1.0 mA Operating Power Supply Current IDD #CS = VIL (max.), I/O = 0 mA; Cycle = min. Duty = 100% - 20 mA ISB #CS = VIH (min.) - 0.3 mA ISB1 #CS VDD -0.2V - 5 A Standby Power Supply Current CAPACITANCE (TA = 25 C, f = 1 MHz) PARAMETER SYM. CONDITIONS MAX. UNIT Input Capacitance CIN VIN = 0V 8 pF Input/Output Capacitance CI/O VOUT = 0V 10 pF Note: These parameters are sampled but not 100% tested. AC CHARACTERISTICS AC Test Conditions PARAMETER CONDITIONS Input Pulse Levels 0V to 3.0V Input Rise and Fall Times 5 nS Input and Output Timing Reference Level 1.5V Output Load See the drawing below AC Test Loads and Waveform 1 TTL 1 TTL OUTPUT OUTPUT 5 pF Including Jig and Scope 30 pF Including Jig and Scope (For TCLZ, TOLZ, TCHZ, TOHZ, TWHZ, TOW ) 3.0V 90% 10% 0V 90% 10% 5 nS 5 nS -3- Publication Release Date: May 6, 2002 Revision A1 Preliminary W24B02 AC Characteristics, continued (VSS = 0V; TA (C) = -20 to 85 for LE, -40 to 85 for LI) Read Cycle PARAMETER SYM. W24B02-55 W24B02-70 MIN. MAX. MIN. MAX. UNIT Read Cycle Time TRC 55 - 70 - nS Address Access Time TAA - 55 - 70 nS Chip Select Access Time TACS - 55 - 70 nS Output Enable to Output Valid TAOE - 35 - 35 nS Chip Selection to Output in Low Z TCLZ* 10 - 10 - nS Output Enable to Output in Low Z TOLZ* 5 - 5 - nS Chip Deselection to Output in High Z TCHZ* - 25 - 30 nS Output Disable to Output in High Z TOHZ* - 25 - 30 nS Output Hold from Address Change TOH 10 - 10 - nS These parameters are sampled but not 100% tested Write Cycle PARAMETER SYM. W24B02-55 W24B02-70 MIN. MAX. MIN. MAX. UNIT Write Cycle Time TWC 55 - 70 - nS Chip Selection to End of Write TCW 45 - 60 - nS Address Valid to End of Write TAW 45 - 60 - nS Address Setup Time TAS 0 - 0 - nS Write Pulse Width TWP 45 - 55 - nS TWR 0 - 0 - nS Data Valid to End of Write TDW 40 - 40 - nS Data Hold from End of Write TDH 0 - 0 - nS Write to Output in High Z TWHZ* - 25 - 30 nS Output Disable to Output in High Z TOHZ* - 25 - 30 nS Output Active from End of Write TOW 5 - 5 - nS Write Recovery Time #CS, #WE These parameters are sampled but not 100% tested -4- Preliminary W24B02 TIMING WAVEFORMS Read Cycle 1 (Address Controlled) TRC Address TOH TAA TOH D OUT Read Cycle 2 (Chip Select Controlled, #OE = VIL, #WE= VIH) TRC Address #CS TACS TCHZ TCLZ #OE TOLZ TAOE HIGH-Z TOHZ HIGH-Z D OUT -5- Publication Release Date: May 6, 2002 Revision A1 Preliminary W24B02 Timing Waveforms, continued Read Cycle 3 (Output Enable Controlled) TR CC Address T AA #OE T OH T AOE T OLZ #CS T ACS T CHZ T CLZ D OUT Write Cycle 1 (#OE Clock) WC Address #OE TCW #CS T AW T WP TAS TOHZ (1, 4) D OUT T DW D IN -6- TDH T OHZ Preliminary W24B02 Timing Waveforms, continued Write Cycle 2 (#OE = VIL Fixed) T WC Address TWR TCW #CS TAW #WE T WP TAS TOH TWHZ (1, 4) DOUT TDW (2) (3) TOW TDH DIN Notes: 1. During this period, I/O pins are in the output state, so input signals of opposite phase to the outputs should not be applied. 2. The data output from DOUT are the same as the data written to DIN during the write cycle. 3. DOUT provides the read data for the next address. 4. Transition is measured 500 mV from steady state with CL = 5 pF. This parameter is guaranteed but not 100% tested. -7- Publication Release Date: May 6, 2002 Revision A1 Preliminary W24B02 DATA RETENTION CHARACTERISTICS (TA (C) = -20 to 85 for LE; -40 to 85 for LI) PARAMETER SYM. TEST CONDITIONS MIN. TYP. MAX. UNIT 1.5 - - V #CS VDD -0.2V VDD for Data Retention VDR Data Retention Current IDDDR #CS VDD -0.2V, VDD = 3.0V - - 5 A Chip Deselect to Data Retention Time TCDR 0 - - nS Operation Recovery Time TR TRC* - - nS See data retention waveform * Read Cycle Time DATA RETENTION WAVEFORM VDD 0.9 x V DD > 1.5V VDR = TR TCDR #CS 0.9 x V DD #CS > = V DD - 0.2V ORDERING INFORMATION ACCESS TIME (nS) OPERATING VOLTAGE (V) STANDBY CURRENT (A) OPERATING TEMPERATURE (C) W24B02B-70LE 70 3V/5 A -20 to 85 TFBGA W24B02Q-70LE 70 3V/5 A -20 to 85 TSOP I (8 x 13.4 mm) W24B02T-70LE 70 3V/5 A -20 to 85 TSOP I (8 x 20 mm) W24B02B-70LI 70 3V/5 A -40 to 85 TFBGA W24B02Q-70LI 70 3V/5 A -40 to 85 TSOP I (8 x 13.4 mm) W24B02T-70LI 70 3V/5 A -40 to 85 TSOP I (8 x 20 mm) W24B02B-55LE 55 3V/5 A -20 to 85 TFBGA W24B02Q-55LE 55 3V/5 A -20 to 85 TSOP I (8 x 13.4 mm) W24B02T-55LE 55 3V/5 A -20 to 85 TSOP I (8 x 20 mm) W24B02B-55LI 55 3V/5 A -40 to 85 TFBGA W24B02Q-55LI 55 3V/5 A -40 to 85 TSOP I (8 x 13.4 mm) W24B02T-55LI 55 3V/5 A -40 to 85 TSOP I (8 x 20 mm) PART NO. PACKAGE Notes: 1. Winbond reserves the right to make changes to its products without prior notice. 2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure. -8- Preliminary W24B02 PACKAGE DIMENSIONS TFBGA 32-Lead Small Type One TSOP (8x13.4) HD Symbol D Min. 1 e E b A 2 A A1 Y L1 Max. Dimension in mm Min. Nom. 0.002 A2 b c 0.037 0.007 Max. 1.25 0.049 A1 D E HD e L Nom. A c Dimension in Inches 0.006 0.05 0.039 0.041 0.95 1.00 1.05 0.008 0.009 0.17 0.20 0.27 0.0056 0.0059 0.0062 0.14 0.15 0.16 0.465 0.469 11.70 11.80 11.90 0.461 0.311 0.315 0.319 7.90 0.15 8.00 8.10 0.520 0.528 0.536 13.20 13.40 13.60 L 0.012 0.020 0.028 L1 0.027 Y 0.000 0.50 0.020 0 0.30 0.50 0.70 0.675 0.004 3 5 0.00 0 0.10 3 5 Controlling dimension: Millimeters -9- Publication Release Date: May 6, 2002 Revision A1 Preliminary W24B02 Package Dimensions, continued 32-Lead TSOP (8 x 20 mm) HD Dimension in Inches Dimension in mm Symbol D A c A1 M e E Min. Nom. __ __ 0.002 __ Max. 0.047 Min. __ 0.006 0.05 Nom. __ __ Max. 1.20 0.15 A2 0.037 0.039 0.041 0.95 1.00 1.05 b 0.007 0.008 0.009 0.17 0.20 0.23 c 0.005 0.006 0.007 0.12 0.15 0.17 D 0.720 0.724 0.728 18.30 18.40 18.50 E 0.311 0.315 0.319 7.90 8.00 8.10 HD 0.780 0.787 0.795 19.80 20.00 20.20 __ __ 0.024 0.40 __ __ 0.004 0.00 5 1 0.10(0.004) b __ e L L A A2 L A1 L1 0.016 __ 1 Y 0.000 1 0.020 0.020 0.031 __ 3 Y Note: Controlling dimension: Millimeters - 10 - 0.50 0.50 0.80 __ 3 __ 0.60 __ 0.10 5 Preliminary W24B02 VERSION HISTORY VERSION DATE PAGE A1 May 6, 2002 - DESCRIPTION Initial Issued Headquarters Winbond Electronics Corporation America Winbond Electronics (Shanghai) Ltd. No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5665577 http://www.winbond.com.tw/ 2727 North First Street, San Jose, CA 95134, U.S.A. TEL: 1-408-9436666 FAX: 1-408-5441798 27F, 2299 Yan An W. Rd. Shanghai, 200336 China TEL: 86-21-62365999 FAX: 86-21-62365998 Taipei Office Winbond Electronics Corporation Japan Winbond Electronics (H.K.) Ltd. 9F, No.480, Rueiguang Rd., Neihu Chiu, Taipei, 114, Taiwan, R.O.C. TEL: 886-2-8177-7168 FAX: 886-2-8751-3579 7F Daini-ueno BLDG, 3-7-18 Shinyokohama Kohoku-ku, Yokohama, 222-0033 TEL: 81-45-4781881 FAX: 81-45-4781800 Unit 9-15, 22F, Millennium City, No. 378 Kwun Tong Rd., Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064 Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. - 11 - Publication Release Date: May 6, 2002 Revision A1