KAF-0261 IMAGE SENSOR
512 (H) X 512 (V) FULL FRAME CCD IMAGE SENSOR
JULY 20, 2012
DEVICE PERFORMANCE SPECIFICATION
REVISION 1.0 PS-0031
KAF-0261 Image Sensor
www.truesenseimaging.com Revision 1.0 PS-0031 Pg 2
TABLE OF CONTENTS
Summary Specification ......................................................................................................................................................................................... 4
Description .................................................................................................................................................................................................... 4
Features ......................................................................................................................................................................................................... 4
Applications .................................................................................................................................................................................................. 4
Ordering Information ............................................................................................................................................................................................ 5
Device Description ................................................................................................................................................................................................. 6
Architecture .................................................................................................................................................................................................. 6
Output Structure ..................................................................................................................................................................................... 7
Image Acquisition ........................................................................................................................................................................................ 7
Charge Transport ......................................................................................................................................................................................... 7
Physical Description .................................................................................................................................................................................... 8
Pin Description and Device Orientation ............................................................................................................................................ 8
Imaging Performance ............................................................................................................................................................................................ 9
Typical Operational Conditions................................................................................................................................................................ 9
Specifications................................................................................................................................................................................................ 9
Electro-Optical ......................................................................................................................................................................................... 9
CCD Parameters Common to Both Outputs ..................................................................................................................................... 9
CCD Parameters Specific to High Gain Output Amplifier ............................................................................................................. 9
CCD Parameters Specific to Low Gain (High Dynamic Range) Output Amplifier .................................................................... 9
Typical Performance Curves (QE) .................................................................................................................................................................. 11
Defect Definitions ................................................................................................................................................................................................ 12
Specifications............................................................................................................................................................................................. 12
Operation .................................................................................................................................................................................................................. 13
Absolute Maximum Ratings ................................................................................................................................................................... 13
DC Bias Operating Conditions ............................................................................................................................................................... 13
AC Operating Conditions ........................................................................................................................................................................ 14
Clock Levels ........................................................................................................................................................................................... 14
Timing ......................................................................................................................................................................................................................... 15
Requirements and Characteristics ....................................................................................................................................................... 15
Normal Readout Timing .......................................................................................................................................................................... 16
Storage and Handling .......................................................................................................................................................................................... 17
Storage Conditions................................................................................................................................................................................... 17
ESD ............................................................................................................................................................................................................... 17
Cover Glass Care and Cleanliness ......................................................................................................................................................... 17
Environmental Exposure ........................................................................................................................................................................ 17
Soldering Recommendations ................................................................................................................................................................ 17
Mechanical Information ..................................................................................................................................................................................... 18
Completed Assembly ............................................................................................................................................................................... 18
Quality Assurance and Reliability .................................................................................................................................................................. 20
Quality and Reliability ............................................................................................................................................................................. 20
Replacement .............................................................................................................................................................................................. 20
Liability of the Supplier ........................................................................................................................................................................... 20
Liability of the Customer ........................................................................................................................................................................ 20
Test Data Retention ................................................................................................................................................................................. 20
Mechanical .................................................................................................................................................................................................. 20
Life Support Applications Policy .................................................................................................................................................................... 20
Revision Changes................................................................................................................................................................................................... 21
MTD/PS-0415 ............................................................................................................................................................................................. 21
KAF-0261 Image Sensor
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PS-0031 ....................................................................................................................................................................................................... 21
TABLE OF FIGURES
Figure 1: Block Diagram ................................................................................................................................................................................ 6
Figure 2: Output Structure ........................................................................................................................................................................... 6
Figure 3: Pinout Diagram .............................................................................................................................................................................. 8
Figure 4: Typical Spectral Response ......................................................................................................................................................... 11
Figure 5: Active Pixel Region .................................................................................................................................................................... 12
Figure 6: Timing diagrams .......................................................................................................................................................................... 16
Figure 7: Completed Assembly (1 of 2) ................................................................................................................................................... 18
Figure 8: Completed Assembly (2 of 2) ................................................................................................................................................... 19
KAF-0261 Image Sensor
www.truesenseimaging.com Revision 1.0 PS-0031 Pg 4
Summary Specification
KAF-0261 Image Sensor
DESCRIPTION
The KAF-0261 Image Sensor is a high performance,
charge coupled device (CCD) designed for a wide range
of image sensing applications.
The sensor incorporates true two-phase CCD technology,
simplifying the support circuits required to drive the
sensor as well as reducing dark current without
compromising charge capacity. The sensor also utilizes
the TRUESENSE Transparent Gate Electrode to improve
sensitivity compared to the use of a standard front side
illuminated polysilicon electrode.
Selectable on-chip output amplifiers allow operation to
be optimized for different imaging needs: Low Noise
(when using the high-sensitivity output) or Maximum
Dynamic Range (when using the low-sensitivity output).
The low dark current of the KAF-0261 makes this device
suitable for low light imaging applications without
sacrificing charge capacity.
FEATURES
True Two Phase Full Frame Architecture
TRUESENSE Transparent Gate Electrode for high
sensitivity
100% Fill Factor
Low Dark Current
User-selectable outputs allow either Low Noise
or High Dynamic Range operation
Single Readout Register
APPLICATIONS
Scientific Imaging
Parameter
Typical Value
Architecture
Full Frame CCD
Number of Active Pixels
512 (H) x 512 (V)
Pixel Size
20 µm (H) x 20 µm (V)
Active Image Size
10.2 mm (H) x 10.2 mm (V)
Chip Size
11.3 mm (H) x 11.6 mm (V)
Optical Fill Factor
100%
Output Sensitivity
High Sensitivity Output
High Dynamic Range Output
10 µV/electron
2.0 µV/electron
Saturation Signal
High Sensitivity Output
High Dynamic Range
200,000 electrons
500,000 electrons
Readout Noise (1 MHz)
22 electrons rms
Dark Current
(25 °C, Accumulation Mode)
<30 pA/cm2
Dark Current Doubling Rate
6 °C
Dynamic Range (Sat Sig/Dark Noise)
High Sensitivity Output
83 dB
High Dynamic Range Output Range
87 dB
Quantum Efficiency (450, 550, 650 nm)
35%, 55%, 58%
Maximum Data Rate
High Sensitivity Output
High Dynamic Range Output
5 MHz
2 MHz
Transfer Efficiency
>0.99997
Package
CERDIP Package
Cover Glass
Clear or AR coated, 2 sides
KAF-0261 Image Sensor
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Ordering Information
Catalog
Number
Product Name
Description
Marking Code
KAF- 0261-AAA-CD-BA
Monochrome, No Microlens, CERDIP Package (sidebrazed), Clear Cover
Glass with AR coating (both sides), Standard Grade
KAF- 0261-AAA
S/N
KAF- 0261-AAA-CD-AE
Monochrome, No Microlens, CERDIP Package (sidebrazed), Clear Cover
Glass with AR coating (both sides), Engineering Sample
KAF- 0261-AAA-CP-BA
Monochrome, No Microlens, CERDIP Package (sidebrazed), Taped Clear
Cover Glass, no coatings, Standard Grade
KAF- 0261-AAA-CP-AE
Monochrome, No Microlens, CERDIP Package (sidebrazed), Taped Clear
Cover Glass, no coatings, Engineering Sample
KEK-4H0081-KAF-0261-12-5
Evaluation Board (Complete Kit)
N/A
See Application Note Product Naming Convention for a full description of the naming convention used for Truesense
Imaging image sensors. For reference documentation, including information on evaluation kits, please visit our web
site at www.truesenseimaging.com.
Please address all inquiries and purchase orders to:
Truesense Imaging, Inc.
1964 Lake Avenue
Rochester, New York 14615
Phone: (585) 784-5500
E-mail: info@truesenseimaging.com
Truesense Imaging reserves the right to change any information contained herein without notice. All information
furnished by Truesense Imaging is believed to be accurate.
KAF-0261 Image Sensor
www.truesenseimaging.com Revision 1.0 PS-0031 Pg 6
Device Description
ARCHITECTURE
Figure 1: Block Diagram
Shaded areas represent 4 non-imaging pixels at the beginning and 8 non-imaging pixels at the end of each line. There
are also 4 non-imaging lines at the top and bottom of each frame.
The KAF-0261 consists of one vertical (parallel) CCD shift register, one horizontal (serial) CCD shift register and a
selectable high or low gain output amplifier (See Figure 1). Both registers incorporate two-phase buried channel CCD
technology. The vertical register consists of 20 µm x 20 µm photocapacitor sensing elements (pixels) that also serves as
the transport mechanism. The pixels are arranged in a 512 (H) x 512 (V) array; an additional 12 columns (4 at the left
and 8 at the right) and 8 rows (4 each at top and bottom) of non-imaging pixels are added as dark reference. There is
no storage array, so this device must be synchronized with strobe illumination or shuttered during readout.
Figure 2: Output Structure
FD 2
KAF-0261
Usable Active Image Area
512(H) x 512(V)
20
m
m x 20
m
m pixels
4 Dark Lines
f
V1
f
V2
Guard
4 Dark Lines
512 Active Pixels/Line
8 Dark
2 Inactive
4 Dark
4 Inactive
f
H22
f
H21
f
R
Vog
Vrd
Vout 1
Vdd 1
Vss
Vout 2
Vdd 2
Sub FD 1
f
H1
f
H2
FD1
f
H1
f
H21
f
H22
f
H2
FD2
Sub
Vdd2
Vout2
Vlg
Vss
Vdd1
Vout1
f
R
Vrd
Vog
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Output Structure
The final gate of the horizontal register is split into two sections, φH21 and φH22. The split gate structure allows the
user to select either of the two output amplifiers. To use the high dynamic range single-stage output (Vout1), φH22 is
tied to a negative voltage to block charge transfer, and φH21 is tied to φH2 to transfer charge. To use the high
sensitivity two-stage output (Vout2), φH21 is tied to a negative voltage and φH22 is tied to φH2. The charge packets
are then dumped onto the appropriate floating diffusion output node whose potential varies linearly with the quantity
of charge in each packet. The amount of potential change is determined by the simple expression Vfd = Q/Cfd.
The translation from electrons to voltages is called the output sensitivity or charge-to-voltage conversion. After the
output has been sensed off-chip, the reset clock (φR) removes the charge from the floating diffusion via the reset
drain (VRD). This, in turn, returns the floating diffusion potential to the reference level determined by the reset drain
voltage.
IMAGE ACQUISITION
An image is acquired when incident light, in the form of photons, falls on the array of pixels in the vertical CCD register
and creates electron-hole pairs (or simply electrons) within the silicon substrate. This charge is collected locally by the
formation of potential wells created at each pixel site by induced voltages on the vertical register clock lines (φV1,
φV2). These same clock lines are used to implement the transport mechanism as well. The amount of charge collected
at each pixel is linearly dependent on light level and exposure time and non-linearly dependent on wavelength until
the potential well capacity is exceeded. At this point charge will 'bloom' into vertically adjacent pixels.
CHARGE TRANSPORT
Integrated charge is transported to the output in a two-step process. Rows of charge are first shifted line by line into
the horizontal CCD. 'Lines' of charge are then shifted to the output pixel by pixel. The timing diagram illustrated in
Figure 5illustrates how the integration of charge is performed with φV1 and φV2 held low. Transfer to the horizontal
CCD begins when φV1 is brought high, causing charge from the φV1 and φV2 gates to combine under the φV1 gate.
The φV1 and φV2 gates are now reversed in polarity, causing the charge packets to 'spill' forward under the φV2 gate
of the next pixel. The rising edge of φV2 also transfers the first line of charge into the horizontal CCD. A second phase
transition places the charge packets under the φV1 electrode of the next pixel. The sequence completes when φV1 is
brought low. Clocking of the vertical register in this way is known as accumulation mode clocking. Next, the horizontal
CCD reads out the first line of charge using traditional complementary clocking (using φH1 and φH2 pins) as shown.
The falling edge of φH2 forces a charge packet over the output gate (OG) onto one of the output nodes (floating
diffusion) which is buffered by the output amplifier. The cycle repeats until all lines are read.
KAF-0261 Image Sensor
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PHYSICAL DESCRIPTION
Pin Description and Device Orientation
Pixel (1,1)
1
2
3
4
5
6
7
8
9
10
11
12
φ
R
VSS
φ
H21
φ
H2
VOUT1
OG
VDD1/VDD2
VOUT2
VRD
φ
H1
φ
H22
N/C
24
23
22
21
20
19
18
17
16
15
14
13
GUARD
φ
V1
SUB
φ
V1
φ
V1
SUB
VLG
φ
V2
φ
V2
φ
V2
φ
V2
φ
V1
Pixel (512,512)
Figure 3: Pinout Diagram
Pin
Name
Description
Pin
Name
Description
1
OG
Output Gate
24
VLG
First Stage Load Transistor Gate for Two-
Stage
2
VOUT2
Video Output from High Sensitivity Two-Stage
23
GUARD
Guard Ring
3
VDD1/VDD2
Amplifier Supply for VOUT1 and VOUT2 amplifiers
22
φV1
Vertical (Parallel) CCD Clock - Phase 1
4
VRD
Reset Drain
21
φV1
Vertical (Parallel) CCD Clock - Phase 1
5
φR
Reset Clock
20
φV2
Vertical (Parallel) CCD Clock - Phase 2
6
VSS
Output Amplifier Return
19
φV2
Vertical (Parallel) CCD Clock - Phase 2
7
φH1
Horizontal (Serial) CCD Clock - Phase 1
18
φV2
Vertical (Parallel) CCD Clock - Phase 2
8
φH2
Horizontal (Serial) CCD Clock - Phase 2
17
φV2
Vertical (Parallel) CCD Clock - Phase 2
9
VOUT1
Video Output from High Dynamic Range Single-Stage
Amplifier
16
φV1
Vertical (Parallel) CCD Clock - Phase 1
10
φH21
Last Horizontal (Serial) CCD Phase - Split Gate
15
φV1
Vertical (Parallel) CCD Clock - Phase 1
11
φH22
Last Horizontal (Serial) CCD Phase - Split Gate
14
VSUB
Substrate
12
N/C
No Connection
13
VSUB
Substrate
Notes:
1. Pins 15, 16, 21, and 22 must be connected together - only one Phase 1-clock driver is required.
2. Pins 17, 18, 19, and 20 must be connected together - only one Phase 2-clock driver is required.
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Imaging Performance
TYPICAL OPERATIONAL CONDITIONS
All values apply to nominal operating conditions with the recommended timing. Correlated doubling sampling of the
output is assumed and recommended. Many units are expressed in electrons - to convert to voltage, multiply by the
amplifier sensitivity.
SPECIFICATIONS
Electro-Optical
Description
Symbol
Min.
Nom.
Max
Units
Notes
Verification Plan
Optical Fill Factor
FF
100
%
Photoresponse Non-uniformity
PRNU
5
% rms
Full Array
die10
Quantum Efficiency
(450, 550, 650 nm)
QE
See QE curve
(Figure 7)
design11
CCD Parameters Common to Both Outputs
Description
Symbol
Min.
Nom.
Max
Units
Notes
Verification Plan
Sat. Signal - Vccd register
Ne-sat
450
500
ke-
2
design11
Dark Current
Jd
15.3
400
30
750
pA/cm2
e-pixel/sec
25 °C
(mean of all pixels)
die10
Dark Current Doubling Temp
DCDR
5
6.3
7.5
°C
design11
Dark Signal Non-uniformity
DSNU
750
e-/pix/sec
4
die10
Charge Transfer Efficiency
CTE
.99997
5
die10
Photoresponse Non-Linearity
PRNL
1
2
%
9
Blooming Suppression
Bs
none
CCD Parameters Specific to High Gain Output Amplifier
Description
Symbol
Min.
Nom.
Max
Units
Notes
Verification Plan
Output Sensitivity
Vout/Ne-
10
µV/electron
design11
Sat. Signal
Ne-sat
180
200
240
ke-
1
design11
Total Sensor Noise
ne-total
13
20
e- rms
7
design11
Horizontal CCD Frequency
fH
2
5
MHz
6
design11
Dynamic Range
DR
79
83
dB
8
design11
CCD Parameters Specific to Low Gain (High Dynamic Range) Output Amplifier
Description
Symbol
Min.
Nom.
Max
Units
Notes
Verification Plan
Output Sensitivity
Vout/Ne-
2
µV/electron
design11
Sat. Signal
Ne-sat
550K
628K
ke-
3
design11
Total Sensor Noise
ne-total
22
30
e- rms
7
die10
Horizontal CCD Frequency
fH
0.5
2
MHz
6
design11
Dynamic Range
DR
85
87
dB
8
design11
KAF-0261 Image Sensor
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Notes:
1. Point where the output saturates when operated with nominal voltages.
2. Signal level at the onset of blooming in the vertical (parallel) CCD register.
3. Maximum signal level at the output of the high dynamic range output. This signal level will only be achieved when binning
pixels containing large signals.
4. None of 16 sub arrays (128 x 128) exceed the maximum dark current specification.
5. For 2 MHz data rate and T = 30 °C to -40 °C.
6. Using maximum CCD frequency and/or minimum CCD transfer times may compromise performance.
7. At Tintegration = 0; data rate = 1 MHz; temperature = -30 °C.
8. Uses 20LOG (Ne-sat / ne-total) where Ne- sat refers to the appropriate saturation signal.
9. Worst case deviation from straight line fit, between 1% and 90% of Vsat.
10. A parameter that is measured on every sensor during production testing.
11. A parameter that is quantified during the design verification activity.
KAF-0261 Image Sensor
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Typical Performance Curves (QE)
Figure 4: Typical Spectral Response
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
400 500 600 700 800 900 1000
Wavelength [nm]
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Defect Definitions
SPECIFICATIONS
Point Defect
Cluster Defect
Column Defect
10
4
0
Dark Defects A pixel which deviates by more than 20% from neighboring pixels when illuminated to 70% of
saturation
Bright Defect A pixel whose dark current exceeds 4500 electrons/pixel/second at 25 °C
Cluster Defect A grouping of not more than 5 adjacent point defects
Column Defect A grouping of point defects along a single column. (Dark Column)
A column that contains a pixel whose dark current exceeds 150,000 electrons/pixel/second at
25 °C. (Bright Column)
A column that does not exhibit the minimum charge capacity specification. (Low charge
capacity)
A column that loses >500 electrons when the array is illuminated to a signal level of
2000 electrons/pix. (Trap like defects)
Neighboring Pixels The surrounding 128 x 128 pixels of ± 64 columns/rows
Defects are separated by no less than 3 pixels in any one direction.
1,512
512,512
All pixels subject to defect specification
1,1
512,1
Figure 5: Active Pixel Region
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Operation
ABSOLUTE MAXIMUM RATINGS
Description
Symbol
Minimum
Maximum
Units
Notes
Voltage
All Clocks
-16
+16
V
1
Voltage
OG
0
+8
V
2
Voltage
VRD, VSS, VDD, GUARD
0
+20
V
2
Current
Output Bias Current (IDD)
10
mA
Capacitance
10
pF
Notes:
1. Voltage between any two clocks or between any clock and Vsub.
2. Voltage with respect to Vsub.
Warning:
For maximum performance, built-in gate protection has been added only to the OG pin. These devices require extreme
care during handling to prevent electrostatic discharge (ESD) induced damage. Devices are rated as
Class 0 (<250 V per JESD22 Human Body Model test), or Class A (<200 V JESD22 Machine Model test).
DC BIAS OPERATING CONDITIONS
Description
Symbol
Minimum
Nominal
Maximum
Units
Pin Impedance
Substrate
VSUB
0.0
0.0
0.0
V
Common
Output Amplifier Supply
VDD
15.0
+17.0
17.5
V
5 pf, 2 K (Note 1)
Output Amplifier Return
VSS
1.4
+2.0
2.1
V
5 pf, 2 K
Reset Drain
VRD
11.5
+12
12.5
V
5 pf, 1 M
Output Gate
OG
4.0
4.5
5.0
V
5 pf, 10 M
Guard Ring
GUARD
9.0
+10.0
15.0
V
350 pF, 10 M
Load Gate
VLG
VSS - 1.0
VSS
VSS + 1.0
V
Notes:
1. Vdd = 17 volts for applications where the expected output voltage > 2.0 volts. For applications where the expected useable
output voltage is < 2 volts Vdd can be reduced to 15 volts.
KAF-0261 Image Sensor
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AC OPERATING CONDITIONS
Clock Levels
Description
Symbol
Level
Minimum
Nominal
Maximum
Units
Pin Impedance
Vertical Clock - Phase 1
φV1
Low
-10.2
-10.0
-9.0
V
13 nf, 10 M
Vertical Clock - Phase 1
φV1
High
0.0
0
2.0
V
Vertical Clock - Phase 2
φV2
Low
-10.2
-10.0
-9.0
V
16 nf, 10 M
Vertical Clock - Phase 2
φV2
High
0.0
0
2.0
V
Horizontal Clock - Phase 1
φH1
Low
-2.2
-2.0
-1.8
V
160 pf, 10 M
Horizontal Clock - Phase 1
φH1
High
7.8
+8.0
8.2
V
Horizontal Clock - Phase 2
φH2
Low
-2.2
-2.0
-1.8
V
110 pf, 10 M
Horizontal Clock - Phase 2
φH2
High
7.8
+8.0
8.2
V
Reset Clock
φR
Low
2.0
3.0
3.5
V
10 pF, 10 M
Reset Clock
φR
High
10.0
V
Using the High Gain
Output (Vout2)
Using the High Dynamic
Range Output (Vout1)
Description
Symbol
Level
Min
Nom
Max
Min
Nom
Max
Units
Pin Impedance
Horizontal Clock - Phase 1
φH21
Low
-4
φH2 low
φH2 low
φH2
V
10 pF, 10 M
Horizontal Clock - Phase 1
φH21
High
-4
φH2 low
φH2 low
φH2
V
Horizontal Clock - Phase 2
φH22
Low
φH2
-4
φH2 low
φH2 low
V
10 pF, 10 M
Horizontal Clock - Phase 2
φH22
High
φH2
-4
φH2 low
φH2 low
V
Notes:
1. When using Vout1 φH21 is clocked identically with φH2 while φH22 is held at a static level. When using Vout2 φH21 and
φH22 are exchanged so that φH22 is identical to φH2 and φH21 is held at a static level. The static level should be the same
voltage as φH2 low.
2. The AC and DC operating levels are for room temperature operation. Operation at other temperatures may require
adjustments of these voltages. Pins shown with impedances greater than 1 MOhm are expected resistances. These pins are
only verified to 1 MOhm.
3. φV1, 2 capacitances are accumulated gate oxide capacitance, and so are an over-estimate of the capacitance.
4. This device is suitable for a wide range of applications requiring a variety of different operating conditions. Consult
Truesense Imaging in those situations in which operating conditions meet or exceed minimum or maximum levels.
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Timing
REQUIREMENTS AND CHARACTERISTICS
Description
Symbol
Minimum
Nominal
Maximum
Units
Notes
φH1, φH2 Clock Frequency
fH
5
8
MHz
1, 2, 3
V1, V2 Clock Frequency
fV
100
125
kHz
1, 2, 3
Pixel Period (1 Count)
tpix
125
200
ns
φH1, φH2 Set-up Time
tφHS
500
1000
ns
φV1, φV2 Clock Pulse Width
tφV
4
5
µs
2
Reset Clock Pulse Width
tφR
10
20
ns
4
Readout Time
treadout
40
64
ms
5
Integration Time
tint
6
Line Time
tline
78
122
µs
7
Notes:
1. 50% duty cycle values.
2. CTE may degrade above the nominal frequency.
3. Rise and fall times (10/90% levels) should be limited to 5-10% of clock period. Crossover of register clocks should be
between 40-60% of amplitude.
4. φR should be clocked continuously.
5. treadout = (520 * tline)
6. Integration time (tint) is user specified. Longer integration times will degrade noise performance due to dark signal fixed
pattern and shot noise.
7. tline= (3 * tφV) + tφHS + 530* tpix + tpix
KAF-0261 Image Sensor
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NORMAL READOUT TIMING
Figure 6: Timing diagrams
Notes:
1. This device is suitable for a wide range of applications requiring a variety of different timing frequencies. Therefore, only
maximum and minimum values are shown above. Consult Truesense Imaging in those situations, which require special
consideration.
Frame Timing
tReadout
Line
1
2
520
520
1 Frame = 520 Lines
f
V1
f
V2
f
H1
f
H2
tint
Pixel Timing Detail
fR
fH1
fH2
Vout
tfR
Vsat
Vdark
Vsub
Vodc
1 count
tpix
Line Timing Detail
1 line
V1
V2
H1
H2
R
530 counts
tfHS
1(tpix)
tfV
tfV
Vpix
Line Content
Photoactive Pixels
Dark Reference Pixels
Dummy Pixels
1-4
5-8
9 - 520
521-528
529-530
Vsat Saturated pixel video output signal
Vdark Video output signal in no light situation, not zero due to Jdark
Vpix Pixel video output signal level, more electrons =more negative*
Vodc Video level offset with respect to vsub
Vsub Analog Ground
* See Image Aquisition section
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Storage and Handling
STORAGE CONDITIONS
Description
Symbol
Minimum
Maximum
Units
Notes
Storage
Temperature
TST
-100
+80
°C
At
Device
Operating
Temperature
TOP
-70
+50
°C
At
Device
ESD
1. This device contains limited protection against
Electrostatic Discharge (ESD). ESD events may
cause irreparable damage to a CCD image
sensor either immediately or well after the ESD
event occurred. Failure to protect the sensor
from electrostatic discharge may affect device
performance and reliability.
2. Devices should be handled in accordance with
strict ESD procedures for Class 0 (<250 V per
JESD22 Human Body Model test), or Class A
(<200 V JESD22 Machine Model test) devices.
Devices are shipped in static-safe containers
and should only be handled at static-safe
workstations.
3. See Application Note Image Sensor Handling
Best Practices for proper handling and
grounding procedures. This application note
also contains workplace recommendations to
minimize electrostatic discharge.
4. Store devices in containers made of electro-
conductive materials.
COVER GLASS CARE AND CLEANLINESS
1. The cover glass is highly susceptible to
particles and other contamination. Perform all
assembly operations in a clean environment.
2. Touching the cover glass must be avoided.
3. Improper cleaning of the cover glass may
damage these devices. Refer to Application
Note Image Sensor Handling Best Practices.
ENVIRONMENTAL EXPOSURE
1. Extremely bright light can potentially harm
CCD image sensors. Do not expose to strong
sunlight for long periods of time, as the color
filters and/or microlenses may become
discolored. In addition, long time exposures to
a static high contrast scene should be avoided.
Localized changes in response may occur from
color filter/microlens aging. For Interline
devices, refer to Application Note Using
Interline CCD Image Sensors in High Intensity
Visible lighting Conditions.
2. Exposure to temperatures exceeding maximum
specified levels should be avoided for storage
and operation, as device performance and
reliability may be affected.
3. Avoid sudden temperature changes.
4. Exposure to excessive humidity may affect
device characteristics and may alter device
performance and reliability, and therefore
should be avoided.
5. Avoid storage of the product in the presence of
dust or corrosive agents or gases, as
deterioration of lead solderability may occur. It
is advised that the solderability of the device
leads be assessed after an extended period of
storage, over one year.
SOLDERING RECOMMENDATIONS
1. The soldering iron tip temperature is not to
exceed 370 °C. Higher temperatures may alter
device performance and reliability.
2. Flow soldering method is not recommended.
Solder dipping can cause damage to the glass
and harm the imaging capability of the device.
Recommended method is by partial heating
using a grounded 30 W soldering iron. Heat
each pin for less than 2 seconds duration.
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Mechanical Information
COMPLETED ASSEMBLY
Figure 7: Completed Assembly (1 of 2)
KAF-0261 Image Sensor
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Figure 8: Completed Assembly (2 of 2)
KAF-0261 Image Sensor
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Quality Assurance and Reliability
QUALITY AND RELIABILITY
All image sensors conform to the specifications stated in this document. This is accomplished through a combination
of statistical process control and visual inspection and electrical testing at key points of the manufacturing process,
using industry standard methods. Information concerning the quality assurance and reliability testing procedures and
results are available from Truesense Imaging upon request. For further information refer to Application Note Quality
and Reliability.
REPLACEMENT
All devices are warranted against failure in accordance with the Terms of Sale. Devices that fail due to mechanical and
electrical damage caused by the customer will not be replaced.
LIABILITY OF THE SUPPLIER
A reject is defined as an image sensor that does not meet all of the specifications in this document upon receipt by the
customer. Product liability is limited to the cost of the defective item, as defined in the Terms of Sale.
LIABILITY OF THE CUSTOMER
Damage from mishandling (scratches or breakage), electrostatic discharge (ESD), or other electrical misuse of the
device beyond the stated operating or storage limits, which occurred after receipt of the sensor by the customer, shall
be the responsibility of the customer.
TEST DATA RETENTION
Image sensors shall have an identifying number traceable to a test data file. Test data shall be kept for a period of 2
years after date of delivery.
MECHANICAL
The device assembly drawing is provided as a reference.
Truesense Imaging reserves the right to change any information contained herein without notice. All information
furnished by Truesense Imaging is believed to be accurate.
Life Support Applications Policy
Truesense Imaging image sensors are not authorized for and should not be used within Life Support Systems without
the specific written consent of Truesense Imaging, Inc.
KAF-0261 Image Sensor
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©Truesense Imaging Inc., 2012. TRUESENSE is a registered trademark of Truesense Imaging, Inc.
Revision Changes
MTD/PS-0415
Revision Number
Description of Changes
1.0
Corrected Figure 3, Pinout Diagram.
Updated DC Operating Conditions. (Section 2.4)
Updated CCD Parameters Specific to Low Gain (high dynamic range) Output Amplifier (page 13)
2.0
Corrected Figure 3, Pinout Diagram. (Pixel locations incorrect.)
Updated DC Operating Conditions for Output Gate. (Section 2.4)
Updated CCD parameters Specific to Low Gain (High Dynamic Range) Output Amplifier for Dynamic Range (page 13).
Removed appendix.
3.0
First version of the document in S9K. Formerly Revision 2 in hard copy format.
Removed Class 0 from the Cosmetic Specification and UV coated device. (Section 3.2)
Added ESD classification. (Section 2.3)
Replaced Quality and Reliability notes with current format. (Section 4.2)
4.0
Update specification format
Updated Completed Assembly Drawing
PS-0031
Revision Number
Description of Changes
1.0
Initial release with new document number, updated branding and document template
Updated Storage and Handling and Quality Assurance and Reliability sections