SPI Interface, 1.5 Ω RON, ±15 V/+12 V,
Quad SPST Switch, Mux Configurable
Data Sheet
ADGS1412
Rev. B Document Feedback
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FEATURES
SPI interface with error detection
Includes CRC, invalid read/write address, and SCLK count
error detection
Supports burst mode and daisy-chain mode
Industry-standard SPI Mode 0 and Mode 3 interface compatible
Guaranteed break-before-make switching allowing external
wiring of switches to deliver multiplexer configurations
1.5 Ω typical on resistance at 25°C
0.3 Ω typical on resistance flatness at 25°C
0.1 Ω typical on resistance match between channels at 25°C
VSS to VDD analog signal range
Fully specified at ±15 V, ±5 V, and +12 V
1.8 V logic compatibility with 2.7 V ≤ VL ≤ 3.3 V
24-lead LFCSP
APPLICATIONS
Automated test equipment
Data acquisition systems
Battery-powered systems
Sample-and-hold systems
Audio signal routing
Video signal routing
Communications systems
Relay replacement
FUNCTIONAL BLOCK DIAGRAM
S4
S3
S2
S1
D4
SDO
SCLK SDI CS RESET/VL
D3
D2
D1
ADGS1412
14960-001
SPI
INTERFACE
Figure 1.
GENERAL DESCRIPTION
The ADGS1412 contains four independent single-pole/single-
throw (SPST) switches. A serial peripheral interface (SPI)
controls the switches. The SPI interface has robust error detection
features such as cyclic redundancy check (CRC) error detection,
invalid read/write address detection, and SCLK count error
detection.
It is possible to daisy-chain multiple ADGS1412 devices together.
Daisy-chain mode enables the configuration of multiple devices
with a minimal amount of digital lines. The ADGS1412 can also
operate in burst mode to decrease the time between SPI
commands.
iCMOS construction ensures ultralow power dissipation, making
the device ideally suited for portable and battery-powered
instruments.
Each switch conducts equally well in both directions when on,
and each switch has an input signal range that extends to the
supplies. In the off condition, signal levels up to the supplies
are blocked.
The on-resistance profile is flat over the full analog input range,
which ensures good linearity and low distortion when switching
audio signals.
PRODUCT HIGHLIGHTS
1. SPI interface removes the need for parallel conversion,
logic traces and reduces general-purpose input/output
(GPIO) channel count.
2. Daisy-chain mode removes additional logic traces when
multiple devices are used.
3. CRC error detection, invalid read/write address detection,
and SCLK count error detection ensures a robust digital
interface.
4. CRC and error detection capabilities allow the use of the
ADGS1412 in safety critical systems.
5. Guaranteed break-before-make switching allows the use of
the ADGS1412 in multiplexer configurations with external
wiring.
6. Minimum distortion.
ADGS1412 Data Sheet
Rev. B | Page 2 of 27
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagrams ............................................................. 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
±15 V Dual Supply ....................................................................... 3
±5 V Dual Supply ......................................................................... 5
12 V Single Supply ........................................................................ 7
Continuous Current per Channel, Sx or Dx ............................. 9
Timing Characteristics ................................................................ 9
Absolute Maximum Ratings .......................................................... 11
Thermal Resistance .................................................................... 11
ESD Caution ................................................................................ 11
Pin Configurations and Function Descriptions ......................... 12
Typical Performance Characteristics ........................................... 13
Test Circuits ..................................................................................... 17
Terminology .................................................................................... 19
Theory of Operation ...................................................................... 20
Address Mode ............................................................................. 20
Error Detection Features ........................................................... 20
Clearing the Error Flags Register ............................................. 21
Burst Mode .................................................................................. 21
Software Reset ............................................................................. 21
Daisy-Chain Mode ..................................................................... 21
Power-On Reset .......................................................................... 22
Applications Information .............................................................. 23
Break-Before-Make Switching .................................................. 23
Digital Input Buffers .................................................................. 23
Power Supply Rails ..................................................................... 23
Power Supply Recommendations ............................................. 23
Register Summary .......................................................................... 24
Register Details ............................................................................... 25
Switch Data Register .................................................................. 25
Error Configuration Register .................................................... 25
Error Flags Register .................................................................... 26
Burst Enable Register ................................................................. 26
Software Reset Register ............................................................. 26
Outline Dimensions ....................................................................... 27
Ordering Guide .......................................................................... 27
REVISION HISTORY
8/2017—Rev. A to Rev. B
Changes to Product Title, Features Section, and Product
Highlights Section ............................................................................ 1
Changes to Table 1 ............................................................................ 3
Changes to Table 2 ............................................................................ 5
Changes to Table 3 ............................................................................ 7
Changes to VL to GND Parameter and Digital Inputs Parameter,
Table 7 .............................................................................................. 11
Changes to Figure 17 ...................................................................... 14
Added Figure 27; Renumbered Sequentially .............................. 16
Changes to Figure 30 ...................................................................... 17
Added Figure 35 .............................................................................. 17
Added Figure 36 .............................................................................. 18
Change to Theory of Operation Section ..................................... 20
Added Break-Before-Make Switching Section, Figure 45, and
Digital Input Buffers Section......................................................... 23
Changes to Ordering Guide .......................................................... 27
3/2017—Rev. 0 to Rev. A
Changes to Features Section and Product Highlights Section .... 1
Change to IL Inactive Parameter, Table 1........................................ 4
Change to VDD = 1 5 V, V SS = −15 V (θJA = 54°C/W) Parameter,
Table 5 .................................................................................................. 7
Change to Theory of Operation Section ..................................... 18
Updated Outline Dimensions Section ......................................... 25
10/2016—Revision 0: Initial Version
Data Sheet ADGS1412
Rev. B | Page 3 of 27
SPECIFICATIONS
±15 V DUAL SUPPLY
VDD = +15 V ± 10%, VSS = −15 V ± 10%, VL = 2.7 V to 5.5 V, and GND = 0 V, unless otherwise noted.
Table 1.
Parameter +25°C
−40°C to
+85°C
−40°C to
+125°C Unit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range VDD to VSS V
On Resistance, RON 1.5 Ω typ VS = ±10 V, IS = −10 mA, see Figure 29
1.8 2.3 2.6 Ω max VDD = +13.5 V, VSS = −13.5 V
On-Resistance Match Between
Channels, ∆RON
0.1 Ω typ VS = ±10 V, IS = −10 mA
0.18 0.19 0.21 Ω max
On-Resistance Flatness, RFLAT (ON) 0.3 Ω typ VS = ±10 V, IS = −10 mA
0.36 0.4 0.45 Ω max
LEAKAGE CURRENTS VDD = +16.5 V, VSS = −16.5 V
Source Off Leakage, IS (Off) ±0.03 nA typ VS = ±10 V, VD = 10 V, see Figure 32
±0.55 ±2 ±12.5 nA max
Drain Off Leakage, ID (Off) ±0.03 nA typ VS = ±10 V, VD = 10 V, see Figure 32
±0.55 ±2 ±12.5 nA max
Channel On Leakage, ID (On), IS (On) ±0.15 nA typ VS = VD = ±10 V, see Figure 28
±2 ±4 ±30 nA max
DIGITAL OUTPUT
Output Voltage
Low, VOL 0.4 V max ISINK = 5 mA
0.2 V max ISINK = 1 mA
High Impedance Leakage Current 0.001 μA typ Output voltage (VOUT) = ground voltage (VGND) or VL
±0.1 μA max
High Impedance Output Capacitance 4 pF typ
DIGITAL INPUTS
Input Voltage
High, VINH 2 V min 3.3 V < VL ≤ 5.5 V
1.35 V min 2.7 V ≤ VL ≤ 3.3 V
Low, VINL 0.8 V max 3.3 V < VL ≤ 5.5 V
0.8 V max 2.7 V ≤ VL ≤ 3.3 V
Input Current, IINL or IINH 0.001 μA typ VIN = VGND or VL
±0.1 μA max
Digital Input Capacitance, CIN 4 pF typ
DYNAMIC CHARACTERISTICS1
tON 400 ns typ Load resistance (RL) = 300 Ω, load capacitance
(CL) = 35 pF
475 480 485 ns max VS = 10 V, see Figure 37
tOFF 160 ns typ RL = 300 Ω, CL = 35 pF
190 210 225 ns max VS = 10 V, see Figure 37
Break-Before-Make Time Delay, tD 215 ns typ RL = 300 Ω, CL = 35 pF
170 ns min VS1 = VS2 = 10 V, see Figure 36
Charge Injection, QINJ −20 pC typ VS = 0 V, RS = 0 Ω, CL = 1 nF, see Figure 38
Off Isolation −76 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 31
Channel to Channel Crosstalk −100 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 30
Total Harmonic Distortion + Noise 0.014 % typ RL = 110 Ω, 15 V p-p, f = 20 Hz to 20 kHz,
see Figure 33
ADGS1412 Data Sheet
Rev. B | Page 4 of 27
Parameter +25°C
−40°C to
+85°C
−40°C to
+125°C Unit Test Conditions/Comments
−3 dB Bandwidth 170 MHz typ RL = 50 Ω, CL = 5 pF, see Figure 34
Insertion Loss −0.2 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 34
CS (Off) 22 pF typ VS = 0 V, f = 1 MHz
CD (Off) 23 pF typ VS = 0 V, f = 1 MHz
CD (On), CS (On) 113 pF typ VS = 0 V, f = 1 MHz
POWER REQUIREMENTS VDD = +16.5 V, VSS = −16.5 V
IDD 0.001 μA typ All switches open
1 μA max
220 μA typ All switches closed, VL = 5.5 V
380 μA max
230 μA typ All switches closed, VL = 2.7 V
380 μA max
Load current (IL)
Inactive 6.3 μA typ Digital inputs = 0 V or VL
8.0 μA max
Inactive, SCLK = 1 MHz 14 μA typ CS = VL and SDI = 0 V or VL, VL = 5 V
7 μA typ
CS = VL and SDI = 0 V or VL, VL = 3 V
SCLK = 50 MHz 390 μA typ CS = VL and SDI = 0 V or VL, VL = 5 V
210 μA typ
CS = VL and SDI = 0 V or VL, VL = 3 V
Inactive, SDI = 1 MHz 15 μA typ CS and SCLK = 0 V or VL, VL = 5 V
7.5 μA typ
CS and SCLK = 0 V or VL, VL = 3 V
SDI = 25 MHz 230 μA typ CS and SCLK = 0 V or VL, VL = 5 V
120 μA typ
CS and SCLK = 0 V or VL, VL = 3 V
Active at 50 MHz 1.8 mA typ Digital inputs toggle between 0 V and VL, VL = 5.5 V
2 2.1 mA max
0.7 mA typ Digital inputs toggle between 0 V and VL, VL = 2.7 V
1.0 mA max
ISS 0.001 μA typ Digital inputs = 0 V or VL
1.0 μA max
VDD/VSS ±4.5/±16.5
V min/
V max
GND = 0 V
1 Guaranteed by design; not subject to production test.
Data Sheet ADGS1412
Rev. B | Page 5 of 27
±5 V DUAL SUPPLY
VDD = +5 V ± 10%, VSS = −5 V ± 10%, VL = 2.7 V to 5.5 V, and GND = 0 V, unless otherwise noted.
Table 2.
Parameter +25°C
−40°C to
+85°C
−40°C to
+125°C Unit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range VDD to VSS V
On Resistance, RON 3.3 Ω typ VS = ±4.5 V, IS = −10 mA, see Figure 29
4 4.9 5.4 Ω max VDD = +4.5 V, VSS = −4.5 V
On-Resistance Match Between
Channels, ∆RON
0.13 Ω typ VS = ±4.5 V, IS = −10 mA
0.22 0.23 0.25 Ω max
On-Resistance Flatness, RFLAT (ON) 0.9 Ω typ VS = ±4.5 V, IS = −10 mA
1.1 1.24 1.31 Ω max
LEAKAGE CURRENTS VDD = +5.5 V, VSS = −5.5 V
Source Off Leakage, IS (Off) ±0.03 nA typ VS = ±4.5 V, VD = 4.5 V, see Figure 32
±0.55 ±2 ±12.5 nA max
Drain Off Leakage, ID (Off) ±0.03 nA typ VS = ±4.5 V, VD = 4.5 V, see Figure 32
±0.55 ±2 ±12.5 nA max
Channel On Leakage, ID (On), IS (On) ±0.05 nA typ VS = VD = ±4.5 V, see Figure 28
±1.0 ±4 ±30 nA max
DIGITAL OUTPUT
Output Voltage
Low, VOL 0.4 V max ISINK = 5 mA
0.2 V max ISINK = 1 mA
High Impedance Leakage Current 0.001 μA typ VOUT = VGND or VL
±0.1 μA max
High Impedance Output Capacitance 4 pF typ
DIGITAL INPUTS
Input Voltage
High, VINH 2 V min 3.3 V < VL ≤ 5.5 V
1.35 V min 2.7 V ≤ VL ≤ 3.3 V
Low, VINL 0.8 V max 3.3 V < VL ≤ 5.5 V
0.8 V max 2.7 V ≤ VL ≤ 3.3 V
Input Current, IINL or IINH 0.001 μA typ VIN = VGND or VL
±0.1 μA max
Digital Input Capacitance, CIN 4 pF typ
DYNAMIC CHARACTERISTICS1
tON 510 ns typ RL = 300 Ω, CL = 35 pF
645 680 710 ns max VS = 3 V, see Figure 37
tOFF 280 ns typ RL = 300 Ω, CL = 35 pF
365 400 435 ns max VS = 3 V, see Figure 37
Break-Before-Make Time Delay, tD 245 ns typ RL = 300 Ω, CL = 35 pF
200 ns min VS1 = VS2 = 3 V, see Figure 36
Charge Injection, QINJ 10 pC typ VS = 0 V, RS = 0 Ω, CL = 1 nF, see Figure 38
Off Isolation −76 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 31
Channel to Channel Crosstalk −100 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 30
Total Harmonic Distortion + Noise 0.03 % typ RL = 110 Ω, 5 V p-p, f = 20 Hz to 20 kHz, see Figure 33
−3 dB Bandwidth 130 MHz typ RL = 50 Ω, CL = 5 pF, see Figure 34
Insertion Loss −0.3 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 34
CS (Off) 32 pF typ VS = 0 V, f = 1 MHz
CD (Off) 33 pF typ VS = 0 V, f = 1 MHz
CD (On), CS (On) 116 pF typ VS = 0 V, f = 1 MHz
ADGS1412 Data Sheet
Rev. B | Page 6 of 27
Parameter +25°C
−40°C to
+85°C
−40°C to
+125°C Unit Test Conditions/Comments
POWER REQUIREMENTS VDD = +5.5 V, VSS = −5.5 V
IDD 0.001 μA typ Digital inputs = 0 V or VL, VL = 5.5 V
1.0 μA max
14 μA typ All switches closed, VL = 2.7 V
20 μA max
IL
Inactive 6.3 μA typ Digital inputs = 0 V or VL
8.0 μA max
Inactive, SCLK = 1 MHz 14 μA typ CS = VL and SDI = 0 V or VL, VL = 5 V
7 μA typ
CS = VL and SDI = 0 V or VL, VL = 3 V
SCLK = 50 MHz 390 μA typ CS = VL and SDI = 0 V or VL, VL = 5 V
210 μA typ
CS = VL and SDI = 0 V or VL, VL = 3 V
Inactive, SDI = 1 MHz 15 μA typ CS and SCLK = 0 V or VL, VL = 5 V
7.5 μA typ
CS and SCLK = 0 V or VL, VL = 3 V
SDI = 25 MHz 230 μA typ CS and SCLK = 0 V or VL, VL = 5 V
120 μA typ
CS and SCLK = 0 V or VL, VL = 3 V
Active at 50 MHz 1.8 mA typ Digital inputs toggle between 0 V and VL, VL = 5.5 V
2.1 mA max
0.7 mA typ Digital inputs toggle between 0 V and VL, VL = 2.7 V
1.0 mA max
ISS 0.001 μA typ Digital inputs = 0 V or VL
1.0 μA max
VDD/VSS ±4.5/±16.5
V min/
V max
GND = 0 V
1 Guaranteed by design; not subject to production test.
Data Sheet ADGS1412
Rev. B | Page 7 of 27
12 V SINGLE SUPPLY
VDD = 12 V ± 10%, VSS = 0 V, VL = 2.7 V to 5.5 V, and GND = 0 V, unless otherwise noted.
Table 3.
Parameter +25°C
−40°C to
+85°C
−40°C to
+125°C Unit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range 0 V to VDD V
On Resistance, RON 2.8 Ω typ VS = 0 V to 10 V, IS = −10 mA, see Figure 29
3.5 4.3 4.8 Ω max VDD = 10.8 V, VSS = 0 V
On-Resistance Match Between
Channels, ∆RON
0.13 Ω typ VS = 0 V to 10 V, IS = −10 mA
0.21 0.23 0.25 Ω max
On-Resistance Flatness, RFLAT (ON) 0.6 Ω typ VS = 0 V to 10 V, IS = −10 mA
1.1 1.2 1.3 Ω max
LEAKAGE CURRENTS VDD = 13.2 V, VSS = 0 V
Source Off Leakage, IS (Off) ±0.02 nA typ VS = 1 V/10 V, VD = 10 V/1 V, see Figure 32
±0.55 ±2 ±12.5 nA max
Drain Off Leakage, ID (Off) ±0.02 nA typ VS = 1 V/10 V, VD = 10 V/1 V, see Figure 32
±0.55 ±2 ±12.5 nA max
Channel On Leakage, ID (On), IS (On) ±0.15 nA typ VS = VD = 1 V/10 V, see Figure 28
±1.5 ±4 ±30 nA max
DIGITAL OUTPUT
Output Voltage
Low, VOL 0.4 V max ISINK = 5 mA
0.2 V max ISINK = 1 mA
High Impedance Leakage Current 0.001 μA typ VOUT = VGND or VL
±0.1 μA max
High Impedance Output Capacitance 4 pF typ
DIGITAL INPUTS
Input Voltage
High, VINH 2 V min 3.3 V < VL ≤ 5.5 V
1.35 V min 2.7 V ≤ VL ≤ 3.3 V
Low, VINL 0.8 V max 3.3 V < VL ≤ 5.5 V
0.8 V max 2.7 V ≤ VL ≤ 3.3 V
Input Current, IINL or IINH 0.001 μA typ VIN = VGND or VL
±0.1 μA max
Digital Input Capacitance, CIN 4 pF typ
DYNAMIC CHARACTERISTICS1
tON 470 ns typ RL = 300 Ω, CL = 35 pF
570 615 300 ns max VS = 8 V, see Figure 37
tOFF 170 ns typ RL = 300 Ω, CL = 35 pF
215 240 265 ns max VS = 8 V, see Figure 37
Break-Before-Make Time Delay, tD 280 ns typ RL = 300 Ω, CL = 35 pF
225 ns min VS1 = VS2 = 8 V, see Figure 36
Charge Injection, QINJ 10 pC typ VS = 6 V, RS = 0 Ω, CL = 1 nF, see Figure 38
Off Isolation −76 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 31
Channel to Channel Crosstalk −100 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 30
Total Harmonic Distortion + Noise 0.06 % typ RL = 110 Ω, 6 V p-p, f = 20 Hz to20 kHz,
see Figure 33
−3 dB Bandwidth 130 MHz typ RL = 50 Ω, CL = 5 pF, see Figure 34
Insertion Loss −0.3 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 34
CS (Off) 29 pF typ VS = 6 V, f = 1 MHz
CD (Off) 30 pF typ VS = 6 V, f = 1 MHz
CD (On), CS (On) 116 pF typ VS = 6 V, f = 1 MHz
ADGS1412 Data Sheet
Rev. B | Page 8 of 27
Parameter +25°C
−40°C to
+85°C
−40°C to
+125°C Unit Test Conditions/Comments
POWER REQUIREMENTS VDD = 13.2 V
IDD 0.001 µA typ All switches open
1.0 µA max
220 µA typ All switches closed, VL = 5.5 V
380 µA max
250 µA typ All switches closed, VL = 2.7 V
430 µA max
IL
Inactive
6.3
µA typ
Digital inputs = 0 V or V
L
8.0 µA max
Inactive, SCLK = 1 MHz 14 µA typ CS = VL and SDI = 0 V or VL, VL = 5 V
7 µA typ CS = VL and SDI = 0 V or VL, VL = 3 V
SCLK = 50 MHz 390 µA typ CS = VL and SDI = 0 V or VL, VL = 5 V
210 µA typ CS = VL and SDI = 0 V or VL, VL = 3 V
Inactive, SDI = 1 MHz 15 µA typ CS and SCLK = 0 V or VL, VL = 5 V
7.5 µA typ CS and SCLK = 0 V or VL, VL = 3 V
SDI = 25 MHz 230 µA typ CS and SCLK = 0 V or VL, VL = 5 V
120 µA typ CS and SCLK = 0 V or VL, VL = 3 V
Active at 50 MHz 1.8 mA typ Digital inputs toggle between 0 V and VL,
VL = 5.5 V
2.1 mA max
0.7 mA typ Digital inputs toggle between 0 V and VL,
VL = 2.7 V
1.0 mA max
VDD 5/20 V min/
V max
GND = 0 V, VSS = 0 V
1 Guaranteed by design; not subject to production test.
Data Sheet ADGS1412
Rev. B | Page 9 of 27
CONTINUOUS CURRENT PER CHANNEL, Sx OR Dx
Table 4. Four Channels On
Parameter 25°C 85°C 125°C Unit
CONTINUOUS CURRENT, Sx OR Dx
1
VDD = 15 V, VSS = −15 V (θJA = 54°C/W) 297 165 79 mA maximum
VDD = 12 V, VSS = 0 V (θJA = 54°C/W) 240 142 74 mA maximum
VDD = 5 V, VSS = −5 V (θJA = 54°C/W) 224 135 72 mA maximum
1 Sx refers to the S1 to S4 pins, and Dx refers to the D1 to D4 pins.
Table 5. One Channel On
Parameter 25°C 85°C 125°C Unit
CONTINUOUS CURRENT, Sx OR Dx1
V
DD
= 15 V, V
SS
= −15 V (θ
JA
= 54°C/W)
531
235
87
mA maximum
VDD = 12 V, VSS = 0 V (θJA = 54°C/W) 433 210 85 mA maximum
VDD = 5 V, VSS = −5 V (θJA = 54°C/W) 404 202 84 mA maximum
1 Sx refers to the S1 to S4 pins, and Dx refers to the D1 to D4 pins.
TIMING CHARACTERISTICS
VL = 2.7 V to 5.5 V, GND = 0 V, and all specifications TMIN to TMAX, unless otherwise noted. Guaranteed by design and characterization,
not production tested.
Table 6.
Parameter Limit Unit Test Conditions/Comments
TIMING CHARACTRISTICS
t1 20 ns min SCLK period
t2 8 ns min SCLK high pulse width
t3 8 ns min SCLK low pulse width
t4 10 ns min CS falling edge to SCLK active edge
t5 6 ns min Data setup time
t6 8 ns min Data hold time
t7 10 ns min SCLK active edge to CS rising edge
t8 20 ns max CS falling edge to SDO data available
t
91
20
ns max
SCLK falling edge to SDO data available
t10 20 ns max CS rising edge to SDO returns to high impedance
t11 20 ns min CS high time between SPI commands
t12 8 ns min CS falling edge to SCLK becomes stable
t13 8 ns min CS rising edge to SCLK becomes stable
1 Measured with the 1 kΩ pull-up resistor to VL and 20 pF load. t9 determines the maximum SCLK frequency when SDO is used.
ADGS1412 Data Sheet
Rev. B | Page 10 of 27
Timing Diagrams
t
1
t
2
t
3
t
4
t
5
t
8
t
9
t
10
t
6
t
7
R/W
CS
SCLK
SDI
SDO
A6 A5 D2 D1 D0
001 D2 D1 D0
14960-002
Figure 2. Address Mode Timing Diagram
t
1
t
2
t
3
t
4
t
5
t
8
t
9
t
10
t
6
t
7
CS
SCLK
SDI
SDO
INP UT BYT E FO R DE V ICE N I NP UT BYTE F OR DEV ICE N + 1
ZERO BYTE INP UT BYT E FO R DE V ICE N
D7 D6 D0 D7 D6 D1 D0
0 0 0 D7 D6 D1 D0
14960-003
Figure 3. Daisy-Chain Timing Diagram
t
13
t
11
t
12
CS
SCLK
14960-004
Figure 4. SCLK/CS Timing Relationship
Data Sheet ADGS1412
Rev. B | Page 11 of 27
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 7.
Parameter Rating
VDD to VSS 35 V
VDD to GND −0.3 V to +25 V
VSS to GND +0.3 V to −25 V
VL to GND −0.3 V to +6 V
Analog Inputs1 VSS − 0.3 V to VDD + 0.3 V or
30 mA, whichever occurs first
Digital Inputs
1
−0.3 V to +6 V
Peak Current, Sx or Dx Pins2 600 mA (pulsed at 1 ms,
10% duty cycle maximum)
Continuous Current, Sx or Dx2, 3 Data + 15%
Temperature Range
Operating −40°C to +125°C
Storage
−65°C to +150°C
Junction Temperature 150°C
Reflow Soldering Peak
Temperature, Pb Free
260(+0/−5)°C
1 Overvoltages at the digital Sx and Dx pins are clamped by internal diodes.
Limit current to the maximum ratings given.
2 Sx refers to the S1 to S4 pins, and Dx refers to the D1 to D4 pins.
3 See Table 4 and Table 5.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Only one absolute maximum rating can be applied at any one time.
THERMAL RESISTANCE
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
Table 8. Thermal Resistance
Package Type θJA θJCB1 Unit
CP-24-172 54 3 °C/W
1 θJCB is the junction to the bottom of the case value.
2 Thermal impedance simulated values are based on JEDEC 2S2P thermal test
board with four thermal vias. See JEDEC JESD-51.
ESD CAUTION
ADGS1412 Data Sheet
Rev. B | Page 12 of 27
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
2
1
3
4
5
6
18
17
16
15
14
13
D4
S4
GND
V
SS
S1
D1
D3
S3
V
DD
NIC
S2
D2
8
9
10
11
7
NIC
RESET/V
L
NIC
GND
12NIC
NIC
20
19
21
SDO
NIC
CS
22 SCLK
23 SDI
24 NIC
ADGS1412
TOP VIEW
(No t t o Scal e)
NOTES
1. NIC = NOT INT ERNALL Y CONNECTED.
2. THE E X P OSE D P AD IS CO NNE CTED INTE RNALL Y . F O R
INCREAS E D RE LI ABILIT Y OF THE SOL DE R JOINTS AND
MAXIMUM THERMAL CAPABILI T Y, I T I S RECOMMENDED
THAT THE P AD BE S OL DERE D TO THE S UBS TRATE , V
SS
.
14960-005
Figure 5. Pin Configuration
Table 9. Pin Function Descriptions
Pin No. Mnemonic Description
1
D1
Drain Terminal 1. This pin can be an input or output.
2 S1 Source Terminal 1. This pin can be an input or output.
3 VSS Most Negative Power Supply Potential. In single-supply applications, tie this pin to ground.
4, 11 GND Ground (0 V) Reference.
5 S4 Source Terminal 4. This pin can be an input or output.
6 D4 Drain Terminal 4. This pin can be an input or output.
7, 8, 10, 12,
16, 19, 24
NIC Not Internally Connected.
9 RESET/VL RESET/Logic Power Supply Input (VL). Under normal operation, drive the RESET/VL pin with a 2.7 V to 5.5 V supply.
Pull the RESET pin low to complete a hardware reset. After a reset, all switches open, and the appropriate registers
are set to their default.
13
D3
Drain Terminal 3. This pin can be an input or output.
14 S3 Source Terminal 3. This pin can be an input or output.
15 VDD Most Positive Power Supply Potential.
17 S2 Source Terminal 2. This pin can be an input or output.
18 D2 Drain Terminal 2. This pin can be an input or output.
20 SDO Serial Data Output. This pin can be used for daisy chaining a number of these devices together or for reading
back the data stored in a register for diagnostic purposes. The serial data is propagated on the falling edge of
SCLK. Pull this open-drain output to VL with an external resistor.
21 CS Active Low Control Input. CS is the frame synchronization signal for the input data.
22 SCLK Serial Clock Input. Data is captured on the positive edge of SCLK. Data can be transferred at rates of up to 50 MHz.
23 SDI Serial Data Input. Data is captured on the positive edge of SCLK.
EPAD
Exposed Pad. The exposed pad is connected internally. For increased reliability of the solder joints and
maximum thermal capability, it is recommended that the exposed pad be soldered to the substrate, VSS.
Data Sheet ADGS1412
Rev. B | Page 13 of 27
TYPICAL PERFORMANCE CHARACTERISTICS
2.5
2.0
1.5
1.0
0.5
0
–16.5 –12.5 –8.5 –4.5 –0.5 3.5 7.5 15.5
ON RESISTANCE (Ω)
V
S
OR V
D
(V) 11.5
V
DD
= +16. 5V ,
V
SS
= –16. 5V
T
A
= 25° C
I
S
= –10mA
V
DD
= +15V,
V
SS
= –15V
V
DD
= +13. 5V ,
V
SS
= –13. 5V
V
DD
= +12V,
V
SS
= –12V
V
DD
= +10V,
V
SS
= –10V
14960-006
Figure 6. On Resistance vs. VS or VD for Various Dual Supplies
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0–7 –6 –5 –3 –1–4 –2 0 1 6
ON RESISTANCE (Ω)
VS OR VD (V) 3 4 752
TA = 25° C
IS = –10mA
VDD = +7V,
VSS = –7V
VDD = + 5.5V,
VSS = –5.5V
VDD = +5V,
VSS = –5V
VDD = + 4.5V,
VSS = –4.5V
14960-007
Figure 7. On Resistance vs. VS or VD for Various Dual Supplies
7
6
5
4
3
2
1
001412108642
ON RESISTANCE (Ω)
V
S
OR V
D
(V)
T
A
= 25° C
I
S
= –10mA
V
DD
= 15V,
V
SS
= 0V
V
DD
= 13. 2V,
V
SS
= 0V
V
DD
= 12V,
V
SS
= 0V
V
DD
= 10. 8V,
V
SS
= 0V
V
DD
= 8V,
V
SS
= 0V
V
DD
= 5V,
V
SS
= 0V
14960-008
Figure 8. On Resistance vs. VS or VD for Various Single Supplies
3.0
2.5
2.0
1.5
1.0
0.5
0
–15 151050–5–10
ON RESISTANCE (Ω)
V
S
OR V
D
(V)
V
DD
= +15V
V
SS
= –15V
I
S
= –10mA
T
A
= +25°C
T
A
= +85°C
T
A
= +125°C
T
A
= –40° C
14960-009
Figure 9. On Resistance vs. VS or VD for Various Temperatures,
±15 V Dual Supply
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0–5 –4 –3 –2 –1 012345
ON RESISTANCE (Ω)
VS OR VD (V)
VDD = +5V
VSS = –5V
IS = –10mA
TA = +25°C
TA = +85°C
TA = –40° C
14960-010
Figure 10. On Resistance vs. VS or VD for Various Temperatures,
±5 V Dual Supply
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0012108642
ON RESISTANCE (Ω)
V
S
OR V
D
(V)
V
DD
= 12V
V
SS
= 0V
I
S
= –10mA
T
A
= +25°C
T
A
= +85°C
T
A
= –40° C
14960-011
Figure 11. On Resistance vs. VS or VD for Various Temperatures,
12 V Single Supply
ADGS1412 Data Sheet
Rev. B | Page 14 of 27
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0–5 –4 –3 –2 –1 012345
ON RESISTANCE (Ω)
VS OR VD (V)
VDD = +5V
VSS = –5V
TA = 125° C
IS = 100mA
TA = 25° C
IS = 190mA
14960-012
Figure 12. On Resistance vs. VS or VD for Various Current Levels and
Temperatures, ±5 V Dual Supply
1.5
–3.5
–3.0
–2.5
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
012010080604020
LEAKAGE CURRE NT (nA)
TEMPERATURE (°C)
V
DD
= +15V
V
SS
= –15V
V
BIAS
= +10V/–10V
I
S
(OFF) + –
I
D
(OFF) + –
I
S
(OFF) – +
I
D
(OFF) – +
I
D
, I
S
(ON) + +
I
D
, I
S
(ON) – –
14960-013
Figure 13. Leakage Current vs. Temperature, ±15 V Dual Supply
1.5
–1.5
–1.0
–0.5
0
0.5
1.0
012080 100604020
LEAKAGE CURRE NT (nA)
TEMPERATURE (°C)
V
DD
= +5V
V
SS
= –5V
V
BIAS
= +4. 5V /–4. 5V
I
D
(OFF) – +
I
S
(OFF) + –
I
D
, I
S
(ON) ++
I
D
, I
S
(ON) – –
I
D
(OFF) + –
I
S
(OFF) – +
14960-014
Figure 14. Leakage Current vs. Temperature, ±5 V Dual Supply
9
8
7
6
5
4
3
2
1
0
–1 012080 100604020
LEAKAGE CURRE NT (nA)
TEMPERATURE (°C)
I
S
(OFF) + –
I
D
(OFF) + –
I
S
(OFF) – +
I
D
(OFF) – +
I
D
, I
S
(ON) ++
I
D
, I
S
(ON) – –
V
DD
= 12V
V
SS
= 0V
V
BIAS
= 1V/ 10V
14960-015
Figure 15. Leakage Current vs. Temperature, 12 V Single Supply
400
–400
–300
–200
–100
0
100
200
300
–500
–15 –10 –5 0 5 10 15
CHARGE INJECTI ON (p C)
V
S
(V)
V
DD
= +15V, V
SS
= –15V
V
DD
= +12V, V
SS
= 0V
V
DD
= +5V, V
SS
= –5V
T
A
= 25° C
14960-016
Figure 16. Charge Injection vs. Source Voltage (VS)
–20–40
14960-017
0
100
200
300
400
500
600
700
020 40 60 80 100 120
t
TRANSITION
(n s)
TEMPERATURE ( °C)
15V DS,
t
ON
15V DS,
t
OFF
5V DS,
t
ON
5V DS,
t
OFF
12V SS,
t
ON
12V SS,
t
OFF
Figure 17. tON/tOFF Time vs. Temperature for Single Supply (SS) and
Dual Supply (DS)
Data Sheet ADGS1412
Rev. B | Page 15 of 27
0
–140
–100
–120
–80
–60
–40
–20
100 1k 10k 100k 1M 10M 1G100M
OFF ISOLATION (dB)
FREQUENCY ( Hz )
V
DD
= +15V
V
SS
= –15V
T
A
= 25° C
14960-018
Figure 18. Off Isolation vs. Frequency, ±15 V Dual Supply
0
–140
–120
–100
–80
–60
–40
–20
10k 100k 1M 10M 100M 1G
CROSS TAL K ( dB)
FREQUENCY ( Hz )
V
DD
= +15V
V
SS
= –15V
T
A
= 25° C
14960-019
Figure 19. Crosstalk vs. Frequency, ±15 V Dual Supply
0
–6
–5
–4
–3
–2
–1
10k 100k 1M 10M 1G100M
INSERTION LOSS (dB)
FREQUENCY ( Hz )
V
DD
= +15V
V
SS
= –15V
T
A
= 25° C
14960-020
Figure 20. Insertion Loss vs. Frequency, ±15 V Dual Supply
0
–120
–100
–80
–60
–40
–20
AC PSRR ( dB)
FREQUENCY ( Hz )
V
DD
= +15V
V
SS
= –15V
T
A
= 25° C
10µF + 100nF DE COUPL ING
CAPACITORS
100nF DECO UP LI NG
CAPACITORS
14960-021
100 1k 10k 100k 1M 10M 1G100M
Figure 21. AC Power Supply Rejection Ratio (AC PSRR) vs. Frequency, ±15 V
Dual Supply
0
0.005
0.010
0.015
0.020
0.025
20 200 2k 20k
THD + N ( %)
FRE Q UE NCY ( Hz )
14960-022
TA = 25° C
RL = 110Ω, VS = 20V p - p
RL = 110Ω, VS = 15V p - p
RL = 110Ω, VS = 10V p - p
RL = 1kΩ, VS = 10V p-p
RL = 1kΩ, VS = 15V p-p
RL = 1kΩ, VS = 20V p-p
Figure 22. THD + N vs. Frequency, ±15 V Dual Supply
0
0.05
0.10
0.15
0.20
20 200 2k 20k
THD + N ( %)
FRE Q UE NCY ( Hz )
14960-023
T
A
= 25° C R
L
= 110Ω, V
S
= 10V p - p
R
L
= 110Ω, V
S
= 2.5V p-p
R
L
= 110Ω, V
S
= 5V p-p
R
L
= 1kΩ, V
S
= 2.5V p-p
R
L
= 1kΩ, V
S
= 5V p-p
R
L
= 1kΩ, V
S
= 10V p - p
Figure 23. THD + N vs. Frequency, ±5 V Dual Supply
ADGS1412 Data Sheet
Rev. B | Page 16 of 27
0
0.14
0.12
0.10
0.08
0.06
0.04
0.02
20 200 2k 20k
THD + N (%)
FREQUENCY (Hz)
14960-124
T
A
= 25°C
R
L
= 110Ω, V
S
= 3V p-p
R
L
= 110Ω, V
S
= 6V p-p
R
L
= 110Ω, V
S
= 9V p-p
R
L
= 1kΩ, V
S
= 3V p-p
R
L
= 1kΩ, V
S
= 6V p-p
R
L
= 1kΩ, V
S
= 9V p-p
Figure 24 . THD + N vs. Frequency, 12 V Single Supply
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
2.0
02468
V
OUT
(mV)
TIME (µs)
14960-125
V
DD
= +15V
V
SS
= –15V
T
A
= 25°C
SCLK = 2.5MHz
SCLK IDLE
Figure 25. Digital Feedthrough
3.0 3.5
80
70
60
50
40
30
20
10
0
2.7 5.5
4.0 4.5 5.0
I
DD
(µA)
V
L
(V)
V
DD
= +15V
V
SS
= –15V
V
DD
= +12V
V
SS
= 0V
V
DD
= +5V
V
SS
= –5V
14960-126
T
A
= 25°C
I
DD
PER CLOSED SWITCH
Figure 26. IDD vs. VL
0
50
100
150
200
250
300
350
400
450
1 1020304050
I
L
(uA)
SCLK FREQUENCY (MHz)
V
L
= 5V
V
L
= 3V
T
A
= 25°C
14960-226
Figure 27. IL vs. SCLK Frequency when CS High
Data Sheet ADGS1412
Rev. B | Page 17 of 27
TEST CIRCUITS
V
D
Sx Dx
V
S
A
I
D
(ON)
14960-024
Figure 28. On Leakage
Sx Dx
V
S
V1
I
DS
R
ON
= V
1
/I
DS
14960-025
Figure 29. On Resistance
14960-026
CHANNEL TO CHANNEL CROSSTALK = 20 log V
OUT
GND
S1
D2
D1
S2
V
OUT
NETWORK
ANALYZER
R
L
50Ω
R
L
50Ω
V
S
V
S
V
DD
V
SS
0.1µF
V
DD
0.1µF
V
SS
NC
Figure 30. Channel to Channel Crosstalk
OFF ISOLATION = 20 log V
OUT
GND
Sx
Dx
V
OUT
NETWORK
ANALYZER
R
L
50Ω
50Ω
50Ω
V
S
V
S
V
DD
V
SS
0.1µF
V
DD
0.1µF
V
SS
14960-027
Figure 31. Off Isolation
Sx Dx
V
S
A A
V
D
I
S
(OFF) I
D
(OFF)
14960-028
Figure 32. Off Leakage
GND
Sx
Dx
V
OUT
AUDIO PRECISION
R
L
110Ω
R
S
V
S
V p-p
V
DD
V
SS
0.1µF
V
DD
0.1µF
V
SS
14960-029
Figure 33. THD + Noise
INSERTION LOSS = 20 log V
OUT
WITH SWITCH
GND
Sx
Dx
V
OUT
NETWORK
ANALYZER
R
L
50Ω
50Ω
V
S
V
S
WITHOUT SWITCH
V
DD
V
SS
0.1µF
V
DD
0.1µF
V
SS
14960-030
Figure 34. −3 dB Bandwidth
AC PSRR = 20 log V
OUT
GND D1S1
V
OUT
NETWORK
ANALYZER
R
L
50Ω
V
S
V
DD
V
SS
V
SS
NC
INTERNAL
BIAS
V
S
R
L
50Ω
NOTES
1. BOARD AND COMPONENT EFFECTS ARE NOT DE-EMBEDDED
FROM THE AC PSRR MEASUREMENT.
14960-235
Figure 35. AC PSRR
ADGS1412 Data Sheet
Rev. B | Page 18 of 27
VDD VSS
VDD VSS
0.1µF 0.1µF
GND
INPUT LOGIC
RL1
300Ω
CL1
35pF
VS1 S1 D1 VOUT1
RL2
300Ω
CL2
35pF
VS2 S2 D2 VOUT2
VOUT1
VOUT2
SCLK 50%
80% 80%
80% 80%
50%
0V
0V
0V
t
D
t
D
14960-236
Figure 36. Break-Before-Make Time Delay, tD
VDD VSS
VDD VSS
0.1µF 0.1µF
GND
RL
300Ω
CL
35pF
VSINPUT LOGIC
Sx Dx VOUT SCLK
VOUT
50% 50%
90%
10%
tON tOFF
14960-031
Figure 37. Switching Times, tON and tOFF
V
DD
V
SS
V
DD
V
SS
GND
INPUT LOGIC
C
L
1nF
Sx Dx V
OUT
R
S
V
S
SCLK
3V
V
OUT
ΔV
OUT
Q
INJ
= C
L
× ΔV
OUT
SWITCH OFF SWITCH ON
14960-032
Figure 38. Charge Injection, QINJ
Data Sheet ADGS1412
Rev. B | Page 19 of 27
TERMINOLOGY
IDD
IDD represents the positive supply current.
ISS
ISS represents the negative supply current.
VD, VS
VD and VS represent the analog voltage on Terminal Dx and
Ter mi na l Sx, respe ct ively.
RON
RON represents the ohmic resistance between Terminal Dx and
Ter mi na l Sx.
ΔRON
ΔRON represents the difference between the RON of any two
channels.
RFLAT (ON)
Flatness that is defined as the difference between the maximum
and minimum value of on resistance measured over the specified
analog signal range is represented by RFLAT (ON).
IS (Off)
IS (Off) is the source leakage current with the switch off.
ID (Off)
ID (Off) is the drain leakage current with the switch off.
ID (On), IS (On)
ID (On) and IS (On) represent the channel leakage currents with
the switch on.
VINL
VINL is the maximum input voltage for Logic 0.
VINH
VINH is the minimum input voltage for Logic 1.
IINL, IINH
IINL and IINH represent the low and high input currents of the
digital inputs.
CD (Off)
CD (Off) represents the off switch drain capacitance, which is
measured with reference to ground.
CS (Off)
CS (Off) represents the off switch source capacitance, which is
measured with reference to ground.
CD (On), CS (On)
CD (On) and CS (On) represent on switch capacitances, which
are measured with reference to ground.
CIN
CIN is the digital input capacitance.
tON
tON represents the delay between applying the digital control
input and the output switching on.
tOFF
tOFF represents the delay between applying the digital control
input and the output switching off.
Off Isolation
Off isolation is a measure of unwanted signal coupling through
an off switch.
Charge Injection
Charge injection is a measure of the glitch impulse transferred
from the digital input to the analog output during switching.
Crosstalk
Crosstalk is a measure of unwanted signal that is coupled
through from one channel to another as a result of parasitic
capacitance.
−3 dB Bandwidth
Bandwidth is the frequency at which the output is attenuated
by 3 dB.
On Response
On response is the frequency response of the on switch.
Insertion Loss
Insertion loss is the loss due to the on resistance of the switch.
Total Harmonic Distortion + Noise (THD + N)
The ratio of the harmonic amplitude plus noise of the signal to
the fundamental is represented by THD + N.
AC Power Supply Rejection Ratio (AC PSRR)
AC PSRR is the ratio of the amplitude of signal on the output to the
amplitude of the modulation. AC PSRR is a measure of the ability
of the device to avoid coupling noise and spurious signals that
appear on the supply voltage pin to the output of the switch. The dc
voltage on the device is modulated by a sine wave of 0.62 V p-p.
ADGS1412 Data Sheet
Rev. B | Page 20 of 27
THEORY OF OPERATION
The ADGS1412 is a set of serially controlled, quad SPST switches
with error detection features. SPI Mode 0 and Mode 3 can be
used with the device, and it operates with SCLK frequencies up
to 50 MHz. The default mode for the ADGS1412 is address mode
in which the registers of the device are accessed by a 16-bit SPI
command that is bounded by CS. The SPI command becomes
24 bit if the user enables CRC error detection. Other error detection
features include SCLK count error and invalid read/write error.
If any of these SPI interface errors occur, they are detectable by
reading the error flags register. The ADGS1412 can also operate
in two other modes, namely burst mode and daisy-chain mode.
The interface pins of the ADGS1412 are CS, SCLK, SDI, and SDO.
Hold CS low when using the SPI interface. Data is captured on
the SDI on the rising edge of SCLK, and data is propagated out on
the SDO on the falling edge of SCLK. SDO has an open-drain
output; thus, connect a pull-up to this output. When not pulled
low by the ADGS1412, SDO is in a high impedance state.
ADDRESS MODE
Address mode is the default mode for the ADGS1412 upon
power up. A single SPI frame in address mode is bounded by
a CS falling edge and the succeeding CS rising edge. It is comprised
of 16 SCLK cycles. The timing diagram for address mode is shown
in Figure 39. The first SDI bit indicates if the SPI command is a
read or write command. When the first bit is set to 0, a write
command is issued, and if the first bit is set to 1, a read command
is issued. The next seven bits determine the target register address.
The remaining eight bits provide the data to the addressed register.
The last eight bits are ignored during a read command, because
during these clock cycles, SDO propagates out the data contained
in the addressed register.
The target register address of an SPI command is determined on
the eighth SCLK rising edge. Data from this register propagates out
on SDO from the 9th to the 16th SCLK falling edge during SPI
reads. A register write occurs on the 16th SCLK rising edge
during SPI writes.
During any SPI command, SDO sends out eight alignment bits
on the first eight SCLK falling edges. The alignment bits observed
at SDO are 0x25.
ERROR DETECTION FEATURES
Protocol and communication errors on the SPI interface are
detectable. There are three detectable errors, which are incorrect
SCLK count error detection, invalid read/write address error
detection, and CRC error detection. Each of these errors has a
corresponding enable bit in the error configuration register. In
addition, there is an error flag bit for each of these errors in the
error flags register.
Cyclic Redundancy Check (CRC) Error Detection
The CRC error detection feature extends a valid SPI frame by
8 SCLK cycles. These eight extra cycles are needed to send the CRC
byte for that SPI frame. The CRC byte is calculated by the SPI block
using the 16-bit payload: the R/W bit, Register Address Bits[6:0],
and Register Data Bits[7:0]. The CRC polynomial used in the
SPI block is x8 + x2 + x1 + 1 with a seed value of 0. For a timing
diagram with CRC enabled, see Figure 40. Register writes occur
at the 24th SCLK rising edge with CRC error checking enabled.
During an SPI write, the microcontroller/central processing
unit (CPU) provides the CRC byte through SDI. The SPI block
checks the CRC byte just before the 24th SCLK rising edge. On
this same edge, the register write is prevented if an incorrect CRC
byte is received by the SPI interface. The CRC error flag is
asserted in the error flags register in the case of the incorrect
CRC byte being detected.
During an SPI read, the CRC byte is provided to the microcon-
troller through SDO.
The CRC error detection feature is disabled by default and can
be configured by the user through the error configuration register.
00100101D7 D6 D5 D4 D3 D2 D1 D0SDO
R/W A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
12345678910111213141516
SDI
SCLK
CS
14960-033
Figure 39. Address Mode Timing Diagram
0 0 1 D7 D6 D0 C7 C6 C5 C4 C3 C2 C1 C0SDO
R/W A6 A0 D7 D6 D0 C7 C6 C5 C4 C3 C2 C1 C0
1 2 8 9 10 16 17 18 19 20 21 22 23 24
SDI
SCLK
CS
14960-034
Figure 40. Timing Diagram with CRC Enabled
Data Sheet ADGS1412
Rev. B | Page 21 of 27
SCLK Count Error Detection
SCLK count error detection allows the user to detect if an
incorrect number of SCLK cycles are sent by the microcontroller/
CPU. When in address mode, with CRC disabled, 16 SCLK
cycles are expected. If 16 SCLK cycles are not detected, the
SCLK count error flag asserts in the error flags register. When
less than 16 SCLK cycles are received by the device, a write to
the register map never occurs. When the ADGS1412 receives
more than 16 SCLK cycles, a write to the memory map still
occurs at the 16th SCLK rising edge, and the flag asserts in the
error flags register. With CRC enabled, the expected number of
SCLK cycles becomes 24. SCLK count error detection is enabled
by default and can be configured by the user through the error
configuration register.
Invalid Read/Write Address Error
An invalid read/write address error detects when a nonexistent
register address is a target for a read or write. In addition, this
error asserts when a write to a read only register is attempted.
The invalid read/write address error flag asserts in the error
flags register when an invalid read/write address error happens.
The invalid read/write address error is detected on the ninth
SCLK rising edge, which means a write to the register never
occurs when an invalid address is targeted. Invalid read/write
address error detection is enabled by default and can be
disabled by the user through the error configuration register.
CLEARING THE ERROR FLAGS REGISTER
To clear the error flags register, write the special 16-bit SPI
frame, 0x6CA9, to the device. This SPI command does not
trigger the invalid R/W address error. When CRC is enabled,
the user must also send the correct CRC byte for a successful
error clear command. At the 16th or 24th SCLK rising edge, the
error flags register resets to zero.
BURST MODE
The SPI interface can accept consecutive SPI commands
without the need to deassert the CS line, which is called burst
mode. Burst mode is enabled through the burst enable register.
This mode uses the same 16-bit command to communicate
with the device. In addition, the response of the device at SDO
is still aligned with the corresponding SPI command. Figure 41
shows an example of SDI and SDO during burst mode.
The invalid read/write address and CRC error checking functions
operate similarly during burst mode as they do during address
mode. However, SCLK count error detection operates in a
slightly different manner. The total number of SCLK cycles
within a given CS frame are counted, and if the total is not a
multiple of 16, or a multiple of 24 when CRC is enabled, the
SCLK count error flag asserts.
SDO
COMMAND0[15:0]
RESPONSE0[15:0]
COMMAND1[15:0]
RESPONSE1[15:0]
COMMAND2[15:0]
RESPONSE2[15:0]
COMMAND3[15:0]
RESPONSE3[15:0]
SDI
CS
14960-035
Figure 41. Burst Mode Frame
SOFTWARE RESET
When in address mode, the user can initiate a software reset.
To do so, write two consecutive SPI commands, 0xA3 followed
by 0x05, targeting Register 0x0B. After a software reset, all
register values are set to default.
DAISY-CHAIN MODE
The connection of several ADGS1412 devices in a daisy-chain
configuration is possible, and Figure 42 illustrates this setup. All
devices share the same CS and SCLK line, whereas the SDO of a
device forms a connection to the SDI of the next device, creating a
shift register. In daisy-chain mode, SDO is an 8 cycle delayed
version of SDI. When in daisy-chain mode, all commands target
the switch data register. Therefore, it is not possible to make
configuration changes while in daisy-chain mode.
S4
SDI
SCLK
CS
V
L
S3
S2
S1
D4
SDO
V
L
D3
D2
D1
ADGS1412
DEVICE 1
S4
S3
S2
S1
D4
SDO
D3
D2
D1
ADGS1412
DEVICE 2
SPI
INTERFACE
SPI
INTERFACE
14960-036
Figure 42. Two ADGS1412 Devices Connected in a Daisy-Chain Configuration
ADGS1412 Data Sheet
Rev. B | Page 22 of 27
The ADGS1412 can only enter daisy-chain mode when in
address mode by sending the 16-bit SPI command, 0x2500
(see Figure 43). When the ADGS1412 receives this command,
the SDO of the device sends out the same command because
the alignment bits at SDO are 0x25, which allows multiple
daisy-connected devices to enter daisy-chain mode in a single
SPI frame. A hardware reset is required to exit daisy-chain mode.
For the timing diagram of a typical daisy-chain SPI frame, see
Figure 44. When CS goes high, Device 1 writes Command 0,
Bits[7:0] to its switch data register, Device 2 writes Command 1,
Bits[7:0] to its switches, and so on. The SPI block uses the last
eight bits it received through SDI to update the switches. After
entering daisy-chain mode, the first eight bits sent out by SDO
on each device in the chain are 0x00. When CS goes high, the
internal shift register value does not reset back to zero.
An SCLK rising edge reads in data on SDI while data is
propagated out SDO on an SCLK falling edge. The expected
number of SCLK cycles must be a multiple of eight before CS
goes high. When this is not the case, the SPI interface sends the
last eight bits received to the switch data register.
POWER-ON RESET
The digital section of the ADGS1412 goes through an initialization
phase during VL power up. This initialization also occurs after a
hardware or software reset. After VL power-up or a reset, ensure
that a minimum of 120 μs from the time of power-up or reset
before any SPI command is issued. Ensure that VL does not
drop out during the 120 μs initialization phase because it may
result in incorrect operation of the ADGS1412.
0010010100000000SDO
0010010100000000
12345678910111213141516
SDI
SCL
K
CS
14960-037
Figure 43. SPI Command to Enter Daisy-Chain Mode
SDO
COMMAND3[7:0]
8’h00
COMMAND2[7:0]
COMMAND3[7:0]
COMMAND1[7:0]
COMMAND2[7:0]
COMMAND0[7:0]
COMMAND1[7:0]
SDI
SDO3
8’h00
8’h00
8’h00
8’h00
COMMAND3[7:0]
8’h00
COMMAND2[7:0]
COMMAND3[7:0]
SDO2
DEVICE 2
DEVICE 1
DEVICE 4
DEVICE 3
CS
14960-038
NOTES
1. SDO2 AND SDO3 ARE THE OUTPUT COMMANDS FROM DEVICE 2 AND DEVICE 3, RESPECTIVELY.
Figure 44. Example of an SPI Frame Where Four ADGS1412 Devices Connect in Daisy-Chain Mode
Data Sheet ADGS1412
Rev. B | Page 23 of 27
APPLICATIONS INFORMATION
BREAK-BEFORE-MAKE SWITCHING
The ADGS1412 exhibits break-before-make switching action.
This feature allows the use of the device in multiplexer
applications. Using the device like a multiplexer can be
accomplished by externally hardwiring the device into the
desired mux configuration, as shown in Figure 45.
4 × SPST
S1
S4
S2
S3
Dx
SCLK SDI CS RESET/VL
SPI
INTERFACE
14960-045
Figure 45. An SPI Controlled Switch Configured into a 4:1 Mux
DIGITAL INPUT BUFFERS
There are input buffers present on the digital input pins (CS,
SCLK, and SDI). These buffers are active at all times. Therefore,
there is current draw from the VL supply if SCLK or SDI is toggling,
regardless of whether CS is active. For typical values of this
current draw, refer to the Specifications section and Figure 27.
POWER SUPPLY RAILS
To guarantee correct operation of the ADGS1412, 0.1 μF
decoupling capacitors are required.
The ADGS1412 can operate with bipolar supplies between
±4.5 V and ±16.5 V. The supplies on VDD and VSS do not have to
be symmetrical; however, the VDD to VSS range must not exceed
33 V. The ADGS1412 can also operate with single supplies
between 5 V and 20 V with VSS connected to GND.
The voltage range that can be supplied to VL is from 2.7 V to 5.5 V.
The device is fully specified at ±15 V, ±5 V, and +12 V analog
supply voltage ranges.
POWER SUPPLY RECOMMENDATIONS
Analog Devices, Inc., has a wide range of power management
products to meet the requirements of most high performance
signal chains.
An example of a bipolar power solution is shown in Figure 46.
The ADP5070 (dual switching regulator) generates a positive and
negative supply rail for the ADGS1412, an amplifier, and/or a
precision converter in a typical signal chain. Also shown in
Figure 46 are two optional low dropout regulators (LDOs), the
ADP7118 and ADP7182 positive and negative LDOs respectively,
that can be used to reduce the output ripple of the ADP5070 in
ultralow noise sensitive applications.
The ADM7160 can be used to generate VL voltage that is
required to power digital circuitry within the ADGS1412.
14960-042
ADM7160
LDO
+3.3V
ADP7118
LDO
+15V
ADP7182
LDO
–15V
+16.5V
–16.5V
ADP5070
+5V
INPUT
.
Figure 46. Bipolar Power Solution
Table 10. Recommended Power Management Devices
Product Description
ADP5070 1 A/0.6 A, dc-to-dc switching regulator with
independent positive and negative outputs
ADM7160 5.5 V, 200 mA, ultralow noise, linear regulator
ADP7118 20 V, 200 mA, low noise, CMOS LDO linear regulator
ADP7182 −28 V, −200 mA, low noise, LDO linear regulator
ADGS1412 Data Sheet
Rev. B | Page 24 of 27
REGISTER SUMMARY
Table 11. Register Summary
Register (Hex) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default R/W
0x01 SW_DATA Reserved SW4_EN SW3_EN SW2_EN SW1_EN 0x00 R/W
0x02 ERR_CONFIG Reserved RW_ERR_EN SCLK_ERR_EN CRC_ERR_EN 0x06 R/W
0x03 ERR_FLAGS Reserved RW_ERR_FLAG SCLK_ERR_FLAG CRC_ERR_FLAG 0x00 R
0x05
BURST_EN
Reserved
BURST_MODE_EN
0x00
R/W
0x0B SOFT_RESETB SOFT_RESETB 0x00 R/W
Data Sheet ADGS1412
Rev. B | Page 25 of 27
REGISTER DETAILS
SWITCH DATA REGISTER
Address: 0x01, Reset: 0x00, Name: SW_DATA
The switch data register controls the status of the four switches of the ADGS1412.
Table 12. Bit Descriptions for SW_DATA
Bits Bit Name Settings Description Default Access
[7:4] Reserved These bits are reserved; set these bits to 0. 0x0 R
3 SW4_EN Enable bit for SW4. 0x0 R/W
0 SW4 open.
1 SW4 closed.
2 SW3_EN Enable bit for SW3. 0x0 R/W
0 SW3 open.
1 SW3 closed.
1 SW2_EN Enable bit for SW2. 0x0 R/W
0 SW2 open.
1 SW2 closed.
0 SW1_EN Enable bit for SW1. 0x0 R/W
0 SW1 open.
1 SW1 closed.
ERROR CONFIGURATION REGISTER
Address: 0x02, Reset: 0x06, Name: ERR_CONFIG
The error configuration register allows the user to enable and disable the relevant error features as required.
Table 13. Bit Descriptions for ERR_CONFIG
Bits Bit Name Settings Description Default Access
[7:3] Reserved These bits are reserved; set these bits to 0. 0x0 R
2 RW_ERR_EN Enable bit for detecting invalid read/write address. 0x1 R/W
0
Disabled.
1
Enabled.
1 SCLK_ERR_EN Enable bit for detecting the correct number of SCLK cycles in an SPI frame.
16 SCLK cycles are expected when CRC is disabled and burst mode is
disabled. 24 SCLK cycles are expected when CRC is enabled and burst
mode is disabled. A multiple of 16 SCLK cycles are expected when CRC is
disabled and burst mode is enabled. A multiple of 24 SCLK cycles are
expected when CRC is enabled and burst mode is enabled.
0x1 R/W
0 Disabled.
1 Enabled.
0 CRC_ERR_EN Enable bit for CRC error detection. SPI frames are 24 bits wide when
enabled.
0x0 R/W
0
Disabled.
1 Enabled.
ADGS1412 Data Sheet
Rev. B | Page 26 of 27
ERROR FLAGS REGISTER
Address: 0x03, Reset: 0x00, Name: ERR_FLAGS
The error flags register allows the user to determine if an error has occurred. To clear the error flags register, write the special 16-bit SPI
command 0x6CA9 to the device. This SPI command does not trigger the invalid R/W address error. When CRC is enabled, the user must
include the correct CRC byte during the SPI write for the clear error flags register command to succeed.
Table 14. Bit Descriptions for ERR_FLAGS
Bits Bit Name Settings Description Default Access
[7:3] Reserved These bits are reserved and are set to 0. 0x0 R
2 RW_ERR_FLAG Error flag for invalid read/write address. The error flag asserts during an
SPI read if the target address does not exist. The error flag also asserts
when the target address of an SPI write does not exist or is read only.
0x0 R
0 No error.
1 Error.
1 SCLK_ERR_FLAG Error flag for the detection of the correct number of SCLK cycles in an SPI
frame.
0x0 R
0 No error.
1 Error.
0 CRC_ERR_FLAG Error flag that determines if a CRC error has occurred during a register
write.
0x0 R
0 No error.
1 Error.
BURST ENABLE REGISTER
Address: 0x05, Reset: 0x00, Name: BURST_EN
The burst enable register allows the user to enable or disable burst mode. When enabled, the user can send multiple consecutive SPI
commands without deasserting CS.
Table 15. Bit Descriptions for BURST_EN
Bits Bit Name Settings Description Default Access
[7:1] Reserved These bits are reserved; set these bits to 0. 0x0 R
0 BURST_MODE_EN Burst mode enable bit. 0x0 R/W
0 Disabled.
1 Enabled.
SOFTWARE RESET REGISTER
Address: 0x0B, Reset: 0x00, Name: SOFT_RESETB
Use the software reset register to perform a software reset. Consecutively, write 0xA3 followed by 0x05 to this register, and the registers of
the device reset to their default state.
Table 16. Bit Descriptions for SOFT_RESETB
Bits Bit Name Settings Description Default Access
[7:0]
SOFT_RESETB
To perform a software reset, consecutively write 0xA3 followed by 0x05 to
this register.
0x0
R
Data Sheet ADGS1412
Rev. B | Page 27 of 27
OUTLINE DIMENSIONS
0.50
BSC
0.50
0.40
0.30
COMPLIANT
TO
JEDEC STANDARDS M O-220- V GGD- 8.
BOTTOM VIEW
TOP VIEW
4.10
4.00 SQ
3.90
1.00
0.95
0.90 0. 05 M AX
0.02 NO M
0.20 REF
COPLANARITY
0.08
PIN 1
INDICATOR
1
24
7
12
13
18
19
6
02-09-2017-A
0.30
0.25
0.18
0.20 MIN
2.70
2.60 SQ
2.50
EXPOSED
PAD
PKG-004677
SEATING
PLANE
PIN 1
INDIC ATOR AREA O P TIONS
(SEE DETAIL A)
DETAIL A
(JEDEC 95)
FO R P ROPE R CONNECT IO N OF
THE EXPOSED PAD, REFER TO
THE P IN CO NFI G URATI ON AND
FUNCT IO N DE S CRIPT IO NS
SECTION OF THIS DATA SHEET.
Figure 47. 24-Lead Lead Frame Chip Scale Package [LFCSP]
4 mm × 4 mm Body and 0.95 mm Package Height
(CP-24-17)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
ADGS1412BCPZ −40°C to +125°C 24-Lead Lead Frame Chip Scale Package [LFCSP] CP-24-17
ADGS1412BCPZ-RL7 −40°C to +125°C 24-Lead Lead Frame Chip Scale Package [LFCSP] CP-24-17
EVAL-ADGS1412SDZ Evaluation Board
1 Z = RoHS Compliant Part.
©2016–2017 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D14960-0-8/17(B)
