FUJITSU SEMICONDUCTOR DATA SHEET DS07-13727-1E 16-bit Proprietary Microcontroller CMOS F2MC-16LX MB90435 Series MB90437L (S) /438L (S) /F438L (S) MB90439 (S) /F439 (S) /V540G DESCRIPTION The MB90435 series with FLASH ROM is specially designed for industrial applications. The instruction set by F2MC-16LX CPU core inherits an AT architecture of the F2MC* family with additional instruction sets for high-level languages, extended addressing mode, enhanced multiplication/division instructions, and enhanced bit manipulation instructions.The micro controller has a 32-bit accumulator for processing long word data. The MB90435 series has peripheral resources of 8/10-bit A/D converters, UART (SCI) , extended I/O serial interfaces, 8/16-bit timer, I/O timer (input capture (ICU) , output compare (OCU) ) . * : F2MC stands for FUJITSU Flexible Microcontroller. FEATURES * Clock Embedded PLL clock multiplication circuit Operating clock (PLL clock) can be selected from : divided-by-2 of oscillation or one to four times the oscillation Minimum instruction execution time : 62.5 ns (operation at oscillation of 4 MHz, four times the oscillation clock, VCC of 5.0 V) Subsystem Clock : 32 kHz (Continued) PACKAGES 100-pin Plastic QFP 100-pin Plastic LQFP (FPT-100P-M06) (FPT-100P-M05) MB90435 Series * Instruction set to optimize controller applications Rich data types (bit, byte, word, long word) Rich addressing mode (23 types) Enhanced signed multiplication/division instruction and RETI instruction functions Enhanced precision calculation realized by the 32-bit accumulator * Instruction set designed for high level language (C language) and multi-task operations Adoption of system stack pointer Enhanced pointer indirect instructions Barrel shift instructions * Program patch function (for two address pointers) * Enhanced execution speed : 4-byte Instruction queue * Enhanced interrupt function : 8 levels, 34 factors * Automatic data transmission function independent of CPU operation Extended intelligent I/O service function (EI2OS) * Embedded ROM size and types Mask ROM : 64 Kbytes / 128 Kbytes / 256 Kbytes Flash ROM : 128 Kbytes/256 Kbytes Embedded RAM size : 2 Kbytes/4 Kbytes/6 Kbytes/8 Kbytes (evaluation chip) * Flash ROM Supports automatic programming, Embedded Algorithm TM* Write/Erase/Erase-Suspend/Resume commands A flag indicating completion of the algorithm Hard-wired reset vector available in order to point to a fixed boot sector in Flash Memory Erase can be performed on each block Block protection with external programming voltage * Low-power consumption (stand-by) mode Sleep mode (mode in which CPU operating clock is stopped) Stop mode (mode in which oscillation is stopped) CPU intermittent operation mode Clock mode Hardware stand-by mode * Process 0.5 m CMOS technology * I/O port General-purpose I/O ports : 81 ports * Timer Watchdog timer : 1 channel 8/16-bit PPG timer : 8/16-bit x 4 channels 16-bit re-load timer : 2 channels * 16-bit I/O timer 16-bit free-run timer : 1 channel Input capture : 8 channels Output compare : 4 channels * Extended I/O serial interface : 1 channel * UART 0 With full-duplex double buffer (8-bit length) Clock asynchronized or clock synchronized (with start/stop bit) transmission can be selectively used. (Continued) 2 MB90435 Series (Continued) * UART 1 With full-duplex double buffer (8-bit length) Clock asynchronized or clock synchronized serial (extended I/O serial) can be used. * External interrupt circuit (8 channels) A module for starting an extended intelligent I/O service (EI2OS) and generating an external interrupt which is triggered by an external input. * Delayed interrupt generation module Generates an interrupt request for switching tasks. * 8/10-bit A/D converter (8 channels) 8/10-bit resolution can be selectively used. Starting by an external trigger input. Conversion time : 26.3 s * External bus interface : Maximum address space 16 Mbytes * Package: QFP-100, LQFP-100 * : Embedded Algorithm is a trade mark of Advanced Micro Devices Inc. 3 MB90435 Series PRODUCT LINEUP Features MB90437L (S) *1 /438L (S) /439 (S) MB90F438L (S) /F439 (S) F2MC-16LX CPU CPU System clock MB90V540G On-chip PLL clock multiplier (x1, x2, x3, x4, 1/2 when PLL stop) Minimum instruction exection time : 62.5 ns (4 MHz osc. PLL x 4) ROM Flash memory MB90F438L(S) : 128 Kbytes MB90F439(S) : 256 Kbytes Mask ROM : MB90437L(S): 64 Kbytes MB90438L(S): 128 Kbytes MB90439(S): 256 Kbytes External RAM MB90F438L(S) : 4 Kbytes MB90F439(S) : 6 Kbytes MB90437L(S): 2 Kbytes MB90438L(S): 4 Kbytes MB90439(S): 6 Kbytes 8 Kbytes Clocks MB90F438L/F439 : Two clocks system MB90F438LS/F439S : One clock system MB90437L/438L/439 : Two clocks system MB90437LS/438LS/439S : One clock system Two clocks system*2 Operating voltage range *5 -40 C to 105 C Temperature range Package Emulator-specify power supply*3 QFP100, LQFP100 PGA-256 None UART0 Full duplex double buffer Support asynchronous/synchronous (with start/stop bit) transfer Baud rate : 4808/5208/9615/10417/19230/38460/62500/500000 bps (asynchronous) 500 K/1 M/2 Mbps (synchronous) at System clock = 16 MHz UART1 (SCI) Full duplex double buffer Asynchronous (start-stop synchronized) and CLK-synchronous communication Baud rate : 1202/2404/4808/9615/19230/31250/38460/62500 bps (asynchronous) 62.5 K/125 K/250 K/500 K/1 M/2 Mbps (synchronous) at 6, 8, 10, 12, 16 MHz Serial I/O Transfer can be started from MSB or LSB Supports internal clock synchronized transfer and external clock synchronized transfer Supports positive-edge and nagative-edge clock synchronization Baud rate : 31.25 K/62.5 K/125 K/500 K/1 Mbps at System clock = 16 MHz A/D Converter 10-bit or 8-bit resolution 8 input channels Conversion time : 26.3 s (per one channel) (Continued) 4 MB90435 Series (Continued) Features MB90F438L (S) /F439 (S) MB90437L (S) *1 /438L (S) /439 (S) MB90V540G 16-bit Reload Timer (2 channels) Operation clock frequency : fsys/21, fsys/23, fsys/25 (fsys = System clock frequency) Supports External Event Count function Signals an interrupt when overflow 16-bit I/O Timer Supports Timer Clear when a match with Output Compare (Channel 0) Operation clock freq. : fsys/22, fsys/24, fsys/26, fsys/28 (fsys = System clock freq.) Signals an interrupt when a match with 16-bit I/O Timer 16-bit Output Compare Four 16-bit compare registers (4 channels) A pair of compare registers can be used to generate an output signal 16-bit Input Capture (8 channels) Rising edge, falling edge or rising & falling edge sensitive Four 16-bit Capture registers Signals an interrupt upon external event 8/16-bit Programmable Pulse Generator (4 channels) Supports 8-bit and 16-bit operation modes Eight 8-bit reload counters Eight 8-bit reload registers for L pulse width Eight 8-bit reload registers for H pulse width A pair of 8-bit reload counters can be configured as one 16-bit reload counter or as 8-bit prescaler plus 8-bit reload counter 4 output pins Operation clock freq. : fsys, fsys/21, fsys/22, fsys/23, fsys/24 or 128 s@fosc = 4 MHz (fsys = System clock frequency, fosc = Oscillation clock frequency) 32 kHz Sub-clock Sub-clock for low power operation External Interrupt (8 channels) Can be programmed edge sensitive or level sensitive External bus interface External access using the selectable 8-bit or 16-bit bus is enabled (external bus mode.) I/O Ports Virtually all external pins can be used as general purpose I/O All push-pull outputs and schmitt trigger inputs Bit-wise programmable as input/output or peripheral signal Flash Memory Supports automatic programming, Embeded Algorithm TM*4 Write/Erase/Erase-Suspend/Erase-Resume commands A flag indicating completion of the algorithm Number of erase cycles : 10,000 times Data retention time : 10 years Boot block configuration Erase can be performed on each block Block protection by externally programmed voltage *1 : Under development *2 : If the one clock system is used, equip X0A and X1A with clocks from the tool side. *3 : It is setting of DIP switch S2 when Emulator pod (MB2145-507) is used.Please refer to the MB2145-507 hardware manual (2.7 Emulator-specific Power Pin) about details. *4 : Embedded Algorithm is a trade mark of Advanced Micro Devices Inc. *5 : OPERATING VOLTAGE RANGE Products Operation guarantee range MB90F439 (S) /439 (S) /V540G 4.5 V to 5.5 V MB90F438L (S) /437L (S) /438L (S) 3.5 V to 5.5 V 5 MB90435 Series PIN ASSIGNMENT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 X0A X1A PA0 RST P97 P96 P95 P94 P93/INT3 P92/INT2 P91/INT1 P90/INT0 P87/TOT1 P86/TIN1 P85/OUT1 P84/OUT0 P83/PPG3 P82/PPG2 P81/PPG1 P80/PPG0 P77/OUT3/IN7 P76/OUT2/IN6 P75/IN5 P74/IN4 P73/IN3 P72/IN2 P71/IN1 P70/IN0 HST MD2 P53/INT6 P54/INT7 P55/ADTG AVCC AVRH AVRL AVSS P60/AN0 P61/AN1 P62/AN2 P63/AN3 VSS P64/AN4 P65/AN5 P66/AN6 P67/AN7 P56/TIN0 P57/TOT0 MD0 MD1 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 P20/A16 P21/A17 P22/A18 P23/A19 P24/A20 P25/A21 P26/A22 P27/A23 P30/ALE P31/RD VSS P32/WRL/WR P33/WRH P34/HRQ P35/HAK P36/RDY P37/CLK P40/SOT0 P41/SCK0 P42/SIN0 P43/SIN1 P44/SCK1 VCC P45/SOT1 P46/SOT2 P47/SCK2 C P50/SIN2 P51/INT4 P52/INT5 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 P17/AD15 P16/AD14 P15/AD13 P14/AD12 P13/AD11 P12/AD10 P11/AD09 P10/AD08 P07/AD07 P06/AD06 P05/AD05 P04/AD04 P03/AD03 P02/AD02 P01/AD01 P00/AD00 VCC X1 X0 VSS (TOP VIEW) (FPT-100P-M06) (Continued) 6 MB90435 Series (Continued) 100 P21/A17 99 P20/A16 98 P17/AD15 97 P16/AD14 96 P15/AD13 95 P14/AD12 94 P13/AD11 93 P12/AD10 92 P11/AD09 91 P10/AD08 90 P07/AD07 89 P06/AD06 88 P05/AD05 87 P04/AD04 86 P03/AD03 85 P02/AD02 84 P01/AD01 83 P00/AD00 82 VCC 81 X1 80 X0 79 VSS 78 X0A 77 X1A 76 PA0 (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 RST P97 P96 P95 P94 P93/INT3 P92/INT2 P91/INT1 P90/INT0 P87/TOT1 P86/TIN1 P85/OUT1 P84/OUT0 P83/PPG3 P82/PPG2 P81/PPG1 P80/PPG0 P77/OUT3/IN7 P76/OUT2/IN6 P75/IN5 P74/IN4 P73/IN3 P72/IN2 P71/IN1 P70/IN0 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 P50/SIN2 P51/INT4 P52/INT5 P53/INT6 P54/INT7 P55/ADTG AVCC AVRH AVRL AVSS P60/AN0 P61/AN1 P62/AN2 P63/AN3 VSS P64/AN4 P65/AN5 P66/AN6 P67/AN7 P56/TIN0 P57/TOT0 MD0 MD1 MD2 HST P22/A18 P23/A19 P24/A20 P25/A21 P26/A22 P27/A23 P30/ALE P31/RD VSS P32/WRL/WR P33/WRH P34/HRQ P35/HAK P36/RDY P37/CLK P40/SOT0 P41/SCK0 P42/SIN0 P43/SIN1 P44/SCK1 VCC P45/SOT1 P46/SOT2 P47/SCK2 C (FPT-100P-M05) 7 MB90435 Series PIN DESCRIPTION Pin No. Pin name Circuit type Function LQFP*2 QFP*1 80 81 82 83 X0 X1 78 80 X0A 77 79 X1A 75 77 RST B External reset request input pin 50 52 HST C Hardware standby input pin A High speed crystal oscillator input pins (Oscillation) Low speed crystal oscillator input pins. For the one clock system parts, perfom external pull-down processing. A (Oscillation) Low speed crystal oscillator input pins. For the one clock system parts, leave it open. P00 to P07 83 to 90 85 to 92 I AD00 to AD07 I/O pins for 8 lower bits of the external address/data bus. This function is enabled when the external bus is enabled. P10 to P17 General I/O port with programmable pull-up. This function is enabled in the single-chip mode. 91 to 98 93 to 100 99 to 6 I AD08 to AD15 I/O pins for 8 higher bits of the external address/data bus. This function is enabled when the external bus is enabled. P20 to P27 General I/O port with programmable pull-up. In external bus mode, this function is valid when the corresponding bits in the external address output control register (HACR) are set to "1". 1 to 8 I A16 to A23 P30 7 8 10 9 I 8-bit output pins for A16 to A23 at the external address bus. In external bus mode, this function is valid when the corresponding bits in the external address output control register (HACR) are set to "0". General I/O port with programmable pull-up. This function is enabled in the single-chip mode. ALE Address latch enable output pin. This function is enabled when the external bus is enabled. P31 General I/O port with programmable pull-up. This function is enabled in the single-chip mode. 10 12 General I/O port with programmable pull-up. This function is enabled in the single-chip mode. I RD Read strobe output pin for the data bus. This function is enabled when the external bus is enabled. P32 General I/O port with programmable pull-up. This function is enabled in the single-chip mode or when the WR/WRL pin output is disabled. WRL WR I Write strobe output pin for the data bus. This function is enabled when both the external bus and the WR/WRL pin output are enabled. WRL is write-strobe output pin for the lower 8 bits of the data bus in 16-bit access. WR is write-strobe output pin for the 8 bits of the data bus in 8-bit access. (Continued) 8 MB90435 Series Pin No. LQFP*2 QFP*1 Pin name Circuit type General I/O port with programmable pull-up. This function is enabled in the single-chip mode, external bus 8-bit mode or when WRH pin output is disabled. P33 11 12 13 14 15 16 13 I WRH Write strobe output pin for the 8 higher bits of the data bus. This function is enabled when the external bus is enabled, when the external bus 16-bit mode is selected, and when the WRH output pin is enabled. P34 General I/O port with programmable pull-up. This function is enabled in the single-chip mode or when the hold function is disabled. 14 I HRQ Hold request input pin. This function is enabled when both the external bus and the hold functions are enabled. P35 General I/O port with programmable pull-up. This function is enabled in the single-chip mode or when the hold function is disabled. 15 I HAK Hold acknowledge output pin. This function is enabled when both the external bus and the hold functions are enabled. P36 General I/O port with programmable pull-up. This function is enabled in the single-chip mode or when the external ready function is disabled. 16 I RDY Ready input pin. This function is enabled when both the external bus and the external ready functions are enabled. P37 General I/O port with programmable pull-up. This function is enabled in the single-chip mode or when the CLK output is disabled. 17 H CLK CLK output pin. This function is enabled when both the external bus and CLK outputs are enabled. P40 General I/O port. This function is enabled when UART0 disables the serial data output. 18 G SOT0 P41 17 19 G SCK0 P42 18 20 19 21 Function SIN0 General I/O port. This function is enabled when UART0 disables serial clock output. Serial clock I/O pin for UART0. This function is enabled when UART0 enables the serial clock output. General I/O port. This function is always enabled. G P43 SIN1 Serial data output pin for UART0. This function is enabled when UART0 enables the serial data output. Serial data input pin for UART0. Set the corresponding Port Direction Register to input if this function is used. General I/O port. This function is always enabled. G Serial data input pin for UART1. Set the corresponding Port Direction Register to input if this function is used. (Continued) 9 MB90435 Series Pin No. LQFP*2 QFP*1 Pin name Circuit type P44 20 22 G SCK1 P45 22 23 24 24 G General I/O port. This function is enabled when the Extended I/O serial interface disables the serial data output. G SOT2 Serial data output pin for the Extended I/O serial interface. This function is enabled when the Extended I/O serial interface enables the serial data output. P47 General I/O port. This function is enabled when the Extended I/O serial interface disables the clock output. G P50 SIN2 31 33 INT4 to INT7 D D 41 to 44 38 to 41 E General I/O port. This function is enabled when the analog input enable register specifies a port. Analog input pins for the 8/10-bit A/D converter. This function is enabled when the analog input enable register specifies A/D. P64 to P67 General I/O port. The function is enabled when the analog input enable register specifies a port. 43 to 46 E P56 47 Trigger input pin for the A/D converter. Set the corresponding Port Direction Register to input if this function is used. AN0 to AN3 AN4 to AN7 45 External interrupt request input pins for INT4 to INT7. Set the corresponding Port Direction Register to input if this function is used. General I/O port. This function is always enabled. D P60 to P63 36 to 39 Serial data input pin for the Extended I/O serial interface . Set the corresponding Port Direction Register to input if this function is used. General I/O port. This function is always enabled. P55 ADTG Serial clock pulse I/O pin for the Extended I/O serial interface . This function is enabled when the Extended I/O serial interface enables the Serial clock output. General I/O port. This function is always enabled. P51 to P54 29 to 32 General I/O port. This function is enabled when UART1 disables the serial data output. P46 26 27 to 30 Serial clock pulse I/O pin for UART1. This function is enabled when UART1 enables the serial clock output. Serial data output pin for UART1. This function is enabled when UART1 enables the serial data output. 25 28 General I/O port. This function is enabled when UART1 disables the clock output. SOT1 SCK2 26 Function TIN0 Analog input pins for the 8/10-bit A/D converter. This function is enabled when the analog input enable register specifies A/D. General I/O port. This function is always enabled. D Event input pin for the 16-bit reload timers 0. Set the corresponding Port Direction Register to input if this function is used. (Continued) 10 MB90435 Series Pin No. LQFP*2 QFP*1 Pin name Circuit type P57 46 48 D TOT0 P70 to P75 51 to 56 53 to 58 IN0 to IN5 57 , 58 59 , 62 59 , 60 61 to 64 D D P80 to P83 General I/O ports. This function is enabled when 8/16-bit PPG disables the waveform output. PPG0 to PPG3 D D TIN1 D D TOT1 P90 to P93 67 to 70 69 to 72 71 73 INT0 to INT3 P94 Waveform output pins for output compares OCU0 and OCU1. This function is enabled when the OCU enables the waveform output. General I/O port. This function is always enabled. P87 68 Output pins for 8/16-bit PPGs. This function is enabled when 8/16-bit PPG enables the waveform output. General I/O ports. This function is enabled when the OCU disables the waveform output. P86 66 Event output pins for output compares OCU2 and OCU3. This function is enabled when the OCU enables the waveform output. Trigger input pins for input captures ICU6 and ICU7. Set the corresponding Port Direction Register to input and disable the OCU waveform output if this function is used. 65 , 66 67 Trigger input pins for input captures ICU0 to ICU5. Set the corresponding Port Direction Register to input if this function is used. IN6 , IN7 OUT0 , OUT1 65 Output pin for the 16-bit reload timers 0. This function is enabled when the 16-bit reload timers 0 enables the output. General I/O ports. This function is enabled when the OCU disables the waveform output. P84 , P85 63 , 64 General I/O port. This function is enabled when the 16-bit reload timers 0 disables the output. General I/O ports. This function is always enabled. P76 , P77 OUT2 , OUT3 Function Input pin for the 16-bit reload timers 1. Set the corresponding Port Direction Register to input if this function is used. General I/O port. This function is enabled when the 16-bit reload timers 0 disables the output. Output pin for the 16-bit reload timers 1.This function is enabled when the 16-bit reload timers 1 enables the output. General I/O port. This function is always enabled. D External interrupt request input pins for INT0 to INT3. Set the corresponding Port Direction Register to input if this function is used. D General I/O port. (Continued) 11 MB90435 Series (Continued) Pin No. Pin name Circuit type 74 P95 D General I/O port. 73 75 P96 D General I/O port. 74 76 P97 D General I/O port. 76 78 PA0 D General I/O port. 32 34 AVCC Power supply Power supply pin for the A/D Converter. This power supply must be turned on or off while a voltage higher than or equal to AVCC is applied to VCC. 35 37 AVSS Power supply Power supply pin for the A/D Converter. 33 35 AVRH Power supply External reference voltage input pin for the A/D Converter. This power supply must be turned on or off while a voltage higher than or equal to AVRH is applied to AVCC. 34 36 AVRL Power supply External reference voltage input pin for the A/D Converter. 47 48 49 50 MD0 MD1 C Input pins for specifying the operating mode. The pins must be directly connected to VCC or VSS. 49 51 MD2 F Input pin for specifying the operating mode. The pin must be directly connected to VCC or VSS. 25 27 C Power supply stabilization capacitor pin. It should be connected externally to an 0.1 F ceramic capacitor. 21, 82 23, 84 VCC Power supply Input pin for power supply (5.0 V) . 9, 40, 79 11, 42, 81 VSS Power supply Input pin for power supply (0.0 V) . LQFP*2 QFP*1 72 *1 : FPT-100P-M06 *2 : FPT-100P-M05 12 Function MB90435 Series I/O CIRCUIT TYPE Circuit type Diagram Remarks X1,X1A Clock input * High-speed oscillation feedback resistor : 1 M approx. * Low-speed oscillation feedback resistor : 10 M approx. X0,X0A A Hard, soft standby control * Hysteresis input * Pull-up resistor : 50 k approx. B R (Pull-up) R HYS input * Hysteresis input R C HYS input * CMOS level output * CMOS Hysteresis input VCC P-ch D N-ch R HYS input (Continued) 13 MB90435 Series Circuit type Diagram Remarks VCC P-ch * CMOS level output * CMOS Hysteresis input * Analog input N-ch E P-ch Analog input N-ch R HYS input R F HYS input * Hysteresis input * Pull-down Resistor : 50 k approx. (except FLASH devices) R (Pull-down) * CMOS level output * CMOS Hysteresis input * TTL level input (FLASH devices in FLASH writer mode only) VCC P-ch N-ch G R HYS input R T TTL level input (Continued) 14 MB90435 Series (Continued) Circuit type Diagram Remarks Pull-up ON/OFF select signal VCC * CMOS level output * CMOS Hysteresis input * Programmable pull-up resistor : 50 k approx. VCC P-ch P-ch H N-ch R HYS input Pull-up ON/OFF select signal VCC VCC P-ch P-ch * CMOS level output * CMOS Hysteresis input * TTL level input (FLASH devices in FLASH writer mode only) * Programmable pull-up resistor : 50 k approx. N-ch I R HYS input R T TTL level input 15 MB90435 Series HANDLING DEVICES (1) Preventing latch-up CMOS IC chips may suffer latch-up under the following conditions : * A voltage higher than VCC or lower than VSS is applied to an input or output pin. * A voltage higher than the rated voltage is applied between VCC and VSS. * The AVcc power supply is applied before the VCC voltage. Latch-up may increase the power supply current drastically, causing thermal damage to the device. For the same reason, care must also be taken in not allowing the analog power-supply voltage (AVCC, AVRH) to exceed the digital power-supply voltage. (2) Handling unused pins Leaving unused input pins open may result in misbehavior or latch up and possible permanent damage of the device. Therefor they must be pulled up or pulled down through resistors. In this case those resistors should be more than 2 k. Unused bi-directional pins should be set to the output state and can be left open, or the input state with the above described connection. (3) Using external clock To use external clock, drive X0 pin only and leave X1 pin unconnected. Below is a diagram of how to use external clock. MB90435 Series X0 Open X1 (4) Use of the sub-clock Use one clock system parts when the sub-clock is not used. In that case, pull-down the pin X0A and leave the pin X1A open. When using two clock system parts, a 32 kHz oscillator has to be connected to the X0A and X1A pins. (5) Power supply pins (VCC/VSS) In products with multiple VCC or VSS pins, the pins of a same potential are internally connected in the device to avoid abnormal operations including latch-up. However you must connect the pins to an external power and a ground line to lower the electro-magnetic emission level to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total current rating. Make sure to connect VCC and VSS pins via the lowest impedance to power lines. It is recommended to provide a bypass capacitor of around 0.1 F between VCC and VSS pins near the device. VCC VSS VCC VSS VSS VCC MB90435 Series VCC VSS VSS 16 VCC MB90435 Series (6) Pull-up/down resistors The MB90435 Series does not support internal pull-up/down resistors (except Port0 - Port3 : pull-up resistors) . Use external components where needed. (7) Crystal Oscillator Circuit Noises around X0 or X1 pins may be possible causes of abnormal operations. Make sure to provide bypass capacitors via the shortest distances from X0, X1 pins, crystal oscillator (or ceramic resonator) and ground lines, and make sure, to the utmost effort, that lines of oscillation circuits do not cross the lines of other circuits. It is highly recommended to provide a printed circuit board artwork surrounding X0 and X1 pins with a ground area for stabilizing the operation. (8) Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs Make sure to turn on the A/D converter power supply (AVCC, AVRH, AVRL) and analog inputs (AN0 to AN7) after turning-on the digital power supply (VCC) . Turn-off the digital power after turning off the A/D converter supply and analog inputs. In this case, make sure that the voltage does not exceed AVRH or AVCC (turning on/off the analog and digital power supplies simultaneously is acceptable) . (9) Connection of Unused Pins of A/D Converter Connect unused pins of A/D converter to AVCC = VCC, AVSS = AVRH = VSS. (10) N.C. Pin The N.C. (internally connected) pin must be opened for use. (11) Notes on Energization To prevent the internal regulator circuit from malfunctioning, set the voltage rise time during energization at 50 s or more (0.2 V to 2.7 V) . (12) Initialization In the device, there are internal registers which are initialized only by a power-on reset. To initialize these registers, please turn on the power again. (13) Directions of "DIV A, Ri" and "DIVW A, RWi" instructions In the Signed multiplication and division instructions ("DIV A, Ri" and "DIVW A, RWi") , the value of the corresponding bank register (DTB, ADB, USB, SSB) is set in "00H". If the values of the corresponding bank registers (DTB, ADB, USB, SSB) are set to other than "00H", the remainder by the execution result of the instruction is not stored in the register of the instruction operand. (14) Using REALOS The use of EI2OS is not possible with the REALOS real time operating system. (15) Caution on Operations during PLL Clock Mode If the PLL clock mode is selected, the microcontroller attempt to be working with the self-oscillating circuit even when there is no external oscillator or external clock input is stopped. Performance of this operation, however, cannot be guaranteed. 17 MB90435 Series BLOCK DIAGRAM X0, X1 X0A, X1A RST Clock Controller F2MC 16LX CPU HST 16-bit I/O Timer RAM 2 K/4 K/6 K/8 K 16-bit Input Capture 8 ch. ROM/Flash 64K/128 K/256 K (ROM only) 16-bit Output Compare 4 ch. IN0 to IN5 IN6/OUT2, IN7/OUT3 OUT0, OUT1 Prescaler 8/16-bit PPG 4 ch. SOT0 SCK0 UART0 PPG0 to PPG3 SIN0 SOT1 SCK1 UART1 (SCI) SIN1 FMC-16 Bus Prescaler 16-bit Reload Timer 2 ch. TIN0, TIN1 TOT0, TOT1 AD00 to AD15 A16 to A23 ALE Prescaler SOT2 SCK2 Serial I/O RD External Bus Interface WRL WRH HRQ SIN2 HAK RDY AVCC CLK AVSS AN0 to AN7 AVRH AVRL ADTG 18 10-bit A/D Converter 8 ch. External Interrupt 8 ch. INT0 to INT7 MB90435 Series MEMORY MAP The memory space of the MB90435 Series is shown below. MB90V540G MB90F437L (S)* FFFFFFH FFFFFFH ROM (FF bank) FF0000H FEFFFFH MB90F438L (S)/438L (S) FFFFFFH ROM (FF bank) FF0000H ROM (FF bank) FF0000H FEFFFFH ROM (FE bank) FE0000H FDFFFFH FD0000H FCFFFFH MB90F439 (S) /439 (S) FFFFFFH ROM (FF bank) FF0000H FEFFFFH ROM (FE bank) FE0000H ROM (FD bank) External External ROM (FC bank) ROM (FE bank) FE0000H FDFFFFH FC0000H FD0000H FCFFFFH ROM (FD bank) ROM (FC bank) FC0000H External External 00FFFFH 00FFFFH 004000H ROM (Image of FF bank) 003FFFH 004000H 003FFFH 00FFFFH 004000H External 002000H 00FFFFH 004000H 002000H ROM (Image of FF bank) 003FFFH Peripheral 003900H 003900H External ROM (Image of FF bank) 003FFFH Peripheral Peripheral 003900H ROM (Image of FF bank) Peripheral 003900H External 002100H External 0020FFH 001FF5H 001FF0H 0018FFH ROM correction 0010FFH RAM 8 K RAM 2 K 000100H 000100H External 0000BFH 000000H RAM 6 K 0008FFH Peripheral 000000H 000100H External 0000BFH Peripheral RAM 4 K 000100H External 0000BFH 000000H Peripheral External 0000BFH 000000H Peripheral * : Under development Note : The high-order portion of bank 00 gives the image of the FF bank ROM to make the small model of the C compiler effective. Since the low-order 16 bits address are the same, the table in ROM can be referenced without using the "far" specification in the pointer declaration. For example, an attempt to access 00C000H accesses the value at FFC000H in ROM.The ROM area in bank FF exceeds 48 Kbytes, and its entire image cannot be shown in bank 00.The image between FF4000H and FFFFFFH is visible in bank 00, while the image between FF0000H and FF3FFFH is visible only in bank FF. 19 MB90435 Series I/O MAP Address Register 00H Port 0 data register PDR0 R/W Port 0 XXXXXXXXB 01H Port 1 data register PDR1 R/W Port 1 XXXXXXXXB 02H Port 2 data register PDR2 R/W Port 2 XXXXXXXXB 03H Port 3 data register PDR3 R/W Port 3 XXXXXXXXB 04H Port 4 data register PDR4 R/W Port 4 XXXXXXXXB 05H Port 5 data register PDR5 R/W Port 5 XXXXXXXXB 06H Port 6 data register PDR6 R/W Port 6 XXXXXXXXB 07H Port 7 data register PDR7 R/W Port 7 XXXXXXXXB 08H Port 8 data register PDR8 R/W Port 8 XXXXXXXXB 09H Port 9 data register PDR9 R/W Port 9 XXXXXXXXB 0AH Port A data register PDRA R/W Port A _ _ _ _ _ _ _XB 0BH to 0FH Abbreviation Access Resource name Initial value Reserved 10H Port 0 direction register DDR0 R/W Port 0 0 0 0 0 0 0 0 0B 11H Port 1 direction register DDR1 R/W Port 1 0 0 0 0 0 0 0 0B 12H Port 2 direction register DDR2 R/W Port 2 0 0 0 0 0 0 0 0B 13H Port 3 direction register DDR3 R/W Port 3 0 0 0 0 0 0 0 0B 14H Port 4 direction register DDR4 R/W Port 4 0 0 0 0 0 0 0 0B 15H Port 5 direction register DDR5 R/W Port 5 0 0 0 0 0 0 0 0B 16H Port 6 direction register DDR6 R/W Port 6 0 0 0 0 0 0 0 0B 17H Port 7 direction register DDR7 R/W Port 7 0 0 0 0 0 0 0 0B 18H Port 8 direction register DDR8 R/W Port 8 0 0 0 0 0 0 0 0B 19H Port 9 direction register DDR9 R/W Port 9 0 0 0 0 0 0 0 0B 1AH Port A direction register DDRA R/W Port A _ _ _ _ _ _ _0B 1BH Analog Input Enable register ADER R/W Port 6, A/D 1 1 1 1 1 1 1 1B 1CH Port 0 pull-up control register PUCR0 R/W Port 0 0 0 0 0 0 0 0 0B 1DH Port 1 pull-up control register PUCR1 R/W Port 1 0 0 0 0 0 0 0 0B 1EH Port 2 pull-up control register PUCR2 R/W Port 2 0 0 0 0 0 0 0 0B 1FH Port 3 pull-up control register PUCR3 R/W Port 3 0 0 0 0 0 0 0 0B 20H Serial Mode Control Register 0 UMC0 R/W 21H Serial Status Register 0 USR0 R/W 22H Serial input data register 0/ Serial output data register 0 UIDR0/ UODR0 R/W 23H Rate and data register 0 URD0 R/W 0 0 0 0 0 1 0 0B 0 0 0 1 0 0 0 0B UART0 XXXXXXXXB 0 0 0 0 0 0 0XB (Continued) 20 MB90435 Series Address Register 24H Serial mode register 1 SMR1 R/W 0 0 0 0 0 0 0 0B 25H Serial control register 1 SCR1 R/W 0 0 0 0 0 1 0 0B 26H Serial input data register 1/ Serial output data register 1 SIDR1/ SODR1 R/W 27H Serial status register 1 SSR1 R/W 0 0 0 0 1_0 0B 28H UART1 prescaler control register U1CDCR R/W 0_ _ _1 1 1 1B 29H Serial Edge select register SES1 R/W _ _ _ _ _ _ _0B 0_ _ _1 1 1 1B 2AH Abbreviation Access Resource name UART1 Initial value XXXXXXXXB Prohibited 2BH Serial I/O prescaler SCDCR R/W 2CH Serial mode control register SMCS R/W _ _ _ _0 0 0 0B Extended I/O Serial Interface 2DH Serial mode control register SMCS R/W 2EH Serial data register SDR R/W XXXXXXXXB 2FH Serial Edge select register SES2 R/W _ _ _ _ _ _ _0B 30H External interrupt enable register ENIR R/W 0 0 0 0 0 0 0 0B 31H External interrupt request register EIRR R/W 32H External interrupt level register ELVR R/W 33H External interrupt level register ELVR R/W 0 0 0 0 0 0 0 0B 34H A/D control status register 0 ADCS0 R/W 0 0 0 0 0 0 0 0B 35H A/D control status register 1 ADCS1 R/W 36H A/D data register 0 ADCR0 R 37H A/D data register 1 ADCR1 R/W 38H PPG0 operation mode control register PPGC0 R/W 39H PPG1 operation mode control register PPGC1 R/W 3AH PPG0/1 clock selection register PPG01 R/W 3BH External Interrupt A/D Converter 0 0 0 0 0 0 1 0B XXXXXXXXB 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B XXXXXXXXB 0 0 0 0 1 _ XXB 0 _ 0 0 0 _ _ 1B 16-bit Programmable Pulse 0 _ 0 0 0 0 0 1B Generator 0/1 0 0 0 0 0 0 _ _B Prohibited 3CH PPG2 operation mode control register PPGC2 R/W 3DH PPG3 operation mode control register PPGC3 R/W 3EH PPG2/3 Clock Selection Register PPG23 R/W 3FH 0 _ 0 0 0 _ _1B 16-bit Programmable Pulse 0 _ 0 0 0 0 0 1B Generator 2/3 0 0 0 0 0 0 _ _B Prohibited 40H PPG4 operation mode control register PPGC4 R/W 41H PPG5 operation mode control register PPGC5 R/W 42H PPG4/5 clock selection register PPG45 R/W 43H 0 _ 0 0 0 _ _ 1B 16-bit Programmable Pulse 0 _ 0 0 0 0 0 1B Generator 4/5 0 0 0 0 0 0 _ _B Prohibited 44H PPG6 operation mode control register PPGC6 R/W 45H PPG7 operation mode control register PPGC7 R/W 46H PPG6/7 clock selection register PPG67 R/W 0 _ 0 0 0 _ _ 1B 16-bit Programmable Pulse 0 _ 0 0 0 0 0 1B Generator 6/7 0 0 0 0 0 0 _ _B (Continued) 21 MB90435 Series Address Register 47H to 4BH Abbreviation Access Resource name Initial value Prohibited 4CH Input capture control status register 0/1 ICS01 R/W Input Capture 0/1 0 0 0 0 0 0 0 0B 4DH Input capture control status register 2/3 ICS23 R/W Input Capture 2/3 0 0 0 0 0 0 0 0B 4EH Input capture control status register 4/5 ICS45 R/W Input Capture 4/5 0 0 0 0 0 0 0 0B 4FH Input capture control status register 6/7 ICS67 R/W Input Capture 6/7 0 0 0 0 0 0 0 0B 50H Timer control status register 0 TMCSR0 R/W 0 0 0 0 0 0 0 0B 51H Timer control status register 0 TMCSR0 R/W _ _ _ _ 0 0 0 0B 52H Timer register 0/reload register 0 TMR0/ TMRLR0 R/W 53H Timer register 0/reload register 0 TMR0/ TMRLR0 R/W XXXXXXXXB 54H Timer control status register 1 TMCSR1 R/W 0 0 0 0 0 0 0 0B 55H Timer control status register 1 TMCSR1 R/W _ _ _ _ 0 0 0 0B 56H Timer register 1/reload register 1 TMR1/ TMRLR1 R/W 57H Timer register 1/reload register 1 TMR1/ TMRLR1 R/W 58H Output compare control status register 0 OCS0 R/W 59H Output compare control status register 1 OCS1 R/W 5AH Output compare control status register 2 OCS2 R/W 5BH Output compare control status register 3 OCS3 R/W Output Compare 0 0 0 0 _ _ 0 0B 2/3 _ _ _ 0 0 0 0 0B 0 0 0 0 0 0 0 0B 5CH to 6BH 16-bit Reload Timer 0 16-bit Reload Timer 1 XXXXXXXXB XXXXXXXXB XXXXXXXXB Output Compare 0 0 0 0 _ _ 0 0B 0/1 _ _ _0 0 0 0 0B Prohibited 6CH Timer Counter Data register TCDT R/W 6DH Timer Counter Data register TCDT R/W 6EH Timer Counter Control status register TCCS R/W 6FH ROM mirror function selection register ROMM R/W ROM Mirror _ _ _ _ _ _ _ 1B Address Match Detection Function 0 0 0 0 0 0 0 0B 70H to 7FH Reserved 80H to 8FH Reserved 90H to 9DH Prohibited I/O Timer 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 9EH Program address detection control status register PACSR R/W 9FH Delayed interrupt/release register DIRR R/W A0H Low-power mode control register LPMCR R/W Low Power Controller 0 0 0 1 1 0 0 0B A1H Clock selection register CKSCR R/W Low Power Controller 1 1 1 1 1 1 0 0B Delayed Interrupt _ _ _ _ _ _ _ 0B (Continued) 22 MB90435 Series (Continued) Address Register A2H to A4H A5H Abbreviation Access Resource name Initial value Prohibited Automatic ready function select register ARSR W 0 0 1 1 _ _ 0 0B External Memory Access A6H External address output control register HACR W A7H Bus control signal selection register ECSR W A8H Watchdog Timer control register WDTC R/W Watchdog Timer XXXXX 1 1 1B A9H Time Base Timer Control register TBTC R/W Time Base Timer 1 - - 0 0 1 0 0B AAH Watch timer control register WTC R/W Watch Timer 1 X 0 0 0 0 0 0B R/W Flash Memory 0 0 0 X 0 0 0 0B ABH to ADH AEH 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 _B Prohibited Flash memory control status register (Flash only, otherwise reserved) AFH FMCS Prohibited B0H Interrupt control register 00 ICR00 R/W 0 0 0 0 0 1 1 1B B1H Interrupt control register 01 ICR01 R/W 0 0 0 0 0 1 1 1B B2H Interrupt control register 02 ICR02 R/W 0 0 0 0 0 1 1 1B B3H Interrupt control register 03 ICR03 R/W 0 0 0 0 0 1 1 1B B4H Interrupt control register 04 ICR04 R/W 0 0 0 0 0 1 1 1B B5H Interrupt control register 05 ICR05 R/W 0 0 0 0 0 1 1 1B B6H Interrupt control register 06 ICR06 R/W 0 0 0 0 0 1 1 1B B7H Interrupt control register 07 ICR07 R/W B8H Interrupt control register 08 ICR08 R/W B9H Interrupt control register 09 ICR09 R/W 0 0 0 0 0 1 1 1B BAH Interrupt control register 10 ICR10 R/W 0 0 0 0 0 1 1 1B BBH Interrupt control register 11 ICR11 R/W 0 0 0 0 0 1 1 1B BCH Interrupt control register 12 ICR12 R/W 0 0 0 0 0 1 1 1B BDH Interrupt control register 13 ICR13 R/W 0 0 0 0 0 1 1 1B BEH Interrupt control register 14 ICR14 R/W 0 0 0 0 0 1 1 1B BFH Interrupt control register 15 ICR15 R/W 0 0 0 0 0 1 1 1B C0H to FFH Interrupt controller 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B External Address Register Abbreviation Access Resource name 1FF0H Program address detection register 0 PADR0 R/W XXXXXXXXB 1FF1H Program address detection register 0 PADR0 R/W XXXXXXXXB 1FF2H Program address detection register 0 PADR0 R/W 1FF3H Program address detection register 1 PADR1 R/W 1FF4H Program address detection register 1 PADR1 R/W XXXXXXXXB 1FF5H Program address detection register 1 PADR1 R/W XXXXXXXXB Address Match Detection Function Initial value XXXXXXXXB XXXXXXXXB (Continued) 23 MB90435 Series Address Register Abbreviation Access 3900H Reload L PRLL0 R/W 3901H Reload H PRLH0 R/W 3902H Reload L PRLL1 R/W 3903H Reload H PRLH1 R/W XXXXXXXXB 3904H Reload L PRLL2 R/W XXXXXXXXB 3905H Reload H PRLH2 R/W 3906H Reload L PRLL3 R/W 3907H Reload H PRLH3 R/W XXXXXXXXB 3908H Reload L PRLL4 R/W XXXXXXXXB 3909H Reload H PRLH4 R/W 390AH Reload L PRLL5 R/W 390BH Reload H PRLH5 R/W XXXXXXXXB 390CH Reload L PRLL6 R/W XXXXXXXXB 390DH Reload H PRLH6 R/W 390EH Reload L PRLL7 R/W 390FH Reload H PRLH7 R/W 3910H to 3917H Resource name Initial value XXXXXXXXB 16-bit Programmable Pulse Generator 0/1 16-bit Programmable Pulse Generator 2/3 16-bit Programmable Pulse Generator 4/5 16-bit Programmable Pulse Generator 6/7 XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB Reserved 3918H Input Capture Register 0 IPCP0 R 3919H Input Capture Register 0 IPCP0 R 391AH Input Capture Register 1 IPCP1 R 391BH Input Capture Register 1 IPCP1 R XXXXXXXXB 391CH Input Capture Register 2 IPCP2 R XXXXXXXXB 391DH Input Capture Register 2 IPCP2 R 391EH Input Capture Register 3 IPCP3 R 391FH Input Capture Register 3 IPCP3 R XXXXXXXXB 3920H Input Capture Register 4 IPCP4 R XXXXXXXXB 3921H Input Capture Register 4 IPCP4 R 3922H Input Capture Register 5 IPCP5 R 3923H Input Capture Register 5 IPCP5 R XXXXXXXXB 3924H Input Capture Register 6 IPCP6 R XXXXXXXXB 3925H Input Capture Register 6 IPCP6 R 3926H Input Capture Register 7 IPCP7 R 3927H Input Capture Register 7 IPCP7 R XXXXXXXXB Input Capture 0/1 Input Capture 2/3 Input Capture 4/5 Input Capture 6/7 XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB (Continued) 24 MB90435 Series (Continued) Address Register Abbreviation Access Resource name Initial value 3928H Output Compare Register 0 OCCP0 R/W 3929H Output Compare Register 0 OCCP0 R/W 392AH Output Compare Register 1 OCCP1 R/W 392BH Output Compare Register 1 OCCP1 R/W XXXXXXXXB 392CH Output Compare Register 2 OCCP2 R/W XXXXXXXXB 392DH Output Compare Register 2 OCCP2 R/W 392EH Output Compare Register 3 OCCP3 R/W 392FH Output Compare Register 3 OCCP3 R/W 3930H to 39FFH Reserved 3A00H to 3AFFH Reserved 3B00H to 3BFFH Reserved 3C00H to 3CFFH Reserved 3D00H to 3DFFH Reserved 3E00H to 3FFFH Reserved XXXXXXXXB Output Compare 0/1 Output Compare 2/3 XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB * Read/write notation R/W : Reading and writing permitted R : Read-only W : Write-only * Initial value notation 0 : Initial value is "0". 1 : Initial value is "1". X : Initial value is undefined. Note : Any write access to reserved addresses in I/O map should not be performed. A read access to reserved addresses results in reading "X". 25 MB90435 Series INTERRUPT MAP Interrupt control register Number Address Number Address Reset N/A #08 FFFFDCH INT9 instruction N/A #09 FFFFD8H Exception N/A #10 FFFFD4H Reserved N/A #11 FFFFD0H Reserved N/A #12 FFFFCCH ICR00 0000B0H Reserved N/A #13 FFFFC8H Reserved N/A #14 FFFFC4H ICR01 0000B1H *1 #15 FFFFC0H N/A #16 FFFFBCH ICR02 0000B2H 16-bit Reload Timer 0 *1 #17 FFFFB8H 8/10-bit A/D Converter *1 #18 FFFFB4H ICR03 0000B3H N/A #19 FFFFB0H External Interrupt INT2/INT3 *1 #20 FFFFACH ICR04 0000B4H Serial I/O *1 #21 FFFFA8H 8/16-bit PPG 0/1 N/A #22 FFFFA4H ICR05 0000B5H Input Capture 0 *1 #23 FFFFA0H External Interrupt INT4/INT5 *1 #24 FFFF9CH ICR06 0000B6H Input Capture 1 *1 #25 FFFF98H 8/16-bit PPG 2/3 N/A #26 FFFF94H ICR07 0000B7H *1 #27 FFFF90H Watch Timer N/A #28 FFFF8CH ICR08 0000B8H 8/16-bit PPG 4/5 N/A #29 FFFF88H Input Capture 2/3 *1 #30 FFFF84H ICR09 0000B9H 8/16-bit PPG 6/7 N/A #31 FFFF80H Output Compare 0 *1 #32 FFFF7CH ICR10 0000BAH Output Compare 1 *1 #33 FFFF78H Input Capture 4/5 *1 #34 FFFF74H ICR11 0000BBH Output Compare 2/3 - Input Capture 6/7 *1 #35 FFFF70H 16-bit Reload Timer 1 *1 #36 FFFF6CH ICR12 0000BCH UART 0 RX *2 #37 FFFF68H UART 0 TX *1 #38 FFFF64H ICR13 0000BDH UART 1 RX *2 #39 FFFF60H UART 1 TX *1 #40 FFFF5CH ICR14 0000BEH Flash Memory N/A #41 FFFF58H Delayed interrupt N/A #42 FFFF54H ICR15 0000BFH External Interrupt INT0/INT1 Time Base Timer I/O Timer External Interrupt INT6/INT7 26 Interrupt vector EI2OS clear Interrupt cause MB90435 Series *1 : The interrupt request flag is cleared by the EI2OS interrupt clear signal. *2 : The interrupt request flag is cleared by the EI2OS interrupt clear signal. A stop request is available. Notes : * N/A : The interrupt request flag is not cleared by the EI2OS interrupt clear signal. * For a peripheral module with two interrupt causes for a single interrupt number, both interrupt request flags are cleared by the EI2OS interrupt clear signal. * At the end of EI2OS, the EI2OS clear signal will be asserted for all the interrupt flags assigned to the same interrupt number. If one interrupt flag starts the EI2OS and in the meantime another interrupt flag is set by a hardware event, the later event is lost because the flag is cleared by the EI2OS clear signal caused by the first event. So it is recommended not to use the EI2OS for this interrupt number. * If EI2OS is enabled, EI2OS is initiated when one of the two interrupt signals in the same interrupt control register (ICR) is asserted. This means that different interrupt sources share the same EI2OS Descriptor which should be unique for each interrupt source. For this reason, when one interrupt source uses the EI2OS, the other interrupt should be disabled. 27 MB90435 Series ELECTRICAL CHARACTERISTICS (VSS = AVSS = 0.0 V) 1. Absolute Maximum Ratings Parameter Power supply voltage Input voltage Output voltage Maximum clamp current Total maximum clamp current "L" level max output current "L" level avg. output current "L" level max overall output current "L" level avg. overall output current "H" level max output current "H" level avg. output current "H" level max overall output current "H" level avg. overall output current Power consumption Operating temperature Storage temperature Symbol VCC AVCC AVRH, AVRL VI VO ICLAMP | ICLAMP | IOL IOLAV IOL IOLAV IOH IOHAV IOH IOHAV PD TA TSTG Value Units Min VSS - 0.3 VSS - 0.3 Max VSS + 6.0 VSS + 6.0 VSS - 0.3 VSS + 6.0 V VSS - 0.3 VSS - 0.3 - 2.0 -40 -55 VSS + 6.0 VSS + 6.0 + 2.0 20 15 4 100 50 -15 -4 -100 -50 500 400 +105 +150 V V mA mA mA mA mA mA mA mA mA mA mW mW C C V V Remarks VCC = AVCC AVCC AVRH/AVRL, AVRH AVRL *1 *1 *2 *2 *6 *6 *3 *4 *5 *3 *4 *5 Flash device Mask ROM *1 : AVCC, AVRH, AVRL should not exceed VCC. Also, AVRH, AVRL should not exceed AVCC, and AVRL does not exceed AVRH. *2 : VI and VO should not exceed VCC + 0.3 V. VI should not exceed the specified ratings. However if the maximum current to/from an input is limited by some means with external components, the ICLAMP rating supercedes the VI rating. *3 : The maximum output current is a peak value for a corresponding pin. *4 : Average output current is an average current value observed for a 100 ms period for a corresponding pin. *5 : Total average current is an average current value observed for a 100 ms period for all corresponding pins. *6 : * Applicable to pins : P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P80 to P87, P90 to P97, PA0 * Use within recommended operating conditions. * Use at DC voltage (current) . * The +B signal should always be applied with a limiting resistance placed between the +B signal and the microcontroller. * The value of the limiting resistance should be set so that when the +B signal is applied the input current to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods. * Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect other devices. * Note that if a +B signal is input when the microcontroller current is off (not fixed at 0 V) , the power supply is provided from the pins, so that incomplete operation may result. * Note that if the +B input is applied during power-on, the power supply is provided from the pins and the resulting supply voltage may not be sufficient to operate the power-on result. (Continued) 28 MB90435 Series (Continued) * Care must be taken not to leave the +B input pin open. * Note that analog system input/output pins other than the A/D input pins (LCD drive pins, comparator input pins, etc.) cannot accept +B signal input. * Sample recommended circuits : * Input/Output Equivalent circuits Protective diode VCC +B input (0 V to 16 V) P-ch Limiting resistance N-ch R Note : Average output current = operating current x operating efficiency WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. 29 MB90435 Series (VSS = AVSS = 0.0 V) 2. Recommended Conditions Parameter Power supply voltage Smooth capacitor Operating temperature Min Value Typ Max 4.5 5.0 5.5 V VCC, AVCC 3.5 5.0 5.5 V CS TA 3.0 0.022 -40 0.1 5.5 1.0 +105 V F C Symbol Units Remarks Under normal operation : MB90F439 (S) /439 (S) /V540G Under normal operation : MB90F438L (S) /437L (S) /438L (S) Maintain RAM data in stop mode * *: Use a ceramic capacitor or a capacitor of better 4. AC characteristics. The VCC Capacitor should be greater than this capacitor. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. * C Pin Connection Diagram C CS 30 MB90435 Series 3. DC Characteristics (MB90F438L (S) /437L (S) /438L (S) : VCC = 3.5 V to 5.5 V, VSS = AVSS = 0.0 V, TA = -40 C to +105 C) (MB90F439 (S) /439 (S) /V540G : VCC = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = -40 C to +105 C) Value SymParameter Pin name Condition Units Remarks bol Min Typ Max CMOS 0.8 VCC VCC + 0.3 V VIHS hysteresis input pin Input H TTL input VIH voltage 2.0 V pin MD input VIHM VCC - 0.3 VCC + 0.3 V pin CMOS VCC - 0.3 0.2 VCC V VILS hysteresis input pin Input L TTL input VIL 0.8 V voltage pin MD input VILM VSS - 0.3 VCC + 0.3 V pin Output H All output VCC = 4.5 V, VOH V VCC - 0.5 voltage pins IOH = -4.0 mA Output L All output VCC = 4.5 V, VOL 0.4 V voltage pins IOL = 4.0 mA Input leak VCC = 5.5 V, IIL -5 5 A current VSS < VI < VCC P00 to P07, P10 to P17, Pull-up RUP P20 to P27, 25 50 100 k resistance P30 to P37, RST Pull-down RDO MD2 25 50 100 k resistance WN (Continued) 31 MB90435 Series (Continued) (MB90F438L (S) /437L (S) /438L (S) : VCC = 3.5 V to 5.5 V, VSS = AVSS = 0.0 V, TA = -40 C to +105 C) (MB90F439 (S) /439 (S) /V540G : VCC = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = -40 C to +105 C) Value SymParameter Pin name Condition Units Remarks bol Min Typ Max Internal frequency : 16 MHz, 40 55 mA At normal operating ICC Internal frequency : 16 MHz, 50 70 mA Flash device At Flash programming/erasing Internal frequency : 16 MHz, ICCS 12 20 mA At sleep mode 300 600 A VCC = 5.0 V 1%, 600 1100 A MB90F348L (S) Internal frequency : 2 MHz, ICTS MB90437L (S) / At pseudo timer mode 200 400 A Power 438L (S) supply VCC 400 750 A MB90F438L (S) current* Internal frequency : 8 kHz, 50 100 A Mask ROM ICCL At sub operation, TA = 25 C 150 300 A Flash device Internal frequency : 8 kHz, ICCLS 15 40 A At sub sleep, TA = 25 C Internal frequency : 8 kHz, ICCT 7 25 A At timer mode, TA = 25 C ICCH1 At stop, TA = 25 C 5 20 A At hardware standby mode, ICCH2 50 100 A TA = 25 C Input capacity CIN Other than AVCC, AVSS, AVRH, AVRL, C, VCC, VSS 5 15 * : The power supply current testing conditions are when using the external clock. 32 pF MB90435 Series 4. AC Characteristics (1) Clock Timing (MB90F438L (S) /437L (S) /438L (S) : VCC = 3.5 V to 5.5 V, VSS = AVSS = 0.0 V, TA = -40 C to +105 C) (MB90F439 (S) /439 (S) /V540G : VCC = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = -40 C to +105 C) Parameter Symbol Oscillation frequency fC X0, X1 fCL X0A, X1A Value Units Remarks Min Typ Max 3 16 MHz VCC = 5.0 V10% 3 5 MHz 32.768 kHz 62.5 333 ns VCC = 5.0 V10% 200 333 ns VCC<4.5 (MB90F438L (S) / 437L (S) /438L (S) ) VCC<4.5 (MB90F438L (S) / 437L (S) /438L (S) ) tCYL X0, X1 tLCYL X0A, X1A 30.5 s PWH, PWL X0 10 ns PWLH, PWLL X0A 15.2 s Duty ratio is about 30% to 70%. tCR, tCF X0 5 ns When using external clock fCP 1.5 16 MHz When using main clock fLCP 8.192 kHz When using sub-clock tCP 62.5 666 ns When using main clock tLCP 122.1 s When using sub-clock Oscillation cycle time Input clock pulse width Pin name Input clock rise and fall time Machine clock frequency Machine clock cycle time * Clock Timing tCYL 0.8 VCC X0 0.2 VCC PWH PWL tCF tCR tLCYL 0.8 VCC X0A 0.2 VCC PWLH PWLL tCF tCR 33 MB90435 Series * Guaranteed PLL operation range Guaranteed operation range (MB90F439(S)/439(S)/V540G) Guaranteed operation range (MB90F438L(S)/437L(S)/438L(S)) 5.5 Power supply voltage VCC (V) 4.5 3.5 Guaranteed PLL operation range (MB90F438L(S)/437L(S)/438L(S)) Guaranteed PLL operation range ( MB90F439(S)/439(S)/V540G) 8 1.5 16 Machine clock fCP (MHz) * External clock frequency and Machine clock frequency x4 16 Machine clock fCP (MHz) x3 x2 x1 12 9 8 PLL off 4 3 4 8 External clock fC (MHz) 34 16 MB90435 Series AC characteristics are set to the measured reference voltage values below. * Input signal waveform Hysteresis Input Pin * Output signal waveform Output Pin 0.8 VCC 2.4 V 0.2 VCC 0.8 V TTL Input Pin 2.0 V 0.8 V 35 MB90435 Series (2) Clock Output Timing (MB90F438L (S) /437L (S) /438L (S) : VCC = 3.5 V to 5.5 V, VSS = AVSS = 0.0 V, TA = -40 C to +105 C) (MB90F439 (S) /439 (S) /V540G : VCC = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = -40 C to +105 C) Parameter Symbol Cycle time tCYC CLK CLK tCHCL Pin name Value Condition VCC = 5 V 10% CLK Units Min Max 62.5 ns 20 ns Remarks tCYC tCHCL CLK 2.4 V 2.4 V 0.8 V (3) Reset and Hardware Standby Input Timing (MB90F438L (S) /437L (S) /438L (S) : VCC = 3.5 V to 5.5 V, VSS = AVSS = 0.0 V, TA = -40 C to +105 C) (MB90F439 (S) /439 (S) /V540G : VCC = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = -40 C to +105 C) Parameter Reset input time Hardware standby input time Symbol tRSTL tHSTL Pin name Value Units Max 4 tCP ns Under normal operation Oscillation time of oscillator + 4 tCP ms In stop mode 100 s Pseudo timer mode (MB90437L (S) /438L (S) ) 4 tCP ns Pseudo timer mode (Other than MB90437L (S) /438L (S) ) 2 tCP s In sub clock mode, sub sleep mode and watch mode 4 tCP ns Under normal operation RST HST Remarks Min "tcp" represents one cycle time of the machine clock. Oscillation time of oscillator is time that amplitude reached the 90%. In the crystal oscillator, the oscillation time is between several ms to tens of ms. In FAR/ceramic oscillator, the oscillation time is between handreds of s to several ms. In the external clock, the oscillation time is 0 ns. Any reset can not fully initialize the Flash Memory if it is performing the automatic algorithm. 36 MB90435 Series * Under normal operation, Pseudo timer mode, Sub clock mode, Sub sleep mode, Watch mode tRSTL, tHSTL RST HST 0.2 VCC 0.2 VCC * In stop mode tRSTL RST 0.2 VCC X0 0.2 VCC 90% of amplitude Internal operation clock 4 tCP Oscillation time of oscillator Internal reset Oscillation setting time Instruction execution 37 MB90435 Series (4) Power On Reset (MB90F438L (S) /437L (S) /438L (S) : VCC = 3.5 V to 5.5 V, VSS = AVSS = 0.0 V, TA = -40 C to +105 C) (MB90F439 (S) /439 (S) /V540G : VCC = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = -40 C to +105 C) Parameter Symbol Pin name Power on rise time tR VCC tOFF VCC Power off time Condition Value Units Remarks Min Max 0.05 30 ms * 50 ms Due to repetitive operation * : VCC must be kept lower than 0.2 V before power-on. Notes : * The above values are used for creating a power-on reset. * Some registers in the device are initialized only upon a power-on reset. To initialize these register, turn on the power supply using the above values. tR VCC 2.7 V 0.2 V 0.2 V 0.2 V tOFF Sudden changes in the power supply voltage may cause a power-on reset. To change the power supply voltage while the device is in operation, it is recommended to raise the voltage smoothly to suppress fluctuations as shown below. In this case, change the supply voltage with the PLL clock not used. If the voltage drop is 1 V or fewer per second, however, you can use the PLL clock. VCC 3.0 V VSS 38 RAM data being held It is recommended to keep the rising speed of the supply voltage at 50 mV/ms or slower. MB90435 Series (5) Bus Timing (Read) (MB90F438L (S) /437L (S) /438L (S) : VCC = 3.5 V to 5.5 V, VSS = AVSS = 0.0 V, TA = -40 C to +105 C) (MB90F439 (S) /439 (S) /V540G : VCC = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = -40 C to +105 C) Parameter Symbol Pin name Condition Value Min Max Units Remarks ALE pulse width tLHLL ALE tCP/2 - 20 ns Valid addressALEtime tAVLL ALE, A16 to A23, AD00 to AD15 tCP/2 - 20 ns ALEAddress valid time tLLAX ALE, AD00 to AD15 tCP/2 - 15 ns Valid addressRDtime tAVRL A16 toA23, AD00 to AD15, RD tCP - 15 ns Valid addressValid data input tAVDV A16 to A23, AD00 to AD15 5 tCP/2 - 60 ns RD pulse width tRLRH RD 3 tCP/2 - 20 ns RDValid data input tRLDV RD, AD00 to AD15 3 tCP/2 - 60 ns RDData hold time tRHDX 0 ns RD, AD00 to AD15 RDALEtime tRHLH RD, ALE tCP/2 - 15 ns RDAddress valid time tRHAX RD, A16 to A23 tCP/2 - 10 ns Valid addressCLKtime tAVCH A16 to A23, AD00 to AD15, CLK tCP/2 - 20 ns RDCLKtime tRLCH RD, CLK tCP/2 - 20 ns ALERDtime tLLRL ALE, RD tCP/2 - 15 ns 39 MB90435 Series * Bus Timing (Read) tAVCH tRLCH 2.4 V 2.4 V CLK tRHLH 2.4 V 2.4 V 2.4 V ALE tLHLL 0.8 V tRLRH 2.4 V RD tAVLL tLLAX 0.8 V tLLRL tAVRL tRLDV tRHAX 2.4 V 2.4 V 0.8 V 0.8 V A16 to A23 tAVDV 2.4 V AD00 to AD15 0.8 V 40 2.4 V Address 0.8 V tRHDX 0.8 VCC 0.2 VCC 0.8 VCC Read data 0.2 VCC MB90435 Series (6) Bus Timing (Write) (MB90F438L (S) /437L (S) /438L (S) : VCC = 3.5 V to 5.5 V, VSS = AVSS = 0.0 V, TA = -40 C to +105 C) (MB90F439 (S) /439 (S) /V540G : VCC = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = -40 C to +105 C) Parameter Symbol Pin name Valid addressWRtime tAVWL A16 to A23 AD00 to AD15, WR WR pulse width tWLWH Valid data outputWRtime Condition Value Units Remarks Min Max tCP - 15 ns WR 3 tCP/2 - 20 ns tDVWH AD00 to AD15, WR 3 tCP/2 - 20 ns WRData hold time tWHDX AD00 to AD15, WR 20 ns WRAddress valid time tWHAX A16 to A23, WR tCP/2 - 10 ns WRALEtime tWHLH WR, ALE tCP/2 - 15 ns WRCLKtime tWLCH WR, CLK tCP/2 - 20 ns * Bus Timing (Write) tWLCH 2.4 V CLK tWHLH 2.4 V ALE tAVWL tWLWH 2.4 V WR (WRL, WRH) 0.8 V tWHAX 2.4 V 2.4 V 0.8 V 0.8 V A16 to A23 tDVWH AD00 to AD15 2.4 V 2.4 V Address 0.8 V tWHDX 2.4 V Write data 0.8 V 0.8 V 41 MB90435 Series (7) Ready Input Timing (MB90F438L (S) /437L (S) /438L (S) : VCC = 3.5 V to 5.5 V, VSS = AVSS = 0.0 V, TA = -40 C to +105 C) (MB90F439 (S) /439 (S) /V540G : VCC = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = -40 C to +105 C) Parameter Symbol Pin name RDY setup time tRYHS RDY RDY hold time tRYHH RDY Condition Value Max 45 ns 0 ns Note : If the RDY setup time is insufficient, use the auto-ready function. * Ready Input Timing 2.4 V CLK ALE RD/WR tRYHS RDY no WAIT is used. RDY When WAIT is used (1 cycle). 42 0.8 VCC 0.2 VCC Units Min tRYHH 0.8 VCC Remarks MB90435 Series (8) Hold Timing (MB90F438L (S) /437L (S) /438L (S) : VCC = 3.5 V to 5.5 V, VSS = AVSS = 0.0 V, TA = -40 C to +105 C) (MB90F439 (S) /439 (S) /V540G : VCC = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = -40 C to +105 C) Parameter Symbol Pin name Pin floatingHAKtime tXHAL HAK HAKtimePin valid time tHAHV HAK Value Condition Units Min Max 30 tCP ns tCP 2 tCP ns Remarks Note : There is more than 1 cycle from the time HRQ is read to the time the HAK is changed. * Hold Timing HAK 2.4 V 0.8 V tXHAL 2.4 V Each pin tHAHV High impedance 0.8 V 2.4 V 0.8 V (9) UART0/1, Serial I/O Timing (MB90F438L (S) /437L (S) /438L (S) : VCC = 3.5 V to 5.5 V, VSS = AVSS = 0.0 V, TA = -40 C to +105 C) (MB90F439 (S) /439 (S) /V540G : VCC = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = -40 C to +105 C) Parameter Symbol Pin name Condition Value Units Remarks Min Max SCK0 to SCK2 8 tCP ns SCK0 to SCK2, SOT0 to SOT2 Internal clock operaSCK0 to SCK2, tion output pins are CL = 80 pF + 1 TTL. SIN0 to SIN2 -80 80 ns 100 ns Serial clock cycle time tSCYC SCKSOT delay time tSLOV Valid SINSCK tIVSH SCKValid SIN hold time tSHIX SCK0 to SCK2, SIN0 to SIN2 60 ns Serial clock "H" pulse width tSHSL SCK0 to SCK2 4 tCP ns Serial clock "L" pulse width tSLSH SCK0 to SCK2 4 tCP ns SCKSOT delay time tSLOV 150 ns Valid SINSCK tIVSH 60 ns SCKValid SIN hold time tSHIX 60 ns SCK0 to SCK2, External clock operSOT0 to SOT2 ation output pins are SCK0 to SCK2, CL = 80 pF + 1 TTL. SIN0 to SIN2 SCK0 to SCK2, SIN0 to SIN2 Notes : * AC characteristic in CLK synchronized mode. * CL is load capacity value of pins when testing. * For tCP (Machine clock cycle time) , refer to " (1) Clock Timing". 43 MB90435 Series * Internal Shift Clock Mode tSCYC 2.4 V SCK 0.8 V 0.8 V tSLOV 2.4 V SOT 0.8 V tIVSH SIN tSHIX 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC * External Shift Clock Mode tSLSH SCK 0.2 VCC tSHSL 0.8 VCC 0.8 VCC 0.2 VCC tSLOV 2.4 V SOT 0.8 V tIVSH SIN 44 tSHIX 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC MB90435 Series (10) Timer Input Timing (MB90F438L (S) /437L (S) /438L (S) : VCC = 3.5 V to 5.5 V, VSS = AVSS = 0.0 V, TA = -40 C to +105 C) (MB90F439 (S) /439 (S) /V540G : VCC = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = -40 C to +105 C) Parameter Input pulse width Symbol Pin name tTIWH TIN0, TIN1 tTIWL IN0 to IN7 Value Condition Min Max 4 tCP Units Remarks ns * Timer Input Timing 0.8 VCC 0.8 VCC 0.2 VCC tTIWH 0.2 VCC tTIWL (11) Timer Output Timing (MB90F438L (S) /437L (S) /438L (S) : VCC = 3.5 V to 5.5 V, VSS = AVSS = 0.0 V, TA = -40 C to +105 C) (MB90F439 (S) /439 (S) /V540G : VCC = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = -40 C to +105 C) Parameter CLKTOUT change time Symbol Pin name Condition tTO TOT0 to TOT1, PPG0 to PPG3 Value Min Max 30 Units Remarks ns * Timer Output Timing 2.4 V CLK 2.4 V 0.8 V TOUT tTO 45 MB90435 Series (12) Trigger Input Timing (MB90F438L (S) /437L (S) /438L (S) : VCC = 3.5 V to 5.5 V, VSS = AVSS = 0.0 V, TA = -40 C to +105 C) (MB90F439 (S) /439 (S) /V540G : VCC = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = -40 C to +105 C) Parameter Symbol Pin name Condition Input pulse width tTRGH tTRGL INT0 to INT7, ADTG Value Units Remarks ns Under nomal operation s In stop mode Min Max 5 tCP 1 * Trigger Input Timing 0.8 VCC 0.8 VCC 0.2 VCC tTRGH 46 0.2 VCC tTRGL MB90435 Series 5. A/D Converter * Electrical Characteristics (VCC = AVCC = 5.0 V10%, VSS = AVSS = 0.0 V, 3.0 V AVRH - AVRL, TA = -40 C to +105 C) Parameter Symbol Pin name Resolution Conversion error Value Units Remarks Min Typ Max 10 bit 5.0 LSB Nonlinearity error 2.5 LSB Differential nonlinearity error 1.9 LSB Zero transition voltage VOT AN0 to AN7 AVRL - 3.5 AVRL + 0.5 AVRL + 4.5 LSB LSB LSB mV Full scale transition voltage VFST AN0 to AN7 AVRH - 6.5 AVRH - 1.5 AVRH + 1.5 LSB LSB LSB mV Compare time 352 tCP ns Internal frequency : 16 MHz Sampling time 64 tCP ns Internal frequency : 16 MHz Analog port input current IAIN AN0 to AN7 -1 1 A VCC = AVCC = 5.0 V 1% Analog input voltage range VAIN AN0 to AN7 AVRL AVRH V Reference voltage range Power supply current Reference voltage supply current Offset between input channels AVRH AVRL + 2.7 AVCC V AVRL 0 AVRH - 2.7 V IA AVCC 5 mA IAH AVCC 5 A * IR AVRH 400 600 A Flash device 140 260 A Mask ROM IRH AVRH 5 A * AN0 to AN7 4 LSB * : When not using an A/D converter, this is the current (VCC = AVCC = AVRH = 5.0 V) when the CPU is stopped. Note: The functionality of the A/D converter is only guaranteed for VCC = 5.0 V 10 % (also for MB90F438L (S) / 437L (S) /438L (S) ) . 47 MB90435 Series * A/D Converter Glossary Resolution : Analog changes that are identifiable with the A/D converter Linearity error : The deviation of the straight line connecting the zero transition point ("00 0000 0000" "00 0000 0001") with the full-scale transition point ("11 1111 1110" "11 1111 1111") from actual conversion characteristics Differential linearity error : The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value Total error : The total error is defined as a difference between the actual value and the theoretical value, which includes zero-transition error/full-scale transition error and linearity error. Total error 3FF 0.5 LSB Actual conversion Value 3FE Digital output 3FD {1 LSB x (N - 1) + 0.5 LSB} 004 VNT (measured value) 003 Actual conversion characteristics Theoretical characteristics 002 001 0.5 LSB AVRL AVRH Analog input 1 LSB = (Theoretical value) AVRH - AVRL [V] 1024 VOT (Theoretical value) = AVRL + 0.5 LSB [V] VFST (Theoretical value) = AVRH - 1.5 LSB [V] Total error for digital output N = VNT - {1 LSB x (N - 1) + 0.5 LSB} [LSB] 1 LSB VNT : Voltage at a transition of digital output from (N - 1) to N (Continued) 48 MB90435 Series (Continued) Linearity error 3FE 3FD Digital output Theorential characteristics Actual conversion value {1 LSB x (N - 1) + VOT } N+1 Actual conversion value VFST (measured value) VNT 004 Actual conversion characteristics 003 Digital output 3FF Differential linearity error N V (N + 1) T (measured value) N-1 VNT (measured value) 002 Theoretical characteristics 001 Acturel conversion value N-2 VOT (measured value) AVRL AVRH AVRL Analog input Linearity error of digital output N = AVRH Analog input VNT - {1 LSB x (N - 1) + VOT} [LSB] 1 LSB Differential linearity error V (N + 1) T - VNT = - 1 LSB [LSB] of digital N 1 LSB 1 LSB = VFST - VOT [V] 1022 VOT : Voltage at transition of digital output from "000H" to "001H" VFST : Voltage at transition of digital output from "3FEH" to "3FFH" * Notes on Using A/D Converter Select the output impedance value for the external circuit of analog input according to the following conditions, : * Output impedance values of the external circuit of 15 k or lower are recommended. * When capacitors are connected to external pins, the capacitance of several thousand times the internal capacitor value is recommended to minimized the effect of voltage distribution between the external capacitor and internal capacitor. Note : When the output impedance of the external circuit is too high, the sampling period for analog voltages may not be sufficient (sampling period = 4.00 s @machine clock of 16 MHz) . * Equipment of analog input circuit model Comparator Analog input 3.2 k Max. 30 pF Max. * Error The smaller the | AVRH - AVRL |, the greater the error would become relatively. 49 MB90435 Series 6. Flash Memory Program/Erase Characteristics Parameter Condition Sector erase time Chip erase time TA = + 25 C VCC = 5.0 V Word (16 bit width) programming time Erase/Program cycle 50 Value Units Remarks 15 s Excludes 00H programming prior erasure 5 s MB90F438L (S) 7 s MB90F439 (S) 16 3,600 s Excludes system-level overhead 10,000 cycle Min Typ Max 1 Excludes 00H programming prior erasure MB90435 Series EXAMPLE CHARACTERISTICS * "H" level output voltage * "L" level output voltage VOL - IOL VOH - IOH (VCC = 4.5 V,Ta = +25C) (VCC = 4.5 V, Ta = +25C) 5 0.9 4.5 0.8 4 0.7 3.5 VOL [V] VOH [V] 0.6 3 2.5 0.5 0.4 2 0.3 1.5 1 0.2 0.5 0.1 0 0 0 -2 -4 -6 -8 -10 0 2 4 6 8 10 IOL [mA] IOH [mA] * "H" level input voltage/ "L" level input voltage (Hysterisis inpiut) Vin - Vcc (Ta = +25C) 5 4 Vin [V] VIH 3 VIL 2 1 0 3 3.5 4 4.5 5 5.5 6 6.5 Vcc [V] 51 MB90435 Series * Power supply current (MB90439) Icc - Vcc Iccs - Vcc (Ta = +25C) (Ta = +25C) 12 40 fcp = 16 MHz fcp = 16 MHz 35 10 fcp = 12 MHz 30 fcp = 12 MHz 8 fcp = 8 MHz 20 Icc [mA] Icc [mA] fcp = 10 MHz fcp = 10 MHz 25 15 fcp = 8 MHz 6 4 fcp = 4 MHz fcp = 4 MHz 10 fcp = 2 MHz fcp = 2 MHz 2 5 0 0 2 3 4 5 6 7 2 3 4 5 6 7 Vcc [V] Vcc [V] ICTS - VCC ICCL - VCC (Ta = +25C) 600 (Ta = +25C) 100 90 500 80 fcp = 2 MHz 70 ICCL [A] ICTS [A] 400 300 60 50 40 200 30 fcp = 8 kHz 20 100 10 0 0 2 3 4 5 Vcc [V] 52 6 7 2 3 4 5 Vcc [V] 6 7 MB90435 Series ICCLS - VCC ICCT - VCC (Ta = +25C) (Ta = +25C) 40 25 35 20 30 ICCT [A] ICCLS [A] 25 20 15 10 15 fcp = 8 kHz fcp = 8 kHz 10 5 5 0 0 2 3 4 5 7 6 Vcc [V] 2 3 4 5 6 7 Vcc [V] ICCH1 - VCC (STOP, Ta = +25C) 20 ICCH1 [A] 15 10 5 0 2 3 4 5 6 7 Vcc [V] 53 MB90435 Series * Power supply current (MB90F439) Iccs - Vcc Icc - Vcc (Ta = +25 C) (Ta = +25 C) 14 45 fcp = 16 MHz 40 fcp = 16 MHz 12 35 fcp = 12 MHz fcp = 12 MHz 10 30 ICC [mA] ICC [mA] fcp = 10 MHz 25 fcp = 8 MHz 20 15 fcp = 4 MHz fcp = 10 MHz 8 fcp = 8 MHz 6 fcp = 4 MHz 4 10 fcp = 2 MHz fcp = 2 MHz 2 5 0 0 2 3 4 5 6 2 7 3 4 5 VCC [V] 6 7 VCC [V] ICTS - VCC ICCL - VCC (Ta = +25 C) (Ta = +25 C) 600 300 250 500 fcp = 2 MHz 200 400 ICCL [A] ICTS [A] fcp = 8 kHz 300 200 100 100 50 0 0 2 3 4 5 VCC [V] 54 150 6 7 2 3 4 5 VCC [V] 6 7 MB90435 Series ICCLS - VCC ICCT - VCC (Ta = +25 C) (Ta = +25 C) 25 45 40 20 35 30 ICCT [A] ICCLS [A] 15 25 20 15 10 fcp = 8 MHz fcp = 8 MHz 10 5 5 0 0 2 3 4 5 6 2 7 3 4 5 6 7 VCC [V] VCC [V] ICCH1 - VCC ICCH2 - VCC (STOP, Ta = +25C) (hardware standby, Ta = +25 C) 100 20 90 85 15 ICCH1 [A] ICCH2 [A] 70 60 50 10 40 30 5 20 10 0 0 2 3 4 5 VCC [V] 6 7 2 3 4 5 6 7 Vcc [V] 55 MB90435 Series ORDERING INFORMATION Part number 56 Package MB90F438LPF MB90F438LSPF MB90F439PF MB90F439SPF MB90437LPF MB90437LSPF MB90438LPF MB90438LSPF MB90439PF MB90439SPF 100-pin Plastic QFP (FPT-100P-M06) MB90F438LPFV MB90F438LSPFV MB90F439PFV MB90F439SPFV MB90437LPFV MB90437LSPFV MB90438LPFV MB90438LSPFV MB90439PFV MB90439SPFV 100-pin Plastic LQFP (FPT-100P-M05) Remarks MB90435 Series PACKAGE DIMENSIONS 100-pin Plastic QFP (FPT-100P-M06) Note: Pins width and pins thickness include plating thickness. 23.900.40(.941.016) 20.000.20(.787.008) 80 51 81 50 0.10(.004) 17.900.40 (.705.016) 14.000.20 (.551.008) INDEX Details of "A" part 100 0.25(.010) +0.35 3.00 -0.20 +.014 .118 -.008 (Mounting height) 0~8 31 1 30 0.65(.026) 0.320.05 (.013.002) 0.13(.005) M 0.170.06 (.007.002) 0.800.20 (.031.008) 0.880.15 (.035.006) "A" C 0.250.20 (.010.008) (Stand off) 2001 FUJITSU LIMITED F100008S-c-4-4 Dimensions in mm (inches) 100-pin Plastic LQFP (FPT-100P-M05) Note : Pins width and pins thickness include plating thickness. 16.000.20(.630.008)SQ 14.000.10(.551.004)SQ 75 51 76 50 0.08(.003) Details of "A" part +0.20 100 26 1 25 C 0.200.05 (.008.002) 0.08(.003) M 0.100.10 (.004.004) (Stand off) 0~8 "A" 0.50(.020) +.008 1.50 -0.10 .059 -.004 (Mounting height) INDEX 0.1450.055 (.0057.0022) 0.500.20 (.020.008) 0.600.15 (.024.006) 0.25(.010) 2000 FUJITSU LIMITED F100007S-3c-5 Dimensions in mm (inches) 57 MB90435 Series FUJITSU LIMITED All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. 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Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. F0207 FUJITSU LIMITED Printed in Japan