MB90F439SPFV - Fujitsu - Product.Network

DS07-13727-1E

FUJITSU SEMICONDUCTOR

DATA SHEET

16-bit Proprietary Microcontroller

CMOS

F2MC-16LX MB90435 Series

MB90437L (S) /438L (S) /F438L (S)

MB90439 (S) /F439 (S) /V540G

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■DESCRIPTION

The MB90435 series with FLASH ROM is specially designed for industrial applications.

The instruction set by F2MC-16LX CPU core inherits an AT architecture of the F2MC* family with additional

instruction sets for high-level languages, extended addressing mode, enhanced multiplication/division instruc-

tions, and enhanced bit manipulation instructions.The micro controller has a 32-bit accumulator for processing

long word data.

The MB90435 series has peripheral resources of 8/10-bit A/D converters, UART (SCI) , extended I/O serial

interfaces, 8/16-bit timer, I/O timer (input capture (ICU) , output compare (OCU) ) .

* : F2MC stands for FUJITSU Flexible Microcontroller.

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■FEATURES

•Clock

Embedded PLL clock multiplication circuit

Operating cloc k (PLL clock) can be selected from : divided-b y-2 of oscillation or one to f our times the oscillation

Minimum instruction e xecution time : 62.5 ns (operation at oscillation of 4 MHz, f our times the oscillation clock,

VCC of 5.0 V)

Subsystem Clock : 32 kHz

(Continued)

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■PACKAGES

100-pin Plastic QFP 100-pin Plastic LQFP

(FPT-100P-M06) (FPT-100P-M05)

MB90435 Series

• Instruction set to optimize controller applications

Rich data types (bit, byte, word, long word)

Rich addressing mode (23 types)

Enhanced signed multiplication/division instruction and RETI instruction functions

Enhanced precision calculation realized by the 32-bit accumulator

• Instruction set designed for high level language (C language) and multi-task operations

Adoption of system stack pointer

Enhanced pointer indirect instructions

Barrel shift instructions

• Program patch function (for two address pointers)

• Enhanced execution speed : 4-byte Instruction queue

• Enhanced interrupt function : 8 levels, 34 factors

• Automatic data transmission function independent of CPU operation

Extended intelligent I/O service function (EI2OS)

• Embedded ROM size and types

Mask ROM : 64 Kbytes / 128 Kbytes / 256 Kbytes

Flash ROM : 128 Kbytes/256 Kbytes

Embedded RAM size : 2 Kbytes/4 Kbytes/6 Kbytes/8 Kbytes (evaluation chip)

•Flash ROM

Supports automatic programming, Embedded Algorithm TM*

Write/Erase/Erase-Suspend/Resume commands

A flag indicating completion of the algorithm

Hard-wired reset vector available in order to point to a fixed boot sector in Flash Memory

Erase can be performed on each block

Block protection with external programming voltage

• Low-power consumption (stand-by) mode

Sleep mode (mode in which CPU operating clock is stopped)

Stop mode (mode in which oscillation is stopped)

CPU intermittent operation mode

Clock mode

Hardware stand-by mode

•Process

0.5 µm CMOS technology

• I/O port

General-purpose I/O ports : 81 ports

•Timer

Watchdog timer : 1 channel

8/16-bit PPG timer : 8/16-bit × 4 channels

16-bit re-load timer : 2 channels

• 16-bit I/O timer

16-bit free-run timer : 1 channel

Input capture : 8 channels

Output compare : 4 channels

• Extended I/O serial interface : 1 channel

•UART 0

With full-duplex double buffer (8-bit length)

Clock asynchronized or clock synchronized (with start/stop bit) transmission can be selectively used.

(Continued)

MB90435 Series

(Continued)

•UART 1

With full-duplex double buffer (8-bit length)

Clock asynchronized or clock synchronized serial (extended I/O serial) can be used.

• External interrupt circuit (8 channels)

A module for starting an extended intelligent I/O service (EI2OS) and generating an exter nal interr upt which

is triggered by an external input.

• Delayed interrupt generation module

Generates an interrupt request for switching tasks.

• 8/10-bit A/D converter (8 channels)

8/10-bit resolution can be selectively used.

Starting by an external trigger input.

Conversion time : 26.3 µs

• External bus interface : Maximum address space 16 Mbytes

• Package: QFP-100, LQFP-100

* : Embedded Algorithm is a trade mark of Advanced Micro Devices Inc.

MB90435 Series

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■PRODUCT LINEUP

(Continued)

Features MB90F438L (S) /F439 (S) MB90437L (S) *1

/438L (S) /439 (S) MB90V540G

CPU F2MC-16LX CPU

System clock On-chip PLL clock multiplier (×1, ×2, ×3, ×4, 1/2 when PLL stop)

Minimum instruction exection time : 62.5 ns (4 MHz osc. PLL × 4)

ROM Flash memory

MB90F438L(S) : 128 Kbytes

MB90F439(S) : 256 Kbytes

Mask ROM :

MB90437L(S): 64 Kbytes

MB90438L(S): 128 Kbytes

MB90439(S): 256 Kbytes

External

RAM MB90F438L(S) : 4 Kbytes

MB90F439(S) : 6 Kbytes

MB90437L(S): 2 Kbytes

MB90438L(S): 4 Kbytes

MB90439(S): 6 Kbytes 8 Kbytes

Clocks

MB90F438L/F439

: Two clocks system

MB90F438LS/F439S

: One clock system

MB90437L/438L/439

: Two clocks system

MB90437LS/438LS/439S

: One clock system

Two clocks system*2

Operating voltage

range *5

Temperature range −40 °C to 105 °C

Package QFP100, LQFP100 PGA-256

Emulator-specify

power supply*3 None

UART0

Full duplex double buffer

Support asynchronous/synchronous (with start/stop bit) transfer

Baud rate : 4808/5208/9615/10417/19230/38460/62500/500000 bps (asynchronous)

500 K/1 M/2 Mbps (synchronous) at System clock = 16 MHz

UART1

(SCI)

Full duplex double buffer

Asynchronous (start-stop synchronized) and CLK-synchronous communication

Baud rate : 1202/2404/4808/9615/19230/31250/38460/62500 bps (asynchronous)

62.5 K/125 K/250 K/500 K/1 M/2 Mbps (synchronous) at 6, 8, 10, 12, 16 MHz

Serial I/O

Transfer can be started from MSB or LSB

Supports internal clock synchronized transfer and external clock synchronized transfer

Supports positive-edge and nagative-edge clock synchronization

Baud rate : 31.25 K/62.5 K/125 K/500 K/1 Mbps at System clock = 16 MHz

A/D Converter 10-bit or 8-bit resolution

8 input channels

Conversion time : 26.3 µs (per one channel)

MB90435 Series

(Continued)

*1 : Under development

*2 : If the one clock system is used, equip X0A and X1A with clocks from the tool side.

*3 : It is setting of DIP switch S2 when Emulator pod (MB2145-507) is used.Please refer to the MB2145-507 hardware

manual (2.7 Emulator-specific Power Pin) about details.

*4 : Embedded Algorithm is a trade mark of Advanced Micro Devices Inc.

*5 : OPERATING VOLTAGE RANGE

Features MB90F438L (S) /F439 (S) MB90437L (S) *1

/438L (S) /439 (S) MB90V540G

16-bit Reload Timer

(2 channels)

Operation clock frequency : fsys/21, fsys/23, fsys/25 (fsys = System clock frequency)

Supports External Event Count function

Signals an interrupt when overflow

16-bit I/O Timer Supports Timer Clear when a match with Output Compare (Channel 0)

Operation clock freq. : fsys/22, fsys/24, fsys/26, fsys/28 (fsys = System clock freq.)

16-bit Output Compare

(4 channels)

Signals an interrupt when a match with 16-bit I/O Timer

Four 16-bit compare registers

A pair of compare registers can be used to generate an output signal

16-bit Input Capture

(8 channels)

Rising edge, falling edge or rising & falling edge sensitive

Four 16-bit Capture registers

Signals an interrupt upon external event

8/16-bit

Programmable

Pulse Generator

(4 channels)

Supports 8-bit and 16-bit operation modes

Eight 8-bit reload counters

Eight 8-bit reload registers for L pulse width

Eight 8-bit reload registers for H pulse width

A pair of 8-bit reload counters can be configured as one 16-bit reload counter or as 8-bit

prescaler plus 8-bit reload counter

4 output pins

Operation clock freq. : fsys, fsys/21, fsys/22, fsys/23, fsys/24 or 128 µs@fosc = 4 MHz

(fsys = System clock frequency, fosc = Oscillation clock frequency)

32 kHz Sub-clock Sub-clock for low power operation

External Interrupt

(8 channels) Can be programmed edge sensitive or level sensitive

External bus

interface External access using the selectable 8-bit or 16-bit bus is enabled

(external bus mode.)

I/O Ports Virtually all external pins can be used as general purpose I/O

All push-pull outputs and schmitt trigger inputs

Bit-wise programmable as input/output or peripheral signal

Flash Memory

Supports automatic programming, Embeded Algorithm TM*4

Write/Erase/Erase-Suspend/Erase-Resume commands

A flag indicating completion of the algorithm

Number of erase cycles : 10,000 times

Data retention time : 10 years

Boot block configuration

Erase can be performed on each block

Block protection by externally programmed voltage

Products Operation guarantee range

MB90F439 (S) /439 (S) /V540G 4.5 V to 5.5 V

MB90F438L (S) /437L (S) /438L (S) 3.5 V to 5.5 V

MB90435 Series

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■PIN ASSIGNMENT

(Continued)

(TOP VIEW)

(FPT-100P-M06)

X0A

X1A

PA0

RST

P97

P96

P95

P94

P93/INT3

P92/INT2

P91/INT1

P90/INT0

P87/TOT1

P86/TIN1

P85/OUT1

P84/OUT0

P83/PPG3

P82/PPG2

P81/PPG1

P80/PPG0

P77/OUT3/IN7

P76/OUT2/IN6

P75/IN5

P74/IN4

P73/IN3

P72/IN2

P71/IN1

P70/IN0

HST

MD2

P20/A16

P21/A17

P22/A18

P23/A19

P24/A20

P25/A21

P26/A22

P27/A23

P30/ALE

P31/RD

VSS

P32/WRL/WR

P33/WRH

P34/HRQ

P35/HAK

P36/RDY

P37/CLK

P40/SOT0

P41/SCK0

P42/SIN0

P43/SIN1

P44/SCK1

VCC

P45/SOT1

P46/SOT2

P47/SCK2

P50/SIN2

P51/INT4

P52/INT5

100

P53/INT6

P54/INT7

P55/ADTG

AVCC

AVRH

AVRL

AVSS

P60/AN0

P61/AN1

P62/AN2

P63/AN3

VSS

P64/AN4

P65/AN5

P66/AN6

P67/AN7

P56/TIN0

P57/TOT0

MD0

MD1

P17/AD15

P16/AD14

P15/AD13

P14/AD12

P13/AD11

P12/AD10

P11/AD09

P10/AD08

P07/AD07

P06/AD06

P05/AD05

P04/AD04

P03/AD03

P02/AD02

P01/AD01

P00/AD00

VCC

VSS

MB90435 Series

(Continued)

(TOP VIEW)

(FPT-100P-M05)

P22/A18

P23/A19

P24/A20

P25/A21

P26/A22

P27/A23

P30/ALE

P31/RD

VSS

P32/WRL/WR

P34/HRQ

P33/WRH

P35/HAK

P36/RDY

P37/CLK

P40/SOT0

P41/SCK0

P42/SIN0

P43/SIN1

P44/SCK1

VCC

P45/SOT1

P46/SOT2

P47/SCK2

RST

P97

P96

P95

P94

P93/INT3

P92/INT2

P91/INT1

P90/INT0

P87/TOT1

P86/TIN1

P85/OUT1

P84/OUT0

P83/PPG3

P82/PPG2

P81/PPG1

P80/PPG0

P77/OUT3/IN7

P76/OUT2/IN6

P75/IN5

P74/IN4

P73/IN3

P72/IN2

P71/IN1

P70/IN0

100

P21/A17

P20/A16

P17/AD15

P16/AD14

P15/AD13

P14/AD12

P13/AD11

P12/AD10

P11/AD09

P10/AD08

P07/AD07

P06/AD06

P05/AD05

P04/AD04

P03/AD03

P02/AD02

P01/AD01

P00/AD00

VCC

VSS

X0A

X1A

PA0

P50/SIN2

P51/INT4

P52/INT5

P53/INT6

P54/INT7

P55/ADTG

AVCC

AVRH

AVRL

AVSS

P60/AN0

P61/AN1

P62/AN2

P63/AN3

VSS

P64/AN4

P65/AN5

P66/AN6

P67/AN7

P56/TIN0

P57/TOT0

MD0

MD1

MD2

HST

MB90435 Series

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■PIN DESCRIPTION

(Continued)

Pin No. Pin name Cir c uit type Function

LQFP*2 QFP*1

81 82

83 X0

X1 A

(Oscillation) High speed crystal oscillator input pins

78 80 X0A A

(Oscillation)

Low speed crystal oscillator input pins. For the one clock

system parts, perfom external pull-down processing.

77 79 X1A Low speed crystal oscillator input pins. For the one clock

system parts, leave it open.

75 77 RST B External reset request input pin

50 52 HST C Hardware standby input pin

83 to 90 85 to 92 P00 to P07 I

General I/O port with programmable pull-up. This function is

enabled in the single-chip mode.

AD00 to AD07 I/O pins for 8 lower bits of the external address/data bus. This

function is enabled when the external bus is enabled.

91 to 98 93 to 100 P10 to P17 I

General I/O port with programmable pull-up. This function is

enabled in the single-chip mode.

AD08 to AD15 I/O pins for 8 higher bits of the external address/data bus. This

function is enabled when the external bus is enabled.

99 to 6 1 to 8

P20 to P27

General I/O port with programmable pull-up. In external bus

mode, this function is valid when the corresponding bits in the

external address output control register (HACR) are set to “1”.

A16 to A23

8-bit output pins for A16 to A23 at the external address bus. In

external bus mode, this function is valid when the correspond-

ing bits in the external address output control register (HACR)

are set to “0”.

79 P30 I

General I/O port with programmable pull-up. This function is

enabled in the single-chip mode.

ALE Address latch enable output pin. This function is enabled

when the external bus is enabled.

810 P31 I

General I/O port with programmable pull-up. This function is

enabled in the single-chip mode.

RD Read strobe output pin for the data bus. This function is

enabled when the external bus is enabled.

10 12

P32

General I/O port with programmable pull-up. This function is

enabled in the single-chip mode or when the WR/WRL pin

output is disabled.

WRL Write strobe output pin for the data bus. This function is

enabled when both the external bus and the WR/WRL pin

output are enabled. WRL is write-strobe output pin for the

lower 8 bits of the data bus in 16-bit access. WR is write-strobe

output pin for the 8 bits of the data bus in 8-bit access.

MB90435 Series

(Continued)

Pin No. Pin name Circuit

type Function

LQFP*2 QFP*1

11 13

P33

General I/O port with programmable pull-up. This function is

enabled in the single-chip mode, external bus 8-bit mode or

when WRH pin output is disabled.

WRH

Write strobe output pin for the 8 higher bits of the data bus.

This function is enabled when the external bus is enabled,

when the external bus 16-bit mode is selected, and when the

WRH output pin is enabled.

12 14 P34 I

General I/O port with programmable pull-up. This function is

enabled in the single-chip mode or when the hold function is

disabled.

HRQ Hold request input pin. This function is enabled when both the

external bus and the hold functions are enabled.

13 15 P35 I

General I/O port with programmable pull-up. This function is

enabled in the single-chip mode or when the hold function is

disabled.

HAK Hold acknowledge output pin. This function is enabled when

both the external bus and the hold functions are enabled.

14 16 P36 I

General I/O port with programmable pull-up. This function is

enabled in the single-chip mode or when the external ready

function is disabled.

RDY Ready input pin. This function is enabled when both the

external bus and the external ready functions are enabled.

15 17 P37 H

General I/O port with programmable pull-up. This function is

enabled in the single-chip mode or when the CLK output is

disabled.

CLK CLK output pin. This function is enabled when both the

external bus and CLK outputs are enabled.

16 18 P40 G

General I/O port. This function is enabled when UART0

disables the serial data output.

SOT0 Serial data output pin for UART0. This function is enabled

when UART0 enables the serial data output.

17 19 P41 G

General I/O port. This function is enabled when UART0

disables serial clock output.

SCK0 Serial clock I/O pin for UART0. This function is enabled when

UART0 enables the serial clock output.

18 20 P42 GGeneral I/O port. This function is always enabled.

SIN0 Serial data input pin for UART0. Set the corresponding Port

Direction Register to input if this function is used.

19 21 P43 GGeneral I/O port. This function is always enabled.

SIN1 Serial data input pin for UART1. Set the corresponding Port

Direction Register to input if this function is used.

MB90435 Series

(Continued)

Pin No. Pin name Cir cuit

type Function

LQFP*2 QFP*1

20 22 P44 G

General I/O port. This function is enabled when UART1

disables the clock output.

SCK1 Serial clock pulse I/O pin for UART1. This function is

enabled when UART1 enables the serial clock output.

22 24 P45 G

General I/O port. This function is enabled when UART1

disables the serial data output.

SOT1 Serial data output pin for UART1. This function is enabled when

UART1 enables the serial data output.

23 25

P46

General I/O port. This function is enabled when the Extended

I/O serial interface disables the serial data output.

SOT2 Serial data output pin for the Extended I/O serial interface. This

function is enabled when the Extended I/O serial interface

enables the serial data output.

24 26

P47

General I/O port. This function is enabled when the Extended

I/O serial interface disables the clock output.

SCK2 Serial clock pulse I/O pin for the Extended I/O serial interface .

This function is enabled when the Extended I/O serial interface

enables the Serial clock output.

26 28

P50

General I/O port. This function is always enabled.

SIN2 Serial data input pin for the Extended I/O serial interface . Set

the corresponding Port Direction Register to input if this

function is used.

27 to 30 29 to 32

P51 to P54

General I/O port. This function is always enabled.

INT4 to INT7 External interrupt request input pins for INT4 to INT7. Set the

corresponding Port Direction Register to input if this function is

used.

31 33 P55 DGeneral I/O port. This function is always enabled.

ADTG Trigger input pin for the A/D converter. Set the corresponding

Port Direction Register to input if this function is used.

36 to 39 38 to 41 P60 to P63 E

General I/O port. This function is enabled when the analog

input enable register specifies a port.

AN0 to AN3 Analog input pins for the 8/10-bit A/D converter. This function is

enabled when the analog input enable register specifies A/D.

41 to 44 43 to 46 P64 to P67 E

General I/O port. The function is enabled when the analog

input enable register specifies a port.

AN4 to AN7 Analog input pins for the 8/10-bit A/D converter. This function is

enabled when the analog input enable register specifies A/D.

45 47

P56

General I/O port. This function is always enabled.

TIN0 Event input pin for the 16-bit reload timers 0. Set the

corresponding Port Direction Register to input if this function is

used.

MB90435 Series

(Continued)

Pin No. Pin name Circuit

type Function

LQFP*2 QFP*1

46 48 P57 D

General I/O port. This function is enabled when the 16-bit

reload timers 0 disables the output.

TOT0 Output pin for the 16-bit reload timers 0. This function is

enabled when the 16-bit reload timers 0 enables the output.

51 to 56 53 to 58

P70 to P75

General I/O ports. This function is always enabled.

IN0 to IN5 Trigger input pins for input captures ICU0 to ICU5. Set the

corresponding Port Direction Register to input if this

function is used.

57 , 58 59 , 60

P76 , P77

General I/O ports. This function is enabled when the OCU

disables the waveform output.

OUT2 , OUT3 Event output pins for output compares OCU2 and OCU3. This

function is enabled when the OCU enables the waveform

output.

IN6 , IN7 Trigger input pins for input captures ICU6 and ICU7. Set the

corresponding Port Direction Register to input and disable the

OCU waveform output if this function is used.

59 , 62 61 to 64 P80 to P83 D

General I/O ports. This function is enabled when 8/16-bit PPG

disables the waveform output.

PPG0 to

PPG3 Output pins for 8/16-bit PPGs. This function is enabled when

8/16-bit PPG enables the waveform output.

63 , 64 65 , 66

P84 , P85

General I/O ports. This function is enabled when the OCU

disables the waveform output.

OUT0 , OUT1 Waveform output pins for output compares OCU0 and OCU1.

This function is enabled when the OCU enables the waveform

output.

65 67

P86

General I/O port. This function is always enabled.

TIN1 Input pin for the 16-bit reload timers 1. Set the

corresponding Port Direction Register to input if this function is

used.

66 68 P87 D

General I/O port. This function is enabled when the 16-bit

reload timers 0 disables the output.

TOT1 Output pin for the 16-bit reload timers 1.This function is

enabled when the 16-bit reload timers 1 enables the output.

67 to 70 69 to 72

P90 to P93

General I/O port. This function is always enabled.

INT0 to INT3 External interrupt request input pins for INT0 to INT3. Set the

corresponding Port Direction Register to input if this function is

used.

71 73 P94 D General I/O port.

MB90435 Series

(Continued)

*1 : FPT-100P-M06

*2 : FPT-100P-M05

Pin No. Pin name Circuit

type Function

LQFP*2 QFP*1

72 74 P95 D General I/O port.

73 75 P96 D General I/O port.

74 76 P97 D General I/O port.

76 78 PA0 D General I/O port.

32 34 AVCC Power

supply

Power supply pin for the A/D Converter. This power supply

must be turned on or off while a voltage higher than or equal to

AVCC is applied to VCC.

35 37 AVSS Power

supply Power supply pin for the A/D Converter.

33 35 AVRH Power

supply

External reference voltage input pin for the A/D Converter.

This power supply must be turned on or off while a voltage

higher than or equal to AVRH is applied to AVCC.

34 36 AVRL Power

supply External reference voltage input pin for the A/D Converter.

48 49

50 MD0

MD1 CInput pins for specifying the operating mode. The pins must be

directly connected to VCC or VSS.

49 51 MD2 F Input pin for specifying the operating mode. The pin must be

directly connected to VCC or VSS.

25 27 C Power supply stabilization capacitor pin. It should be connect-

ed externally to an 0.1 µF ceramic capacitor.

21, 82 23, 84 VCC Power

supply Input pin for power supply (5.0 V) .

9, 40, 79 11, 42,

81 VSS Power

supply Input pin for power supply (0.0 V) .

MB90435 Series

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■I/O CIRCUIT TYPE

(Continued)

Circuit type Diagram Remarks

• High-speed oscillation feedback resistor

: 1 MΩ approx.

• Low-speed oscillation feedback resistor

: 10 MΩ approx.

• Hysteresis input

• Pull-up resistor : 50 kΩ approx.

• Hysteresis input

• CMOS level output

• CMOS Hysteresis input

X1,X1A

X0,X0A

Hard, soft

standby control

Clock

input

R (Pull-up)

HYS input

RHYS input

P-ch

N-ch

HYS input

VCC

MB90435 Series

(Continued)

Circuit type Diagram Remarks

• CMOS level output

• CMOS Hysteresis input

• Analog input

• Hysteresis input

• Pull-down Resistor : 50 kΩ approx.

(except FLASH devices)

• CMOS level output

• CMOS Hysteresis input

• TTL level input (FLASH devices in

FLASH writer mode only)

VCC P-ch

N-ch

HYS input

Analog input

P-ch

N-ch

R (Pull-down)

HYS input

P-ch

N-ch

HYS input

TTL level input

MB90435 Series

(Continued)

Circuit type Diagram Remarks

• CMOS level output

• CMOS Hysteresis input

• Programmable pull-up resistor :

50 kΩ approx.

• CMOS level output

• CMOS Hysteresis input

• TTL level input (FLASH devices in

FLASH writer mode only)

• Programmable pull-up resistor :

50 kΩ approx.

VCC

P-chP-ch

N-ch

VCC

HYS input

Pull-up ON/OFF

select signal

VCC

P-ch

N-ch

VCC Pull-up ON/OFF

select signal

HYS input

TTL level input

MB90435 Series

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■HANDLING DEVICES

(1) Preventing latc h-up

CMOS IC chips may suffer latch-up under the following conditions :

• A voltage higher than VCC or lower than VSS is applied to an input or output pin.

• A voltage higher than the rated voltage is applied between VCC and VSS.

• The AVcc power supply is applied before the VCC voltag e.

Latch-up may increase the power supply current drastically, causing thermal damage to the device.

F or the same reason, care must also be tak en in not allo wing the analog pow er-supply v oltage (AVCC, AVRH) to

exceed the digital power-supply voltage.

(2) Handling unused pins

Leaving unused input pins open may result in misbehavior or latch up and possible permanent damage of the

de vice. Therefor they must be pulled up or pulled do wn through resistors. In this case those resistors should be

more than 2 kΩ.

Unused bi-directional pins should be set to the output state and can be left open, or the input state with the

above described connection.

(3) Using external clock

To use external clock, drive X0 pin only and leave X1 pin unconnected.

Below is a diagram of how to use external clock.

(4) Use of the sub-clock

Use one clock system par ts when the sub-clock is not used. In that case, pull-down the pin X0A and leave the

pin X1A open. When using two cloc k system parts, a 32 kHz oscillator has to be connected to the X0A and X1A

pins.

(5) Power supply pins (VCC/VSS)

In products with multiple VCC or VSS pins, the pins of a same potential are internally connected in the device to

avoid abnor mal operations including latch-up. However you must connect the pins to an external power and a

ground line to lo wer the electro-magnetic emission le vel to pre v ent abnormal operation of strobe signals caused

by the rise in the ground level, and to conform to the total current rating.

Make sure to connect VCC and VSS pins via the lowest impedance to power lines.

It is recommended to provide a bypass capacitor of around 0.1 µF between VCC and VSS pins near the device.

MB90435 Series

Open

VCC

VSS

MB90435

Series

MB90435 Series

(6) Pull-up/down resistors

The MB90435 Series does not support internal pull-up/down resistors (except Port0 − Port3 : pull-up

resistors) . Use external components where needed.

(7) Crystal Oscillator Circuit

Noises around X0 or X1 pins may be possible causes of abnormal operations. Make sure to provide bypass

capacitors via the shortest distances from X0, X1 pins, crystal oscillator (or ceramic resonator) and ground lines,

and make sure, to the utmost effort, that lines of oscillation circuits do not cross the lines of other circuits.

It is highly recommended to provide a printed circuit board artwork surrounding X0 and X1 pins with a ground

area for stabilizing the operation.

(8) Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs

Make sure to turn on the A/D conv erter pow er supply (A VCC, AVRH, AVRL) and analog inputs (AN0 to AN7) after

turning-on the digital power supply (VCC) .

Turn-off the digital power after turning off the A/D converter supply and analog inputs. In this case, make sure

that the vo ltage does not exceed AVRH or AVCC (tur ning on/off the analog and digital power supplies simulta-

neously is acceptable) .

(9) Connection of Unused Pins of A/D Converter

Connect unused pins of A/D converter to AVCC = VCC, AVSS = AVRH = VSS.

(10) N.C. Pin

The N.C. (internally connected) pin must be opened for use.

(11) Notes on Energization

To prevent the internal regulator circuit from malfunctioning, set the voltage rise time during energization at

50 µs or more (0.2 V to 2.7 V) .

(12) Initialization

In the device, there are internal registers which are initialized only by a power-on reset. T o initialize these registers,

please turn on the power again.

(13) Directions of “DIV A, Ri” and “DIVW A, RWi” instructions

In the Signed multiplication and division instructions (“DIV A, Ri” and “DIVW A, RWi”) , the value of the

corresponding bank register (DTB, ADB, USB, SSB) is set in “00H”.

If the values of the corresponding bank registers (DTB, ADB, USB, SSB) are set to other than “00H”, the remainder

by the execution result of the instruction is not stored in the register of the instruction operand.

(14) Using REALOS

The use of EI2OS is not possible with the REALOS real time operating system.

(15) Caution on Operations during PLL Clock Mode

If the PLL clock mode is selected, the microcontroller attempt to be w orking with the self-oscillating circuit e ven

when there is no external oscillator or external clock input is stopped. Performance of this operation, however,

cannot be guaranteed.

MB90435 Series

■

■■

■BLOCK DIAGRAM

X0, X1

SOT0

SCK0

SIN0

SOT1

SCK1

SIN1

SOT2

SCK2

SIN2

AVCC

AVSS

AN0 to AN7

AVRH

AVRL

ADTG

X0A, X1A

RST

HST

F2MC 16LX

CPU

FMC-16 Bus

IN0 to IN5

IN6/OUT2,

IN7/OUT3

OUT0, OUT1

TIN0, TIN1

AD00 to AD15

A16 to A23

ALE

WRL

WRH

HRQ

HAK

RDY

CLK

INT0 to INT7

TOT0, TOT1

PPG0 to PPG3

Clock

Controller

RAM

2 K/4 K/6 K/8 K

ROM/Flash

64K/128 K/256 K

(ROM only)

Prescaler

UART0

UART1

(SCI)

Prescaler

Serial I/O

10-bit A/D

Converter

8 ch.

Prescaler

16-bit I/O

Timer

16-bit Input

Capture

8 ch.

16-bit Output

Compare

4 ch.

8/16-bit

PPG

4 ch.

16-bit Reload

Timer 2 ch.

External

Bus

Interface

External

Interrupt

8 ch.

MB90435 Series

■

■■

■MEMORY MAP

The memory space of the MB90435 Series is shown below.

Note : The high-order portion of bank 00 gives the image of the FF bank ROM to make the small model of the C

compiler effective. Since the low-order 16 bits address are the same, the table in ROM can be referenced

without using the “far” specification in the pointer declaration.

F or example, an attempt to access 00C000H accesses the v alue at FFC000H in ROM.The R OM area in bank

FF e xceeds 48 Kb ytes, and its entire image cannot be sho wn in bank 00.The image betw een FF4000H and

FFFFFFH is visible in bank 00, while the image between FF0000H and FF3FFFH is visible only in bank FF.

MB90V540G

FFFFFF

FEFFFF

FF0000

FDFFFF

FE0000

FCFFFF

FD0000

00FFFF

004000

003FFF

003900

0020FF

001FF5

001FF0

000100

0000BF

000000

FC0000

ROM

(FF bank)

ROM

(FE bank)

ROM

(FD bank)

ROM

(FC bank)

External

ROM

(Image of

FF bank)

Peripheral

External

RAM 8 K

External

Peripheral

ROM correction

MB90F438L (S)/438L (S)

FFFFFF

FEFFFF

FF0000

FE0000

00FFFF

004000

003FFF

003900

002000

0010FF

000100

0000BF

000000

ROM

(FF bank)

ROM

(FE bank)

External

ROM

(Image of

FF bank)

Peripheral

External

RAM 4 K

External

Peripheral

MB90F439 (S) /439 (S)

FDFFFF

FCFFFF

FD0000

FC0000

ROM

(FD bank)

ROM

(FC bank)

FFFFFF

FEFFFF

FF0000

FE0000

00FFFF

004000

003FFF

003900

002100

0018FF

000100

0000BF

000000

ROM

(FF bank)

ROM

(FE bank)

External

ROM

(Image of

FF bank)

Peripheral

External

RAM 6 K

External

Peripheral

FFFFFF

FF0000

00FFFF

004000

003FFF

003900

002000

0008FF

000100

0000BF

ROM

(FF bank)

ROM

(Image of

FF bank)

Peripheral

External

RAM 2 K

External

Peripheral

MB90F437L (S)*

000000

External

* : Under development

MB90435 Series

■

■■

■I/O MAP

(Continued)

Address Register Abbreviation Access Resource name Initial value

00HPort 0 data register PDR0 R/W Port 0 XXXXXXXXB

01HPort 1 data register PDR1 R/W Port 1 XXXXXXXXB

02HPort 2 data register PDR2 R/W Port 2 XXXXXXXXB

03HPort 3 data register PDR3 R/W Port 3 XXXXXXXXB

04HPort 4 data register PDR4 R/W Port 4 XXXXXXXXB

05HPort 5 data register PDR5 R/W Port 5 XXXXXXXXB

06HPort 6 data register PDR6 R/W Port 6 XXXXXXXXB

07HPort 7 data register PDR7 R/W Port 7 XXXXXXXXB

08HPort 8 data register PDR8 R/W Port 8 XXXXXXXXB

09HPort 9 data register PDR9 R/W Port 9 XXXXXXXXB

0AHPort A data register PDRA R/W Port A _ _ _ _ _ _ _XB

0BH to 0FHReserved

10HPort 0 direction register DDR0 R/W Port 0 0 0 0 0 0 0 0 0B

11HPort 1 direction register DDR1 R/W Port 1 0 0 0 0 0 0 0 0B

12HPort 2 direction register DDR2 R/W Port 2 0 0 0 0 0 0 0 0B

13HPort 3 direction register DDR3 R/W Port 3 0 0 0 0 0 0 0 0B

14HPort 4 direction register DDR4 R/W Port 4 0 0 0 0 0 0 0 0B

15HPort 5 direction register DDR5 R/W Port 5 0 0 0 0 0 0 0 0B

16HPort 6 direction register DDR6 R/W Port 6 0 0 0 0 0 0 0 0B

17HPort 7 direction register DDR7 R/W Port 7 0 0 0 0 0 0 0 0B

18HPort 8 direction register DDR8 R/W Port 8 0 0 0 0 0 0 0 0B

19HPort 9 direction register DDR9 R/W Port 9 0 0 0 0 0 0 0 0B

1AHPort A direction register DDRA R/W Port A _ _ _ _ _ _ _0B

1BHAnalog Input Enable register ADER R/W Port 6, A/D 1 1 1 1 1 1 1 1B

1CHPort 0 pull-up control register PUCR0 R/W Port 0 0 0 0 0 0 0 0 0B

1DHPort 1 pull-up control register PUCR1 R/W Port 1 0 0 0 0 0 0 0 0B

1EHPort 2 pull-up control register PUCR2 R/W Port 2 0 0 0 0 0 0 0 0B

1FHPort 3 pull-up control register PUCR3 R/W Port 3 0 0 0 0 0 0 0 0B

20HSerial Mode Control Register 0 UMC0 R/W

UART0

0 0 0 0 0 1 0 0B

21HSerial Status Register 0 USR0 R/W 0 0 0 1 0 0 0 0B

22HSerial input data register 0/

Serial output data register 0 UIDR0/

UODR0 R/W XXXXXXXXB

23HRate and data register 0 URD0 R/W 0 0 0 0 0 0 0XB

MB90435 Series

(Continued)

Address Register Abbreviation Access Resource name Initial value

24HSerial mode register 1 SMR1 R/W

UART1

0 0 0 0 0 0 0 0B

25HSerial control register 1 SCR1 R/W 0 0 0 0 0 1 0 0B

26HSerial input data register 1/

Serial output data register 1 SIDR1/

SODR1 R/W XXXXXXXXB

27HSerial status register 1 SSR1 R/W 0 0 0 0 1_0 0B

28HUART1 prescaler control register U1CDCR R/W 0_ _ _1 1 1 1B

29HSerial Edge select register SES1 R/W _ _ _ _ _ _ _0B

2AHProhibited

2BHSerial I/O prescaler SCDCR R/W

Extended I/O

Serial Interface

0_ _ _1 1 1 1B

2CHSerial mode control register SMCS R/W _ _ _ _0 0 0 0B

2DHSerial mode control register SMCS R/W 0 0 0 0 0 0 1 0B

2EHSerial data register SDR R/W XXXXXXXXB

2FHSerial Edge select register SES2 R/W _ _ _ _ _ _ _0B

30HExternal interrupt enable register ENIR R/W

External Interrupt

0 0 0 0 0 0 0 0B

31HExternal interrupt request register EIRR R/W XXXXXXXXB

32HExternal interrupt level register ELVR R/W 0 0 0 0 0 0 0 0B

33HExternal interrupt level register ELVR R/W 0 0 0 0 0 0 0 0B

34HA/D control status register 0 ADCS0 R/W

A/D Converter

0 0 0 0 0 0 0 0B

35HA/D control status register 1 ADCS1 R/W 0 0 0 0 0 0 0 0B

36HA/D data register 0 ADCR0 R XXXXXXXXB

37HA/D data register 1 ADCR1 R/W 0 0 0 0 1 _ XXB

38HPPG0 operation mode control register PPGC0 R/W 16-bit Programmable

Pulse

Generator 0/1

0 _ 0 0 0 _ _ 1B

39HPPG1 operation mode control register PPGC1 R/W 0 _ 0 0 0 0 0 1B

3AHPPG0/1 clock selection register PPG01 R/W 0 0 0 0 0 0 _ _B

3BHProhibited

3CHPPG2 operation mode control register PPGC2 R/W 16-bit Programmable

Pulse

Generator 2/3

0 _ 0 0 0 _ _1B

3DHPPG3 operation mode control register PPGC3 R/W 0 _ 0 0 0 0 0 1B

3EHPPG2/3 Clock Selection Register PPG23 R/W 0 0 0 0 0 0 _ _B

3FHProhibited

40HPPG4 operation mode control register PPGC4 R/W 16-bit Programmable

Pulse

Generator 4/5

0 _ 0 0 0 _ _ 1B

41HPPG5 operation mode control register PPGC5 R/W 0 _ 0 0 0 0 0 1B

42HPPG4/5 clock selection register PPG45 R/W 0 0 0 0 0 0 _ _B

43HProhibited

44HPPG6 operation mode control register PPGC6 R/W 16-bit Programmable

Pulse

Generator 6/7

0 _ 0 0 0 _ _ 1B

45HPPG7 operation mode control register PPGC7 R/W 0 _ 0 0 0 0 0 1B

46HPPG6/7 clock selection register PPG67 R/W 0 0 0 0 0 0 _ _B

MB90435 Series

(Continued)

Address Register Abbreviation Access Resource name Initial value

47H to 4BHProhibited

4CHInput capture control status register 0/1 ICS01 R/W Input Capture 0/1 0 0 0 0 0 0 0 0B

4DHInput capture control status register 2/3 ICS23 R/W Input Capture 2/3 0 0 0 0 0 0 0 0B

4EHInput capture control status register 4/5 ICS45 R/W Input Capture 4/5 0 0 0 0 0 0 0 0B

4FHInput capture control status register 6/7 ICS67 R/W Input Capture 6/7 0 0 0 0 0 0 0 0B

50HTimer control status register 0 TMCSR0 R/W

16-bit Reload

Timer 0

0 0 0 0 0 0 0 0B

51HTimer control status register 0 TMCSR0 R/W _ _ _ _ 0 0 0 0B

52HTimer register 0/reload register 0 TMR0/

TMRLR0 R/W XXXXXXXXB

53HTimer register 0/reload register 0 TMR0/

TMRLR0 R/W XXXXXXXXB

54HTimer control status register 1 TMCSR1 R/W

16-bit Reload

Timer 1

0 0 0 0 0 0 0 0B

55HTimer control status register 1 TMCSR1 R/W _ _ _ _ 0 0 0 0B

56HTimer register 1/reload register 1 TMR1/

TMRLR1 R/W XXXXXXXXB

57HTimer register 1/reload register 1 TMR1/

TMRLR1 R/W XXXXXXXXB

58HOutput compare control status register 0 OCS0 R/W Output Compare

0/1 0 0 0 0 _ _ 0 0B

59HOutput compare control status register 1 OCS1 R/W _ _ _0 0 0 0 0B

5AHOutput compare control status register 2 OCS2 R/W Output Compare

2/3 0 0 0 0 _ _ 0 0B

5BHOutput compare control status register 3 OCS3 R/W _ _ _ 0 0 0 0 0B

5CH to 6BHProhibited

6CHTimer Counter Data register TCDT R/W

I/O Timer

0 0 0 0 0 0 0 0B

6DHTimer Counter Data register TCDT R/W 0 0 0 0 0 0 0 0B

6EHTimer Counter Control status register TCCS R/W 0 0 0 0 0 0 0 0B

6FHROM mirror function selection register ROMM R/W ROM Mirror _ _ _ _ _ _ _ 1B

70H to 7FHReserved

80H to 8FHReserved

90H to 9DHProhibited

9EHProgram address detection

control status register PACSR R/W Address Match

Detection

Function 0 0 0 0 0 0 0 0B

9FHDelayed interrupt/release register DIRR R/W Delayed Interrupt _ _ _ _ _ _ _ 0B

A0HLow-power mode control register LPMCR R/W Low Power

Controller 0 0 0 1 1 0 0 0B

A1HClock selection register CKSCR R/W Low Power

Controller 1 1 1 1 1 1 0 0B

MB90435 Series

(Continued)

Address Register Abbreviation Access Resource name Initial value

A2H to A4HProhibited

A5HAutomatic ready function select register ARSR W External Memory

Access

0 0 1 1 _ _ 0 0B

A6HExternal address output control register HACR W 0 0 0 0 0 0 0 0B

A7HBus control signal selection register ECSR W 0 0 0 0 0 0 0 _B

A8HWatchdog Timer control register WDTC R/W Watchdog Timer XXXXX 1 1 1B

A9HTime Base Timer Control register TBTC R/W Time Base Timer 1 - - 0 0 1 0 0B

AAHWatch timer control register WTC R/W Watch Timer 1 X 0 0 0 0 0 0B

ABH to ADHProhibited

AEHFlash memory control status register

(Flash only, otherwise reserved) FMCS R/W Flash Memory 0 0 0 X 0 0 0 0B

AFHProhibited

B0HInterrupt control register 00 ICR00 R/W

Interrupt

controller

0 0 0 0 0 1 1 1B

B1HInterrupt control register 01 ICR01 R/W 0 0 0 0 0 1 1 1B

B2HInterrupt control register 02 ICR02 R/W 0 0 0 0 0 1 1 1B

B3HInterrupt control register 03 ICR03 R/W 0 0 0 0 0 1 1 1B

B4HInterrupt control register 04 ICR04 R/W 0 0 0 0 0 1 1 1B

B5HInterrupt control register 05 ICR05 R/W 0 0 0 0 0 1 1 1B

B6HInterrupt control register 06 ICR06 R/W 0 0 0 0 0 1 1 1B

B7HInterrupt control register 07 ICR07 R/W 0 0 0 0 0 1 1 1B

B8HInterrupt control register 08 ICR08 R/W 0 0 0 0 0 1 1 1B

B9HInterrupt control register 09 ICR09 R/W 0 0 0 0 0 1 1 1B

BAHInterrupt control register 10 ICR10 R/W 0 0 0 0 0 1 1 1B

BBHInterrupt control register 11 ICR11 R/W 0 0 0 0 0 1 1 1B

BCHInterrupt control register 12 ICR12 R/W 0 0 0 0 0 1 1 1B

BDHInterrupt control register 13 ICR13 R/W 0 0 0 0 0 1 1 1B

BEHInterrupt control register 14 ICR14 R/W 0 0 0 0 0 1 1 1B

BFHInterrupt control register 15 ICR15 R/W 0 0 0 0 0 1 1 1B

C0H to FFHExternal

Address Register Abbreviation Access Resource name Initial value

1FF0HProgram address detection register 0 PADR0 R/W

Address Match

Detection Function

XXXXXXXXB

1FF1HProgram address detection register 0 PADR0 R/W XXXXXXXXB

1FF2HProgram address detection register 0 PADR0 R/W XXXXXXXXB

1FF3HProgram address detection register 1 PADR1 R/W XXXXXXXXB

1FF4HProgram address detection register 1 PADR1 R/W XXXXXXXXB

1FF5HProgram address detection register 1 PADR1 R/W XXXXXXXXB

MB90435 Series

(Continued)

Address Register Abbreviation Access Resource name Initial value

3900HReload L PRLL0 R/W

16-bit Programmable Pulse

Generator 0/1

XXXXXXXXB

3901HReload H PRLH0 R/W XXXXXXXXB

3902HReload L PRLL1 R/W XXXXXXXXB

3903HReload H PRLH1 R/W XXXXXXXXB

3904HReload L PRLL2 R/W

16-bit Programmable Pulse

Generator 2/3

XXXXXXXXB

3905HReload H PRLH2 R/W XXXXXXXXB

3906HReload L PRLL3 R/W XXXXXXXXB

3907HReload H PRLH3 R/W XXXXXXXXB

3908HReload L PRLL4 R/W

16-bit Programmable Pulse

Generator 4/5

XXXXXXXXB

3909HReload H PRLH4 R/W XXXXXXXXB

390AHReload L PRLL5 R/W XXXXXXXXB

390BHReload H PRLH5 R/W XXXXXXXXB

390CHReload L PRLL6 R/W

16-bit Programmable Pulse

Generator 6/7

XXXXXXXXB

390DHReload H PRLH6 R/W XXXXXXXXB

390EHReload L PRLL7 R/W XXXXXXXXB

390FHReload H PRLH7 R/W XXXXXXXXB

3910H to

3917HReserved

3918HInput Capture Register 0 IPCP0 R

Input Capture 0/1

XXXXXXXXB

3919HInput Capture Register 0 IPCP0 R XXXXXXXXB

391AHInput Capture Register 1 IPCP1 R XXXXXXXXB

391BHInput Capture Register 1 IPCP1 R XXXXXXXXB

391CHInput Capture Register 2 IPCP2 R

Input Capture 2/3

XXXXXXXXB

391DHInput Capture Register 2 IPCP2 R XXXXXXXXB

391EHInput Capture Register 3 IPCP3 R XXXXXXXXB

391FHInput Capture Register 3 IPCP3 R XXXXXXXXB

3920HInput Capture Register 4 IPCP4 R

Input Capture 4/5

XXXXXXXXB

3921HInput Capture Register 4 IPCP4 R XXXXXXXXB

3922HInput Capture Register 5 IPCP5 R XXXXXXXXB

3923HInput Capture Register 5 IPCP5 R XXXXXXXXB

3924HInput Capture Register 6 IPCP6 R

Input Capture 6/7

XXXXXXXXB

3925HInput Capture Register 6 IPCP6 R XXXXXXXXB

3926HInput Capture Register 7 IPCP7 R XXXXXXXXB

3927HInput Capture Register 7 IPCP7 R XXXXXXXXB

MB90435 Series

(Continued)

• Read/write notation

• Initial value notation

Note : Any write access to reserved addresses in I/O map should not be performed. A read access to reserved

addresses results in reading “X”.

Address Register Abbreviation Access Resource name Initial value

3928HOutput Compare Register 0 OCCP0 R/W

Output Compare 0/1

XXXXXXXXB

3929HOutput Compare Register 0 OCCP0 R/W XXXXXXXXB

392AHOutput Compare Register 1 OCCP1 R/W XXXXXXXXB

392BHOutput Compare Register 1 OCCP1 R/W XXXXXXXXB

392CHOutput Compare Register 2 OCCP2 R/W

Output Compare 2/3

XXXXXXXXB

392DHOutput Compare Register 2 OCCP2 R/W XXXXXXXXB

392EHOutput Compare Register 3 OCCP3 R/W XXXXXXXXB

392FHOutput Compare Register 3 OCCP3 R/W XXXXXXXXB

3930H to

39FFHReserved

3A00H to

3AFFHReserved

3B00H to

3BFFHReserved

3C00H to

3CFFHReserved

3D00H to

3DFFHReserved

3E00H to

3FFFHReserved

R/W : Reading and writing permitted

R : Read-only

W : Write-only

0 : Initial value is “0”.

1 : Initial value is “1”.

X : Initial value is undefined.

MB90435 Series

■

■■

■INTERRUPT MAP

Interrupt cause EI2OS

clear Interrupt vector Interrupt control register

Number Address Number Address

Reset N/A #08 FFFFDCH

INT9 instruction N/A #09 FFFFD8H

Exception N/A #10 FFFFD4H

Reserved N/A #11 FFFFD0HICR00 0000B0H

Reserved N/A #12 FFFFCCH

Reserved N/A #13 FFFFC8HICR01 0000B1H

Reserved N/A #14 FFFFC4H

External Interrupt INT0/INT1 *1 #15 FFFFC0HICR02 0000B2H

Time Base Timer N/A #16 FFFFBCH

16-bit Reload Timer 0 *1 #17 FFFFB8HICR03 0000B3H

8/10-bit A/D Converter *1 #18 FFFFB4H

I/O Timer N/A #19 FFFFB0HICR04 0000B4H

External Interrupt INT2/INT3 *1 #20 FFFFACH

Serial I/O *1 #21 FFFFA8 HICR05 0000B5H

8/16-bit PPG 0/1 N/A #22 FFFFA4H

Input Capture 0 *1 #23 FFFFA0HICR06 0000B6H

External Interrupt INT4/INT5 *1 #24 FFFF9CH

Input Capture 1 *1 #25 FFFF98HICR07 0000B7H

8/16-bit PPG 2/3 N/A #26 FFFF94H

External Interrupt INT6/INT7 *1 #27 FFFF90HICR08 0000B8H

Watch Timer N/A #28 FFFF8CH

8/16-bit PPG 4/5 N/A #29 FFFF88HICR09 0000B9H

Input Capture 2/3 *1 #30 FFFF84H

8/16-bit PPG 6/7 N/A #31 FFFF80HICR10 0000BAH

Output Compare 0 *1 #32 FFFF7CH

Output Compare 1 *1 #33 FFFF78HICR11 0000BBH

Input Capture 4/5 *1 #34 FFFF74H

Output Compare 2/3 - Input Capture 6/7 *1 #35 FFFF70HICR12 0000BCH

16-bit Reload Timer 1 *1 #36 FFFF6CH

UART 0 RX *2 #37 FFFF68HICR13 0000BDH

UART 0 TX *1 #38 FFFF64H

UART 1 RX *2 #39 FFFF60HICR14 0000BEH

UART 1 TX *1 #40 FFFF5CH

Flash Memory N/A #41 FFFF58HICR15 0000BFH

Delayed interrupt N/A #42 FFFF54H

MB90435 Series

*1 : The interrupt request flag is cleared by the EI2OS interrupt clear signal.

*2 : The interrupt request flag is cleared by the EI2OS interrupt clear signal. A stop request is available.

Notes : • N/A : The interrupt request flag is not cleared by the EI2OS interrupt clear signal.

• For a peripheral module with two interrupt causes for a single interrupt number, both interrupt request flags

are cleared by the EI2OS interrupt clear signal.

• At the end of EI2OS, the EI2OS clear signal will be asserted f or all the interrupt flags assigned to the same

interrupt number . If one interrupt flag starts the EI2OS and in the meantime another interrupt flag is set by

a hardware e vent, the later e vent is lost because the flag is cleared by the EI2OS clear signal caused by the

first event. So it is recommended not to use the EI2OS for this interrupt number.

• If EI2OS is enabled, EI2OS is initiated when one of the two interrupt signals in the same interrupt control

which should be unique for each interrupt source. For this reason, when one interrupt source uses the

EI2OS, the other interrupt should be disabled.

MB90435 Series

■

■■

■ELECTRICAL CHARACTERISTICS

1. Absolute Maximu m Ratings (VSS = AVSS = 0.0 V)

*1 : AVCC, AVRH, AVRL should not exceed VCC. Also, AVRH, AVRL should not exceed AVCC, and AVRL does not

exceed AVRH.

*2 : VI and VO should not exceed VCC + 0.3 V. VI should not exceed the specified ratings. Howe ver if the maximum

current to/from an input is limited by some means with external components, the ICLAMP rating supercedes the

VI rating.

*3 : The maximum output current is a peak value for a corresponding pin.

*4 : Average output current is an average current value observed for a 100 ms period for a corresponding pin.

*5 : Total average current is an average current value observed for a 100 ms period for all corresponding pins.

*6 : • Applicable to pins : P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67,

P70 to P77, P80 to P87, P90 to P97, PA0

• Use within recommended operating conditions.

• Use at DC voltage (current) .

• The +B signal should always be applied with a limiting resistance placed between the +B signal and the

microcontroller.

• The value of the limiting resistance should be set so that when the +B signal is applied the input current to

the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.

• Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input

potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect

other devices.

• Note that if a +B signal is input when the microcontroller current is off (not fixed at 0 V) , the power supply is

provided from the pins, so that incomplete operation may result.

• Note that if the +B input is applied during power-on, the power supply is provided from the pins and the

resulting supply voltage may not be sufficient to operate the power-on result.

(Continued)

Parameter Symbol Value Units Remarks

Min Max

Power supply voltage

VCC VSS − 0.3 VSS + 6.0 V

AVCC VSS − 0.3 VSS + 6.0 V VCC = AVCC *1

AVRH,

AVRL VSS − 0.3 VSS + 6.0 V AVCC ≥ AVRH/AVRL,

AVRH ≥ AVRL *1

Input voltage VIVSS − 0.3 VSS + 6.0 V *2

Output voltage VOVSS − 0.3 VSS + 6.0 V *2

Maximum clamp current ICLAMP − 2.0 + 2.0 mA *6

Total maximum clamp current ∑| ICLAMP | 20 mA *6

“L” level max output current IOL 15 mA *3

“L” level avg. output current IOLAV 4mA *4

“L” level max overall output current ∑IOL 100 mA

“L” level avg. overall output current ∑IOLAV 50 mA *5

“H” level max output current IOH −15 mA *3

“H” level avg. output current IOHAV −4mA *4

“H” level max overall output current ∑IOH −100 mA

“H” level avg. overall output current ∑IOHAV −50 mA *5

Power consumption PD500 mW Flash device

400 mW Mask ROM

Operating temperature TA−40 +105 °C

Storage temperature TSTG −55 +150 °C

MB90435 Series

(Continued)

• Care must be taken not to leave the +B input pin open.

• Note that analog system input/output pins other than the A/D input pins (LCD drive pins, comparator input

pins, etc.) cannot accept +B signal input.

• Sample recommended circuits :

Note : Average output current = operating current × operating efficiency

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

P-ch

N-ch

VCC

• Input/Output Equivalent circuits

+B input (0 V to 16 V)

Limiting

resistance

Protective diode

MB90435 Series

2. Recommended Conditions (VSS = AVSS = 0.0 V)

*: Use a ceramic capacitor or a capacitor of better 4. A C characteristics. The VCC Capacitor should be greater than

this capacitor.

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All of the device’s electrical characteristics are warranted when the device is

operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges. Operation

outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on

the data sheet. Users considering application outside the listed conditions are advised to contact their

FUJITSU representatives beforehand.

Parameter Symbol Value Units Remarks

Min Typ Max

Power supply voltage VCC,

AVCC

4.5 5.0 5.5 V Under normal operation :

MB90F439 (S) /439 (S) /V540G

3.5 5.0 5.5 V Under normal operation :

MB90F438L (S) /437L (S) /438L (S)

3.0 5.5 V Maintain RAM data in stop mode

Smooth capacitor CS0.022 0.1 1.0 µF*

Operating temperature TA−40 +105 °C

• C Pin Connection Diagram

MB90435 Series

3. DC Characteristics

(MB90F438L (S) /437L (S) /438L (S) : VCC = 3.5 V to 5.5 V, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)

(MB90F439 (S) /439 (S) /V540G : VCC = 5.0 V ± 10%, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)

(Continued)

Parameter Sym-

bol Pin name Condition Value Units Remarks

Min Typ Max

Input H

voltage

VIHS CMOS

hysteresis

input pin 0.8 VCC VCC + 0.3 V

VIH TTL input

pin 2.0 V

VIHM MD input

pin VCC − 0.3 VCC + 0.3 V

Input L

voltage

VILS CMOS

hysteresis

input pin VCC − 0.3 0.2 VCC V

VIL TTL input

pin 0.8 V

VILM MD input

pin VSS − 0.3 VCC + 0.3 V

Output H

voltage VOH All output

pins VCC = 4.5 V,

IOH = −4.0 mA VCC − 0.5 V

Output L

voltage VOL All output

pins VCC = 4.5 V,

IOL = 4.0 mA 0.4 V

Input leak

current IIL VCC = 5.5 V,

VSS < VI < VCC −55µA

Pull-up

resistance RUP

P00 to P07,

P10 to P17,

P20 to P27,

P30 to P37,

RST

25 50 100 kΩ

Pull-down

resistance RDO

WN MD2 25 50 100 kΩ

MB90435 Series

(Continued)

(MB90F438L (S) /437L (S) /438L (S) : VCC = 3.5 V to 5.5 V, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)

(MB90F439 (S) /439 (S) /V540G : VCC = 5.0 V ± 10%, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)

* : The power supply current testing conditions are when using the external clock.

Parameter Sym-

bol Pin name Condition Value Units Remarks

Min Typ Max

Power

supply

current*

ICC

VCC

Internal frequency : 16 MHz,

At normal operating 40 55 mA

Internal frequency : 16 MHz,

At Flash programming/erasing 50 70 mA Flash device

ICCS Internal frequency : 16 MHz,

At sleep mode 12 20 mA

ICTS VCC = 5.0 V ± 1%,

Internal frequency : 2 MHz,

At pseudo timer mode

300 600 µA

600 1100 µA MB90F348L (S)

200 400 µAMB90437L (S) /

438L (S)

ICCL Internal frequency : 8 kHz,

At sub operation, TA = 25 °C

400 750 µA MB90F438L (S)

50 100 µAMask ROM

150 300 µA Flash device

ICCLS Internal frequency : 8 kHz,

At sub sleep, TA = 25 °C15 40 µA

ICCT Internal frequency : 8 kHz,

At timer mode, TA = 25 °C725µA

ICCH1 At stop, TA = 25 °C520µA

ICCH2 At hardware standby mode,

TA = 25 °C50 100 µA

Input

capacity CIN

Other than

AVCC, AVSS,

AVRH,

AVRL, C,

VCC, VSS

515pF

MB90435 Series

4. AC Characteristics

(1) Clock Timing

(MB90F438L (S) /437L (S) /438L (S) : VCC = 3.5 V to 5.5 V, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)

(MB90F439 (S) /439 (S) /V540G : VCC = 5.0 V ± 10%, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)

Parameter Symbol Pin name Value Units Remarks

Min Typ Max

Oscillation frequency fCX0, X1 316 MHz VCC = 5.0 V±10%

35MHz

VCC<4.5 (MB90F438L (S) /

437L (S) /438L (S) )

fCL X0A, X1A 32.768 kHz

Oscillation cycle time tCYL X0, X1 62.5 333 ns VCC = 5.0 V±10%

200 333 ns VCC<4.5 (MB90F438L (S) /

437L (S) /438L (S) )

tLCYL X0A, X1A 30.5 µs

Input clock pulse width PWH, PWL X0 10 ns Duty ratio is about 30% to

70%.

PWLH, PWLL X0A 15.2 µs

Input clock rise and fall

time tCR, tCF X0  5 ns When using external clock

Machine clock frequency fCP 1.5 16 MHz When using main clock

fLCP 8.192 kHz When using sub-clock

Machine clock cycle time tCP 62.5 666 ns When using main clock

tLCP 122.1 µs When using sub-clock

tCYL

tCF tCR

0.8 VCC

0.2 VCC

PWH PWL

X0A

tLCYL

tCF tCR

0.8 VCC

0.2 VCC

PWLH PWLL

• Clock Timing

MB90435 Series

5.5

3.5

1.5 816

Guaranteed operation range

(MB90F438L(S)/437L(S)/438L(S))

Guaranteed PLL operation range

(MB90F438L(S)/437L(S)/438L(S))

4.5

Guaranteed operation range

(MB90F439(S)/439(S)/V540G)

Guaranteed PLL operation range

( MB90F439(S)/439(S)/V540G)

Power supply voltage

VCC (V)

Machine clock fCP (MHz)

• Guaranteed PLL operation range

34 8 16

×4×3×2×1

PLL off

• External clock frequency and Machine clock frequency

Machine clock

fCP (MHz)

External clock fC (MHz)

MB90435 Series

AC characteristics are set to the measured reference voltage values below.

0.8 VCC

0.2 VCC

2.4 V

0.8 V

2.0 V

0.8 V

• Input signal waveform • Output signal waveform

Hysteresis Input Pin

TTL Input Pin

Output Pin

MB90435 Series

(2) Clock Output Timing

(MB90F438L (S) /437L (S) /438L (S) : VCC = 3.5 V to 5.5 V, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)

(MB90F439 (S) /439 (S) /V540G : VCC = 5.0 V ± 10%, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)

(3) Reset and Hardware Standby Input Timing

(MB90F438L (S) /437L (S) /438L (S) : VCC = 3.5 V to 5.5 V, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)

(MB90F439 (S) /439 (S) /V540G : VCC = 5.0 V ± 10%, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)

“tcp” represents one cycle time of the machine clock.

Oscillation time of oscillator is time that amplitude reached the 90%. In the crystal oscillator, the oscillation time is

between several ms to tens of ms. In FAR/ceramic oscillator, the oscillation time is between handreds of µs to

several ms. In the external clock, the oscillation time is 0 ns.

Any reset can not fully initialize the Flash Memory if it is performing the automatic algorithm.

Parameter Symbol Pin name Condition Value Units Remarks

Min Max

Cycle time tCYC CLK VCC = 5 V ± 10%62.5 ns

CLK↑ →CLK↓tCHCL 20 ns

Parameter Symbol Pin

name Value Units Remarks

Min Max

Reset input time tRSTL RST

4 tCP ns Under normal operation

Oscillation time of

oscillator + 4 tCP ms In stop mode

100 µsPseudo timer mode

(MB90437L (S) /438L (S) )

4 tCP ns Pseudo timer mode

(Other than MB90437L (S)

/438L (S) )

2 tCP µsIn sub clock mode, sub

sleep mode and watch

mode

Hardware standby input time tHSTL HST 4 tCP ns Under normal operation

CLK

tCYC

2.4 V 2.4 V

0.8 V

tCHCL

MB90435 Series

RST

HST 0.2 VCC

tRSTL, tHSTL

0.2 VCC

tRSTL

0.2 VCC 0.2 VCC

4 tCP

RST

Internal operation clock

Internal reset

90% of

amplitude

Oscillation time of

oscillator Oscillation setting time

Instruction execution

• Under normal operation, Pseudo timer mode, Sub clock mode, Sub sleep mode, Watch mode

• In stop mode

MB90435 Series

(4) Power On Reset

(MB90F438L (S) /437L (S) /438L (S) : VCC = 3.5 V to 5.5 V, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)

(MB90F439 (S) /439 (S) /V540G : VCC = 5.0 V ± 10%, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)

* : VCC must be kept lower than 0.2 V before power-on.

Notes : • The above values are used for creating a power-on reset.

• Some registers in the de vice are initialized only upon a power-on reset. To initialize these register, turn on

the power supply using the above values.

Parameter Symbol Pin

name Condition Value Units Remarks

Min Max

Power on rise time tRVCC 0.05 30 ms *

Power off time tOFF VCC 50 ms Due to repetitive operation

VCC

VSS

3.0 V

tOFF

2.7 V

0.2 V 0.2 V0.2 V

RAM data being held

It is recommended to keep the

rising speed of the supply voltage

at 50 mV/ms or slower.

Sudden changes in the power supply voltage may cause a power-on reset.

To change the power supply voltage while the device is in operation, it is recommended to

raise the voltage smoothly to suppress fluctuations as shown below.

In this case, change the supply voltage with the PLL clock not used. If the voltage drop is

1 V or fewer per second, however, you can use the PLL clock.

MB90435 Series

(5) Bus Timing (Read)

(MB90F438L (S) /437L (S) /438L (S) : VCC = 3.5 V to 5.5 V, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)

(MB90F439 (S) /439 (S) /V540G : VCC = 5.0 V ± 10%, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)

Parameter Symbol Pin name Condition Value Units Remarks

Min Max

ALE pulse width tLHLL ALE



tCP/2 − 20 ns

Valid address→ALE↓time tAVLL ALE,

A16 to A23,

AD00 to AD15 tCP/2 − 20 ns

ALE↓→Address valid time tLLAX ALE,

AD00 to AD15 tCP/2 − 15 ns

Valid address→RD↓time tAVRL A16 toA23,

AD00 to AD15,

RD tCP − 15 ns

Valid address→Valid data

input tAVDV A16 to A23,

AD00 to AD15 5 tCP/2 − 60 ns

RD pulse width tRLRH RD 3 tCP/2 − 20 ns

RD↓→Valid data input tRLDV RD,

AD00 to AD15 3 tCP/2 − 60 ns

RD↑→Data hold time tRHDX RD,

AD00 to AD15 0ns

RD↓→ALE↑time tRHLH RD, ALE tCP/2 − 15 ns

RD↑→Address valid time tRHAX RD, A16 to A23 tCP/2 − 10 ns

Valid address→CLK↑time tAVCH A16 to A23,

AD00 to AD15,

CLK tCP/2 − 20 ns

RD↓→CLK↑time tRLCH RD, CLK tCP/2 − 20 ns

ALE↓→RD↓time tLLRL ALE, RD tCP/2 − 15 ns

MB90435 Series

0.8 V

2.4 V

0.8 V

2.4 V

0.8 V

2.4 V

0.8 V

2.4 V

0.8 V

2.4 V

0.2 VCC

0.8 VCC

0.2 VCC

0.8 VCC

CLK

ALE

A16 to A23

AD00 to AD15

2.4 V

tAVCH

tLHLL

tRHLH

tAVLL

tAVRL tRLDV

tRLRH

tRHAX

tRHDX

tLLAX

tLLRL

tRLCH

tAVDV

Address Read data

• Bus Timing (Read)

MB90435 Series

(6) Bus Timing (Write)

(MB90F438L (S) /437L (S) /438L (S) : VCC = 3.5 V to 5.5 V, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)

(MB90F439 (S) /439 (S) /V540G : VCC = 5.0 V ± 10%, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)

Parameter Symbol Pin name Condition Value Units Remarks

Min Max

Valid address→WR↓time tAVWL A16 to A23

AD00 to AD15,



tCP − 15 ns

WR pulse width tWLWH WR 3 tCP/2 − 20 ns

Valid data output→WR↑time tDVWH AD00 to AD15,

WR 3 tCP/2 − 20 ns

WR↑→Data hold time tWHDX AD00 to AD15,

WR 20 ns

WR↑→Address valid time tWHAX A16 to A23,

WR tCP/2 − 10 ns

WR↑→ALE↑time tWHLH WR, ALE tCP/2 − 15 ns

WR↑→CLK↑time tWLCH WR, CLK tCP/2 − 20 ns

0.8 V

2.4 V

0.8 V

2.4 V

0.8 V

2.4 V

0.8 V

2.4 V

0.8 V

2.4 V

CLK

ALE

WR (WRL, WRH)

A16 to A23

AD00 to AD15

tWHLH

tAVWL tWLWH

tWHAX

tWHDX

tWLCH

tDVWH

Address Write data

• Bus Timing (Write)

MB90435 Series

(7) Ready Input Timing

(MB90F438L (S) /437L (S) /438L (S) : VCC = 3.5 V to 5.5 V, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)

(MB90F439 (S) /439 (S) /V540G : VCC = 5.0 V ± 10%, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)

Note : If the RDY setup time is insufficient, use the auto-ready function.

Parameter Symbol Pin name Condition Value Units Remarks

Min Max

RDY setup time tRYHS RDY 45 ns

RDY hold time tRYHH RDY 0 ns

tRYHS tRYHH

2.4 V

0.8 VCC

0.2 VCC

0.8 VCC

CLK

ALE

RD/WR

RDY

no WAIT is used.

RDY

When WAIT is used

(1 cycle).

• Ready Input Timing

MB90435 Series

(8) Hold Timing

(MB90F438L (S) /437L (S) /438L (S) : VCC = 3.5 V to 5.5 V, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)

(MB90F439 (S) /439 (S) /V540G : VCC = 5.0 V ± 10%, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)

Note : There is more than 1 cycle from the time HRQ is read to the time the HAK is changed.

(9) UART0/1, Serial I/O Timing

(MB90F438L (S) /437L (S) /438L (S) : VCC = 3.5 V to 5.5 V, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)

(MB90F439 (S) /439 (S) /V540G : VCC = 5.0 V ± 10%, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)

Notes : • AC characteristic in CLK synchronized mode.

• CL is load capacity value of pins when testing.

• For tCP (Machine clock cycle time) , refer to “ (1) Clock Timing”.

Parameter Symbol Pin name Condition Value Units Remarks

Min Max

Pin floating→HAK↓time tXHAL HAK 30 tCP ns

HAK↑time→Pin valid time tHAHV HAK tCP 2 tCP ns

Parameter Symbol Pin name Condition Value Units Remarks

Min Max

Serial clock cycle time tSCYC SCK0 to SCK2

Internal clock opera-

tion output pins are

CL = 80 pF + 1 TTL.

8 tCP ns

SCK↓→SOT delay time tSLOV SCK0 to SCK2,

SOT0 to SOT2 −80 80 ns

Valid SIN→SCK↑tIVSH SCK0 to SCK2,

SIN0 to SIN2 100 ns

SCK↑→Valid SIN hold time tSHIX SCK0 to SCK2,

SIN0 to SIN2 60 ns

Serial clock “H” pulse width tSHSL SCK0 to SCK2

External clock oper-

ation output pins are

CL = 80 pF + 1 TTL.

4 tCP ns

Serial clock “L” pulse width tSLSH SCK0 to SCK2 4 tCP ns

SCK↓→SOT delay time tSLOV SCK0 to SCK2,

SOT0 to SOT2 150 ns

Valid SIN→SCK↑tIVSH SCK0 to SCK2,

SIN0 to SIN2 60 ns

SCK↑→Valid SIN hold time tSHIX SCK0 to SCK2,

SIN0 to SIN2 60 ns

HAK

tXHAL tHAHV

2.4 V

0.8 V 2.4 V

2.4 V

0.8 V

Each pin High impedance

• Hold Timing

MB90435 Series

SCK

SOT

SIN

tSCYC

tSLOV

tIVSH tSHIX

0.8 V 0.8 V

2.4 V

0.8 V

0.8 VCC

0.2 VCC

0.8 VCC

0.2 VCC

• Internal Shift Clock Mode

SCK

SOT

SIN

tSLSH tSHSL

tSLOV

tIVSH tSHIX

0.2 VCC 0.2 VCC

0.8 VCC 0.8 VCC

2.4 V

0.8 V

0.8 VCC

0.2 VCC

0.8 VCC

0.2 VCC

• External Shift Clock Mode

MB90435 Series

(10) Timer Input Timing

(MB90F438L (S) /437L (S) /438L (S) : VCC = 3.5 V to 5.5 V, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)

(MB90F439 (S) /439 (S) /V540G : VCC = 5.0 V ± 10%, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)

(11) Timer Output Timing

(MB90F438L (S) /437L (S) /438L (S) : VCC = 3.5 V to 5.5 V, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)

(MB90F439 (S) /439 (S) /V540G : VCC = 5.0 V ± 10%, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)

Parameter Symbol Pin name Condition Value Units Remarks

Min Max

Input pulse width tTIWH TIN0, TIN1 4 tCP ns

tTIWL IN0 to IN7

Parameter Symbol Pin name Condition Value Units Remarks

Min Max

CLK↑→TOUT change time tTO TOT0 to TOT1,

PPG0 to PPG3 30 ns

0.8 VCC 0.8 VCC

0.2 VCC 0.2 VCC

tTIWH tTIWL

• Timer Input Timing

CLK

TOUT

2.4 V

tTO

2.4 V

0.8 V

• Timer Output Timing

MB90435 Series

(12) Trigger Input Timing

(MB90F438L (S) /437L (S) /438L (S) : VCC = 3.5 V to 5.5 V, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)

(MB90F439 (S) /439 (S) /V540G : VCC = 5.0 V ± 10%, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)

Parameter Symbol Pin name Condition Value Units Remarks

Min Max

Input pulse width tTRGH

tTRGL INT0 to INT7,

ADTG 5 tCP ns Under nomal operation

1µs In stop mode

0.8 VCC 0.8 VCC

0.2 VCC 0.2 VCC

tTRGH tTRGL

• Trigger Input Timing

MB90435 Series

5. A/D Converter

• Electrical Characteristics

(VCC = AVCC = 5.0 V±10%, VSS = AVSS = 0.0 V, 3.0 V ≤ AVRH − AVRL, TA = −40 °C to +105 °C)

* : When not using an A/D converter, this is the current (VCC = AVCC = AVRH = 5.0 V) when the CPU is stopped.

Note: The functionality of the A/D converter is only guaranteed for VCC = 5.0 V ± 10 % (also for MB90F438L (S) /

437L (S) /438L (S) ) .

Parameter Symbol Pin name Value Units Remarks

Min Typ Max

Resolution    10 bit

Conversion error    ±5.0 LSB

Nonlinearity error   ±2.5 LSB

Differential nonlinearity

error   ±1.9 LSB

Zero transition voltage VOT AN0 to AN7 AVRL − 3.5

LSB AVRL + 0.5

LSB AVRL + 4.5

LSB mV

Full scale transition voltage V FST AN0 to AN7 AVRH − 6.5

LSB AVRH − 1.5

LSB AVRH + 1.5

LSB mV

Compare time 352 tCP ns Internal

frequency :

16 MHz

Sampling time 64 tCP ns Internal

frequency :

16 MHz

Analog port input current IAIN AN0 to AN7 −11µAVCC = AVCC =

5.0 V ± 1%

Analog input voltage range VAIN AN0 to AN7 A VRL AVRH V

Reference voltage range AVRH AVRL + 2.7 AVCC V

AVRL 0 AVRH − 2.7 V

Power supply current IAAVCC 5mA

IAH AVCC  5µA*

Reference voltage supply

current IRAVRH 400 600 µA Flash device

140 260 µA Mask ROM

IRH AVRH  5µA*

Offset between input

channels AN0 to AN7  4LSB

MB90435 Series

• A/D Converter Glossary

Resolution : Analog changes that are identifiable with the A/D converter

Linearity error : The deviation of the str aight line connecting the zero transition point (“00 0000 0000” ←→ “00

0000 0001”) with the full-scale transition point (“11 1111 1110” ←→ “11 1111 1111”) from actual

conversion characteristics

Diff erential linearity error : The deviation of input voltage needed to change the output code by 1 LSB from the

theoretical value

Total error : The total error is defined as a difference between the actual value and the theoretical v alue, which

includes zero-transition error/full-scale transition error and linearity error.

(Continued)

3FF

3FE

3FD

004

003

002

001

AVRL AVRH

VNT

0.5 LSB

{1 LSB × (N − 1) + 0.5 LSB}

Analog input

Digital output

Total error

Actual conversion

Value

Actual conversion

characteristics

(measured value)

Theoretical

characteristics

[V]

AVRH − AVRL

1024

1 LSB = (Theoretical value)

VOT (Theoretical value) = AVRL + 0.5 LSB [V]

VFST (Theoretical value) = AVRH − 1.5 LSB [V]

Total error for digital output N = [LSB]

VNT − {1 LSB × (N − 1) + 0.5 LSB}

1 LSB

VNT : Voltage at a transition of digital output from (N − 1) to N

MB90435 Series

(Continued)

• Notes on Using A/D Converter

Select the output impedance value for the e xternal circuit of analog input according to the following conditions, :

• Output impedance values of the external circuit of 15 kΩ or lower are recommended.

• When capacitors are connected to external pins, the capacitance of several thousand times the internal

capacitor v alue is recommended to minimized the eff ect of v oltage distribution between the e xternal capacitor

and internal capacitor.

Note : When the output impedance of the e xternal circuit is too high, the sampling period for analog voltages ma y

not be sufficient (sampling period = 4.00 µs @machine clock of 16 MHz) .

•Error

The smaller the | AVRH − AVRL |, the greater the error would become relatively.

3FF

3FE

3FD

004

003

002

001

AVRL AVRH AVRL AVRH

N + 1

N − 1

N − 2

VNT

V (N + 1) T

VOT

VFST

{1 LSB × (N − 1) + VOT }

Digital output

Linearity error Differential linearity error

Analog input Analog input

Actual conversion

value

(measured value)

Actual conversion

characteristics

Theoretical

characteristics

(measured value)

Theorential characteristics

Actual conversion value

(measured value)

Acturel conversion

value

Linearity error of

digital output N [LSB]

VNT − {1 LSB × (N − 1) + VOT}

1 LSB

[V]

VFST − VOT

1022

1 LSB

− 1 LSB [LSB]

V (N + 1) T − VNT

1 LSB

Differential linearity error

of digital N

VOT : Voltage at transition of digital output from “000H” to “001H”

VFST : Voltage at transition of digital output from “3FEH” to “3FFH”

3.2 kΩ Max.

30 pF Max.

Analog input Comparator

• Equipment of analog input circuit model

MB90435 Series

6. Flash Memory Program/Erase Characteristics

Parameter Condition Value Units Remarks

Min Typ Max

Sector erase time

TA = + 25 °C

VCC = 5.0 V

1 15 s Excludes 00H programming prior erasure

Chip erase time 5s MB90F438L (S) Excludes 00H

programming

prior erasure

7s MB90F439 (S)

Word (16 bit width)

programming time 16 3,600 µs Excludes system-level overhead

Erase/Program cycle 10,000 cycle

MB90435 Series

■

■■

■EXAMPLE CHARACTERISTICS

4.5

3.5

2.5

1.5

0.5

00 -10-8-6-4-2

IOH [mA]

VOH [V]

VOH – IOH

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

00108642

IOL [mA]

VOL [V]

VOL – IOL

(VCC = 4.5 V, Ta = +25˚C) (VCC = 4.5 V,Ta = +25˚C)

03 5.554.543.5 Vcc [V]

Vin [V]

Vin – Vcc

6 6.5

VIH

VIL

(Ta = +25˚C)

• “H” level output voltage

• “H” level input voltage/ “L” level input voltage

(Hysterisis inpiut)

• “L” level output voltage

MB90435 Series

• Power supply current (MB90439)

0276543

Vcc [V]

Icc [mA]

Icc – Vcc

fcp = 12 MHz

fcp = 16 MHz

fcp = 10 MHz

fcp = 8 MHz

fcp = 4 MHz

fcp = 2 MHz

276543 Vcc [V]

Icc [mA]

Iccs – Vcc

fcp = 12 MHz

fcp = 16 MHz

fcp = 10 MHz

fcp = 8 MHz

fcp = 4 MHz

fcp = 2 MHz

600

500

400

300

200

100

0276543

Vcc [V]

ICTS [µA]

ICTS – VCC

fcp = 2 MHz

0276543

Vcc [V]

ICCL [µA]

ICCL – VCC

fcp = 8 kHz

100

(Ta = +25˚C) (Ta = +25˚C)

MB90435 Series

Vcc [V]

ICCLS [µA]

ICCLS – VCC

fcp = 8 kHz

027

6543

Vcc [V]

ICCT [µA]

ICCT – VCC

0276543

Vcc [V]

ICCH1 [µA]

ICCH1 – VCC

6543

(ST OP, Ta = +25˚C)

(Ta = +25˚C) (Ta = +25˚C)

fcp = 8 kHz

MB90435 Series

• Power supply current (MB90F439)

023456

fcp = 8 MHz

fcp = 4 MHz

fcp = 2 MHz

fcp = 16 MHz

fcp = 12 MHz

fcp = 10 MHz

Icc – Vcc

ICC [mA]

VCC [V]

023456

Iccs – Vcc

ICC [mA]

VCC [V]

600

500

400

300

200

100

023456

fcp = 2 MHz

ICTS – VCC

ICTS [µA]

VCC [V]

300

250

200

150

100

023456

fcp = 8 kHz

ICCL – VCC

ICCL [µA]

VCC [V]

(Ta = +25 ˚C) (Ta = +25 ˚C)

fcp = 8 MHz

fcp = 4 MHz

fcp = 2 MHz

fcp = 16 MHz

fcp = 12 MHz

fcp = 10 MHz

MB90435 Series

023456

fcp = 8 MHz

ICCLS – VCC

ICCLS [µA]

VCC [V] 7

023456

ICCT – VCC

ICCT [µA]

VCC [V] 7

100

23456

ICCH2 – VCC

ICCH2 [µA]

VCC [V] 7

(hardware standby, Ta = +25 ˚C)

(Ta = +25 ˚C)

fcp = 8 MHz

276543

Vcc [V]

ICCH1 [µA]

ICCH1 – VCC (ST OP, Ta = +25˚C)

MB90435 Series

■

■■

■ORDERING INFORMATION

Part number Package Remarks

MB90F438LPF

MB90F438LSPF

MB90F439PF

MB90F439SPF

MB90437LPF

MB90437LSPF

MB90438LPF

MB90438LSPF

MB90439PF

MB90439SPF

100-pin Plastic QFP

(FPT-100P-M06)

MB90F438LPFV

MB90F438LSPFV

MB90F439PFV

MB90F439SPFV

MB90437LPFV

MB90437LSPFV

MB90438LPFV

MB90438LSPFV

MB90439PFV

MB90439SPFV

100-pin Plastic LQFP

(FPT-100P-M05)

MB90435 Series

■

■■

■PACKAGE DIMENSIONS

100-pin Plastic QFP

(FPT-100P-M06)

Dimensions in mm (inches)

100-pin Plastic LQFP

(FPT-100P-M05)

Dimensions in mm (inches)

Note: Pins width and pins thickness include plating thickness.

2001 FUJITSU LIMITED F100008S-c-4-4

1 30

5180

100

20.00±0.20(.787±.008)

23.90±0.40(.941±.016)

14.00±0.20

(.551±.008)

17.90±0.40

(.705±.016)

INDEX

0.65(.026) 0.32±0.05

(.013±.002) M

0.13(.005)

"A"

0.17±0.06

(.007±.002)

0.10(.004)

Details of "A" part

0~8°

(.035±.006)

0.88±0.15

(.031±.008)

0.80±0.20

0.25(.010)

3.00 +0.35

–0.20

+.014

–.008

.118

(Mounting height)

0.25±0.20

(.010±.008)

(Stand off)

Note : Pins width and pins thickness include plating thickness.

2000 FUJITSU LIMITED F100007S-3c-5

14.00±0.10(.551±.004)SQ

16.00±0.20(.630±.008)SQ

125

76 50

100

0.50(.020) 0.20±0.05

(.008±.002) M

0.08(.003) 0.145±0.055

(.0057±.0022)

0.08(.003)

"A"

INDEX .059 –.004

+.008

–0.10

+0.20

1.50

(Mounting height)

0°~8°

0.50±0.20

(.020±.008)

0.60±0.15

(.024±.006)

0.25(.010)

0.10±0.10

(.004±.004)

Details of "A" part

(Stand off)

MB90435 Series

FUJITSU LIMITED

The contents of this document are subject to change without notice.

Customers are advised to consult with FUJITSU sales

representatives before ordering.

The information and circuit diagrams in this document are

presented as examples of semiconductor device applications, and

are not intended to be incorporated in devices for actual use. Also,

FUJITSU is unable to assume responsibility for infringement of

any patent rights or other rights of third parties arising from the use

of this information or circuit diagrams.

The products described in this document are designed, developed

and manufactured as contemplated for general use, including

without limitation, ordinary industrial use, general office use,

personal use, and household use, but are not designed, developed

and manufactured as contemplated (1) for use accompanying fatal

risks or dangers that, unless extremely high safety is secured, could

have a serious effect to the public, and could lead directly to death,

personal injury, severe physical damage or other loss (i.e., nuclear

reaction control in nuclear facility, aircraft flight control, air traffic

control, mass transport control, medical life support system, missile

launch control in weapon system), or (2) for use requiring

extremely high reliability (i.e., submersible repeater and artificial

satellite).

Please note that Fujitsu will not be liable against you and/or any

third party for any claims or damages arising in connection with

above-mentioned uses of the products.

Any semiconductor devices have an inherent chance of failure. You

must protect against injury, damage or loss from such failures by

incorporating safety design measures into your facility and

equipment such as redundancy, fire protection, and prevention of

over-current levels and other abnormal operating conditions.

If any products described in this document represent goods or

technologies subject to certain restrictions on export under the

Foreign Exchange and Foreign Trade Law of Japan, the prior

authorization by Japanese government will be required for export

of those products from Japan.

F0207

 FUJITSU LIMITED Printed in Japan