Intel
®
Wireless Flash Memory
(W18)
28F320W18, 28F640W18, 28F128W18
Datasheet
Product Features
The Intel® Wireless Flash Memory (W18) device with flexible multi-partition dual-operation
architecture, provides high-performance Asynchronous and Synchronous Burst reads. It is an
ideal memory for low-voltage burst CPUs. Combining high read performance with flash
memory intrinsic non-volatility, the W18 device eliminates the traditional system-performance
paradigm of shadowing redundant code memory from slow nonvolatile storage to faster
execution memory. It reduces total memory requirement that increases reliability and reduces
overall system power consumption and cost. The W18 device’s flexible multi-partition
architecture allows program or erase to occur in one partition while reading from another
partition. This allows for higher data write throughput compared to single-partition architectures
and designers can choose code and data partition sizes. The dual-operation architecture allows
two processors to interleave code operations while program and erase operations take place in
the background.
■High Performance Read-While-Write/
Erase
—Burst frequency at 66 MHz
(zero wait states)
—60 ns Initial access read speed
—11 ns Burst mode read speed
—20 ns Page mode read speed
—4-, 8-, 16-, and Continuous-Word Burst
mode reads
—Burst and Page mode reads in all
Blocks, across all partition boundaries
—Burst Suspend feature
—Enhanced Factory Programming at
3.1 µs/word
■Security
—128-bit OTP Protection Register:
64 unique pre-programmed bits +
64 user-programmable bits
—Absolute Write Protection with VPP at
ground
—Individual and Instantaneous Block
Locking/Unlocking with Lock-Down
Capability
■Quality and Reliability
—Temperature Range: –40 °C to +85 °C
—100K Erase Cycles per Block
—90 nm ETOX™ IX Process
—130 nm ETOX™ VIII Process
—180 nm ETOX™ VII Process
■Architecture
—Multiple 4-Mbit partitions
—Dual Operation: RWW or RWE
—Parameter block size = 4-Kword
—Main block size = 32-Kword
—Top or bottom parameter devices
—16-bit wide data bus
■Software
—5 µs (typ.) Program and Erase Suspend
latency time
—Flash Data Integrator (FDI) and
Common Flash Interface (CFI)
Compatible
—Programmable WAIT signal polarity
■Packag ing and Power
—90 nm: 32- and 64-Mbit in VF BGA
—130 nm: 32-, 64-, and 128-Mbit in VF
BGA; 128-Mbit in QUAD+ package
—180 nm: 32- and 128-Mbit densities in
VF BGA
—56 Active Ball Matrix, 0.75 mm Ball-
Pitch
—VCC = 1.70 V to 1.95 V
—VCCQ (90 nm) = 1.70 V to 1.95 V
—VCCQ (130 nm) = 1.70 V to 2.24 V or
1.35 V to 1.80 V
—VCCQ (180 nm) = 1.70 V to 2.24 V
—Standby current (130 nm): 8 µA (typ.)
—Read current: 8 mA (4-word burst, typ.)
290701-013
Augu st 2004
Notice: This document contains information on new products in production. The specifications
are subject to change without notice. Verify with your local Intel sales office that you have the
latest datasheet before finalizing a design.
2 Preliminary Datasheet
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY
ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN
INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS
ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND /OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES
RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER
INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or life sustaining applications.
Intel may make changes t o spec ifications and product descriptions at any time, without notice.
The Intel® WirelessFlash Memory may contain design defects or errors known as errata which may c ause the product to deviate from published
specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-
548-4725 or by visiting Intel's website at http://www .intel.com.
Copyright © 2004, Intel Corporation.
*Other names and brands may be claimed as the property of others.
Preliminary Datasheet 3
Contents
Contents
1.0 Introduction ...............................................................................................................................9
1.1 Nomenclature .......................................................................................................................9
1.2 Conventions..........................................................................................................................9
2.0 Functional Overview ............................................................................................................11
2.1 Memory Map and Partitioning.............................................................................................12
3.0 Package Information............................................................................................................15
3.1 W18 - 180 nm Lithography .................................................................................................15
3.2 W18 - 130 nm Lithography .................................................................................................18
4.0 Ballout and Signal Descriptions......................................................................................21
4.1 Signal Ballout......................................................................................................................21
4.2 Signal Descriptions.............................................................................................................23
5.0 Maximum Ratings and Operat ing Cond itions ...........................................................26
5.1 Absolute Maximum Ratings................................................................................................26
5.2 Operating Conditions..........................................................................................................27
6.0 Electrical Specifications.....................................................................................................28
6.1 DC Current Characteristics.................................................................................................28
6.2 DC Voltage Characteristics.................................................................................................30
7.0 AC Characteristics................................................................................................................31
7.1 Read Operations – 90 nm and 130 nm Lithography...........................................................31
7.2 Read Operations – 180 nm Lithography.............................................................................33
7.3 AC Write Characteristics..................... ........... .......................................... ........... ................43
7.4 Erase and Program Times..................................................................................................49
7.5 Reset Specifications...........................................................................................................50
7.6 AC I/O Test Conditions.......................................................................................................51
7.7 Device Capacitance............................................................................................................52
8.0 Power and Reset Specifications .....................................................................................52
8.1 Active Power.................................................. .......... ........................................... ................52
8.2 Automatic Power Savings (APS) ........................................................................................52
8.3 Standby Power ...................................................................................................................52
8.4 Power-Up/Down Characteristics.........................................................................................53
8.4.1 System Reset and RST# .......................................................................................53
8.4.2 VCC, VPP, and RST# Transitions .........................................................................53
8.5 Power Supply Decoupling...................................................................................................53
9.0 Bus Operations Overview..................................................................................................54
9.1 Bus Operations...................................................................................................................54
9.1.1 Reads ....................................................................................................................54
9.1.2 Writes.....................................................................................................................55
9.1.3 Output Disable.......................................................................................................55
9.1.4 Burst Suspend.......................................................................................................55
Contents
4Preliminary Datasheet
9.1.5 Standby..................................................................................................................56
9.1.6 Reset .....................................................................................................................56
9.2 Device Commands .............................................................................................................56
9.3 Command Sequencing.......................................................................................................60
10.0 Read Operations....................................................................................................................61
10.1 Asynchronous Page Read Mode........................................................................................61
10.2 Synchronous Burst Read Mode..........................................................................................61
10.3 Read Array............. ........... .......... ........... ........................................... ..................................62
10.4 Read Identifier....... ........................................... .......... ........................................... .............62
10.5 CFI Query...........................................................................................................................63
10.6 Read Status Register.................. ........... ........................................... ..................................63
10.7 Clear Status Re gister..........................................................................................................65
11.0 Program Operations.............................................................................................................65
11.1 Word Program ....................................................................................................................65
11.2 Factory Programming.........................................................................................................66
11.3 Enhanced Factory Program (EFP) .....................................................................................67
11.3.1 EFP Require ments and Considerations ................................................................67
11.3.2 Setup .....................................................................................................................68
11.3.3 Program.................................................................................................................68
11.3.4 Verify......................................................................................................................68
11.3.5 Exit.........................................................................................................................69
12.0 Program and Erase Operations.......................................................................................71
12.1 Program/Erase Suspend and Resume...............................................................................71
12.2 Block Erase.........................................................................................................................73
12.3 Read-While-Wr ite and Read-While-Erase..........................................................................75
13.0 Security Modes.......................................................................................................................76
13.1 Block Lock Operations........................................................................................................76
13.1.1 Lock.......................................................................................................................77
13.1.2 Unlock....................................................................................................................77
13.1.3 Lock-Down.............................................................................................................77
13.1.4 Block Lock Status..................................................................................................78
13.1.5 Lock During Erase Suspend..................................................................................78
13.1.6 Status Register Error Checking.............................................................................78
13.1.7 WP# Lock-Down Control .......................................................................................79
13.2 Protection Register..................... ........... ........... .......................................... ........................79
13.2.1 Reading the Protection Register............................................................................80
13.2.2 Programing the Protection Register.......................................................................80
13.2.3 Locking the Protection Register.............................................................................81
13.3 VPP Protection...................................................................................................................82
14.0 Set Read Configuration Register....................................................................................83
14.1 Read Mode (RCR[15])........................... ........................................... ..................................85
14.2 First Access Latency Count (RCR[13:11])..........................................................................85
14.2.1 Latency Count Settings..........................................................................................86
14.3 WAIT Signal Polarity (RCR[10])..........................................................................................87
14.4 WAIT Signal Function............................ ........................................... .......... ........................87
14.5 Data Hold (RCR[9]).............................................................................................................88
Preliminary Datasheet 5
Contents
14.6 WAIT Delay (RCR[8]) .........................................................................................................89
14.7 Burst Sequence (RCR[7])...................................................................................................89
14.8 Clock Edge (RCR[6])..........................................................................................................90
14.9 Burst Wrap (RCR[3])...........................................................................................................91
14.10 Burst Length (RCR[2:0]).....................................................................................................91
Appendix A Write State Machine St ates...............................................................................92
Appendix B Common Flash Interface (CFI).........................................................................95
Appe ndix C Ordering Information.........................................................................................106
Contents
6Preliminary Datasheet
Revision History
Date of
Revision Version Description
09/13/00 -00 1 Initial Release
01/29/01 -002
Dele ted 16- M b it den s ity
Revised ADV#, Se ct io n 2.2
Revised P rotection R eg ist ers , Section 4.16
Revised Program Protection Register, Section 4.18
Revised Example in Firs t Access Latency Count, Section 5.0.2
Rev ised Figure 5, Data Output with LC Setting at Code 3
Added W AIT Signal Function, Section 5.0.3
Revised WAIT Signal Polarity, Se ct io n 5.0. 4
Revised Data Output Configuration, Section 5.0.5
Added Figure 7, Data Output Configuration with WAIT Signal Delay
Revised WAIT Delay Configuration, Se ction 5.0. 6
Changed VCCQ S pec from 1.7 V – 1.95 V to 1.7 V – 2.24 V in Section 8.2,
Extended Temperature Operation
Changed ICCS Spec from 15 µA to 18 µA in Section 8.4, DC
Characteristics
Changed ICCR Spec from 10 mA (CLK = 40 MHz, burst length = 4) and 13
mA (C LK = 52 MH z, burst length = 4) to 13 mA, and 16 mA respectively in
Section 8.4, DC Characteristics
Changed ICCWS Spec from 15 µA to 18 µA in Section 8.4, DC
Characteristics
Changed ICCES Spec from 15 µA to 18 µA in Section 8.4, DC
Characteristics
Changed tCHQX Spec f rom 5 ns to 3 ns in Se c tion 8.6 , AC Read
Characteristics
Add ed Figu r e 25, W AIT Si gna l in Syn chr on ous Non- Read Arr ay Opera ti on
Waveform
Add ed Figure 26, WAIT Signal in Asy nchronous Page Mode Read
Operation Waveform
Add ed Figure 27, WAIT Signal in Asynchronous Single Word Read
Operation Waveform
Revised Appendix E, Ordering Information
06/12/01 -003
Revise d ent i re Se cti on 4.1 0, Enhanc ed F actor y Pro gram C ommand ( EFP )
and Figure 6, Enhanced Factory Program Flowchart
Revised Section 4.13, P rotection Register
Revised Section 4.15, Program Protection Register
Revised Section 7.3, Capacitance, to inc lude 128-Mbi t specs
Revised Section 7.4, DC Characterist ics, to include 128-Mbit specs
Revised Section 7.6, AC Read Characteri stics, to include 128-Mbi t device
specifications
Add ed tVHGL Spec in Section 7.6, AC Read Characteristics
Revised Section 7.7, AC Write Characteristics, to include 128-Mbit device
specifications
Minor text edits
Preliminary Datasheet 7
Contents
04/05/02 -004
New Sections Organization
Added 16-Word Burst Feature
Added Bur s t Suspend Section
Revised Block Locking State Diagram
Revised Active Power Section
Revised Automatic P ower Savings Section
Revised Powe r-Up /Down Operation Sec tion
Revised Extended Temperature Operation
Added 128 Mb DC Characteristics Table
Added 128 Mb AC Read Characteristics
Revised Table 17. Test Configuration Component Values for Worst Case
Speed Cond itions
Added 0.13 µm Product DC and A C Read Characteristics
Revised AC Wr ite Characteristics
Added Read to Writ e and Write to Read Transition Waveforms
Rev is e d R e se t Spec ifi c at io ns
Various text edits
10/10/02 -005
Various text edits
Updated Latency Count Section, inc luding adding Latency Count Tables
Added s ection 8.4 WAIT Fun c tion and WAIT Summary Table
Updated Package Drawing and Dimensions
11/12/02 -006 Various text clarifications
01/14/03 -007 Removed Intel Burst Order
Revised Table 10 “DC Current Characteristics”
Various text edits
03/21/03 -008 Re vised Table 22, Read Operations, tAPA
Add ed note t o tabl e 15, Conf ig urat io n R eg i ster Descript io ns
Added no te to section 3.1.1, Read
12/17/03 -009
Updated Block-Lock Operations (Sec tion 7.1 and Figure 11)
Updated Table 21 (128 Mb ICCR)
Updated Table 4 (WAIT behavior)
Added QUAD+ ballout, package mechanicals, and order information
Vari ous text edits inclu ding latest product-nami ng conventio n
02/12/04 -010
Added 90 nm product line
Removed µBGA* package
Added Page- and Burst-Mode descriptions
Mino r tex t edits
05/06/04 -011
Fixed omitted text for Table 21, note 1 regarding max DC voltage on I/O
pins
Removed Extended I/O Supply Voltage for 90 nm p roducts
Mino r tex t edits
06/03/04 -012 Updated the title and layou t of the dat asheet
06/29/04 -013
VCCQ Max. changed for 90 nm products
Updated “Absolute Maximum R atings” table
Typical ICCS upated as 35 µA
Updated subtitle
Date of
Revision Version Description
Contents
8Preliminary Datasheet
Intel® Wireless Flash Memory (W 18)
1.0 Introduction
Preliminary Datasheet 9
1.0 Introduction
This datasheet contains information about the Intel® W ireless Flash Memory (W18) device family.
This section describes nomenclature used in the datasheet. Section 2.0 provides an overview of the
W18 flash memory device. Section 6.0, Section 7.0, and S ection 8.0 describe the electrical
specifications for extended temperature product offerings. Ordering information can be found in
Appendix C.
1.1 Nomenclature
Acronyms that describe product features or usage are defined here:
1.2 Conventions
The following list describes abbreviated terms and phrases used throughout this document:
APS Automatic Power Savings
BBA Block Base Address
CFI Common Flash Interface
CUI Command User Interface
DU Don’t Use
EFP Enhanced Factory Programming
FDI Flash Data Integrator
NC No Connect
OTP One-Time Programmable
PBA Partition Base Address
RCR Read Conf iguration Register
RWE Read-While-Erase
RWW Read-While-Write
SCSP Stacked Chip Scale Package
SRD Status Register Data
VF BGA Very-thi, Fine-pitch, Ball Grid Array
WSM W rite State Machine
“1.8 V” Refers to the full VCC voltage range of 1.7 V – 1.95 V (except where noted) and “VPP = 12 V” refers to 12
V ±5%.
Set Refers to registers means the bit is a logical 1 and cleared means the bit is a logical 0.
Pin an d si gna l Often used in terchangeably to refer to the external signal connections on the package (ball is the term
us ed for VF BGA).
Intel® Wireless Flash Memory (W 18)
1.0 Introduction
10 Preliminary Datasheet
Throughout this document, references are made to top, bottom, parameter, and partition. To clarify
these references, the following conventions have been adopted:
Word 2 bytes or 16 bits.
Signal Names are in all CAPS (see Section 4.2, “Signal Descriptions” on page 2 2.)
Voltage Applied to the s ignal is subscr ipted for example VPP.
Block A group of bits ( or words) that erase simultaneously with one block erase instruction.
Main block Contains 32-Kwords.
Parameter block Contains 4-Kwords.
Block Base
Address (BBA) The first addre ss of a block.
Partition A group of blocks that share erase and program circuitry and a common Status Register.
Partition Base
Address (PBA) The first address of a partitio n. For examp le, on a 32-M bit top-parameter device partition number 5 has a
PBA of 0x140000.
Top partition Located at the highest physical device address. This partition may be a mai n partition or a parameter
partition.
Bottom partition Located at the lowest physical device address. This partition may be a main partition or a parameter
partition.
Main partition Contains only ma in blocks.
Parameter
partition Contains a mixture of m ain blocks and parame ter blocks.
To p parameter
device (TPD) Has the param e te r part ition at th e to p of the mem o ry ma p w it h th e para m e ter bloc ks at th e to p of that
partition. This was former ly referred to as a Top-Boot device.
Bottom parameter
device (BPD) Has the param e te r part iti on at the bottom of th e m em o ry ma p w it h th e para m et er block s at th e bo tt om of
that partition. This was formerly referred to as a Bottom-Boot Block flash device.
Intel® Wireless Flash Memory (W 18)
2.0 Functional Overview
Preliminary Datasheet 11
2.0 Functional Overview
This section provides an overview of the W18 device features and architecture.
The W18 device provides Read-While-Write (RWW) and Read-White-Erase (RWE) capability
with high-performance synchronous and asynchronous reads on package-compatible densities with
a 16-bit data bus. Individually-erasable memory blocks are optimally sized for code and data
storage. Eight 4-Kword parameter blocks are located in the parameter partition at either the top or
bottom of the memory map. The rest of the memory array is grouped into 32-Kword main blocks.
The memory architecture for the W18 device consists of multiple 4-Mbit partitions, the exact
number depending on device density. By dividing the memory array into partitions, program or
erase operations can take place simultaneously during read operations. Burst reads can traverse
partition boundaries, but user application code is responsible for ensuring that they don’t extend
into a partition that is actively programming or erasing. Although each partition has burst-read,
write, and erase capabilities, simultaneous operation is limited to write or erase in one partition
while other partitions are in a read mode.
Augmented erase-suspend functionality further enhances the RWW capabilities of this device. An
erase can be suspended to perform a program or read operation within any block, except that which
is erase-suspended. A program operation nested within a suspended erase can subsequently be
suspended to read yet another memory location.
After device power-up or reset, the W18 device defaults to asynchronous page-mode read
configuration. Writing to the device’s Read Configuration Register (RCR) enables synchronous
burst-mode read operation. In synchronous mode, the CLK input increments an internal burst
address generator . CLK also synchronizes the flash memory with the host CP U and outputs data on
every, or on every other, valid CLK cycle after an initial latency. A programmable WAIT output
signals to the CPU when data from the flash memory device is ready.
In addition to its improved architecture and interface, the W18 device incorporates Enhanced
Factory Programming (EFP), a feature that enables fast programming and low-power designs. The
EFP feature provides the fastest currently-available program performance, which can increase a
factory’s manufacturing throughput.
The device supports read operations at 1.8 V and erase and program operations at 1.8 V or 12 V.
With the 1.8 V option, VCC and VPP can be tied together for a simple, ultra-low-power design. In
addition to voltage flexibility, the dedicated VPP input provides complete data protection when
VPP ≤ VPPLK.
This device (130 nm) allows I/O operation at voltages lower than the minimum VCCQ of 1.7 V.
This Extended VCCQ range, 1.35 V – 1.8 V, permits even greater system design flexibility.
A 128-bit protection register enhances the user’s ability to implement new security techniques and
data protection schemes. Unique flash device identification and fraud-, cloning-, or content-
protection schemes are possible through a combination of factory-programmed and user-OTP data
cells. Zero-latency locking/unlocking on any memory block provides instant and complete
protection for critical system code and data. An additional block lock-down capability provides
hardware protection where software commands alone cannot change the block’s protection status.
Intel® Wireless Flash Memory (W 18)
2.0 Functional Overview
12 Preliminary Datasheet
The Command User Interface (CUI) is the system processor’s link to internal flash memory
operation. A valid command sequence written to the CUI initiates device Write State Machine
(WSM) operation that automatically executes the algorithms, timings, and verifications necessary
to manage flash memory program and erase. An internal Status Register provides ready/busy
indication results of the operation (success, fail, and so on).
Three power-saving features– Automatic Power Savings (APS), standby, and RST# – can
significantly reduce power consumption. The device automatically enters APS mode following
read cycle completion. Standby mode begins when the system deselects the flash memory by
de-asserting CE#. Driving RST# low produces power savings similar to standby mode. It also
resets the part to read-array mode (important for system-level reset), clears internal Status
Registers, and provides an additional level of flash write protection.
2.1 Memory Map and Partitioning
The W18 device is divided into 4-Mbit physical partitions, which allows simultaneous RWW or
RWE operations and allows users to segment code and data areas on 4-Mbit boundaries. The
device’s memory array is asymmetrically blocked, which enables system code and data integration
within a single flash device. Each block can be erased independently in block erase mode.
Simultaneous program and erase operations are not allowed; only one partition at a time can be
actively programming or erasing. See Table 1, “Bottom Parameter Memory Map” on page 13 and
Table 2, “Top Parameter Memory Map” on page 14.
The 32-Mbit device has eight partitions, the 64-Mbit device has 16 partitions, and the 128-Mbit
device has 32 partitions. Each device density contains one parameter partition and several main
partitions. The 4-Mbit parameter partition contains eight 4-Kword parameter blocks and seven 32-
Kword main blocks. Each 4-Mbit main partition contains eight 32-Kword blocks each.
The bulk of the array is divided into main blocks that can store code or data, and parameter blocks
that allow storage of frequently updated small parameters that are normally stored in EEPROM. By
using software techniques, the word-rewrite functionality of EEPROMs can be emulated.
..
Intel® Wireless Flash Memory (W 18)
2.0 Functional Overview
Preliminary Datasheet 13
Table 1. Bottom Parameter Memory Map
Size
(KW) Blk # 32-Mbit Blk # 64-Mbit Blk # 128-Mbit
Main Partitions
Sixteen
Partitions
32 262 7F8000-7FFFFF
..
.
..
.
..
.
32 135 400000-407FFF
Eight
Partitions
32 134 3F8000-3FFFFF 134 3F8000-3FFFFF
..
.
..
.
..
.
..
.
..
.
32 71 200000-207FFF 71 200000-207FFF
Four
Partitions
32 70 1F8000-1FFFFF 70 1F8000-1FFFFF 70 1F8000-1FFFFF
..
.
..
.
..
.
..
.
..
.
..
.
..
.
32 39 100000-107FFF 39 100000-107FFF 39 100000-107FFF
One
Partition
32 38 0F8000-0FFFFF 38 0F8000-0FFFFF 38 0F8000-0FFFFF
..
.
..
.
..
.
..
.
..
.
..
.
..
.
32 31 0C0000-0C7FFF 31 0C0000-0C7FFF 31 0C0000-0C7FFF
One
Partition
32 30 0B8000-0BFFFF 30 0B8000-0BFFFF 30 0B8000-0BFFFF
..
.
..
.
..
.
..
.
..
.
..
.
..
.
32 23 080000-087FFF 23 080000-087FFF 23 080000-087FFF
One
Partition
32 22 078000-07FFFF 22 078000-07FFFF 22 078000-07FFFF
..
.
..
.
..
.
..
.
..
.
..
.
..
.
32 15 040000-047FFF 15 040000-047FFF 15 040000-047FFF
Parameter Partition
On e Partition
32 14 038000-03FFFF 14 038000-03FFFF 14 038000-03FFFF
..
.
..
.
..
.
..
.
..
.
..
.
..
.
32 8 008000-00FFFF 8 008000-00FFFF 8 008000-00FFFF
4 7 007000-007FFF 7 007000-007FFF 7 007000-007FFF
..
.
..
.
..
.
..
.
..
.
..
.
..
.
4 0 000000-000FFF 0 000000-000FFF 0 000000-000FFF
Intel® Wireless Flash Memory (W 18)
2.0 Functional Overview
14 Preliminary Datasheet
Table 2. Top Parameter Memory Map
Size
(KW) B l k # 32- M bit Blk # 64-Mbit Blk # 1 28 - M bi t
Parameter Partition
One Par tition
4 70 1FF000-1FFFFF 134 3FF000-3FFFFF 262 7FF000-7FFFFF
..
.
..
.
..
.
..
.
..
.
..
.
..
.
4 63 1F8000-1F8FFF 127 3F8000-3F8FFF 255 7F8000-7F8FFF
32 62 1F0000-1F7FFF 126 3F0000-3F7FFF 254 7F0000-7F7FFF
..
.
..
.
..
.
..
.
..
.
..
.
..
.
32 56 1C0000-1C7FFF 120 3C0000-3C7FFF 248 7C0000-7C7FFF
Main Pa rtitions
One
Partition
32 55 1B8000-1BFFFF 119 3B8000-3BFFFF 247 7B8000-7BFFFF
..
.
..
.
..
.
..
.
..
.
..
.
..
.
32 48 18000-187FFF 112 380000-387FFF 240 780000-787FFF
One
Partition
32 47 178000-17FFFF 111 378000-37FFFF 239 778000-77FFFF
..
.
..
.
..
.
..
.
..
.
..
.
..
.
32 40 140000-147FFF 104 340000-347FFF 232 740000-747FFF
One
Partition
32 39 138000-13FFFF 103 338000-33FFFF 231 738000-73FFFF
..
.
..
.
..
.
..
.
..
.
..
.
..
.
32 32 100000-107FFF 96 300000-307FFF 224 700000-707FFF
Four
Partitions
32 31 0F8000-0FFFFF 95 2F8000-2FFFFF 223 6F8000-6FFFFF
..
.
..
.
..
.
..
.
..
.
..
.
..
.
32 0 000000-007FFF 64 200000-207FFF 192 600000-607FFF
Eight
Partitions
32 63 1F8000-1FFFFF 191 5F8000-5FFFFF
..
.
..
.
..
.
..
.
..
.
32 0 000000-007FFF 128 400000-407FFF
Sixteen
Partitions
32 127 3F8000-3FFFFF
..
.
..
.
..
.
32 0 000000-007FFF
Intel® Wireless Flash Memory (W 18)
3.0 Package Information
Preliminary Datasheet 15
3.0 Pac kage Informatio n
3.1 W18 - 90 nm Lithography
Figure 1. 32- and 64-Mbit VF BGA Package Drawing
Table 3. 32- and 64-Mbit VF BGA Packag e Dimensions
Dimension Symbol Millimeters Inches
Min Nom Max Min Nom Max
Packa ge Height A - - 1.000 - - 0.0394
Ball Height A10.150 - - 0.0059 - -
Package Body Thickness A2- 0.665 - - 0.0262 -
Ball (Lead) Wid th b 0.325 0.375 0.425 0 .0128 0.0148 0 .0167
Packa ge Body Widt h D 7.600 7.700 7.800 0.2992 0.3031 0.3071
Packa ge Body Length E 8.900 9.000 9.100 0.3504 0.3543 0.3583
Pitch [e] - 0.750 - - 0.0295 -
Ball (Lead) Count N - 56 - - 56 -
Seating Plane Coplanarity Y - - 0.100 - - 0.0039
Corner to Ball A1 Distance Along D S11.125 1.225 1.325 0.0443 0.0482 0.0522
Corner to Ball A1 Distance Along E S22.150 2.250 2.350 0.0846 0.0886 0.0925
E
Seating
Plane
Top View - B um p Side Down Bottom View - Ball Side Up
Y
A
A1
D
A2
2
Ball A1
Corne
r
87654321
A
B
C
D
E
F
G
S
1
S
e
b
Ball A1
Corner
87654321
A
B
C
D
E
F
G
Intel® Wireless Flash Memory (W 18)
3.0 Package Information
16 Preliminary Datasheet
3.2 W18 - 130 nm Lithography
Figure 2. 32-, 64-, and 128-Mbit VF BGA Package Drawing
Table 4. 32-, 64-, and 128-Mbit VF BGA Package Dimensions
Dimension Symbol Millimeters Inches
Min Nom Max Min Nom Max
Package Height A - - 1.000 - - 0.0394
Ball H e ig ht A10.150 - - 0.0059 - -
Package Body Thickness A2- 0.665 - - 0.0262 -
Ball (Lead) Width b 0.325 0.375 0.425 0.0128 0.0148 0.0167
Package Body Width (32/64-Mbit) D 7.6 00 7.700 7.800 0.2992 0.3031 0.3071
Package Body Width (128-Mbit) D 10.900 11.000 11.100 0.4291 0.4331 0.4370
Package Body Length (32/64/128-Mbit) E 8.900 9.000 9.100 0.3504 0.3543 0.3583
Pitch [e] - 0.750 - - 0.0295 -
Ball (Lead) Count N - 56 - - 56 -
Seating Plane Coplanarity Y - - 0.100 - - 0.0039
Corner to Ball A 1 Distanc e Along D (32/6 4-Mbit) S11.125 1.225 1.325 0.0443 0.0482 0.0522
Corner to Ball A 1 Distanc e Along D (128-M bit) S12.775 2.2875 2.975 0.1093 0.1132 0.1171
Corner to Ball A 1 Distanc e Along E (32/64/128-Mbit) S22.150 2.250 2.350 0.0846 0.0886 0.0925
E
Seating
Plane
Top View - Bump Sid e Dow n Bottom View - Ball Side Up
Y
A
A1
D
A2
2
Ball A1
Corne
r
87654321
A
B
C
D
E
F
G
S
1
S
e
b
Ball A1
Corner
87654321
A
B
C
D
E
F
G
Intel® Wireless Flash Memory (W 18)
3.0 Package Information
Preliminary Datasheet 17
Figure 3. 128-Mbit QUAD+ Package Drawing
Millimeters Inches
Dimensions Symbol Min Nom Max Notes Min Nom Max
Package Height A 1.200 0.0472
Ball Height A1 0.200 0.0079
P a ckage Body Thickness A2 0.860 0.03 39
Ball (Lead) Width b 0.325 0.375 0.425 0.0128 0.0148 0.0167
P a c kage Body Length D 9 .9 00 1 0. 00 0 10. 100 0. 3898 0.3937 0.3976
P a ckage Body Wi dth E 7.900 8 .00 0 8 . 100 0.3110 0.3150 0.3189
Pi tch e 0.8 0 0 0 .0 3 1 5
Ball (Le ad) Count N 88 88
Seating Plane Coplanarity Y 0.100 0.0039
Cor ner to Ball A1 Distance Along E S 1 1 . 100 1 .20 0 1 . 300 0. 0433 0.0472 0.0512
Cor ner to Ball A1 Distance Along D S 2 0 . 500 0 .60 0 0 . 700 0. 0197 0.0236 0.0276
Top View - Ball Down Bottom View - Ball Up
A
A2
D
E
Y
A1
Drawing not to sc al e.
S2
S1
A
C
B
E
D
G
F
J
H
K
L
M
e
1
2345678
b
A
C
B
E
D
G
F
J
H
K
L
M
A1 Index
Mark
12345678
Intel® Wireless Flash Memory (W 18)
3.0 Package Information
18 Preliminary Datasheet
3.3 W18 - 180 nm Lithography
Figure 4. 32-Mbit VF BGA Package Drawing
Figure 5. 128-Mbit VF BGA Package Drawing
E
Seating
Plane
T op View - Bum p Side D own Bottom View - Ball Side U p
Y
A
A1
D
A2
2
Ball A1
Corne
r
S
1
S
e
b
Ball A1
Corner
A
B
C
D
E
F
G
87654321 87654321
A
B
C
D
E
F
G
Note: Drawin
g
not to scale
Side View
Seating
Plane
Y
A
A1
A2
Note: Drawin
g
not to scale
Side View
E
Top View - Bu mp Side
Down Bottom View - Ball Side
Up
DBal l A1
Corner
S1
S2
e
b
765432110 9 8
A
B
C
D
E
F
G
H
J
76543211098
A
B
C
D
E
F
G
H
J
Ba ll A 1
Corner
Intel® Wireless Flash Memory (W 18)
3.0 Package Information
Preliminary Datasheet 19
Table 5. 32- and 128-Mbit VF BGA Package Dimensions
Dimension Symbol Millimeters Inches
Min Nom Max Min Nom Max
Packa ge Height A 0.850 - 1.000 0.0335 - 0.0394
Ball Height A10.150 - - 0.0059 - -
Package Body Thickness A20.615 0.665 0.715 0.0242 0.0262 0.0281
Ball (Lead) Width b 0.325 0.375 0.425 0.0128 0.0148 0.0167
Packa ge Body Width (32-Mbit) D 7.6 00 7.700 7.800 0.2992 0.3031 0.3071
Package Body Length (32-Mbit) E 8.900 9.000 9.100 0.3503 0.3543 0.3583
Packa ge Body Width (128-Mbit) D 12.400 12.500 12.600 0.4882 0.4921 0.4961
Package Body Length (128-Mbit) E 11.900 12.000 12.100 0.4685 0.4724 0.4764
Pitch [e] - 0.750 - - 0.0295 -
Ball (Lead) Count 32-Mbit N - 56 - - 56 -
Ball (Lead) Count 128-Mbit N - 60 - - 60 -
Seating Plane Coplanarity Y - - 0.100 - - 0.0039
Corner to Ball A1 Distance Along D (32-Mbit) S11.125 1.225 1.325 0.0443 0.0482 0.0522
Corner to Ball A1 Distance Along E (32-Mbit) S22.150 2.250 2.350 0.0846 0.0886 0.0925
Corner to Ball A1 Distance Along D (128-Mbit) S12.775 2.875 2.975 0.1093 0.1132 0.1171
Corner to Ba ll A1 Distance Along E (128-Mbit) S22.900 3.000 3.1000 0.1142 0.1181 0.1220
Intel® Wireless Flash Memory (W 18)
4.0 Ballout and Signal Descriptions
20 Preliminary Datasheet
4.0 Ballout and Signal Descriptions
4.1 Signal Ballout
The W18 device is available in a 56-ball VF BGA and µBGA Chip Scale Package with 0.75 mm
ball pitch, or the 88-ball (80 active balls) QUAD+ SCSP package. Figure 6 shows the device
ballout for the VF BGA package. Figure 7 shows the device ballout for the QUAD+ package.
Figure 6. 56-Ball VF BGA Ballout
Notes:
1. On low er density de vices, upper address balls can be treated as NC. (Example: Fo r 32-Mbit densit y, A21 and A22 are
NC).
2. See Appendix , “” on page 15 for mechanical specifications for the package.
A
B
C
D
E
F
G
A
B
C
D
E
F
G
Top View - Ball Side Down
Comp let e Ink Ma r k Not Sh o wn
8 7 6 5 4 3 2 11 2 3 4 5 6 7 8
Bottom View - Ball Side Up
A4 A6 A18 VPP VCC VSS A8 A11
A3 A5 A17 RST# CLK A20 A9 A12
A2 A7 WE# ADV#
A19 A10 A13
A1 A14WP# DQ12 A16 WAIT A15
A0 CE# DQ1 DQ2 DQ4 DQ6 DQ15 VCCQ
OE# DQ0 DQ9 DQ10 DQ11 DQ13 DQ14 VSS
VSSQ DQ8 VCCQ DQ3 VCC DQ5 VSSQ DQ7
A22
A21
A4
A6A18
VPP
VCC
VSSA8A11
A3A5A17
RST#
CLKA20A9A12
A2A7
WE#ADV# A19A10A13
A1A14 WP#DQ12A16WAITA15
A0CE#DQ1DQ2DQ4DQ6DQ15VCCQ
OE#DQ0DQ9DQ10DQ11DQ13DQ14VSS
VSSQDQ8VCCQDQ3VCCDQ5VSSQDQ7
A22
A21
Intel® Wireless Flash Memory (W 18)
4.0 Ballout and Signal Descriptions
Preliminary Datasheet 21
Figure 7. 88-Ball (80 Active Balls) QUAD+ Ballout
Notes:
1. Unused upper address balls can be tr eated as NC (for 128-Mbit device, A[ 25:23] are not used).
2. See “Package Information” on page 15 for the mechanical specifications for the package.
Flash specific
SRAM/PSRAM specifi c
Global
Legend:
Top View - Ball Side Down
87654321
A
B
C
D
E
F
G
H
J
K
L
M
DU
A4
DU DU DU
DUDUDU DU
A5
A3
A2 A7
A1 A6
A0
A18 A19 VSS
VSSA23
A24
A25
A17
F2-VCC
CLK
A21
A22 A12
A11
A13A9P1-CS#
F-VPP,
F-VPEN
A20 A10 A15
F-WE# A8
D8 D2 D10 D5 D13 WAIT
A14 A16
F1-CE# P-Mode,
P-CRE
VSS VSS VSS
P2-CS#
F1-VCC
F2-VCC VCCQF3-CE#
D0 D1
D9
D3
D4 D6
D7
D15D11
D12 D14
F1-OE#
F2-OE#
P-VCC
S-CS2
R-WE#
R-UB#
R-LB#
R-OE#
S-VCC
S-CS1#
F1-VCC
F-WP# ADV#
F-RST#
F2-CE#
VCCQ
VSS VSSVCCQ VSS
Intel® Wireless Flash Memory (W 18)
4.0 Ballout and Signal Descriptions
22 Preliminary Datasheet
4.2 Signal Descriptions
Table 6 describes the signals used on the VF BGA package. Table 7 on page 23 describes the
signals used on the QUAD+ package.
Table 6. Signal Descriptions - VF BGA Package
Symbol Typ e Nam e an d Fu nc tio n
A[22:0] Input ADDRESS INPUTS: For memory addresses. 32-Mbit : A[20:0]; 64-Mbit: A[21:0]; 128-Mbi t: A[22:0]
D[15:0] Input/
Output
DATA INP UTS/OUT PU T S: Inputs data and commands during write cycles; outputs data during
memor y, Status Register, protection register, and con figuration code re ads. Data pins float when the
chip or outputs ar e deselected. Data is internal ly latched duri ng writes.
ADV# Input ADDRESS VALID: ADV# indicates valid address presence on addres s inputs. During synchronous
read operation s, all addresses are latched on ADV#’ s rising edge or the next valid C LK edge with
ADV# low, whichever occurs first.
CE# Input CHIP ENABLE: Ass ertin g CE# activa tes inter nal con trol log ic, I/ O buf fers, dec oder s, and sense am ps.
De-asserting CE# deselect s the device, pla c es it in standby mode, and places all outputs in High-Z.
CLK Input CLOCK: CLK synchronizes the device to the s ystem bus frequency during synchronous reads and
increme nts an int ernal add ress gene rato r . Dur ing syn chronou s read op erati ons, ad dresses ar e latc hed
on ADV#’s rising edge or the next vali d CLK edge wi th ADV# low, which ever occurs f irst.
OE# Input OUTPUT ENABLE: When assert ed, OE# enable s the device ’s ou tput data buf fe rs durin g a read cy cle.
When OE# is deasserted, data outputs are placed in a high-impedance st ate.
RST# Input RESET: When low, RST# resets internal automation and inhibits write opera tions. This provides data
pro tection dur ing power tr ansitions. de-assert ing RST# enables normal operation and places the
device in asynchro no us read -a rray mod e .
WAIT Output WAIT: The WAIT signal indicates valid data during synchronous read modes. It can be configured to
be asserted-high or asserted-l ow base d on bit 10 of the Read Configuration Register. WAIT is tri-
stated if CE# is deasserted. WAIT is not gated by OE#.
WE# Input WRITE ENABLE: WE# controls wri tes to the CUI and array. Addr esses and data are latc hed on the
rising edge of WE#.
WP# Input WRITE PROTECT: Disables/enables the lock-down function. When WP# is asserted, the l ock-down
mechanism is enabled and blocks marked lock- down cannot be unlocked through software. See
Section 13.1, “Block Lock Operations” on page 82 for de tails on block locking.
VPP Power
ERASE AND PROGRAM POWER: A valid voltage on this pin allows erasing or programming.
Memory contents cannot be alte red when VPP ≤ VPPLK. Block erase and program at invalid VPP
voltages should not be attempted.
Set VPP = VCC for in-system program and erase operations. To accommodate resistor or diode drops
from the system supply, the VIH level of VPP can be as low as VPP1 min. VPP must remain above VPP1
min to perform in-system flash modification. VPP may be 0 V during read operations.
VPP2 can be app lied t o main bl ocks f or 100 0 cycl es ma ximu m a nd t o p arame ter b locks f or 2 500 c ycles.
VPP can be connected to 12 V for a cumulative to tal not to exceed 80 ho urs. Extended use of thi s pin
at 12 V may reduce block cycling capability.
VCC Power DEVICE POWER SUPPLY: Writes are inhibited at VCC ≤ VLKO. Device operations at invalid VCC
voltages should not be attempted.
VCCQ Power OUTPUT POWER SUPPLY: Enables all outputs to be driven at VCCQ. This input may be tied directly
to VCC.
VSS Power GROUND: Pins for all internal device circuitry must be connected to system ground.
VSSQ Power OUTPUT GROUND: Provide s ground t o all o utput s whic h are dri ven by VCCQ. This si gnal ma y be tied
direc tly to VSS.
DU — DO NOT USE: Do not use thi s pi n. Thi s pi n sho uld not be con nec te d to any po wer supp lies, si gna ls or
other pins and must be floated.
NC — NO CONNECT: No internal conn ection; can be driven or floated.
Intel® Wireless Flash Memory (W 18)
4.0 Ballout and Signal Descriptions
Preliminary Datasheet 23
Table 7. Signal Descriptions - QUAD+ Package (Sheet 1 of 3)
Symbol Type Description
A[MAX:MIN] Input
ADDRESS INP UTS: Inputs for all die addresses during read and write operations.
•256-Mbit Die : AMAX= A23
•128-Mbit Die : AMAX = A22
•64-Mbit Die : AMAX = A21
•32-Mbit Die : AMAX = A20
•8-Mbit Die : AMAX = A18
A0 i s the lowest-order 16-bit wide address.
A[25:24] denote high-order addresses reserved for future device densiti es.
D[15:0] Input/
Output
DATA INPUTS/OUTPUTS: Inputs data an d commands duri ng write cycles, outputs data during read
cycles. Data signals float when the device or its outputs are deselected. Data are int ernally la tched
during writes on the flash device.
F[3:1]-CE# Input
FLASH CHIP ENABL E: Low-true input.
F[3:1]-CE# low sele cts the associated flash memory die . When asserted, flash int ernal control logic,
input buffers, decoders, and sense amplifiers ar e active. When deas serted, the associat ed flash die is
deselected, pow er is reduc ed to standb y levels, data and WAIT outputs are placed in high-Z state.
F1-CE# select s or deselects flash die #1; F2-CE# selects or de selects flash die #2 and is RFU on
combinations with only one flash die . F3-CE# selects or des elects flash die #3 a nd is RFU on stacked
combinations with only one or two f lash dies.
S-CS1#
S-CS2 Input
SRAM CHIP SELECT: Low-true / High-true input (S-CS1# / S-CS2 respectively).
When either/both SRAM Chip Select signals are asserted, SRAM internal control logic, input buffers,
decoders, and sense amplifiers are active. When eit her/both SRAM C hip Select signals are
deasserted, the SRAM is deselected and its power is reduced to s tandby levels.
S-C S1# and S-CS2 are available on stacked combi nations with SRAM die and are RFU on stacked
combination s without SRAM die.
P[2:1]-CS# Input
PSRAM CHIP SELECT: Low-true input.
When asserte d, PSRAM int erna l contro l logic, input buff ers, de coder s, and sense ampli fiers ar e active .
When deasserted, the PSRAM is deselected and its power is reduced to standby levels.
P1-CS# selects PSRAM die #1 and is available only on stacked combinations with PSRAM die. This
ball is an RFU on stacked combinations without PSRAM. P2-CS# selects PSRAM die #2 and is
available onl y on stacked combinations with two PSRAM dies. This ball is an RFU on stacked
com b in ations w ith o ut PSR AM or with a si ng l e P SRAM .
F[2:1]-OE# Input
FLASH OUTPUT ENA BLE: Low-true input.
Fx-OE# low enables the selected flash’s outpu t buffers. F[2:1]-OE# high disables the selected flash’s
out put buffers, placing them in High- Z.
F1-OE# contro ls the outputs of flash die #1; F2-OE# controls the outputs of flash die #2 and flash die
#3. F2-OE# is available on stacked combinations with two or three flash die and is RFU on stacked
combinations with only one flash die.
R-OE# Input
RAM OUTPUT ENABLE: Low-tru e in pu t.
R-OE# low enables the sele cted RAM’s output buffers. R- OE# high disables the RAM output buffers,
and places the selected RAM outputs in High-Z.
R-OE# is availa ble on stacked combinations with PSRAM or SRAM die, and is an RFU on flash-only
stacked combinations.
F-WE# Input FLASH WRITE ENABLE: Low-true input.
F-WE# controls w rites to the selected flash die. Address and data are latched on the rising edge of F-
WE#.
R-WE# Input
RAM WRITE ENABLE: Low-true input.
R-WE# controls writes to the selected RAM die.
R-WE# is available on stacked combinations with PSRAM or SR AM die and i s an RFU on flash-only
stacked combinations.
Intel® Wireless Flash Memory (W 18)
4.0 Ballout and Signal Descriptions
24 Preliminary Datasheet
CLK Input
CLOCK: Synchronizes the flash die with the system bus clock in synchronous read mode and
increments th e internal address generator.
Duri ng synchro nous re ad operat ions, address es are l atched on t he ris ing edge of ADV#, or on the nex t
valid CLK edge with ADV# low, whichever occurs first.
In asynchronous mode, addresses are latched on the rising edge ADV#, or are continuously flow-
through when ADV# is kept asserted.
WAIT Output
WAIT: Output signal.
Indi cates invalid data during synchron ous array or non-ar ray flas h reads. Read Confi guration Register
bit 10 (RCR[10]) determines WAIT-asserted polarity (high or low). WAIT is High-Z if F-CE# is
deasserted; WAIT is not gated by F-OE#.
• In synchronous array or non-array flash read modes, WAIT indicates invalid data when asse rted
and valid data when deasserted.
• In asynchronous flash p age read, and all flash write modes, WAIT is asserted.
F-WP# Input
FLASH WRITE PROTECT: Low-true input.
F-WP# enables/disables the lock-down protection mechanism of the selected fl ash die.
• F -WP# low enable s the lock- down mec hanism where lo cked down blocks c annot be un locked with
sof tware commands.
• F-WP# high disables t he lock-do wn mechanism, allowing locked down blocks to be unlocked with
sof tware commands.
ADV# Input
ADDRESS VALID: Low- t r ue inp u t.
During synchronous fl ash read operations, addresses are latched on the rising edge of ADV#, or on
the next valid CLK edge wi th ADV# low, whichever occurs first.
In asynchronous flash read operations, addresses are latched on the rising edg e of ADV#, or are
continuously flow-through when ADV# is kept asserted.
R-UB#
R-LB# Input
RAM UPPER / LOWER BYTE ENABLES: Low-true in put.
During RAM read and write cycles, R-UB# low enables the RAM high order bytes on D[15:8], and R-
LB# l ow enables the RAM low -order bytes on D[7: 0].
R-UB# and R-LB # are available on stacked combinations with PSRAM or SRAM die and are RFU on
fla sh-only stacked combinations.
F-RST# Input FLASH RESET: Lo w-true in pu t.
F-RST# low in itializes flash internal circuitry and disables fla s h operati ons. F-RS T# high enables flash
oper ation. Exit from reset plac es the flash in asynchronous rea d array mode.
P-Mode,
P-CRE Input
P-Mode (PSRAM Mode): Low-true input.
P-Mode is us ed t o prog r am the C on figur a tion Re gis ter, and enter /ex it Low P ower Mode of PS RAM di e.
P-Mode is available on stacked combinations with asynchronous-only PSRAM die.
P-CRE (PSRAM Configuration Register Enable): High-true input.
P-CRE is high, write operations load the refresh control regi ster or bus contr ol register.
P-CRE is applicable only on combinations with synchronous PSRAM die.
P-Mode, P-CRE is an R FU on stacked combinations without PSRAM die.
F-VPP,
F-VPEN Power
FLASH PROGRAM AND ERASE POWER: Valid F-VPP voltage on this bal l enables flash program/
eras e operations.
Flash memory array contents cannot be altered when F-VPP(F-VPEN) < VPPLK (VPENLK). Erase /
progr am operat ions at invali d F-VPP (F-VPEN) voltages s hould no t be att emp te d. Ref er to f las h di scr ete
pro duct datash eet for additional details.
F-VP EN (Erase/Program/Block Lock Enables) is not available for L18/L30 SCSP products.
F[2:1]-VCC Power
FLASH LOGIC POWER: F1-V CC supplies power to the core logic of flash die #1; F2-VCC su pplies
power to the core logic of flash die #2 and flash die #3. Write operations are inhibited when F-VCC <
VLKO. Device operations at invalid F-VCC voltages should not be attempted.
F2-VCC is available on stacked combinations with two or three flash dies, and is an RFU on stacked
combinations with only one flash die.
Table 7. Signal Descriptions - QUAD+ Package (Sheet 2 of 3)
Intel® Wireless Flash Memory (W 18)
4.0 Ballout and Signal Descriptions
Preliminary Datasheet 25
S-VCC Power SRAM POWER SUPPLY: Supplies power for SRAM operations.
S-VCC is av ailable on stacked combinations wit h SRAM die, and is RFU on stacked combinat ions
without SRAM die.
P-VCC Power PSRAM POWER SUPPLY: Supplies power for PSRAM operations.
P-VCC is av ailable on stacked combinations with PSRAM die, and is RFU on stacked combinations
without PS RAM die.
VCCQ Power DEV ICE I/O POWER: Supply p ower for the device input and output buffers.
VSS Power DEVICE GROUND: Connect to system ground. Do not float any VSS connection.
RFU — RESERVED for FUTURE USE: Reserv ed fo r fut ure devi ce func ti onali t y/ enhanceme nt s . Contact Intel
re garding the use of balls designated RFU.
DU — DO NOT USE: Do not connect to any other signal, or power supply; must be left floating.
Table 7. Signal Descriptions - QUAD+ Package (Sheet 3 of 3)
Intel® Wireless Flash Memory (W 18)
5.0 Maximum Ratings and Operating Conditions
26 Preliminary Datasheet
5.0 Maximum Ratings and Operating Conditions
5.1 Absolute Maximum Ratings
Warning: Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage.
These are stress ratings only.
Notice: This datas heet contains information on products in the design phase of development. The information
here is subject to change without notice. Do not finaliz e a design with this information.
Table 8. Absolute Maximum Ratings
Parameter Maximum Rating Notes
Temperatur e under Bias –40 °C to +85 °C
S torage Temperature –65 °C to +125 °C
Voltage on Any Pin (except VCC, VCCQ, VPP) –0.5 V to +2.45 V 1,2
VPP V oltage –0.2 V to +13.1 V 1,3,4
VCC and VCCQ Voltage –0.2 V to +2.45 V 1, 2
Output Short Circuit Current 100 mA 5
Notes:
1. All specified voltages are relative to VSS.
2. During transitions, this level may undershoot to –2.0 V for pe riods < 20 ns and overshoot to
VCCQ +2.0 V for periods < 20 ns.
3. Maximum DC voltage on VPP may overshoot to +14. 6 V for periods < 20 ns.
4. VPP program voltage is normally VPP1. VPP can be 12 V ± 0.6 V f or 1000 cycl es on the main
blocks and 2500 cycles on the parameter bloc ks during progr am/erase.
5. Output shorted for no more tha n one second. No more than one outp ut shor ted at a time.
Intel® Wireless Flash Memory (W 18)
5.0 Maximum Ratings and Operating Conditions
Preliminary Datasheet 27
5.2 Operating Conditions
Warning: Operation beyond the “Operating Conditions” is not recommended, and extended exposure beyond
the “Operating Conditions” may affect device reliability.
Table 9. Extended Temperature Operation
Symbol Parameter1Min Nom Max Unit Note
TAOperating Temperature –40 25 85 °C
VCC Supp l y Voltag e 1.7 1.8 1 .9 5
V
3
I/O Supply Voltage (90 nm) 1.7 1.8 1.95 3
I/ O Supply Vo ltage (130 nm and 180 nm) 1.7 1.8 2.24 3
Extended I/O Supply Voltage (130 nm) 1.35 1.5 1.8 4
VPP1 VPP Voltage Supply (Logic Level) 0.90 1.80 1.95 2
Programming VPP 11.4 12.0 12.6 2
tPPH Maximum VPP Hours VPP = 12 V - - 80 Hours 2
Block
Erase
Cycles
Mai n an d P a r a m eter Blo c ks VPP ≤ VCC 100,000 - -
Cycles
2
Main Blocks VPP = 12 V - - 1000 2
Parameter Blocks VPP = 12 V - - 2500 2
Notes:
1. See Sec t io n 6.1 and Secti on 6.2, “DC Voltage Characterist ics” on page 30 for specific voltage-range specificat ions.
2. VPP is normally VPP1. VPP can be connected to 11.4 V–12.6 V for 1000 cycl es on main blocks at extended
temper atures and 2500 cycles on parameter block s at extended temperatures.
3. Con tact yo u r Inte l fiel d re pre s en tat iv e fo r VCC/VCCQ opera tions down t o 1.65 V.
4. See the t ables in Section 5.0, “Maximum Ratings and Operating Conditions” on page 26 and in Section 7.0, “AC
Chara c ter istics” on page 31 for operating characteristics within the Extended VCCQ voltage range.
Intel® Wireless Flash Memory (W 18)
6.0 Electrical Specifications
28 Preliminary Datasheet
6.0 El ectrical Specifications
6.1 DC Current Characteristics
Table 10. DC Current Characteristics (Sheet 1 of 2)
Symbol Parameter (1)
VCCQ= 1.35 V
– 1.8 V (2) VCCQ= 1. 8 V
Unit Tes t C on dit ion Note32/64/128-
Mbit 32/64-Mbit 128-Mbit
Typ Max Typ Max Typ Max
ILI Input Load - TBD - ±1 - ±1 µA VCC = VCCMax
VCCQ = VCCQMax
VIN = VCCQ or GND 8
ILO Output
Leakage D[15:0] - TBD - ±1 - ±1 µA VCC = V CCMax
VCCQ = VCCQMax
VIN = VCCQ or GND
180 nm
ICCS
VCC Standby
TBD TBD 5 18 5 25
µA
VCC = VCCMax
VCCQ = VCCQMax
CE# = VCC
RST# =VSSQ
9
130 nm
ICCS TBD TBD 8 50 8 70
90 nm
ICCS - - 35 50 - -
180 nm
ICCAPS
APS
TBD TBD 5 18 5 25
µA
VCC = VCCMax
VCCQ = VCCQMax
CE# = VSSQ
RST# =VCCQ
All ot he r in puts =VCCQ or
VSSQ
10
130 nm
ICCAPS TBD TBD 8 50 8 70
90 nm
ICCAPS - - 35 50 - -
ICCR Average
VCC
Read
Asynchronous
Page Mode
f=13 M Hz TBDTBD3647mA4 Word Read 3
Synchronous
CLK = 40 MHz
TBD TBD 6 13 6 13 mA Burst leng th = 4
3
TBD TBD 8 14 8 14 mA Burst leng th = 8
TBD TBD 10 18 11 19 mA Bur s t length =16
TBD TBD 11 20 11 20 mA Burst length = Continuous
Synchronous
CLK = 54 MHz
TBD TBD 7 16 7 16 mA Burst leng th = 4
3
TBD TBD 10 18 10 18 mA Burst length = 8
TBD TBD 12 22 12 22 mA Burst length = 16
TBD TBD 13 25 13 25 mA Burst length = Continuous
ICCR Average
VCC
Read
Synchronous
CLK = 66 MHz
TBD TBD 8 17 - - mA Burst length = 4
3, 4
TBD TBD 11 20 - - mA Burst length = 8
TBD TBD 14 25 - - mA Burst length = 16
TBD TBD 16 30 - - mA Burst length = Continuous
Intel® Wireless Flash Memory (W 18)
6.0 Electrica l Specificat ions
Preliminary Datasheet 29
ICCW VCC Program TBD TBD 18 40 18 40 mA VPP = VPP1, Program in
Progress 4,5,6
TBDTBD815815mA
VPP = VPP2, Program in
Progress
ICCE VCC Block Erase TBD TBD 18 40 18 40 mA VPP = VPP1, Block Erase in
Progress 4,5,6
TBDTBD815815mA
VPP = VPP2, Block Erase in
Progress
ICCWS VCC Program Suspend TBD TBD 5 18 5 25 µA CE# = VCC, Program Sus-
pended 7
ICCES VCC Erase Suspend TBD TBD 5 18 5 25 µA CE# = VCC, Erase Sus-
pended 7
IPPS
(IPPWS,
IPPES)
VPP Standby
VPP Program Suspend
VPP Erase Suspend TBDTBD0.250.25µAV
PP <VCC 4
IPPR VPP Read TBDTBD215215µA
VPP ≤ VCC
IPPW VPP Program TBD TBD 0.05 0.10 0.05 0.10 mA
VPP = VPP1, Program in
Progress 5
TBD TBD 8 22 16 37 VPP = VPP2, Program in
Progress
IPPE VPP Erase TBD TBD 0.05 0.10 0.05 0.10 mA
VPP = VPP1, Erase in
Progress 5
TBDTBD822822 VPP = VPP2, Erase in
Progress
Notes:
1. All currents are RMS unless noted. Typical values at ty pical VCC, TA = +25° C.
2. VCCQ = 1. 35 V - 1.8V is available on 130 nm products onl y.
3. Automatic Power Savings (APS) reduces ICCR to approximately standby levels in static operation. See ICCRQ
specification for deta ils.
4. Sampled, not 100% tested.
5. VCC read + pr ogram current is the sum of VCC read and VCC program currents.
6. VCC read + erase current is the su m of VCC read and VCC era s e currents.
7. ICCES is specified with device deselected. If device is read wh ile in erase suspend, current is ICCES plus ICCR.
8. If VIN>VCC the input load current increase s to 10 µA max.
9. ICCS is the average current measured over any 5 ms time interval 5 µs after a CE# de-assertion.
10. Refer to sec t io n Sectio n 8. 2, “A utoma t i c Po w e r Sa v in g s ( APS)” on page 5 6 for ICCAPS measurement details.
11. TBD values are to be determined pending silicon characterization.
Table 10. DC Current Characteristics (Sheet 2 of 2)
Symbol Parameter (1)
VCCQ= 1.35 V
– 1.8 V (2) VCCQ= 1.8 V
Unit Test Condition Note32/64/128-
Mbit 32/64-Mbit 128-Mbit
Typ Max Typ Max Typ Max
Intel® Wireless Flash Memory (W 18)
6.0 Electrical Specifications
30 Preliminary Datasheet
6.2 DC Voltage Characteristics
Table 11. DC Voltage Characteristics
Symbol Parameter
VCCQ= 1.35 V –
1.8 V (1) VCCQ= 1. 8 V
Unit Te st Condition Note
32/64/128-Mbit 32/64-Mbit 128-Mbit
Min Max Min Max Min Max
VIL Input Low 0 0.2 0 0.4 0 0.4 V 2
VIH Input High VCCQ
– 0.2 VCCQ VCCQ
– 0.4 VCCQ VCCQ
– 0.4 VCCQ V2
VOL Output Low - 0.1 - 0.1 - 0.1 V VCC = VCCMin
VCCQ = VCCQMin
IOL = 100 µA
VOH Output High VCCQ
– 0.1 -VCCQ
– 0.1 -VCCQ
– 0.1 -V
VCC = VCCMin
VCCQ = VCCQMin
IOH = –100 µA
VPPLK VPP Loc k- O ut - 0 .4 - 0. 4 - 0.4 V 3
VLKO VCC Lock 1.0 - 1.0 - 1.0 - V
VILKOQ VCCQ Lock TBD - 0.9 - 0.9 - V
Notes:
1. VCCQ = 1.35 V - 1.8V is available on 130 nm devices only.
2. VIL can unde rshoo t t o –1. 0 V for durat ions of 2 ns or le ss and VIH can ove rs hoo t to VCCQ+1.0 V for durations of
2 ns or less.
3. VPP <= VPPLK inhibits erase and program operations. Don’t use VPPL and VPPH outside their valid ranges.
Intel® Wireless Flash Memory (W 18)
7.0 AC Characteristics
Preliminary Datasheet 31
7.0 AC Characteristics
Table 12. Read Ope rations - 90 nm Lithography (Sheet 1 of 2)
#
Symbol
Parameter (1,2)
VCCQ=
1.7 V – 1.95 V Unit Notes
Min Max
Asynchronous S pecifi cations
R1 tAVAV Read Cycle Time 60 - ns 7,8
R2 tAVQV Address to Output Valid - 60 ns 7,8
R3 tELQV CE # Low to Output Va li d - 60 n s 7 , 8
R4 tGLQV OE# Low to Output Valid - 20 ns 4
R5 tPHQV RST# High to Output Valid - 150 ns
R6 tELQX CE # Low to Output Lo w -Z 0 - ns 5
R7 tGLQX OE# Low to Output Low-Z 0 - ns 4,5
R8 tEHQZ CE# High to Output High-Z - 1 4 ns 5
R9 tGHQZ OE# High to Output High-Z - 14 ns 4,5
R10 tOH CE# (OE#) High to Output Low-Z 0 - ns 4,5
Latching Specifications
R101 tAVVH Address Se tup to ADV# Hi gh 7 - ns
R102 tELVH CE# Low to ADV# High 10 - n s
R103 tVLQV ADV# Low to Output Valid - 60 ns 7,8
R104 tVLVH ADV# Pulse Width Low 7 - ns
R105 tVHVL ADV# Pulse Width High 7 - ns
R106 tVHAX Address Hold from A DV # High 7 - ns 3
R108 tAPA Page Address Access Ti me - 20 ns
Cloc k Sp ec ifi ca ti ons
R200 fCLK CLK Frequency - 66 MHz
R201 tCLK CLK Period 15 - n s
R202 tCH/L CLK High or Lo w Time 3.5 - ns
R203 tCHCL CLK Fall or Rise Time - 3 ns
Intel® Wireless Flash Memory (W 18)
7.0 AC Characteristics
32 Preliminary Datasheet
1. See Figure 22, “AC Input/Output Reference Wav eform” on page 54 for timing measur ements and
ma xi m um al lo w a bl e in pu t s lew rate .
2. AC specifications assume the data bus voltag e is less than or equal to VCCQ when a read operation is
initiated.
3. Address hold in synchronous-burst mode is defined as tCHAX or tVHAX, whichever timing specification is
satisfied first.
4. OE# may be delayed by up to tELQV– tGLQV a fter the falling edge of CE# without impact to tELQV.
5. Sampl ed, not 100% t ested.
6. Applies only to sub s equent synchronous reads .
7. During the initial access of a synchronous burst read, data from the f irst word may begin to be driven
onto the data bus as early as the first clock edge after t AVQV.
8. All the preceding specifications apply to all densities.
Synchronous Specifications
R301 tAVCH Address Valid Setup to CLK 7 - ns
R302 tVLCH ADV# Low Setup to CLK 7 - ns
R303 tELCH CE# Low Setup to C LK 7 - ns
R304 tCHQV CLK to Output Valid - 11 ns 8
R305 tCHQX Outp ut Ho ld from CLK 3 - ns
R306 tCHAX Address Hold from CLK 7 - ns 3
R307 tCHTV CLK to WAIT Valid - 11 ns 8
R308 tELTV CE# Low to WAIT Valid - 11 ns 6
R309 tEHTZ CE# High to WAIT High-Z - 11 ns 5,6
R310 tEHEL CE# Pulse Width High 14 - ns 6
Table 12. Read Operations - 90 nm Lithography (Sheet 2 of 2)
#
Symbol
Parameter (1,2)
VCCQ=
1.7 V – 1.95 V Unit Notes
Min Max
Intel® Wireless Flash Memory (W 18)
7.0 AC Characteristics
Preliminary Datasheet 33
Table 13. Read Operations - 130 nm Lithography (Sheet 1 of 2)
#
Symbol
Parameter (1,2)
VCCQ=
1.35 V – 1.8 V VCCQ=
1.7 V – 2.24 V
Unit Notes
-65 -85 -60 -80
Min Max Min Max Min Max Min Max
Asynchronous Specifications
R1 tAVAV Read Cycle Time 65 - 85 - 60 - 80 - ns 7,8
R2 tAVQV Address to Output Valid - 65 - 85 - 60 - 80 ns 7,8
R3 tELQV CE# Low to Output Valid - 65 - 85 - 60 - 80 ns 7,8
R4 tGLQV OE# Low to Output Val id - 25 - 30 - 20 - 2 5 ns 4
R5 tPHQV RST# High to Out put Valid - 150 - 150 - 150 - 150 ns
R6 tELQX CE# Low to Output Low-Z 0 - 0 0 - 0 ns 5
R7 tGLQX OE# Low to Outp ut Low- Z 0 - 0 0 - 0 - ns 4,5
R8 tEHQZ CE# High to Output High-Z - 17 - 20 - 14 - 17 ns 5
R9 tGHQZ OE# High to Output High-Z - 14 - 14 - 14 - 14 ns 4,5
R10 tOH CE# (OE#) High to Output Low- Z 0 - 0 0 - 0 - ns 4,5
Latching Specifications
R101 tAVVH Addres s Setu p to ADV# High 7 - 7 - 7 - 7 - ns
R102 tELVH CE# Lo w to ADV# H igh 10 - 10 - 10 - 10 - ns
R103 tVLQV ADV# Low to Output Valid - 65 - 85 - 60 - 80 ns 7,8
R104 tVLVH ADV# Pulse Width Low 7-7-7-7-ns
R105 tVHVL ADV# Pulse Width High 7-7-7-7-ns
R106 tVHAX Address Hol d from ADV# High 7 - 7 - 7 - 7 - ns 3
R108 tAPA Page Addr ess Access Time - 25 - 30 - 20 - 25 ns
Cloc k Sp ec ification s
R200 fCLK CLK Frequency - 54 - 40 - 66 - 54 MHz
R201 tCLK CLK Period 18.5 - 25 - 15 - 18.5 - ns
R202 tCH/L CLK High or Low Time 4.5 - 9.5 - 3.5 - 4.5 - ns
R203 tCHCL CLK Fall or Rise Time -3-3-3-3ns
Intel® Wireless Flash Memory (W 18)
7.0 AC Characteristics
34 Preliminary Datasheet
Note: For all numbered note references in this table, refer to the no tes in Table 12, “Re ad Operations - 90 nm
Lithography” on page 31.
Syn c hronous Specifications
R301 tAVCH Address Valid Setup to CLK 7-7-7-7-ns
R302 tVLCH ADV# Low Setup to CLK 7-7-7-7-ns
R303 tELCH CE# Low Setup to CLK 7 - 7 - 7 - 7 - ns
R304 tCHQV CLK to Output Valid - 14 - 20 - 11 - 14 ns 8
R305 tCHQX Output Hold from CLK 3 - 3 - 3 - 3 - ns
R306 tCHAX Address Hold from CLK 7-7-7-7-ns 3
R307 tCHTV CLK to WAIT Valid - 14 - 20 - 11 - 14 ns 8
R308 tELTV CE# Low to WAI T Valid - 14 - 20 - 11 - 14 ns 6
R309 tEHTZ CE# High to WAIT High-Z - 14 - 20 - 11 - 14 ns 5,6
R310 tEHEL CE# Pulse Width High 14 - 14 - 14 - 14 - ns 6
Table 13. Read Operations - 130 nm Lithography (Sheet 2 of 2)
#
Symbol
Parameter (1,2)
VCCQ=
1.3 5 V – 1. 8 V VCCQ=
1.7 V – 2.24 V
Unit Notes
-65 -85 -60 -80
Min Max Min Max Min Max Min Max
Intel® Wireless Flash Memory (W 18)
7.0 AC Characteristics
Preliminary Datasheet 35
Table 14. Read Operations - 180 nm Lithography (Sheet 1 of 2)
# Sym Parameter (1,2)
32/64-Mbit 128-Mbit
Unit Notes–70 –85 -85
MinMaxMinMax Min Max
Asynchronous Specifications
R1 tAVAV Read Cycle Time 70 - 85 - 85 - ns
R2 tAVQV Address to Output Delay - 70 - 85 - 85 ns
R3 tELQV CE# Low to Output Delay - 70 - 85 - 85 ns
R4 tGLQV OE# Low to Output Delay - 30 - 30 - 30 ns 5
R5 tPHQV R ST# High to Output Delay - 150 - 150 - 150 ns
R6 tELQX CE# Low to Output in Low-Z 0 - 0 - 0 - ns 6
R7 tGLQX OE# Low to Output in Low-Z 0 - 0 - 0 - ns 5,6
R8 tEHQZ CE# High to Output in High-Z - 20 - 20 - 20 ns 6
R9 tGHQZ OE# High to Output in High-Z - 14 - 14 - 14 ns 5,6
R10 tOH CE# (OE#) High to Output in Low-Z 0 - 0 - 0 - ns 5,6
Latching Specifications
R101 tAVVH Address Setup to ADV# High 10 - 10 - 10 - ns
R102 tELVH CE # Low to ADV# High 10 - 10 - 10 - ns
R103 tVLQV ADV# Low to Output Delay - 70 85 - 85 ns
R104 tVLVH ADV# Pulse Width Low 10 - 10 - 10 - ns
R105 tVHVL ADV# Pul s e Width High 10 - 10 - 10 - ns
R106 tVHAX Address Hold from ADV# High 9 - 9 - 9 - ns 4
R108 tAPA Page Add ress Access Time - 20 - 25 - 25 ns
Cloc k Sp ec ification s
R200 fCLK C LK Frequency - 52 - 40 - 40 MHz
R201 tCLK C LK Period 19 - 25 - 25 - ns
R202 tCH/L CLK High or Low Time 5 - 5 - 5 - ns
R203 tCHCL CLK Fall or Rise T ime - 3 - 3 - 3 ns
Intel® Wireless Flash Memory (W 18)
7.0 AC Characteristics
36 Preliminary Datasheet
Note: For all numbered note references in this table, refer to the no tes in Table 12, “Re ad Operations - 90 nm
Lithography” on page 31.
Syn c hronous Specifications
R301 tAVCH Add re s s Vali d Se tu p to CL K 9 - 9 - 9 - ns
R302 tVLCH ADV# Low Setup to CLK 10 - 10 - 10 - ns
R303 tELCH C E# Low Se tu p to CL K 9 - 9 - 9 - ns
R304 tCHQV CLK to Output Valid - 14 - 18 - 18 ns
R305 tCHQX Output Hold from CLK 3.5 - 3.5 - 3.5 - ns
R306 tCHAX Ad dress Hold from CLK 10 - 10 - 10 - ns 4
R307 tCHTV CLK to WAIT Valid - 14 - 18 - 18 ns
R308 tELTV CE# Low to WAIT Valid - 14 - 18 - 18 ns 7
R309 tEHTZ CE# High to WAIT High-Z - 20 - 25 - 25 ns 6,7
R310 tEHEL CE# Puls e Width High 15 - 20 - 20 - ns 7
Table 14. Read Operations - 180 nm Lithography (Sheet 2 of 2)
# Sym Parameter (1,2)
32/64-Mbit 128-Mbit
Unit Notes–70 –85 -85
Min Max Min Max Min Max
Intel® Wireless Flash Memory (W 18)
7.0 AC Characteristics
Preliminary Datasheet 37
Notes:
1. W AIT shown asserted (RCR[10 ]= 0)
2. ADV# assumed to be driven to VIL in this waveform
Figure 8. Asynchronous Read Operation Waveform
V
IH
V
IL
Valid
Address
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
High Z
V
OH
V
OL
Valid
Output
V
IH
V
IL
R1
R2
R3
R4
R5
R7
R10
Address [A]
CE# [E]
OE# [G]
WE# [W]
Data [D/Q]
RST# [P]
R8
R9
V
OH
V
OL
High Z
WAIT [T]
High Z
Note 1
Intel® Wireless Flash Memory (W 18)
7.0 AC Characteristics
38 Preliminary Datasheet
Figure 9. Latched Asynchronous Re ad Operation Waveform
V
OH
V
OL
High Z Valid
Output
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
Valid
Address
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
Data [Q]
WE# [W]
OE# [G]
CE# [E]
A[MAX:2] [A]
ADV # [V ]
RST# [P]
R102
R104
R1
R2
R3
R4
R5
R6
R7
R10
R103
R101
R105 R106
A[1:0] [A]
V
IH
V
IL
Valid
Address
Valid
Address
Valid
Address
R8
R9
Intel® Wireless Flash Memory (W 18)
7.0 AC Characteristics
Preliminary Datasheet 39
Note: WAIT shown asserted (RCR[10] = 0).
Figure 10. Page-Mode Read Operation Waveform
R105
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
High Z Valid
Output Valid
Output Valid
Output Valid
Output
V
IH
V
IL
V
IH
V
IL
Valid
Address
V
IH
V
IL
Valid
Address Valid
Address Valid
Address Valid
Address
R102
R104
ADV# [V]
CE# [E]
OE# [G]
WE# [ W]
Data [D/Q]
RST# [P]
A[MAX:2] [A]
A[1:0] [A]
R1
R2
R101
R106
R103
R3
R4
R7
R6
R108
R10R5
R9
R8
V
OH
V
OL
High Z
WAIT [T]
High Z
Note 1
Intel® Wireless Flash Memory (W 18)
7.0 AC Characteristics
40 Preliminary Datasheet
Notes:
1. Section 14.2, “First Access Latency Count (RCR[13:11])” on pa ge 91 describes how to insert clock cycles during the initial
access.
2. WAIT (shown asserted; RCR[10]=0) can be configured to assert either during, or one data cycle before, valid data.
3. This waveform illustrates the case in which an x-word burst is initiated to the main array and it is terminated by a CE# de-
asser tion aft er the first word in the burst . If this access had been done to Stat us, ID, or Query read s, the asserted (low)
W AIT signal would have remained asserted (low) as long as CE# is asserted (low).
Figure 11. Single Sy nchronous R ead-Array O pe r ation Wa veform
Note 1
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
Valid
Address
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
V
OH
V
OL
High Z Valid
Output
V
IH
V
IL
R101
R102
R302
R301 R306
R2
R106R105
R103
R3
R4
R7
R8
R9
R10
R5
R305
High Z
R304
CLK [C]
RST# [P]
Address [A]
ADV# [V]
OE# [G]
WE # [W]
WAIT [T ]
Data [Q]
CE# [E]
R303
R104
High Z
R308
R309
Note 2
Intel® Wireless Flash Memory (W 18)
7.0 AC Characteristics
Preliminary Datasheet 41
Notes:
1. Sec tion 14.2, “First Access Latency Count (RC R[ 13:11])” on page 91 describes how to insert clock cycles during the initial
access.
2. WAIT (shown asserted; RCR[10] = 0) can be configured to assert either during, or one data cycle before, valid data.
Figure 12. Synchronous 4-Word Burst Read Operatio n Waveform
V
IH
V
IL
V
OH
V
OL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
Valid
Address
V
IH
V
IL
Note 1
V
OH
V
OL
Valid
Output Valid
Output Valid
Output Valid
Output
High Z
R105
R102
R301
R302
R306
R101
R2
R106
R103
R3
R4
R7
R304
R5
R305
R8
R9
01
RST# [P]
WAIT [T]
WE# [W]
OE# [G]
CE# [E]
ADV# [V]
A
ddress [A]
CLK [C]
Data [Q]
Note 2
R104
R303
R10
R307
High Z
R308 R309
R310
High
Z
High Z
Intel® Wireless Flash Memory (W 18)
7.0 AC Characteristics
42 Preliminary Datasheet
Notes:
1. Section 14.2, “First Access Latency Count (RCR[13:11])” on pa ge 91 describes how to insert clock cycles during the initial
access.
2. WAIT (shown asserted; RCR[10]=0) can be configured to assert either during, or one data cycle before, valid data
(ass umed wait delay of two clocks, for example).
Figure 13. WAIT Functionality for EOWL ( E nd-of-Word L i ne) Condition Wa veform
V
IH
V
IL
V
OH
V
OL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
Valid
Address
V
IH
V
IL
Note 1
V
OH
V
OL
Valid
Output Valid
Output Valid
Output Valid
Output
High Z
R105
R102
R301
R302
R306
R101
R2
R106
R103
R3
R4
R7
R304
R5
R305
01
RST# [P]
WAIT [T]
WE# [W]
OE# [G]
CE# [E]
ADV# [V]
Address [A]
CLK [C]
Data [D /Q ]
Note 2
R104
R303
R307
High Z
R308
High Z
Intel® Wireless Flash Memory (W 18)
7.0 AC Characteristics
Preliminary Datasheet 43
Notes:
1. Sec tion 14.2, “First Access Latency Count (RC R[ 13:11])” on page 91 describes how to insert clock cycles during the initial
access.
2. WAIT shown asserted (RCR[ 10]=0).
Figure 1 4. WAIT Signal in S yn ch ronous Non-Read Arra y Op eration Waveform
Note 1
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
Valid
Address
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
V
OH
V
OL
High Z Valid
Output
V
IH
V
IL
R101
R102
R302
R301 R306
R2
R106R105
R103
R3
R4
R7
R8
R9
R10
R5
R305
High Z
R304
CLK [C]
RST# [P]
Address [A]
ADV# [V]
OE# [G]
WE# [W]
WAIT [T]
Data [Q]
CE# [E]
R303
R104
High Z
R308
R309
Note 2
Intel® Wireless Flash Memory (W 18)
7.0 AC Characteristics
44 Preliminary Datasheet
Note: During Burst Suspend, Clock signal can be held high or low.
Figure 15. Burst Suspend
Q0 Q1 Q1 Q2
R304R304
R7
R6
R13
R12
R9R4R9R4
R8R3
R106
R101
R105R105
R1R1
R2
R305R305R305R304
CLK
Address [A]
ADV#
CE# [E]
OE# [G]
WAIT [T]
WE# [W]
DA TA [D/Q]
Intel® Wireless Flash Memory (W 18)
7.0 AC Characteristics
Preliminary Datasheet 45
7.1 AC Write Characteristics
Table 15. AC Write Characteristics - 90 nm Lithogra phy
# Sym Paramet er (1,2)
VCCQ =
1.7 V – 1. 95 V Unit Notes
Min Max
W1 tPHWL (tPHEL) RST# Hi gh Recovery to WE# (CE#) Low 150 - ns 3
W2 tELWL (tWLEL) CE# (WE#) Setu p to WE # (CE#) Lo w 0 - ns
W3 tWLWH (tELEH) WE # (C E#) Writ e Pul se W idt h Lo w 40 - ns 4
W4 tDVWH (tDVEH) Data Setup t o WE# (CE#) High 40 - ns
W5 tAVWH (tAVEH) Address Setup t o WE# (CE#) Hig h 40 - ns
W6 tWHEH (tEHWH) CE# (WE#) Hold from WE# (CE#) High 0 - ns
W7 tWHDX (tEHDX) Data Hold from WE# (CE#) High 0 - ns
W8 tWHAX (tEHAX) Address Ho ld from WE# (CE # ) H ig h 0 - ns
W9 tWHWL (tEHEL) WE# (CE# ) Pu ls e Wi dth Hi gh 20 - ns 5 ,6,7
W10 tVPWH (tVPEH) VPP Setup to WE# (CE#) High 200 - ns 3
W11 tQVVL VPP Hold from Valid SRD 0 - ns 3,8
W12 tQVBL WP# Hold from Valid SRD 0 - ns 3,8
W13 tBHWH (tBHEH) WP# Setup to WE# (CE#) High 200 - ns 3
W14 tWHGL (tEHGL) Write Recovery before Read 0 - ns
W16 tWHQV WE# High to Valid Data tAVQV
+20 - ns 3,6,10
W18 tWHAV WE# High to Address Valid 0 - ns 3,9,10
W19 tWHCV WE# High t o CLK Valid 12 - ns 3,10
W20 tWHVH WE# High to ADV# High 12 - ns 3,10
Notes:
1. Write timing characteristics during erase suspend are the same as during write-only
operations.
2. A write operation can be terminated with either CE# or WE#.
3. Sampled, not 100% tested.
4. Write pulse width low (tWLWH or tELEH) is defined fr o m CE # or WE # low (w hi c he v er oc c u r s
last) to CE# or WE# high (whichever occurs first). Hence, tWLWH = tELEH = tWLEH = tELWH.
5. Write pulse width high (tWHWL or tEHEL) is defined from CE# or WE# high (whichever is
first) to CE# or WE# low (whichever is last). Hence, tWHWL = tEHEL = tWHEL = tEHWL.
6. System desi gners shoul d take this into account and may insert a software No-Op
instruction to delay the first read after issuing a command.
7. For commands other than resume commands.
8. VPP shoul d be held at VPP1 or VPP2 until block erase or program success is determined.
9. Applica ble during asynchronous r eads following a write.
10. tWHC H/L OR tWHVH must be me t w he n tr an s iti on i ng f rom a w rit e cy c le t o a sy n c hro n ous burst
read. t WHCH/L and tWHVH both refer to the address latching event (e ither the rising/falling clock
edge or the rising AD V# edge, whichever occurs first).
Intel® Wireless Flash Memory (W 18)
7.0 AC Characteristics
46 Preliminary Datasheet
Table 16. AC Write Characteristics - 130 nm Lithography
# Sym Pa rameter (1,2)
VCCQ =
1.3 5 V – 1. 8 V VCCQ =
1.7 V – 2.24 V
Unit Notes
-65 -85 -60 -80
Min Max Min Max Min Max Min Max
W1 tPHWL (tPHEL)RST# High Recovery to WE#
(CE#) Low 150 - 150 - 150 - 150 - ns 3
W2 tELWL (tWLEL)CE# (WE#) Setup to WE# (CE#)
Low 0-0-0-0-ns
W3 tWLWH (tELEH)WE# (CE#) Write Pulse Width
Low 50 - 60 - 40 - 60 - ns 4
W4 tDVWH (tDVEH) Data Setup to WE# (CE#) High 50 - 60 - 40 - 60 - ns
W5 tAVWH (tAVEH)Address Setup to WE# ( CE #)
High 50 - 60 - 40 - 60 - ns
W6 tWHEH
(tEHWH)CE# (WE# ) Hold fr om WE#
(CE#) High 0-0-0-0-ns
W7 tWHDX (tEHDX)Data Hold from WE# (CE#) High0-0-0-0-ns
W8 tWHAX (tEHAX)Address Hold from WE# (CE#)
High 0-0-0-0-ns
W9 tWHWL (tEHEL) WE# ( CE # ) P u ls e Wi dth Hi gh 20 - 25 - 2 0 - 25 - ns 5,6, 7
W10 tVPWH (tVPEH) VPP Setup to WE# (CE#) High 200 - 200 - 200 - 200 - ns 3
W11 tQVVL VPP Hold from Valid SRD 0 - 0 - 0 - 0 - ns 3,8
W12 tQVBL WP# Hold from Valid SRD 0 - 0 - 0 - 0 - ns 3,8
W13 tBHWH (tBHEH) WP# Setup to WE# (CE#) High 200 - 200 - 200 - 200 - ns 3
W14 tWHGL (tEHGL)Write Recovery before Read 0-0-0-0-ns
W16 tWHQV WE# High to Vali d Data tAVQV
+ 25 -tAVQV
+ 55 -tAVQV
+20 -tAVQV
+50 - ns 3,6,10
W18 tWHAV WE# High to Ad dress Valid 0 - 0 - 0 - 0 - n s 3,9,10
W19 tWHCV WE# High to CLK Valid 16 - 20 - 12 - 20 - n s 3,10
W20 tWHVH WE# High to ADV# High 16 - 20 - 12 - 20 - ns 3,10
Notes: For all numbered note r eference s in this table, refe r to th e notes in Table 1 5, “AC Wri te Char acter ist ics - 90 nm
Lithography” on page 45.
Intel® Wireless Flash Memory (W 18)
7.0 AC Characteristics
Preliminary Datasheet 47
Table 17. AC Write Characteristics – 180 nm Lithography
# Sym Parameter (1,2)
VCCQ =
1.7 V - 2.24 V
Unit Notes
-70 -85
Min Max Min Max
W1 tPHWL (tPHEL) RST# High Reco very to WE # (CE#) Low 1 50 - 150 - ns 3
W2 tELWL (tWLEL) CE# (WE#) Setup to WE# (CE#) Low 0 - 0 - ns
W3 tWLWH (tELEH) WE# (CE#) Write Puls e Width Low 45 - 60 - ns 4
W4 tDVWH (tDVEH) Data Setup to WE# (CE #) High 45 - 60 - ns
W5 tAVWH (tAVEH) A dd r e ss Se tup to WE # (C E #) H ig h 45 - 6 0 - ns
W6 tWHEH (tEHWH) CE# (WE#) Hold from WE # (CE# ) High 0 - 0 - ns
W7 tWHDX (tEHDX) Data Hold from WE# (CE#) High 0 - 0 - ns
W8 tWHAX (tEHAX) Address Hold from WE# (CE#) High 0 - 0 - ns
W9 tWHWL (tEHEL) WE# (CE#) Pulse Width High 25 - 25 - ns 5,6,7
W10 tVPWH (t VPEH) VPP Setup to WE# (CE#) High 200 - 200 - ns 3
W11 tQVVL VPP Hold from Valid SRD 0 - 0 - ns 3,8
W12 tQVBL WP# Hold from Valid SRD 0 - 0 - ns 3,8
W13 tBHWH (tBHEH) WP# Setup to WE# (CE#) High 200 - 200 - ns 3
W14 tWHGL (tEHGL) Write Recovery before Read 0 - 0 - ns
W16 tWHQV WE# High to Valid Data tAVQV
+ 40 -tAVQV
+ 50 - ns 3,6,10
W18 tWHAV WE# High to Address Valid 0 - 0 ns 3,9,10
W19 tWHCV WE# High to CLK Valid 20 - 20 - ns 3,10
W20 tWHVH WE# High to ADV# High 20 - 20 - ns 3,10
Notes: For all numbered note references in this table, refer to the notes in Table 15, “AC Wri te Characteristics - 90
nm Lithography” on page 45.
Intel® Wireless Flash Memory (W 18)
7.0 AC Characteristics
48 Preliminary Datasheet
Notes:
1. VCC power-up and standby.
2. Write Pro gram or E ra s e S e tu p co m m an d .
3. Write valid address and data (for program) or Erase Confirm command.
4. Autom a te d pro g r am / erase del ay.
5. Read Status Register data (SRD) to determine program/erase operation completion.
6. OE# and CE# must be asserted a nd WE# must be deasserted for read operations.
7. CLK is ignor ed. (but may be kept active/toggling)
Figure 16. Write Operations Waveform
Note 1 Note 2 Note 3 Note 4 Note 5
Address [A]
V
IH
V
IL
Valid
Address Valid
Address
CE# (WE#) [E(W)]
V
IH
V
IL
Note 6
OE# [G]
V
IH
V
IL
WE# (CE#) [W(E)]
V
IH
V
IL
RST# [P]
V
IH
V
IL
W6
W7
W8
W11
W12
R105
VPP [V]
V
PPH
V
PPLK
V
IL
WP# [B]
V
IH
V
IL
Data [Q]
V
IH
V
IL
Data In Valid
SRD
ADV# [V]
V
IH
V
IL
W16W1
W2
W3
W4
W9
W10
W13
W14
R101
R106
Data In
Valid
Address
Note 6
R104
W5 W18
W19
W20
CLK [C]
V
IH
V
IL
Intel® Wireless Flash Memory (W 18)
7.0 AC Characteristics
Preliminary Datasheet 49
Figure 17. Asynchronous Read to Write Operation Waveform
Figure 18. Asynchronous Write to Read Operation
Q D
R5
W7
W4R10
R7
R6
W6
W3W3
W2
R9R4
R8R3
W8W5
R1
R2 R1
A
ddress [A]
CE# [E}
OE# [ G]
WE# [W]
Data [D/Q]
RST# [P]
D Q
W1
R9
R8
R4
R3
R2W7
W4
W14
W18W3W3
R10W6W2
R1R1W8W5
A
ddress [A]
CE# [ E}
WE# [W]
OE# [G]
Data [D/Q]
RS T# [ P ]
Intel® Wireless Flash Memory (W 18)
7.0 AC Characteristics
50 Preliminary Datasheet
Figure 19. Synchronous Read to Write Operation
Lat ency Count
Q D D
W7
R13
R305
R304
R7
R307R12
W15
W9
W19
W8
W9W3W3
W2
R8
R4
W6R11R11
R303
R3
W20
R104R104R106
R102
R105R105
W18
W5
R101 R2
R306
R302
R301
CLK [C]
A
ddress [A ]
ADV# [V]
CE# [E ]
OE # [ G]
WE#
WAI T [T]
Data [D/Q]
Intel® Wireless Flash Memory (W 18)
7.0 AC Characteristics
Preliminary Datasheet 51
Figure 2 0. Synchronous Write To Read Operation
Latenc y C ount
D Q Q
W1
R304
R305
R304
R3
W7
W4
R307R12
R4
W18
W19W3W3
R11 R303
R11
W6
W2
W20 R104
R106
R104
R306W8W5
R302
R301 R2
CLK
A
ddress [A]
ADV#
CE # [ E }
WE# [W]
OE# [G]
WAIT [T]
Data [D/Q ]
RS T# [ P ]
Intel® Wireless Flash Memory (W 18)
7.0 AC Characteristics
52 Preliminary Datasheet
7.2 Erase and Program Times
Table 18. Erase and Program Tim es
Operation Symbol Parameter Description (1) Notes VPP1 VPP2 Unit
Typ Max Typ Max
Erasing and Suspending
Erase Time W500 tERS/PB 4-Kword Parameter Block 2,3 0.3 2.5 0.25 2.5 s
W501 tERS/MB 32-Kword Main Block 2,3 0.7 4 0.4 4 s
Suspend
Latency W600 tSUSP/P Program Suspend 2 5 10 5 10 µs
W601 tSUSP/E Erase Suspend 2 5 20 5 20 µ s
Programming
Program
Time
W200 tPROG/W Single Word 2 12 150 8 130 µs
W201 tPROG/PB 4-Kword Parameter Block 2,3 0.05 .23 0.03 0.07 s
W202 tPROG/MB 32-Kword Main Block 2,3 0.4 1.8 0.24 0.6 s
En hanced Factory Programming (5)
Program
W400 tEF P / W Sin gl e Word 4 N/A N/A 3 .1 16 µs
W401 tEFP/PB 4-Kword Parameter Block 2,3 N/A - 15 - ms
W402 tEFP/MB 32-Kw ord Main Bloc k 2,3 N/A - 120 - ms
Operation
Latency
W403 tEFP/SETUP E FP Setu p - N/A - 5 µs
W404 tEFP/TRAN Program to Verify Transition N/A N/A 2.7 5.6 µs
W405 tEFP/VERIFY Verify N/A N/A 1.7 130 µs
Notes:
1. Unless noted otherwise, all parameters are measured at TA = +25 °C and nominal volt ages, and they are sampled, not
100% t ested.
2. Excludes external system-level overhead.
3. Exac t results may vary based on system overh ead.
4. W400-Typ is the calculated delay for a single programming pulse. W400-Max incl udes the delay when pr ogramming
within a new word-line.
5. Some EFP performance degradation may occur if block cycling exceeds 10.
Intel® Wireless Flash Memory (W 18)
7.0 AC Characteristics
Preliminary Datasheet 53
7.3 Reset Specifications
Table 19. Reset Specifications
# Symbol Parameter (1) Notes Min Max Unit
P1 tPLPH RST# Low to Reset during Read 1, 2, 3, 4 100 - ns
P2 tPLRH RST# to 1, 3, 4, 5 - µs
RST# to Reset during 1, 3, 4, 5 - µs
P3 tVCCPH VCC Power Valid to Reset 1,3,4,5,6 60 - µs
Notes:
1. These specifications ar e valid for all product versions (packages and speeds).
2. The device may reset if tPLPH< tPLPHMin, but this is not guaranteed.
3. Not applicable if RST# is tied to VCC.
4. Sampled, but not 100% te sted.
5. If RST# is tied to VCC, the device is not ready until tVCCPH occurs after w hen VCC ≥ VCCMin.
6. If RST# is tied to any supply/signal with VCCQ volt age levels, the RST# input voltage must not exceed VCC until VCC ≥
VCCMin.
Figure 21. Reset Operations Waveforms
(
A) Reset during
read mod e
(B) Reset during
program or block erase
P1
≤
P2
(C) Reset during
program or block erase
P1
≥
P2
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
RST# [P]
RST# [P]
RST# [P]
Abort
Complete
Abort
Complete
V
CC
0V
VCC
(D) VCC Pow er-up to
RST# high
P1 R5
P2
P3
P2 R5
R5
Intel® Wireless Flash Memory (W 18)
7.0 AC Characteristics
54 Preliminary Datasheet
7.4 AC I/O Test Conditions
Note: Input timing begins, and output timing ends, at VCCQ/2. Input rise and fall times (10% to 90%) < 5 ns.
Wo rst case speed conditions are when VCC = VCCMin.
Note: See Table 19 for com p on e nt v alue s .
Figure 22. AC Input/Out put Reference Waveform
V
CCQ
0V
V
CCQ
/2 V
CCQ
/2
Test Points
Input Outpu
t
Figure 23. Tr an sient Equivalent Testing Load Circuit
Device
Under Test
V
CCQ
C
L
R
2
R
1
Out
Table 20. Test Configuration Component Values for Worst Case Speed Conditions
Test Configuration CL (pF) R1 (kΩ)R
2 (kΩ)
30 13.5 13.5
30 16.7 16.7
Note: CL includes jig capacitance.
Figure 24. Cloc k Input AC Waveform
CLK [C]
VIH
VIL
R203R202
R201
Intel® Wireless Flash Memory (W 18)
7.0 AC Characteristics
Preliminary Datasheet 55
7.5 Device Capacitance
TA = +25 °C, f = 1 MHz
Symbol Parameter§Typ Max Unit Condition
CIN Inpu t Capa c ita nc e 6 8 pF VIN = 0.0 V
COUT Output Capacitance 8 12 pF VOUT = 0.0 V
CCE CE# Input Capacitance 10 12 pF VIN = 0.0 V
§Sampl ed, not 100% te sted.
Intel® Wireless Flash Memory (W 18)
8.0 Power and Reset Specifications
56 Preliminary Datasheet
8.0 Power and Rese t Specifications
Intel® Wireless Flash Memory (W18) devices have a layered approach to power savings that can
significantly reduce overall system power consumption. The APS feature reduces power
consumption when the device is selected but idle. If CE# is deasserted, the memory enters its
standby mode, where current consumption is even lower . Asserting RST# provides current savings
similar to standby mode. The combination of these features can minimize memory power
consumption, and therefore, overall system power consumption.
8.1 Active Power
With CE# at VIL and RST# at VIH, the device is in the active mode. Refer to Section 6.1, “DC
Current Characteristics” on page 28, for ICC values. When the device is in “active” state, it
consumes the most power from the system. Minimizing device active current therefore reduces
system power consumption, especially in battery-powered applications.
8.2 Automatic Power Savings (APS)
Automatic Power Saving (APS) provides low-power operation during a read’s active state. During
APS mode, ICCAPS is the average current measured over any 5 ms time interval 5 µs after the
following events happen:
•There is no internal sense activity;
•CE# is asserted;
•The address lines are quiescent, and at VSSQ or VCCQ.
OE# may be asserted during APS.
8.3 Standby Power
W ith CE# at VIH and the device in read mode, the flash memory is in standby mode, which disables
most device circuitry and substantially reduces power consumption. Outputs are placed in a high-
impedance state independent of the OE# signal state. If CE# transitions to VIH during erase or
program operations, the device continues the operation and consumes corresponding active power
until the operation is complete. ICCS is the average current measured over any 5 ms time interval 5
µs after a CE# de-assertion.
8.4 Power-Up/Down Characteristics
The device is protected against accidental block erasure or programming during power transitions.
Power supply sequencing is not required if VCC, VCCQ, and VPP are connected together; so it
doesn’t matter whether VPP or VCC powers-up first. If VCCQ and/or VPP are not connected to the
system supply, then VCC should attain VCCMIN before applying VCCQ and VPP. Device inputs
should not be driven before supply voltage = VCCMIN. Power supply transitions should only occur
when RST# is low.
Intel® Wireless Flash Memory (W 18)
8.0 Power and Reset Specifications
Preliminary Datasheet 57
8.4.1 System Reset and RST#
The use of RST# during system reset is important with automated program/erase devices because
the system expects to read from the flash memory when it comes out of reset. If a CPU reset occurs
without a flash memory reset, proper CPU initialization will not occur because the flash memory
may be providing status information instead of array data. To allow proper CPU/flash initialization
at system reset, connect RST# to the system CPU RESET# signal.
System designers must guard against spurious writes when VCC voltages are above VLKO.
Because both WE# and CE# must be low for a command write, driving either signal to VIH inhibits
writes to the device. The CUI architecture provides additional protection because alteration of
memory contents can only occur after successful completion of the two-step command sequences.
The device is also disabled until RST# is brought to VIH, regardless of its control input states. By
holding the device in reset (RST# connected to system PowerGood) during power-up/down,
invalid bus conditions during power-up can be masked, providing yet another level of memory
protection.
8.4.2 VCC, VPP, and RST# Transitions
The CUI latches commands issued by syste m software and is not altered by VPP or CE# transitions
or WSM actions. Read-array mode is its power-up default state after exit from reset mode or after
VCC transitions above VLKO (Lockout voltage). After completing program or block erase
operations (even after VPP transitions below VPPLK), the Read Array command must reset the CUI
to read-array mode if flash memory array access is desired.
8.5 Power Supply Decoupling
When the device is accessed, many internal conditions change. Circuits are enabled to charge
pumps and switch voltages. This internal activity produces transient noise. To minimize the effect
of this transient noise, device decoupling capacitors are required. Transient current magnitudes
depend on the device outputs’ capacitive and inductive loading. Two-line control and proper
decoupling capacitor selection suppresses these transient voltage peaks. Each flash device should
have a 0.1 µF ceramic capacitor connected between each power (VCC, VCCQ, VPP), and ground
(VSS, VSSQ) signal. High-frequency, inherently low-inductance capacitors should be as close as
possible to package signals.
Intel® Wireless Flash Memory (W 18)
9.0 Bus Operatio ns Overview
58 Preliminary Datasheet
9.0 Bus Operations Overview
This section provides an overview of device bus operations. The Intel® Wireless Flash Memory
(W18) family includes an on-chip WSM to manage block erase and program algorithms. Its
Command User Interface (CUI) allows minimal processor overhead with RAM-like interface
timings. Device commands are written to the CUI using standard microprocessor timings.
9.1 Bus Operations
Bus cycles to/from the W18 device conform to standard microprocessor bus operations. Table 21
summarizes the bus operations and the logic levels that must be applied to the device’s control
signal inputs.
9.1.1 Reads
Device read operations are performed by placing the desired address on A[22:0] and asserting CE#
and OE#. ADV# must be low, and WE# and RST# must be high. All read operations are
independent of the voltage level on VPP.
CE#-low selects the device and enables its internal circuits. OE#-low or WE#-low determine
whether DQ[15:0] are outputs or inputs, respectively. OE# and WE# must not be low at the same
time - indeterminate device operation will result.
In asynchronous-page mode, the rising edge of ADV# can be used to latch the address. If only
asynchronous read mode is used, ADV# can be tied to ground. CLK is not used in asynchronous-
page mode and should be tied high.
In synchronous-burst mode, ADV# is used to latch the initial address - either on the rising edge of
ADV# or the rising (or falling) edge of CLK with ADV# low, whichever occurs first. CLK is used
in synchronous-burst mode to increment the internal address counter, and to output read data on
DQ[15:0].
Each device partition can be placed in any of several read states:
Table 21. Bus Operations Summary
Bus Ope ration RST# CLK AD V# CE# OE# WE# WAIT DQ[15:0] Notes
Read
Asynchronous VIH X L L L H Asserted Output
Synchronous VIH Running L L L H Driven Output 1
Burst Suspend V IH Halted X L H H Active Output
Write VIH X L L H L Asserted Input 2
Output Disable VIH XX L H HAssertedHigh-Z3
Standby VIH X X H X X High-Z High-Z 3
Reset VIL X X X X X High-Z High-Z 3,4
Notes:
1. WA IT is on ly va li d du r i ng sy nc h ro nous array- re ad ope r at io n s.
2. Refer to the Table 23, “Bus Cycle Definitions” on page 63 for va li d D Q [1 5: 0] durin g a write operat io n.
3. X = Don’t Care (H or L).
4. RST# must be at VSS ± 0.2 V to mee t the maximum spec ified power-down current.
Intel® Wireless Flash Memory (W 18)
9.0 Bus Operations Overview
Preliminary Datasheet 59
•Read Array: Returns flash array data from the addressed location.
•Read Identifier (ID): Returns manufacturer ID and device ID codes, block lock status, and
protection register data. Read Identifier information can be accessed from any 4-Mbit partition
base address.
•CFI Query: Returns Common Flash Interface (CFI) information. CFI information can be
accessed starting at 4-Mbit partition base addresses.
•Read Status Register: Returns Status Register (SR) data from the addressed partition.
The appropriate CUI command must be written to the partition in order to place it in the desired
read state (see Table 22, “Command Codes and Descriptions” on page 61). Non-array read
operations (Read ID, CFI Query, and Read Status Register) execute as single synchronous or
asynchronous read cycles. WAIT is asserted throughout non-array read operations.
9.1.2 Writes
Device write operations are performed by placing the desired address on A[22:0] and asserting
CE# and WE#. OE# and RST# must be high. Data to be written at the desired address is placed on
DQ[15:0]. ADV# must be held low throughout the write cycle or it can be toggled to latch the
address. If ADV# is held low, the address and data are latched on the rising edge of WE#. CLK is
not used during write operations, and is ignored; it can be either free-running or halted at VIL or
VIH. All write operations are asynchronous.
Table 22, “Command Codes and Descriptions” on page 61 shows the available device commands.
Appendix A, “Write State Machine States” on page 98 provides information on moving between
different device operations by using CUI commands.
9.1.3 Output Disable
When OE# is deasserted, device outputs DQ[15:0] are disabled and placed in a high-impedance
(High-Z) state.
9.1.4 Burst Suspend
The Burst Suspend feature allows the system to temporarily suspend a synchronous-burst read
operation. This can be useful if the system needs to access another device on the same address and
data bus as the flash during a burst-read operation.
Synchronous-burst accesses can be suspended during the initial latency (before data is received) or
after the device has output data. When a burst access is suspended, internal array sensing continues
and any previously latched internal data is retained.
Burst Suspend occurs when CE# is asserted, the current address has been latched (either ADV#
rising edge or valid CLK edge), CLK is halted, and OE# is deasserted. CLK can be halted when it
is at VIH or VIL. To resume the burst access, OE# is reasserted and CLK is restarted. Subsequent
CLK edges resume the burst sequence where it left off.
Within the device, CE# gates WAIT. Therefore, during Burst Suspend WAIT is still driven. This
can cause contention with another device attempting to control the system’s READY signal during
a Burst Suspend. Systems using the Burst Suspend feature should not connect the device’s WAIT
signal directly to the system’s READY signal. Refer to Figure 15, “Burst Suspend” on page 44.
Intel® Wireless Flash Memory (W 18)
9.0 Bus Operatio ns Overview
60 Preliminary Datasheet
9.1.5 Standby
De-asserting CE# deselects the device and places it in standby mode, substantially reducing device
power consumption. In standby mode, outputs are placed in a high-impedance state independent of
OE#. If deselected during a program or erase algorithm, the device shall consume active power
until the program or erase operation completes.
9.1.6 Reset
The device enters a reset mode when RST# is asserted. In reset mode, internal circuitry is turned
off and outputs are placed in a high-impedance state.
After returning from reset, a time tPHQV is required until outputs are valid, and a delay (tPHWV) is
required before a write sequence can be initiated. After this wake-up interval, normal operation is
restored. The device defaults to read-array mode, the Status Register is set to 80h, and the
Configuration Register defaults to asynchronous page-mode reads.
If RST# is asserted during an erase or program operation, the operation aborts and the memory
contents at the aborted block or address are invalid. See Figure 21, “Reset Operations Waveforms”
on page 53 for detailed information regarding reset timings.
Like any automated device, it is important to assert RST# during system reset. When the system
comes out of reset, the processor expects to read from the flash memory array. Automated flash
memories provide status information when read during program or erase operations. If a CPU reset
occurs with no flash memory reset, proper CPU initialization may not occur because the flash
memory may be providing status information instead of array data. Intel flash memories allow
proper CPU initialization following a system reset through the use of the RST# input. In this
application, RST# is controlled by the same CPU reset signal.
9.2 Device Commands
The device’s on-chip WSM manages erase and program algorithms. This local CPU (WSM)
controls the device’ s in-system read, program, and erase operations. Bus cycles to or from the flash
memory conform to standard microprocessor bus cycles. RST#, CE#, OE#, WE#, and ADV#
control signals dictate data flow into and out of the device. WAIT informs the CPU of valid data
during burst reads. Table 21, “Bus Operations Summary” on page 58 summarizes bus operations.
Device operations are selected by writing specific commands into the device’s CUI. Table 22,
“Command Codes and Descriptions” on page 61 lists all possible command codes and
descriptions. Table 23, “Bus Cycle Definitions” on page 63 lists command definitions. Because
commands are partition-specific, it is important to issue write commands within the target address
range.
Intel® Wireless Flash Memory (W 18)
9.0 Bus Operations Overview
Preliminary Datasheet 61
Table 22. Comman d Codes and Descriptions (Sheet 1 of 2)
Operation Code Device
Command Description
Read
FFh Read Arr ay Places selected partition in Read Array mode.
70h Read Status
Register
Pla c es selected partition in Status Register read mode. Aft er issuing t h is
command, reading from the partition outputs SR data on DQ[15:0]. A partition
automatically enters this mode after issuing the Program or Erase comma nd.
90h Rea d Id en ti fi er Places the selected part ition in Read ID mode. Device reads from partition
address es ou tp ut manu fa ctur er/ dev ic e cod es, C onfig ur at ion R eg ister da ta , bl oc k
lock status, or protection r egister data on DQ[15:0].
98h CFI Que r y Puts the addressed partition in CFI Query mode. Device reads from the partiti on
addr esses output CFI information on DQ[7:0 ].
50h Clear Status
Register
The WSM can set the Status Register’s block lock (SR[1]), VPP (SR[3]), program
(SR[4]), and erase (SR[5]) status bit s, but it cannot clear them. SR[5:3,1] can
only be cleared by a device reset or through the Cl ear Status Register command.
Program
40h Word Pr ogram
Setup
This preferred program command’s first cycle prepares the CUI for a progr am
oper ation. The second cycle latches address and data, and executes the WSM
pro gram algorithm at this location. Status re gister upda tes occur when C E# or
OE# is toggled. A Read Arra y command is required to read array data after
programming.
10h Alternate Setup Equivalent to a Program Setup command (40h).
30h EFP Setup
This program command activates EFP mode . The first wr ite cycle sets up the
command. If the second cycle is an EFP Con firm command (D0h), subsequent
writes provide program data. All other commands are ignore d after EFP mode
begins.
D0h EFP Confirm If th e fi r st command w as EFP Set up (30 h) , t he CUI l at ch es th e a ddre ss and dat a,
and pr epares th e device for E FP mode.
Erase
20h Erase Setup
This comman d prepares the CUI for Block Erase. The device erases the block
addressed by the Erase Co nfirm command. If the next command is not Erase
Confirm, the CUI sets Status Register bits SR[5:4] to indicate command
sequence error and places the partition in the read Status Regist er mode.
D0h Erase Confirm
If the first command was Erase Setup (20h), the CUI la tches address and data,
and erases the block indicated by the erase confirm cycle address. During
pro gram or erase, t he partition responds only to R ead Status Register , Program
Suspend, and Erase Suspend command s. CE# or O E# tog gle updates Sta tus
Register data.
Suspend B0h Program
Suspend or
Erase Suspend
This command, issued at any device address, suspends the currently executing
program or erase ope ration. Status register data indi cates the operation was
successfully suspended if SR[2] (program suspend) or SR[6] (erase suspend)
and SR[ 7] are set. The WSM remains in the su spended state re gardless of
cont rol signal states (except RST#).
D0h Suspend
Resume This command, issued at any device address, resumes the suspended program
or erase operation.
Intel® Wireless Flash Memory (W 18)
9.0 Bus Operatio ns Overview
62 Preliminary Datasheet
Block Locking
60h Lock Setup This command prepares the CUI loc k c onfigura tion. If th e next command is not
Lock Block, Unlock Bloc k, or Lock- Down, the CUI sets SR[5:4] to indicate
command sequence error.
01h Lock Block If the previous command was Lock Setup (60h), the CUI locks the addressed
block.
D0h Unlock Block If the p re vi ous comma nd w as Loc k Set up (60 h) , th e C UI l atche s t he a ddre ss an d
unlocks the addressed block. If previously locked-down, the operation has no
effect.
2Fh Lock-Down If the pre vi ous comma nd w as Loc k Set up (60 h) , th e C UI l atche s t he a ddre ss an d
locks- down the addressed block.
Protection C0h Protection
Program
Setup
This command prepares the CUI for a protection register program operation. The
second cycl e latch es add re ss and dat a, and star t s the WSM’ s pr otec ti on regi st er
program or lock algorithm. Toggling CE# or OE# updates the flash Status
Register data. To read array data after prog ramming, iss ue a Read Array
command.
Configuration
60h Configuration
Setup
This command prep ares the CUI for device configuration. If Set Configuration
Register is not the next command, the CUI sets SR[5:4] to indicate command
sequence error.
03h Set
Configuration
Register
If the previous command was Configuration Setup (60h), the CUI latches the
addre ss and writes the data from A[15:0] into the configuration register.
Subsequent read operations access array data.
Note: Do not use unassigned commands. Intel reserves the righ t to redefi ne these codes for future fu nctions.
Table 22. Command Codes and Descriptio ns (Sheet 2 of 2)
Operation Code Device
Command Description
Intel® Wireless Flash Memory (W 18)
9.0 Bus Operations Overview
Preliminary Datasheet 63
Table 23. Bus Cycle Definitions
Operation Command Bus
Cycles
First Bus Cycle Second Bus Cycle
Oper Addr1Data2,3 Oper Addr1Data2,3
Read
Read Array/Reset ≥1WritePnA FFhRead
Read
Address Array
Data
Rea d Id en ti fie r ≥ 2 Write PnA 90h Read PBA+IA IC
CFI Query ≥ 2 Write PnA 98h Read PBA+QA QD
Rea d Status Re gister 2 Write PnA 70h Re ad Pn A SRD
Clear St a tu s R e gi ster 1 Wr ite XX 50h
Program
and
Erase
Bloc k Er ase 2 Wr ite BA 20h W rite BA D0h
Word Program 2 Write WA 40h/10h Write WA WD
EFP >2 Write WA 30h Write WA D0h
Program/Erase Suspend 1 Write XX B0h
Program/Erase Resume 1 Write XX D0h
Lock
Lock Block 2 Write BA 60h Writ e BA 01h
Unlock Block 2 Write BA 60h Write BA D0h
Lock-Down Block 2 Write BA 60h Write BA 2Fh
Protection
Protection Program 2 Write PA C0h Write PA PD
Lock Protection Program 2 Write LPA C0h Write LPA FFFDh
Configuration Set Co nf ig urati o n Reg i ster 2 Write CD 60h Write CD 03h
Notes:
1. First-cy cle comma nd addres ses shou ld be th e same as t he operat ion’ s ta rget add ress. Ex amples: the fir st-cyc le addre ss
for the Read Identifier command should be the same a s the Identification code ad dress (IA); the first -cycle address for
the W ord Program command should be the same as the word address (WA) to be programmed; the first-cyc le address
for the Erase/Program Suspend command should be the same as the address within the block to be suspended; et c.
XX = Any valid address within the device.
IA = Identification code address.
BA = Block A ddress. Any address within a specific block.
LPA = Lock Protectio n Address is obtained from the CFI (through th e CFI Qu ery command). The Intel Wireless Flash
Memory family’s LPA is at 0080h.
PA = User programmable 4-word protection address.
PnA = Any address within a specific p artition.
PBA = Par tition Bas e Address. The very first address of a particul ar partition.
QA = CF I code address.
W A = Word address of memory location t o be written.
2. SRD = Stat us register data.
WD = D a ta to be writte n at location WA.
IC = Iden ti fi er code data.
PD = User programma ble 4-word protection dat a.
QD = Query code data on DQ[7:0].
CD = Co nfiguration register code data presented on device addresses A[15:0]. A[MAX:16] address bits can select any
partition. Se e Ta b le 31, “Read Co nf igura ti o n R eg is ter De sc r i pt ions” on page 89 for Configuration Register bits
descriptions.
3. Commands other than those shown above are reserved by Intel for future device impl ementations and shou ld not be
used.
Intel® Wireless Flash Memory (W 18)
9.0 Bus Operatio ns Overview
64 Preliminary Datasheet
9.3 Command Sequencing
When issuing a 2-cycle write sequence to the flash device, a read operation is allowed to occur
between the two write cycles. The setup phase of a 2-cycle write sequence places the addressed
partition into read-status mode, so if the same partition is read before the second “confirm” write
cycle is issued, Status Register data will be returned. Reads from other partitions, however, can
return actual array data assuming the addressed partition is already in read-array mode. Figure 25
on page 64 and Figure 26 on page 64 illustrate these two conditions.
By contrast, a write bus cycle may not interrupt a 2-cycle write sequence. Doing so causes a
command sequence error to appear in the Status Register. Figure 27 illustrates a command
sequence error.
Figure 25. Normal Write and Read Cycles
Figure 26. Interleaving a 2-Cycle Write Sequence with an Array Read
Partition A Partition A Partition A
20h D0h FFh
Bloc k Erase Setup Bloc k Erase C onfirm Read A rray
A
ddre ss [A ]
WE# [W]
OE# [G]
Da t a [Q ]
Parti ti on B Partition A Parti ti on B Partition A
FFh 20h
A
rray D at
a
D0h
Read Array Era s e Setup Bus Read Eras e C onfirm
A
ddr ess [A]
WE# [W]
OE# [ G]
Data [Q]
Figure 27. Improper Comma nd Sequencing
Partiti on X Partition Y Partition X Partiti on X
20h FFh D0h S R Data
Address [A]
WE# [W]
OE# [G]
Da ta [D/Q]
Intel® Wireless Flash Memory (W 18)
10.0 Read Operations
Preliminary Datasheet 65
10.0 Read Opera ti ons
The device supports two read modes - asynchronous page and synchronous burst mode.
Asynchronous page mode is the default read mode after device power-up or a reset. The Read
Configuration Register (RCR) must be configured to enable synchronous burst reads of the flash
memory array (see Section 14.0, “Set Read Configuration Register” on page 89).
Each partition of the device can be in any of four read states: Read Array, Read Identifier, Read
Status or CFI Query . Upon power-up, or after a reset, all partitions of the device default to the Read
Array state. To change a partition’s read state, the appropriate read command must be w ritten to the
device (see Section 9.2, “Device Commands” on page 60).
The following sections describe device read modes and read states in detail.
10.1 Asynchronous Page Read Mode
Following a device power-up or reset, asynchronous page mode is the default read mode and all
partitions are set to Read Array. However, to perform array reads after any other device operation
(e.g. write operation), the Read Array command must be issued in order to read from the flash
memory array.
Note: Asynchronous page-mode reads can only be performed when Read Configuration Register bit
RCR[15] is set (see Section 14.0, “Set Read Configuration Register” on page 89).
To perform an asynchronous page mode read, an address is driven onto A[MAX:0], and CE#, OE#
and ADV# are asserted. WE# and RST# must be deasserted. WAIT is asserted during
asynchronous page mode. ADV# can be driven high to latch the address, or it must be held low
throughout the read cycle. CLK is not used for asynchronous page-mode reads, and is ignored. If
only asynchronous reads are to be performed, CLK should be tied to a valid VIH level, WAIT
signal can be floated and ADV# must be tied to ground. Array data is driven onto DQ[15:0] after
an initial access time tAVQV delay. (see Section 7.0, “AC Characteristics” on page 31).
In asynchronous page mode, four data words are “sensed” simultaneously from the flash memory
array and loaded into an internal page buffer. The buffer word corresponding to the initial address
on A[MAX:0] is driven onto DQ[15:0] after the initial access delay . Address bits A[MAX:2] select
the 4-word page. Address bits A[1:0] determine which word of the 4-word page is output from the
data buffer at any given time.
10.2 Synchronous Burst Read Mode
Section 14.0, “Set Read Configuration Register” on page 89continuous wordsTo perform a
synchronous burst- read, an initial address is driven onto A[MAX:0], and CE# and OE# are
asserted. WE# and RST# must be deasserted. ADV# is asserted, and then deasserted to latch the
address. Alternately, ADV# can remain asserted throughout the burst access, in which case the
address is latched on the next valid CLK edge after ADV# is asserted.
Intel® Wireless Flash Memory (W 18)
10.0 Read Operations
66 Preliminary Datasheet
During synchronous array and non-array read modes, the first word is output from the data buffer
on the next valid CLK edge after the initial access latency delay (see Section 14.2, “First Access
Latency Count (RCR[13:11])” on page 91). Subsequent data is output on valid CLK edges
following a minimum delay. However, for a synchronous non-array read, the same word of data
will be output on successive clock edges until the burst length requirements are satisfied.
Section 7.0, “AC Characteristics” on page 31
10.3 Read Array
The Read Array command places (or resets) the partition in read-array mode and is used to read
data from the flash memory array. Upon initial device power-up, or after reset (RST# transitions
from VIL to VIH), all partitions default to asynchronous read-array mode. To read array data from
the flash device, first write the Read Array command (FFh) to the CUI and specify the desired
word address. Then read from that address. If a partition is already in read-array mode, issuing the
Read Array command is not required to read from that partition.
If the Read Array command is written to a partition that is erasing or programming, the device
presents invalid data on the bus until the program or erase operation completes. After the program
or erase finishes in that partition, valid array data can then be read. If an Erase Suspend or Program
Suspend command suspends the WSM, a subsequent Read Array command places the addressed
partition in read-array mode. The Read Array command functions independently of VPP.
10.4 Read Identifier
The Read Identifier mode outputs the manufacturer/device identifier, block lock status, protection
register codes, and Configuration Register data. The identifier information is contained within a
separate memory space on the device and can be accessed along the 4-Mbit partition address range
supplied by the Read Identifier command (90h) address. Reads from addresses in Table 24 retrieve
ID information. Issuing a Read Identifier command to a partition that is programming or erasing
places that partition’s outputs in read ID mode while the partition continues to program or erase in
the background.
Table 24. Device Identification Codes (Sheet 1 of 2)
Item Address1
Data Description
Base Offset
Manufacturer ID Partition 00h 0089h Intel
Devic e ID Partition 01h
8862h 32-Mbit TPD
8863h 32-M bit BPD
8864h 64-Mbit TPD
8865h 64-M bit BPD
8866h 128-Mbit TPD
8867h 128-Mbit BPD
Block Lock Status(2) Block 02h D0 = 0 Block is unlocked
D0 = 1 Block is locked
Intel® Wireless Flash Memory (W 18)
10.0 Read Operations
Preliminary Datasheet 67
10.5 CFI Query
This device contains a separate CFI query database that acts as an “on-chip datasheet.” The CFI
information within this device can be accessed by issuing the Read Query command and supplying
a specific address. The address is constructed from the base address of a partition plus a particular
offset corresponding to the desired CFI field. Appendix B, “Common Flash Interface (CFI)” on
page 101 shows accessible CFI fields and their address offsets.
Issuing the Read Query command to a partition that is programming or erasing puts that partition in
read query mode while the partition continues to program or erase in the background.
10.6 Read Status Register
The device’s Status Register displays program and erase operation status. A partition’s status can
be read after writing the Read Status Register command to any location within the partition’s
address range. Read-status mode is the default read mode following a Program, Erase, or Lock
Block command sequence. Subsequent single reads from that partition will return its status until
another valid command is written.
The read-status mode supports single synchronous and single asynchronous reads only; it doesn’t
support burst reads. The first falling edge of OE# or CE# latches and updates Status Register data.
The operation doesn’t affect other partitions’ modes. Because the Status Register is 8 bits wide,
only DQ [7:0] contains valid Status Register data; DQ [15:8] contains zeros. See Table 25, “Status
Register Definitions” on page 68 and Table 26, “Status Register Descriptions” on page 68.
Each 4-Mbit partition contains its own Status Register. Bits SR[6:0] are unique to each partition,
but SR[7], the Device WSM Status (DWS) bit, pertains to the entire device. SR[7] provides
program and erase status of the entire device. By contrast, the Partition WSM Status (PWS) bit,
SR[0], provides program and erase status of the addressed partition only. Status register bits
SR[6:1] present information about partition-specific program, erase, suspend, VPP, and block-lock
states. Table 27, “S tatus Register Device WSM and Partition W r ite Status Description” on page 68
presents descriptions of DWS (SR[7]) and PWS (SR[0]) combinations.
Block Lock-Down Status(2) Block 02h D1 = 0 Block is not locked-down
D1 = 1 Block is locked down
Configurat io n R e gi st er P a rt it io n 05h R e gi s te r Data
Protection Regi ster Lock Status Part ition 80h Lock Da ta
Protection Register Partition 81h - 88h Register Data Multiple reads required to read
the entire 128-bit Protection
Register.
Notes:
1. The addr ess is constructed from a base address plus an offset. For example, to read the Block Lock
Status for block number 38 in a BPD, set the address to the BBA ( 0F8000h) pl us the offset (02h), i.e.
0F8002h. Then examine bit 0 of th e data to determine if the block is locked.
2. See Section 13.1.4, “Block Lock Status” on page 84 for valid lock status.
Table 24. D e vice Identification Codes (Sheet 2 of 2)
Item Address1
Data Description
Base Offset
Intel® Wireless Flash Memory (W 18)
10.0 Read Operations
68 Preliminary Datasheet
Table 25. Status Register Definitions
DWS ESS ES PS VPPS PSS DPS PWS
76543210
Table 26. Status Register Descriptions
Bit Name State Description
7DWS
Device WSM Status 0 = Device WSM is Busy
1 = Device WSM is Ready
SR[7] indicates erase or program completion in the
device. SR[6:1] are i nvalid while SR[7 ] = 0. See Table
27 for valid SR[7] and SR[0] combinations.
6ESS
Erase Suspend Status 0 = Erase in progress/completed
1 = Erase suspended
After issuing an Erase Suspend command, the WSM
halts and sets SR[7] and SR[6]. SR[6] remains set until
the de vice receive s an Erase Resume command.
5ES
Erase Status 0 = Erase successful
1 = Erase error SR[5] is set if an attempted erase failed. A Command
Sequ ence Error is indicated when SR[7,5:4] are set.
4PS
Program Status 0 = Program successful
1 = Program error SR[4] is set if the WSM failed to program a word.
3VPPS
VPP Status 0 = VPP OK
1 = VPP low detect, operation aborted
The WS M indicates the VPP level aft er progr a m or
erase completes. SR[3] does not provide continuous
VPP feed ba ck and is n’t gu ar an teed w hen VPP ≠ VPP1/2.
2PSS
Program Suspend
Status
0 = Program in progress/completed
1 = Pr ogram suspende d
After receiving a Program Suspend command, the
WSM halts execution and sets SR[7] and SR[2]. They
remain set until a Resume command is received.
1DPS
Device Protect Status
0 = Unlocked
1 = Aborted erase/program attempt on
lock e d bl oc k
If an erase or program operation is attempted to a
locked block (if WP# = VIL), the WSM sets SR[1] and
abor ts the operation.
0PWS
Par t it ion Write Status
0 = This partition is busy, but only if
SR[7]=0
1 = Another partition is busy, but only if
SR[7]=0
Addres sed p arti t ion is er asi ng or pr ogr ammi ng. I n E FP
mode, SR[0] indic ates th at a data-stream word has
fini shed programming or verif y ing depending on the
part ic ul ar EFP ph ase . See Table 27 for valid SR[7] and
SR[0] combinations.
Table 27. Status Register Device WSM and Partition Write Status Description
DWS
(SR[7]) PWS
(SR[0]) Description
00
The addressed partition is performing a program/erase operation.
EFP: device has fi nished programming or verifying data, or is ready for data.
01
A pa rtition other than the one currently address ed is performing a pr ogram/erase operation.
EFP: the device is either programming or verif y ing data.
10
No program/erase operation is in progress in any partition. Erase and Program suspend bits (SR[6,2])
indicate whether other partitions are suspended.
EFP: the device has exi ted EFP mode.
11
Wo n’t occur in standard program or erase modes.
EFP : this co m bi n atio n do e s no t oc c ur.
Intel® Wireless Flash Memory (W 18)
10.0 Read Operations
Preliminary Datasheet 69
10.7 Clear Status Register
The Clear Status Register command clears the Status Register and leaves all partition output states
unchanged. The WSM can set all Status Register bits and clear bits SR[7:6,2,0]. Because bits
SR[5,4,3,1] indicate various error conditions, they can only be cleared by the Clear Status Register
command. By allowing system software to reset these bits, several operations (such as
cumulatively programming several addresses or erasing multiple blocks in sequence) can be
performed before reading the Status Register to determine error occurrence. If an error is detected,
the Status Register must be cleared before beginning another command or sequence. Device reset
(RST# = VIL) also clears the Status Register. This command functions independently of VPP.
Intel® Wireless Flash Memory (W 18)
11.0 Program Operations
70 Preliminary Datasheet
11 .0 Program Operations
11.1 Word Program
When the Word Program command is issued, the WSM executes a sequence of internally timed
events to program a word at the desired address and verify that the bits are sufficiently
programmed. Programming the flash array changes specifically addressed bits to 0; 1 bits do not
change the memory cell contents.
Programming can occur in only one partition at a time. All other partitions must be in either a read
mode or erase suspend mode. Only one partition can be in erase suspend mode at a time.
The Status Register can be examined for program progress by reading any address within the
partition that is busy programming. However, while most S tatus Register bits are partition-specific,
the Device WSM Status bit, SR[7], is device-specific; that is, if the Status Register is read from any
other partition, SR[7] indicates program status of the entire device. This permits the system CPU to
monitor program progress while reading the status of other partitions.
CE# or OE# toggle (during polling) updates the Status Register. Several commands can be issued
to a partition that is programming: Read Status Register, Program Suspend, Read Identifier, and
Read Query. The Read Array command can also be issued, but the read data is indeterminate.
After programming completes, three Status Register bits can signify various possible error
conditions. SR[4] indicates a program failure if set. If SR[3] is set, the WSM couldn’t execute the
Word Program command because VPP was outside acceptable limits. If SR[1] is set, the program
was aborted because the WSM attempted to program a locked block.
After the Status Register data is examined, clear it with the Clear Status Register command before
a new command is issued. The partition remains in S tatus Register mode until another command is
written to that partition. Any command can be issued after the Status Register indicates program
completion.
If CE# is deasserted while the device is programming, the devices will not enter standby mode until
the program operation completes.
Intel® Wireless Flash Memory (W 18)
11.0 Program Operations
Preliminary Datasheet 71
11.2 Factory Programming
The standard factory programming mode uses the same commands and algorithm as the Word
Program mode (40h/10h). When VPP is at VPP1, program and erase currents are drawn through
VCC. If VPP is driven by a logic signal, VPP1 must remain above the VPP1Min value to perform in-
system flash modifications. When VPP is connected to a 12 V power supply, the device draws
program and erase current directly from VPP. This eliminates the need for an external switching
transistor to control the VPP voltage. Figure 37, “Examples of VPP Power Supply Configurations”
on page 88 shows examples of flash power supply usage in various configurations.
Figure 28. Word Program Flowchart
Suspend
Program
Loop
Start
Writ e 40 h,
Word Address
Write Data
Word Address
Read Status
Register
SR[7] =
Fu ll Progra m
Status Check
(if des ire d)
Program
Complete
FUL L PROGRAM ST ATUS CHECK PROCEDURE
Suspend
Program
Read Status
Register
Program
Successful
SR[3] =
SR[1] =
0
0
SR[4] =
0
1
1
1
1
0
No
Yes
V
PP
Range
Error
Device
Protect Error
Program
Error
WO RD PROGRAM PROCEDURE
SR [3 ] MUST be cleare d before t he WSM w ill allow fur th e r
program attempts
Only the Clear Staus Register command clears SR[4:3 ,1].
If an e rror is detected, clea r t he s tatu s regi s ter before
attempting a program retry or other error recovery .
Standby
Standby
Bus
Operation Command
Check SR[3]
1 = V
PP
error
Check SR[4]
1 = Data program error
Comments
Repeat for subsequent programming operations.
Full sta tus register check c an be done after ea ch prog r am or
after a s equ ence of prog r am op erations.
Comments
Bus
Operation Command
Data = 40h
Ad dr = Location to program (WA)
Write Program
Setup
Data = Data to program (W D)
Ad dr = Location to program (WA)
Write Data
Read SRD
Toggl e C E# or OE# to upd ate SR D
Read
Check SR[7]
1 = WSM ready
0 = WSM busy
Standby
Standby Check SR[1]
1 = Attempted program to locked block
Program aborted
Intel® Wireless Flash Memory (W 18)
11.0 Program Operations
72 Preliminary Datasheet
The 12-V VPP mode enhances programming performance during the short time period typically
found in manufacturing processes; however, it is not intended for extended use.12 V may be
applied to VPP during program and erase operations as specified in Section , “” on page 26. VPP
may be connected to 12 V for a total of tPPH hours maximum. Stressing the device beyond these
limits may cause permanent damage.
11.3 Enhanced Factory Program (EFP)
EFP substantially improves device programming performance through a number of enhancements
to the conventional 12 Volt word program algorithm. EFP's more efficient WSM algorithm
eliminates the traditional overhead delays of the conventional word program mode in both the host
programming system and the flash device. Changes to the conventional word programming
flowchart and internal WSM routine were developed because of today's beat-rate-sensitive
manufacturing environments; a balance between programming speed and cycling performance was
attained.
The host programmer writes data to the device and checks the Status Register to determine when
the data has completed programming. This modification essentially cuts write bus cycles in half.
Following each internal program pulse, the WSM increments the device's address to the next
physical location. Now, programming equipment can sequentially stream program data throughout
an entire block without having to setup and present each new address. In combination, these
enhancements reduce much of the host programmer overhead, enabling more of a data streaming
approach to device programming.
EFP further speeds up programming by performing internal code verification. With this, PROM
programmers can rely on the device to verify that it has been programmed properly. From the
device side, EFP streamlines internal overhead by eliminating the delays previously associated to
switch voltages between programming and verify levels at each memory-word location.
EFP consists of four phases: setup, program, verify and exit. Refer to Figure 29, “Enhanced
Factory Program Flowchart” on page 75 for a detailed graphical representation of how to
implement EFP.
11.3.1 EFP Requirements and Considerations
EFP Requi reme nts
Ambient temperature: TA = 25 °C ± 5 °C
VCC within specified operating range
VPP within specif ied VPP2 range
Target bl ock unlocked
EFP Considerations
Block cycling below 100 er ase cycles 1
RWW not supported2
EFP pr ograms one block at a time
EFP cannot be suspended
Notes:
1. Recommen ded fo r optimu m perfor mance. Some degr adatio n in per forman ce may
occur if this limit is exceed ed, but the in ternal al gorithm will continue to work
properly.
2. Cod e or data can not be read from another partition during EFP.
Intel® Wireless Flash Memory (W 18)
11.0 Program Operations
Preliminary Datasheet 73
11.3.2 Setup
After receiving the EFP Setup (30h) and EFP Confirm (D0h) command sequence, SR[7] transitions
from a 1 to a 0 indicating that the WSM is busy with EFP algorithm startup. A delay before
checking SR[7] is required to allow the WSM time to perform all of its setups and checks (VPP
level and block lock status). If an error is detected, Status Register bits SR[4], SR[3], and/or SR[1]
are set and EFP operation terminates.
Note: After the EFP Setup and Confirm command sequence, reads from the device automatically output
Status Register data. Do not issue the Read Status Register command; it will be interpreted as data
to program at WA0.
11.3.3 Program
After setup completion, the host programming system must check SR[0] to determine “data-stream
ready" status (SR[0]=0). Each subsequent write after this is a program-data write to the flash array .
Each cell within the memory word to be programmed to 0 receives one WSM pulse; additional
pulses, if required, occur in the verify phase. SR[0]=1 indicates that the WSM is busy applying the
program pulse.
The host programmer must poll the device's Status Register for the "program done" state after each
data-stream write. SR[0]=0 indicates that the appropriate cell(s) within the accessed memory
location have received their single WSM program pulse, and that the device is now ready for the
next word. Although the host may check full status for errors at any time, it is only necessary on a
block basis, after EFP exit.
Addresses must remain within the target block. Supplying an address outside the target block
immediately terminates the program phase; the WSM then enters the EFP verify phase.
The address can either hold constant or it can increment. The device compares the incoming
address to that stored from the setup phase (WA0); if they match, the WSM programs the new data
word at the next sequential memory location. If they differ, the WSM jumps to the new address
location.
The program phase concludes when the host programming system writes to a different block
address, and data supplied must be FFFFh. Upon program phase completion, the device enters the
EFP verify phase.
11.3.4 Verify
A high percentage of the flash bits program on the first WSM pulse. However, for those cells that
do not completely program on their first attempt, EFP internal verification identifies them and
applies additional pulses as required.
The verify phase is identical in flow to the program phase, except that instead of programming
incoming data, the WSM compares the verify-stream data to that which was previously
programmed into the block. If the data compares correctly, the host programmer proceeds to the
next word. If not, the host waits while the WSM applies an additional pulse(s).
The host programmer must reset its initial verify-word address to the same starting location
supplied during the program phase. It then reissues each data word in the same order as during the
program phase. Like programming, the host may write each subsequent data word to WA0 or it may
increment up through the block addresses.
Intel® Wireless Flash Memory (W 18)
11.0 Program Operations
74 Preliminary Datasheet
The verification phase concludes when the interfacing programmer writes to a different block
address; data supplied must be FFFFh. Upon completion of the verify phase, the device enters the
EFP exit phase.
11.3.5 Exit
SR[7]=1 indicates that the device has returned to normal operating conditions. A full status check
should be performed at this time to ensure the entire block programmed successfully. After EFP
exit, any valid CUI command can be issued.
Intel® Wireless Flash Memory (W 18)
11.0 Program Operations
Preliminary Datasheet 75
Figure 29. Enhanced Factory Program Flowchart
EFP Setup EFP Program EFP Verify
EFP Exit
1. WA
0
= fi r st Word Address to be programmed within the target block. The BBA (Block Base
Addr ess) must r em ain constant throughout t he program phase data st ream; WA can be held
constant at the first address location, or it can be written to sequence up thr ough the addresses
wit hin the block. Writi ng to a BBA not equal to that of the block currently being writt en to
termina tes the EFP p rogr am phase, and instructs the device to ent er the EFP verify phase.
2. For proper ver if ication to occur, the verify data stream must be presented to the device in the
same sequence as that of the progr am phase dat a stream. Wr iting to a BBA not equal to WA
termina tes the EFP v erify phase, and instructs the device to exit EFP.
3. Bits that did not fully prog ram with the single WSM pul se of the EFP program phase receive
additio nal program-pulse attempts duri ng the EFP verify phase. The device will report any
program failure by setti ng SR[ 4]=1; thi s check can be per f ormed during the full status check after
EFP has been exited for that block, and will indi cate any error within t he entire data str eam.
Comments
Bus
State
Repeat for subsequent oper ations.
After EFP exit, a Full Status Check can
determine if any program er ror occurred.
See the Full Status Check procedure in the
Word Prog ram flowchart .
Write
Standby
Read
Write
Write
(note 2)
Read
Standby
Write
Read
Standby
EFP
Setup
Program
Done?
Exit
Program
Phase
Last
Data?
Exit
Verify
Phase
EFP
Exited?
Write EFP
Confirm
Read
Standby EFP
Setup
Done?
Read
Standby Verify
Stream
Ready?
Write Unlock
Block
Write
(note 1)
Standby Last
Data?
Standby
(note 3) Verify
Done?
S R [0]= 1 = N
Write Data
Addr ess = WA
0
Last
Data?
Wr it e FFFFh
Address
≠
BBA
Program
Done?
Read
Stat us Register
SR[0]=0=Y
Y
S R [0]= 1 = N
N
Write Data
Addr ess = WA
0
Verify
Done?
Last
Data?
Read
S t atu s Regi st er
Wr it e FFFFh
Address
≠
BBA
Y
Ve rify Strea m
Ready?
Read
S t atu s Regi st er
SR[7]=0=N
Full Sta t us Check
Procedure
Operation
Complete
Read
Statu s Regi st er
EFP
Exited?
SR[7]=1=Y
SR[0]=1=N
Start
Write 30h
Addr ess = WA
0
V
PP
= 12V
Unlock Block
Write D0h
Addr ess = WA
0
EFP Setup
Done?
Read
Status Register
SR[7]=1=N
Exit
N
EFP Program EFP Verify EFP ExitEFP Setup
ENHANCED FACTORY PROGRAMMING PROCEDURE
Comments
Bus
State
Data = 30h
Addr ess = WA
0
Data = D0h
Addr ess = WA
0
Status R eg ister
Check SR [ 7 ]
0 = EFP ready
1 = EFP not ready
V
PP
= 12V
Unlock block
Check SR [ 0]
0 = Program done
1 = Program not done
Status Register
Data = FFFFh
Addressnot within same
BBA
Data = Data to program
Addr ess = WA
0
Device automat ically
increments address.
Comments
Bus
State
Data = Word to verify
Address = WA
0
S t at us Regi ster
Device autom atically
increment s addr ess.
Data = FFFFh
Addressnot within same
BBA
S t at us Regi ster
Check SR[ 0]
0 = Ready f or ver if y
1 = Not ready for verify
Check SR[ 0]
0 = Verify done
1 = Verify not done
S t at us Regi ster
Check SR[ 7]
0 = Exit not fi nished
1 = Exit com pleted
Check V
PP
& Lock
errors (SR[3,1])
Data Stream
Ready?
Read
Stat us Register
SR[0] =0=Y
S R [7 ]= 0 = Y
SR[0]=1=N
Standby
Read
Data
Stream
Ready?
Check SR [ 0]
0 = Ready for data
1 = Not ready for data
Status Register
SR[0]=0=Y
SR[0] =0=Y
EFP setup ti me
Standby EFP setup time
Standby Error
Condition
Check
If SR[7] = 1:
Check SR[3,1]
SR[3] = 1 = V
PP
error
SR[1] = 1 = locked block
Intel® Wireless Flash Memory (W 18)
12.0 Program and Erase Operations
76 Preliminary Datasheet
12.0 Program and E rase Operat ions
12.1 Program/Erase Suspend and Resume
The Program Suspend and Erase Suspend commands halt an in-progress program or erase
operation. The command can be issued at any device address. The partition corresponding to the
command’s address remains in its previous state. A suspend command allows data to be accessed
from memory locations other than the one being programmed or the block being erased.
A program operation can be suspended only to perform a read operation. An erase operation can be
suspended to perform either a program or a read operation within any block, except the block that
is erase suspended. A program command nested within a suspended erase can subsequently be
suspended to read yet another location. Once a program or erase process starts, the Suspend
command requests that the WSM suspend the program or erase sequence at predetermined points
in the algorithm. The partition that is actually suspended continues to output Status Register data
after the Suspend command is written. An operation is suspended when status bits SR[7] and SR[6]
and/or SR[2] are set.
To read data from blocks within the partition (other than an erase-suspended block), you can write
a Read Array command. Block erase cannot resume until the program operations initiated during
erase suspend are complete. Read Array, Read Status Register, Read Identifier (ID), Read Query,
and Program Resume are valid commands during Program or Erase Suspend. Additionally, Clear
Status Register, Program, Program Suspend, Erase Resume, Lock Block, Unlock Block, and Lock-
Down Block are valid commands during erase suspend.
To read data from a block in a partition that is not programming or erasing, the operation does not
need to be suspended. If the other partition is already in Read Array, ID, or Query mode, issuing a
valid address returns corresponding data. If the other partition is not in a read mode, one of the read
commands must be issued to the partition before data can be read.
During a suspend, CE# = VIH places the device in standby state, which reduces active current. VPP
must remain at its program level and WP# must remain unchanged while in suspend mode.
A resume command instructs the WSM to continue programming or erasing and clears Status
Register bits SR[2] (or SR[6]) and SR[7]. The Resume command can be written to any partition.
When read at the partition that is programming or erasing, the device outputs data corresponding to
the partition’s last mode. If Status Register error bits are set, the Status Register can be cleared
before issuing the next instruction. RST# must remain at VIH. See Figure 30, “Program Suspend /
Resume Flowchart” on page 77, and Figure 31, “Erase Suspend / Resume Flowchart” on page 78.
If a suspended partition was placed in Read Array, Read S tatus Register , ID, or Query mode during
the suspend, the device remains in that mode and outputs data corresponding to that mode after the
program or erase operation is resumed. After resuming a suspended operation, issue the read
command appropriate to the read operation. To read status after resuming a suspended operation,
issue a Read Status Register command (70h) to return the suspended partition to status mode.
Intel® Wireless Flash Memory (W 18)
12.0 Program and Erase Operations
Preliminary Datasheet 77
Figure 30. Program Suspend / Resume Flowchart
Read Status
Register
SR.7 =
SR.2 =
Write FFh
Su s p Part it ion
Read Array
Data
Program
Completed
Done
Reading
Write FFh
Pgm'd Partition
Write D0h
Any Address
Program
Resumed Read Array
Data
0
No
0
Yes
1
1
PROGRAM SUSPEND / RESUME PROCEDURE
Write Program
Resume Dat a = D0h
Addr = Suspen ded block (BA)
Bus
Operation Command Comments
Write Program
Suspend Data = B0h
Addr = Block to suspend (BA)
Standby Ch eck SR.7
1 = WSM ready
0 = WSM busy
Standby Ch eck SR.2
1 = Program suspended
0 = Program completed
Write Read
Array
Dat a = FF h
Addr = Any address within the
suspended partition
Read Read arra y data from b lock other than
the one being programmed
Read
Status register data
Toggle CE# or OE# to update Status
register
Addr = Suspen ded block (BA)
PGM_SUS.WMF
Start
Write B0h
Any Address
Program S uspend
Read Status
Program Resume Read Array
R ead Array
Write 70h
Sa me Part ition
Write Read
Status Dat a = 7 0h
Addr = Same partition
If the suspended partition was placed in Read Array mode:
Write Read
Status
Return partition to Status mode:
Dat a = 7 0h
Addr = Same partition
Write 70h
Sa me Part ition
Read Status
Intel® Wireless Flash Memory (W 18)
12.0 Program and Erase Operations
78 Preliminary Datasheet
12.2 Block Erase
The 2-cycle block erase command sequence, consisting of Erase Setup (20h) and Erase Confirm
(D0h), initiates one block erase at the addressed block. Only one partition can be in an erase mode
at a time; other partitions must be in a read mode. The Erase Confirm command internally latches
the address of the block to be erased. Erase forces all bits within the block to 1. SR[7] is cleared
while the erase executes.
Figure 31. Erase Suspend / Resume Flowchart
Erase
Completed
Write FFh
Erased Partit ion
Read Array
Data
0
0
No
Read
1
Program
Program
Loop
Read Array
Data
1
Yes
Start
Write B0h
Any A ddress
Read Status
Register
SR.7 =
SR.6 =
Wri t e D0 h
Any A ddress
Erase Resumed
Read or
Program?
Done?
Write
Write
Standby
Standby
Write
Erase
Suspend
Read Array
or Program
Program
Resume
Data = B0h
Addr = Any address
Data = FFh or 40h
Addr = Block to program or read
Check SR.7
1 = WSM ready
0 = WSM busy
Check SR.6
1 = E rase suspended
0 = E rase completed
Data = D0h
Addr = Any address
Bus
Operation Command Comments
Read Status register data. Toggle CE# or
OE# to update Status register
Addr = Same partition
Read or
Write Read array or program data from/to
block other than the one being erased
ERASE SUSPEND / RESUME PROCEDURE
ERAS_SUS.WMF
Writ e 70h
Sa me Par t it ion
Write Read
Status Data = 70h
Addr = Same partition
Erase Resume
Erase S uspen d
Re ad St at us
Re ad Ar ray
Writ e 70h
Sa me Par t it ion
Re ad St at us
If the suspended parti ti on was placed in
Read Array mode or a Program Loop:
Write Read
Status
Return partition to Status mode:
Data = 70h
Addr = Same partition
Intel® Wireless Flash Memory (W 18)
12.0 Program and Erase Operations
Preliminary Datasheet 79
After writing the Erase Confirm command, the selected partition is placed in read Status Register
mode and reads performed to that partition return the current status data. The address given during
the Erase Confirm command does not need to be the same address used in the Erase Setup
command. So, if the Erase Confirm command is given to partition B, then the selected block in
partition B will be erased even if the Erase Setup command was to partition A.
The 2-cycle erase sequence cannot be interrupted with a bus write operation. For example, an Erase
Setup command must be immediately followed by the Erase Confirm command in order to e xecute
properly. If a different command is issued between the setup and confirm commands, the partition
is placed in read-status mode, the Status Register signals a command sequence error, and all
subsequent erase commands to that partition are ignored until the Status Register is cleared.
The CPU can detect block erase completion by analyzing SR[7] of that partition. If an error bit
(SR[5,3,1]) was flagged, the Status Register can be cleared by issuing the Clear Status Register
command before attempting the next operation. The partition remains in read-status mode until
another command is written to its CUI. Any CUI instruction can follow after erasing completes.
The CUI can be set to read-array mode to prevent inadvertent Status Register reads.
Intel® Wireless Flash Memory (W 18)
12.0 Program and Erase Operations
80 Preliminary Datasheet
12.3 Read-While-Write and Read-While-Erase
The Intel® Wireless Flash Memory (W18) supports flexible multi-partition dual-operation
architecture. By dividing the flash memory into many separate partitions, the device can read from
one partition while programing or erasing in another partition; hence the terms, RWW and RWE.
Both of these features greatly enhance data storage performance.
Figure 32. Block Erase Flowchart
SR[3,1]
must
be cleared before the WSM will allow further
erase attempt s.
Only the Clear Status Register command clears SR[5:3,1].
If an error is det ec ted, clea r the S tat us register before
attempting a n e r as e re tr y o r other error rec ov ery.
Start
FULL ER ASE STATUS CHECK PROCEDURE
Repeat for subsequent block erasures.
Full sta tus reg ister c he ck c an be done after eac h blo c k er ase
or after a s e quence of block erasures.
No
Suspend
Erase
1
0
0
0
1
1
1
1
0Yes
Suspend
Erase
Loop
0
Wri te 20h
Block Address
Wri te D0h and
Block Address
Read Status
Register
SR[7] =
Full Erase
Status Check
(if desire d)
Block Erase
Complete
Read Status
Register
Block Erase
Successful
SR[1] = Erase of
Locked Block
Aborted
BLO CK ER ASE PROC EDU RE
Bus
Operation Command Comments
Write Block
Erase
Setup
Dat a =20h
Addr = Block to be erased (BA)
Write Erase
Confirm Da t a = D0 h
Addr = Block to be erased (BA)
Read Re ad SRD
Toggle CE# or OE# to update SR D
Standby Check SR[7]
1 = WSM ready
0 = WSM busy
Bus
Operation Command Comments
SR[3] = V
PP
Rang e
Error
SR[5:4] = Command
Sequen ce Error
SR[5] = Block Erase
Error
Standby Check SR[3]
1 = V
PP
error
Standby Check SR[5:4]
Both 1 = Command s equence error
Standby Check SR[5]
1 = Block er ase error
Standby Check SR[1]
1 = Attempted erase of locked block
Erase abo rted
Intel® Wireless Flash Memory (W 18)
12.0 Program and Erase Operations
Preliminary Datasheet 81
The product does not support simultaneous program and erase operations. Attempting to perform
operations such as these results in a command sequence error. Only one partition can be
programming or erasing while another partition is reading. However, one partition may be in erase
suspend mode while a second partition is performing a program operation, and yet another partition
is executing a read command. Table 22, “Command Codes and Descriptions” on page 61 describes
the command codes available for all functions.
Intel® Wireless Flash Memory (W 18)
13.0 Security Modes
82 Preliminary Datasheet
13.0 Security Modes
The Intel W ireless Flash Memory offers both hardware and software security features to protect the
flash data. The software security feature is used by executing the Lock Block command. The
hardware security feature is used by executing the Lock-Down Block command and by asserting
the WP# signal.
Refer to Figure 33, “Block Locking State Diagram” on page 83 for a state diagram of the flash
security features. Also see Figure 34, “Locking Operations Flowchart” on page 85.
13.1 Block Lock Operations
Individual instant block locking protects code and data by allowing any block to be locked or
unlocked with no latency. This locking scheme offers two levels of protection. The first allows
software-only control of block locking (useful for frequently changed data blocks), while the
second requires hardware interaction before locking can be changed (protects infrequently changed
code blocks).
The following sections discuss the locking system operation. The term “state [abc]” specifies
locking states; for example, “state [001],” where a = WP# value, b = block lock-down status bit
D1, and c = Block Lock Status Register bit D0. Figure 33, “Block Locking State Diagram” on
page 83 defines possible locking states.
The following summarizes the locking functionality.
•All blocks power-up in a locked state.
•Unlock commands can unlock these blocks, and lock commands can lock them again.
•The Lock-Down command locks a block and prevents it from being unlocked when WP# is
asserted.
— Locked-down blocks can be unlocked or locked with commands as long as WP# is
deasserted.
— The lock-down status bit is cleared only when the device is reset or powered-down.
Block lock registers are not affected by the VPP level. They may be modified and read even if VPP
≤ VPPLK.
Each block’s locking status can be set to locked, unlocked, and lock-down, as described in the
following sections. See Figure 34, “Locking Operations Flowchart” on page 85.
Intel® Wireless Flash Memory (W 18)
13. 0 Security Modes
Preliminary Datasheet 83
13.1.1 Lock
All blocks default to locked (state [x01]) after initial power-up or reset. Locked blocks are fully
protected from alteration. Attempted program or erase operations to a locked block will return an
error in SR[1]. Unlocked blocks can be locked by using the Lock Block command sequence.
Similarly, a locked block’s status can be changed to unlocked or lock-down using the appropriate
software commands.
13.1.2 Unlock
Unlocked blocks (states [x00] and [1 10]) can be programmed or erased. All unlocked blocks return
to the locked state when the device is reset or powered-down. An unlocked block’s status can be
changed to the locked or locked-down state using the appropriate software commands. A locked
block can be unlocked by writing the Unlock Block command sequence if the block is not locked-
down.
13.1.3 Lock-Down
Locked-down blocks (state [011]) offer the user an additional level of write protection beyond that
of a regular locked block. A block that is locked-down cannot have it’s state changed by software if
WP# is asserted. A locked or unlocked block can be locked-down by writing the Lock-Down Block
command sequence. If a block was set to locked-down, then later changed to unlocked, a Lock-
Figure 33. Block Locking State Diagram
[X00]
[X01]
Power-Up/Reset
Unlocked
Locked
[011]
[111] [110]
Locked-
Down4,5
Software
Locked
[011]
Hardware
Locked5
Unlocked
WP# Hardware Control
Notes: 1. [a,b,c] represents [WP#, D1, D0]. X = Don’t Care.
2. D1 indicates block Lock-down status. D1 = ‘0 ’, Lock-down has not been issued to
this block. D1 = ‘1’, Lock-down has been issued to this block.
3. D0 indi cates block lock status. D0 = ‘0’, block is unlocked. D0 = ‘1’, block is locked.
4. Loc ked-down = Hardware + S oftware locked.
5. [011] states should be tracked by system software to determine difference between
Hardware Locked and Locked-D own s tates.
Software Block Lock (0x60/0x01) or So ft w are Block Unlock (0x60/0x D0 )
Software Block Lock-Down (0x60/0x2F)
WP# hardware control
Intel® Wireless Flash Memory (W 18)
13.0 Security Modes
84 Preliminary Datasheet
Down command should be issued prior asserting WP# will put that block back to the locked-down
state. When WP# is deasserted, locked-down blocks are changed to the locked state and can then
be unlocked by the Unlock Block command.
13.1.4 Block Lock Status
Every block’s lock status can be read in read identifier mode. To enter this mode, issue the Read
Identifier command to the device. Subsequent reads at BBA + 02h will output that block’s lock
status. For example, to read the block lock status of block 10, the address sent to the device should
be 50002h (for a top-parameter device). The lowest two data bits of the read data, DQ1 and DQ0,
represent the lock status. DQ0 indicates the block lock status. It is set by the Lock Block command
and cleared by the Block Unlock command. It is also set when entering the lock-down state. DQ1
indicates lock-down status and is set by the Lock-Down command. The lock-down status bit
cannot be cleared by software–only by device reset or power-down. See Ta ble 28.
13.1.5 Lock During Erase Suspend
Block lock configurations can be performed during an erase suspend operation by using the
standard locking command sequences to unlock, lock, or lock-down a block. This feature is useful
when another block requires immediate updating.
To change block locking during an erase operation, first write the Erase Suspend command. After
checking SR[6] to determine the erase operation has suspended, write the desired lock command
sequence to a block; the lock status will be changed. After completing lock, unlock, read, or
program operations, resume the erase operation with the Erase Resume command (D0h).
If a block is locked or locked-down during a suspended erase of the same block, the locking status
bits change immediately. When the erase operation is resumed, it will complete normally.
Locking operations cannot occur during program suspend. Appendix A, “Write State Machine
States” on page 98 shows valid commands during erase suspend.
13.1.6 Status Register Error Checking
Using nested locking or program command sequences during erase suspend can introduce
ambiguity into Status Register results.
Because locking changes require 2-cycle command sequences, for example, 60h followed by 01h
to lock a block, following the Configuration Setup command (60h) with an invalid command
produces a command sequence error (SR[5:4]=1 1b). If a Lock Block command error occurs during
erase suspend, the device sets SR[4] and SR[5] to 1 even after the erase is resumed. When erase is
Table 28. Write Protection Truth Table
VPP WP# RST# Write Protection
XXV
IL Device inaccessibl e
VIL XV
IH W ord program and block erase prohi bited
XV
IL VIH All lo ck-down blocks locked
XV
IH VIH All lock-down blocks can be unlocked
complete, possible errors during the erase cannot be detected from the Status Register because of
the previous locking command error. A similar situation occurs if a program operation error is
nested within an erase suspend.
13.1.7 WP# Lock-Down Control
The W rite Protect signal, WP#, adds an additional layer of block security. WP# only affects blocks
that once had the Lock-Down command written to them. After the lock-down status bit is set for a
block, asserting WP# forces that block into the lock-down state [011] and prevents it from being
unlocked. After WP# is deasserted, the block’s state reverts to locked [111] and software
commands can then unlock the block (for erase or program operations) and subsequently re-lock it.
Only device reset or power-down can clear the lock-down status bit and render WP# ineffective.
13.2 Protection Register
The Intel Wireless Flash Memory includes a 128-bit Protection Register. This protection register is
used to increase system security and for identification purposes. The protection register value can
match the flash component to the system’s CPU or ASIC to prevent device substitution.
The lower 64 bits within the protection register are programmed by Intel with a unique number in
each flash device. The upper 64 OTP bits within the protection register are left for the customer to
program. Once programmed, the customer segment can be locked to prevent further programming.
Figure 34. Loc k i ng Operations Flowchart
No
Optional
Start
Write 60h
Block Address
Write 90h
BBA + 02h
Read Block Lock
Status
Locking
Change?
Lock Change
Complete
Write 01,D0,2Fh
Block Address
Write FFh
Partition Address
Yes
Write
Write
Write
(Optional)
Read
(Optional)
Standby
(Optional)
Write
Lock
Setup
Lock,
Unlock, or
Lockdown
Confirm
Read ID
Plane
Block L o ck
Status
Read
Array
Dat a = 60h
Addr = Block to lock/unlock/lock-down (BA)
Data = 01h (Lock block)
D0h (Unlock block)
2Fh (Lock down block)
Addr = Block to lock/unlock/lock-down (BA)
Dat a = 90h
Addr = BBA + 02h
Block Lock status data
Addr = BBA + 02h
Confirm locking change on DQ [1:0].
(See Block Locking State Transitions Table
for valid combinations.)
Dat a = FFh
Addr = Any add res s in same partition
Bus
Operation Command Comments
LOCKING OPERATIONS PROCEDURE
Intel® Wireless Flash Memory (W 18)
13.0 Security Modes
86 Preliminary Datasheet
Note: The individual bits of the user segment of the protection register are OTP, not the register in total.
The user may program each OTP bit individually, one at a time, if desired. After the protection
register is locked, however, the entire user segment is locked and no more user bits can be
programmed.
The protection register shares some of the same internal flash resources as the parameter partition.
Therefore, RWW is only allowed between the protection register and main partitions. Table 29
describes the operations allowed in the protection register, parameter partition, and main partition
during RWW and RWE.
13.2.1 Reading the Protection Register
W r iting the Read Identifier command allows the protection register data to be read 16 bits at a time
from addresses shown in Table 24, “Device Identification Codes” on page 66. The protection
register is read from the Read Identifier command and can be read in any partition.Writing the
Read Array command returns the device to read-array mode.
13.2.2 Programing the Protection Register
The Protection Program command should be issued only at the parameter (top or bottom) partition
followed by the data to be programmed at the specified location. It programs the upper 64 bits of
the protection register 16 bits at a time. Table 24, “Device Identification Codes” on page 66 shows
allowable addresses. See also Figure 35, “Protection Register Programming Flowchart” on
page 87. Issuing a Protection Program command outside the register’s address space results in a
Status Register error (SR[4]=1).
Table 29. Simultaneous Operations Allowed with the Protection Register
Protection
Register
Parameter
Partition
Array Data
Main
Partitions Description
Read See
Description Write/Erase While program ming or er asing in a mai n part ition, the pro tection register can be
read from any other partit ion. Reading the parameter partition data is not
all owed if the protection register is being read from addresses within the
parameter partition.
See
Description Read Write/Erase While programm ing or erasing i n a main partition, read op erations are allowed
in the parameter partition. Accessing the protection registers from parameter
partition addresses is not allowed.
Read Read Write/Erase While progr amming or erasing in a main partition, read operati ons are allowed
in the paramet er partition. Accessi ng the protection registers in a partitio n that
is different from the one being programmed or erased, and als o different from
the parameter partition, is allowed.
Write No Access
Allowed Read While programming the protection register, reads a re only allowed in the other
main partitio ns. Access to the paramete r p artition is not allowed. This is
bec au s e pr o gra mming of the pr ote cti on re g is t e r ca n on ly occ ur in the
parameter par tition, so i t will exist in status mode .
No Access
Allowed Write/Erase Read While progr amming or erasing the parameter par tition, re ads of t he protection
registers are no t allowed in any partition. Reads in other main partitions are
supported.
Intel® Wireless Flash Memory (W 18)
13. 0 Security Modes
Preliminary Datasheet 87
13.2.3 Locking the Protection Register
PR-LK.0 is programmed to 0 by Intel to protect the unique device number. PR-LK.1 can be
programmed by the user to lock the user portion (upper 64 bits) of the protection register (See
Figure 36, “Protection Register Locking“). This bit is set using the Protection Program command
to program “FFFDh” into PR-LK.
After PR-LK register bits are programmed (locked), the protection register’s stored values can’t be
changed. Protection Program commands written to a locked section result in a Status Register error
(SR[4]=1, SR[5]=1).
Figure 35. Protection Register Programming Flowchart
FULL STATUS CHECK PROCEDURE
Prote ction Progr am operat ions a ddresses must be within the
protection register address space. Addresses outside this
space will r etur n an error.
Repeat for subsequent programming oper ati ons.
Ful l status register check can be done after eac h program or
after a sequence of program operations.
SR[3] MUST be cleared before the WSM will allow further
pr og ram attem pts.
Only the Clear Staus R egis ter com m and clear s SR [4:3,1].
If an error is detected, clear the status register before
attempting a program retry or other error recovery.
Yes
No
1,1
1,0
1,1
PROTECTION REGISTER PROGRAMMING PROCED U RE
Start
Wr ite C0h
Addr=Prot addr
Write Prote ct.
Register
Address / Data
Read Status
Register
SR[7] = 1?
Ful l St atus
Check
(if desired)
Program
Complete
Read SRD
Program
Successful
SR[4:3] =
SR[4,1] =
SR[4,1] =
V
PP
Range Error
Programming Error
Locked-Register
Progra m Abo rt ed
Standby
Standby
Bus
Operation Command
SR[1] SR[3] SR[4]
011V
PP
Error
0 0 1 Protection register
pr og ram err or
Comments
Write
Write
Standby
Protection
Program
Setup
Protection
Program
Data = C0h
Addr = Protection a ddres s
Data = Data to program
Addr = Protection a ddres s
C he ck SR[7]
1 = W SM Rea dy
0 = W SM Busy
Bus
Operation Command Comments
Read Read SRD
Toggl e CE# or OE # to updat e SR D
Standby 1 0 1 Regist er loc k ed;
Operat ion abor ted
Intel® Wireless Flash Memory (W 18)
13.0 Security Modes
88 Preliminary Datasheet
13.3 VPP Protection
The Intel® Wireless Flash Memory (W18) provides in-system program and erase at VPP1. For
factory programming, it also includes a low-cost, backward-compatible 12 V programming
feature.(See “Factory Programming” on page 71.) The EFP feature can also be used to greatly
improve factory program performance as explained in Section 11.3, “Enhanced Factory Program
(EFP)” on page 72.
In addition to the flexible block locking, holding the VPP programming voltage low can provide
absolute hardware write protection of all flash-device blocks. If VPP is below VPPLK, program or
erase operations result in an error displayed in SR[3]. (See Figure 37.)
Note: If the VCC supply can sink adeq uate current, you can use an appropriately valued resistor.
Figure 36. P rotection R eg i ster Locking
0x84
0x88
0x85
0x81
0x80 PR Lock Register 0
User-Programmable
Intel Factory-Programmed
15 14 13 12 11 10 9876543210
Figure 37. Examples of VPP Power Supply Configurations
•
12 V fast programmi ng
•
Absolute write protec t ion with V
PP
≤ V
PPLK
System supply
(Note 1)
VCC
VPP
12 V su pp ly
•
Low voltage and 12 V fast programming
System supply
12 V su pp ly
•
Low-voltage programming
•
Absol ut e w r ite protectio n vi a logic signal
System supply
Pr ot# (logi c sign al)
•
Low-voltage programming
System supply
≤
10K
Ω
VCC
VPP
VCC
VPP
VCC
VPP
Intel® Wireless Flash Memory (W 18)
14.0 Set Read Configuration Register
Preliminary Datasheet 89
14.0 Set Read Configuration Register
The Set Read Configuration Register (RCR) command sets the burst order, frequency
configuration, burst length, and other parameters.
A two-bus cycle command sequence initiates this operation. The Read Configuration Register data
is placed on the lower 16 bits of the address bus (A[15:0]) during both bus cycles. The Set Read
Configuration Register command is written along with the configuration data (on the address bus).
This is followed by a second write that confirms the operation and again presents the Read
Configuration Register data on the address bus. The Read Configuration Register data is latched on
the rising edge of ADV#, CE#, or WE# (whichever occurs first). This command functions
independently of the applied VPP voltage. After executing this command, the device returns to
read-array mode. The Read Configuration Register’ s contents can be examined by writing the Read
Identifier command and then reading location 05h. See Table 30 and Table 31.
Table 30. Read Configuration Register Summary
Read Mode
Res’d
First Access
Latency Count
WAIT Polarity
Data Output Config
WAIT Config
Burst Seq
Clock Config
Res’d
Res’d
Burst Wrap
Burst Lengt h
RM R LC2 LC1 LC0 WT DOC WC BS CC R R BW BL2 BL1 BL0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Table 31. Read Configuration Register Descriptions (Sheet 1 of 2)
Bit Name Description1Notes
15 RM
Read Mode 0 = Synchronous Burst R eads Enabled
1 = Asynchronous Reads Enabled (Default) 2
14 RReserved 5
13-11 LC[2:0]
First Access Latency
Count
001 = Reserved
010 = Code 2
011 = Code 3
100 = Code 4
101 = Code 5
111 = Reserv ed (Default) 6
10 WT
WAIT Signa l Polarity 0 = WAI T signal is asserted low
1 = WAIT signal is asserted high (Default) 3
9DOC
Data Output
Configuration
0 = Hold Data for One Clock
1 = Hold Data for Tw o Clock (Default) 6
8WC
WAIT Configuration 0 = WAIT Asserted Dur ing Delay
1 = WAIT Asserted One Data Cycle before Delay (De fault) 6
7BS
Burst Sequence 1 = Linear Burst Order (Default)
6CC
Clock
Configuration
0 = Burst Starts and Data Output on Falling Clock Edge
1 = Burst Starts and Da ta Output on Rising Clock Edge
(Default)
Intel® Wireless Flash Memory (W 18)
14.0 Set Read Configuration Register
90 Preliminary Datasheet
5RReserved 5
4RReserved 5
3BW
Burst Wrap
0 = Wrap bursts within burst length set by CR[2:0]
1 = Don’t wrap acce sse s wit hin burs t le ngth se t by
CR[2:0].(Default)
2-0 BL[2:0]
Burst Length
001 = 4-Word Burst
010 = 8-Word Burst
011 = 16 - Word Bu rst
111 = Continuous Bu r s t (Default) 4
Notes:
1. Undocumented combinat ions of bi ts are reserved by Intel for future implementations.
2. Sync hronous and page read mode configurations affect reads from main blocks and par ameter
blocks. Status Register and confi guration reads support si ngle read cyc les. RCR[15]=1 dis ables
conf iguration set by RCR[14:0] .
3. Data is not ready when WA IT is ass erted.
4. Set th e synchronous burst length. In asynchronous page mode, the page size equal s four words.
5. Set all reserved R ead Co nfiguration Register bit s to zer o.
6. Setti n g t h e R ea d Conf igur at ion Re gister for sy n ch r o nous burs t-mode with a lat e nc y co unt of 2
(RCR[ 13:11] = 010) , data hold fo r 2 cl ocks (RCR[9] = 1), and WAIT asserted one data cycle before
delay (RCR[8] =1) is not supported.
Table 31. Read Configuration Register Descriptions (Sheet 2 of 2)
Bit Name Description1Notes
Intel® Wireless Flash Memory (W 18)
14.0 Set Read Configuration Register
Preliminary Datasheet 91
14.1 Read Mode (RCR[15])
All partitions support two high-performance read configurations: synchronous burst mode and
asynchronous page mode (default). RCR[15] sets the read configuration to one of these modes.
Status register , query , and identifier modes support only asynchronous and single-synchronous read
operations.
14.2 First Access Latency Count (RCR[13:11])
The First Access Latency Count (RCR[13:11]) configuration tells the device how many clocks
must elapse from ADV# de-assertion (VIH) before the first data word should be driven onto its data
pins. The input clock frequency determines this value. See Tabl e 31, “Rea d Conf ig ura ti on Re gi ste r
Descrip tions” on page 89 for latency values. Figure 38 shows data output latency from ADV#
assertion for different latencies. Refer to Section 14.2.1, “Latency Count Settings” on page 92 for
Latency Code Settings.
Note: Other First Access Latency Configuration settings are reser ved.
)
Figure 38. First Access Latency Configuration
Code 5
Code 4
Code 3
Code 2
Valid
Address
Valid
Output Valid
Output Valid
Output Valid
Output Valid
Output Valid
Output
Valid
Output Valid
Output Valid
Output Valid
Output Valid
Output
Valid
Output Valid
Output Valid
Output Valid
Output
Valid
Output Valid
Output Valid
Output
Address [A]
ADV# [V]
CLK [C]
D[15:0] [Q]
D[15:0] [Q]
D[15:0] [Q]
D[15:0] [Q]
Figure 39. Word Boundary
0123456789ABCDEF
16 Word Boundary
Word 0 - 3 Word 4 - 7 Word 8 - B Word C - F
4 Word Boundary
Intel® Wireless Flash Memory (W 18)
14.0 Set Read Configuration Register
92 Preliminary Datasheet
Note: The 16 -word boundary is the end of the device sense word-li ne.
14.2.1 Latency Count Setti ngs
Table 32. Latency Count Setting for VCCQ = 1.7 V - 1.95 V (90 nm lithography)
VCCQ = 1.7 - 1. 95 V Unit
tAVQV/tCHQV (60ns/11ns)
Latency Count Settings 234, 5
Frequency Support < 40 < 61 < 66 MHz
Table 33. Latency Count Setting for VCCQ = 1.7 V - 2.24 V (130 nm lithography)
VCCQ = 1.7 - 2.24 V Unit
tAVQV/tCHQV (60ns/11ns) tAVQV/tCHQV (80ns/14ns)
Latency Count
Settings 2 3 4, 5 2 3 4, 5
Frequency
Support < 40 < 61 < 66 < 30 < 45 < 54 MHz
Table 34. Latency Count Settings for VCCQ = 1.35 V - 1.8 V (130 nm lithography)
VCCQ = 1. 35 V - 1.8 V Unit
tAVQV/tCHQV (65ns/14ns) tAVQV/tCHQV (85ns/20ns)
Latency Count
Settings 2 3, 4, 5 2 3 , 4, 5
Frequency
Support < 39 < 54 < 30 < 40 MHz
Table 35. Latency Count Setting for VCCQ = 1.7 V - 2.24 V (180 nm lithography)
VCCQ = 1.7 - 2.24 V Unit
tAVQV/tCHQV (70ns/14ns) tAVQV/tCHQV (85ns/18ns)
Latency Count
Settings 2 3, 4, 5 2 3, 4, 5
Frequency
Support < 35 <52 < 29 < 40 MH z
Intel® Wireless Flash Memory (W 18)
14.0 Set Read Configuration Register
Preliminary Datasheet 93
14.3 WAIT Signal Polarity (RCR[10])
If the WAIT bit is cleared (RCR[10]=0), then WAIT is configured to be asserted low. This means
that a 0 on the WAIT signal indicates that data is not ready and the data bus contains invalid data.
Conversely, if RCR[10] is set, then WAIT is asserted high. In either case, if WAIT is deasserted,
then data is ready and valid. WAIT is asserted during asynchronous page mode reads.
14.4 WAIT Signal Function
The WAIT signal indicates data valid when the device is operating in synchronous mode
(RCR[15]=0), and when addressing a partition that is currently in read-array mode. The WAIT
signal is only “deasserted” when data is valid on the bus.
When the device is operating in synchronous non-read-array mode, such as read status, read ID, or
read query, WAIT is set to an “asserted” state as determined by RCR[10]. See Figure 14, “WAIT
Signal in Synchronous Non-Read Array Operation Waveform” on page 43.
When the device is operating in asynchronous page mode or asynchronous single word read mode,
WAIT is set to an “asserted” state as determined by RCR[10]. See Figure 10, “Page-Mode Read
Operation Waveform” on page 39, and Figure 8, “Asynchronous Read Operation Waveform” on
page 37.
From a system perspective, the WAIT signal is in the asserted state (based on RCR[10]) when the
device is operating in synchronous non-read-array mode (such as Read ID, Read Query, or Read
Status), or if the device is operating in asynchronous mode (RCR[15]=1). In these cases, the system
software should ignore (mask) the WAIT signal, because it does not convey any useful information
about the validity of what is appearing on the data bus.
Figure 40. Example: Latency Count Se tting at 3
AMAX-0 (A)
DQ15-0 (D /Q )
CLK (C)
CE# (E)
ADV# (V)
R103
Valid
Output Valid
Output
High Z
tADD-DELAY tDATA
1nd0st 2rd 3th 4th
Valid Address
Code 3
Intel® Wireless Flash Memory (W 18)
14.0 Set Read Configuration Register
94 Preliminary Datasheet
14.5 Data Hold (RCR[9])
The Data Output Configuration (DOC) bit (RCR[9]) determines whether a data word remains valid
on the data bus for one or two clock cycles. The processor’s minimum data set-up time and the
flash memory’s clock-to-data output delay determine whether one or two clocks are needed.
A DOC set at 1-clock data hold corresponds to a 1-clock data cycle; a DOC set at 2-clock data hold
corresponds to a 2-clock data cycle. The setting of this configuration bit depends on the system and
CPU characteristics. For clarification, see Figure 41, “Data Output Configuration with WAIT
Signal Delay” on page 95.
A method for determining this configuration setting is shown below.
To set the device at 1-clock data hold for subsequent reads, the following condition must be
satisfied:
tCHQV (ns) + tDATA (ns) ≤ One CLK Per iod (ns)
As an example, use a clock frequency of 66 MHz and a clock period of 15 ns. Assume the data
output hold time is one clock. Apply this data to the formula above for the subsequent reads:
11 ns + 4 ns ≤ 15 ns
This equation is satisfied, and data output will be available and valid at every clock period. If tDATA
is long, hold for two cycles.
During page-mode reads, the initial access time can be determined by the formula:
tADD-DELAY (ns) + tDATA (ns) + tAVQV (ns)
Subsequent reads in page mode are defined by:
tAPA (ns) + tDATA (ns) (minimum time)
Table 36. WAIT S ig na l Conditions
CONDITION WAIT
CE# = VIH
CE# = VIL
Tri-State
Active
OE# No-Effect
Synchronous Array Read Active
Synchronous Non-Array Read Asserted
All Asynchronous Read and all Write Asserted
Intel® Wireless Flash Memory (W 18)
14.0 Set Read Configuration Register
Preliminary Datasheet 95
Note: WAIT shown asserted high (RCR[10]=1).
14.6 WAIT Delay (RCR[8])
The WAIT configuration bit (RCR[8]) controls WAIT signal delay behavior for all synchronous
read-array modes. Its setting depends on the system and CPU characteristics. The WAIT can be
asserted either during, or one data cycle before, a valid output.
In synchronous linear read array (no-wrap mode RCR[3]=1) of 4-, 8-, 16-, or continuous-word
burst mode, an output delay may occur when a burst sequence crosses its first device-row boundary
(16-word boundary). If the burst start address is 4-word boundary aligned, the delay does not occur .
If the start address is misaligned to a 4-word boundary, the delay occurs once per burst-mode read
sequence. The WAIT signal informs the system of this delay.
14.7 Burst Sequence (RCR[7])
The burst sequence specifies the synchronous-burst mode data order (see Table 37, “Sequence and
Burst Length” on page 96). When operating in a linear burst mode, either 4-, 8-, or 16-word burst
length with the burst wrap bit (RCR[3]) set, or in continuous burst mode, the device may incur an
output delay when the burst sequence crosses the first 16-word boundary. (See Figure 39, “Word
Boundary” on page 91 for word boundary description.) This depends on the starting address. If the
starting address is aligned to a 4-word boundary, there is no delay. If the starting address is the end
of a 4-word boundary , the output delay is one clock cycle less than the First Access Latency Count;
this is the worst-case delay. The delay takes place only once, and only if the burst sequence crosses
a 16-word boundary. The WAIT pin informs the system of this delay. For timing diagrams of WAIT
functionality, see these figures:
•Figure 11, “Single Synchronous Read-Array Operation Waveform” on page 40
•Figure 12, “Synchronous 4-Word Burst Read Operation Waveform” on page 41
Figure 41. Data Out put Configuration with WAIT Signal Delay
DQ15-0 [Q ]
CLK [C]
Valid
Output Valid
Output Valid
Output
DQ15-0 [Q] Valid
Output
1 CLK
Data Hold
WAIT (CR.8 = 1)
WAIT (CR.8 = 0)
tCHQV
tCHQV
WAIT (C R .8 = 0)
WAIT (CR.8 = 1)
2 CLK
Data Hold
tCHTL/H
Note 1
N ote 1
Note 1
Note 1
Valid
Output
Intel® Wireless Flash Memory (W 18)
14.0 Set Read Configuration Register
96 Preliminary Datasheet
•Figure 13, “WAIT Functionality for EOWL (End-of-Word Line) Condition Waveform” on
page 42
14.8 Clock Edge (RCR[6])
Configuring the valid clock edge enables a flexible memory interface to a wide range of burst
CPUs. Clock configuration sets the device to start a burst cycle, output data, and assert WAIT on
the clock’s rising or falling edge.
Table 37. Sequence and Burst Length
Sta rt Add r. (Dec)
Burst Ad dressing S equence (Deci mal)
4-Word Burst
RCR[2:0]=001b 8-Word Burst
RCR[2:0]=010b 16-Word Burst
RCR[2:0]=011b Co ntinuous Burst
RCR[2:0]=111b
Linear Linear Linear Linear
Wrap (RCR[3]=0)
0 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2...14-15 0-1-2-3-4-5-6-...
1 1-2-3-0 1-2-3-4-5-6-7-0 1-2-3...14-15-0 1-2-3-4-5-6-7-...
2 2-3-0-1 2-3-4-5-6-7-0-1 2-3-4...15-0-1 2-3-4-5-6-7-8-...
3 3-0-1-2 3-4-5-6-7-0-1-2 3-4-5...15-0-1-2 3-4-5-6-7-8-9-...
44-5-6-7-0-1-2-3 4-5-6...15-0-1-2-3 4-5-6-7-8-9-10...
55-6-7-0-1-2-3-4 5-6-7...15-0-1...4 5-6-7-8-9-10-11...
66-7-0-1-2-3-4-5 6-7-8...15-0-1...5 6-7-8-9-10-11-12-...
77-0-1-2-3-4-5-6 7-8-9...15-0-1...6 7-8-9-10-11-12-13...
...
...
...
...
...
14 14-15-0-1...13 14-15-16-17-18-19-20-...
15 15-0-1-2-3...14 15-16-17-18-19-...
No-Wrap (RCR[3]=1)
0 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2...14-15 0-1-2-3-4-5-6-...
1 1-2-3-4 1-2-3-4-5-6-7-8 1-2-3...15-16 1-2-3-4-5-6-7-...
2 2-3-4-5 2-3-4-5-6-7-8-9 2-3-4...16-17 2-3-4-5-6-7-8-...
3 3-4-5-6 3-4-5-6-7-8-9-10 3-4-5...17-18 3-4-5-6-7-8-9-...
44-5-6-7-8-9-10-11 4-5-6...18-19 4-5-6-7-8-9-10...
55-6-7-8-9-10-11-12 5-6-7...19-20 5-6-7-8-9-10-11...
66-7-8-9-10-11-12-13 6-7-8...20-21 6-7-8-9-10-11-12-...
77-8-9-10-11-12-13-14 7-8-9...21-22 7-8-9-10-11-12-13...
...
...
...
...
...
14 14-15...28-29 14-15-16-17-18-19-20-...
15 15-16...29-30 15-16-17-18-19-20-21-...
Intel® Wireless Flash Memory (W 18)
14.0 Set Read Configuration Register
Preliminary Datasheet 97
14.9 Burst Wrap (RCR[3])
The burst wrap bit determines whether 4-, 8-, or 16-word burst accesses wrap within the burst-
length boundary or whether they cross word-length boundaries to perform linear accesses. No-
wrap mode (RCR[3]=1) enables WAIT to hold off the system processor, as it does in the
continuous burst mode, until valid data is available. In no-wrap mode (RCR[3]=0), the device
operates similarly to continuous linear burst mode but consumes less power during 4-, 8-, or 16-
word bursts.
For example, if RCR[3]=0 (wrap mode) and RCR[2:0] = 1h (4-word burst), possible linear burst
sequences are 0-1-2-3, 1-2-3-0, 2-3-0-1, 3-0-1-2.
If RCR[3]=1 (no-wrap mode) and RCR[2:0] = 1h (4-word burst length), then possible linear burst
sequences are 0-1-2-3, 1-2-3-4, 2-3-4-5, and 3-4-5-6. RCR[3]=1 not only enables limited non-
aligned sequential bursts, but also reduces power by minimizing the number of internal read
operations.
Setting RCR[2:0] bits for continuous linear burst mode (7h) also achieves the above 4-word burst
sequences. However, significantly more power may be consumed. The 1-2-3-4 sequence, for
example, consumes power during the initial access, again during the internal pipeline lookup as the
processor reads word 2, and possibly again, depending on system timing, near the end of the
sequence as the device pipeli nes the next 4-word sequence. RCR[3]= 1 while in 4-word burst mode
(no-wrap mode) reduces this excess power consumption.
14.10 Burst Length (RCR[2:0])
The Burst Length bit (BL[2:0]) selects the number of words the device outputs in synchronous read
access of the flash memory array. The burst lengths are 4-word, 8-word, 16-word, and continuous
word .
Continuous-burst accesses are linear only, and do not wrap within any word length boundaries (see
Table 37, “Sequence and Burst Length” on page 96). When a burst cycle begins, the device outputs
synchronous burst data until it reaches the end of the “burstable” address space.
Intel® Wireless Flash Memory (W 18)
Appendix A Write State Machine States
98 Preliminary Datasheet
Appendix A Write State Machine Sta tes
This table shows the command state transitions based on incoming commands. Only one partition
can be actively programming or erasing at a time.
Figure 42. Write State Mach ine — Next State Table (Sheet 1 of 2)
Chi
p
Next State after Com mand In
p
ut
Read
Array
(3)
Program
Setup
(4,5)
Erase
Setup
(4,5)
Enhanced
Factory
Pgm
Setup
(4)
BE Confirm,
P/E Resume,
ULB
Confirm
(9)
Program/
Erase
Suspend
Read
Status
Clear
Status
Register
(6)
Read
ID /Q uery
(FFH) (10H /40H ) (20H) (30H ) (D 0H) (B 0H ) (70H) (50H ) (90H , 98H )
Ready Ready Program
Setup Erase
Setup EFP
Setup Ready
Lock/C R Setup Ready (Lock Error) Ready Ready (Lock Error)
Setup OTP Busy
Busy
Setup Program Busy
Busy Program Busy Pgm Susp Program Busy
Suspend Program Suspend Pgm Busy Program Suspend
Setup R eady (E rror) E rase Busy Ready (E rror)
Busy Erase Busy Erase Susp Erase Busy
Suspend Erase
Suspend
Pgm in
Erase
Susp Setup Erase Suspend Erase Busy Erase Suspend
Setup Program in Erase Suspend Busy
Busy Program in Erase Suspend Busy Pgm Susp in
Erase Susp Program in Erase Suspend Busy
Suspend Program S uspend in E rase Suspend Pgm in Erase
Susp Busy P rogram Suspend in Erase Suspend
Erase Suspend (Lock Error) Erase Susp Erase Suspend
(Loc k E rror)
Setup R eady (E rror) E FP Busy R eady (E rror)
EFP Busy EFP Bus
y
(7)
EFP Verify Verif
y
Bus
y
(7)
Out
p
ut Next State after Comm and In
p
ut
Status
Status
Status
ID /Q uery
Write State M achine (WSM ) Next State Table
Output Next State Table
(1)
Lock/C R Setup,
Lock/C R Setup in Erase Susp
OTP Busy
Current Chip
State(8)
Ready,
Pgm Busy,
Pgm Suspend,
Erase Busy,
Erase Suspend,
Pgm In Erase Susp Busy,
P gm S u sp In Era se S u sp
Pgm Setup,
Erase Setup,
OTP Setup,
Pgm in Erase Susp Setup,
EFP Setup,
EFP Busy,
V erify Bu sy
Lock/C R Setup in Erase
Suspend
Erase
Program
Program in
Erase Suspend
OTP
Enhanced
Factory
Program
Output
does not
change
Array
(3)
Status Output does not change Status
Intel® Wireless Flash Memory (W 18)
Appendix A Write State Machine States
Preliminary Datasheet 99
Notes:
1. The output state shows the type of data that appea rs at the outputs if the p ar ti t ion address is the s ame as the com m and
address.
A p ar t it ion can be placed in Read Ar r ay, Read Status or Read ID/CFI, depending on the c om mand issued.
Eac h partition stays in its last out put state (Array, ID/CFI or Status) until a new com m and changes it. The next WSM st ate
does not depend on the partition's output state.
For example, if par ti ti on #1's ou tput state is Read Arr ay and partitio n #4's out put state is Read Status, ev er y re ad from
partition #4 (without issuing a new command) outputs the Status register.
Figure 42. Write State Machine — Next State Table (Sheet 2 of 2)
Chi
p
Next State after Com m and In
p
ut
Lock,
Unlock,
Lock-down,
CR setup
(5)
OTP
Setup
(5)
Lock
Block
Confirm
(9)
Lock-
Down
Block
Confirm
(9)
Write CR
Confirm
(9)
Enhanced
Fact Pgm
Exit (blk add
< > W A 0 )
Illegal
com mands or
EFP data
(2)
(60H) (C0H) (01H) (2FH) (03H) (XXXXH) (other codes)
Ready Lock/CR
Setup OTP
Setup Ready
Lock/CR Setup Ready (Lock Error) Ready Ready Ready Ready (Lock Error)
Setup OTP Busy
Busy Ready
Setup Program Busy N/A
Busy Program B usy R eady
Suspend Program Suspend
Setup Ready (Error)
Busy Erase Busy Erase Busy Ready
Suspend Lock/CR
Setup in
Erase Susp Erase Suspend
Setup Program in Erase Suspend Busy
Busy Program in Erase Suspend Busy Erase
Suspend
Suspend Program Suspend in Erase Suspend
Erase Suspend
(Lo ck E rror) Erase Susp Erase Susp Erase Susp Erase Suspend (Lock Error)
Setup Ready (Error)
EFP Busy EFP Bus
y
(7)
EFP Verify EFP Bus
y
(7)
EFP Verify Verif
y
Bus
y
(7)
Ready EFP Verif
y
(7)
Ready
Out
p
ut Next State after Com m and In
p
ut
Status
Status Array Status
Write State M achine (W SM) Next State Table
Output Next State Table
(1)
Program
Erase
Program in
Erase Suspend
Current Chip
State
(8)
OTP
Lock/CR Setup in Erase
Suspend
Enhanced
Factory
Program
Output does
not change
Output does
not change
WSM
Operation
Completes
N/A
N/A
N/A
N/A
O utput does not change ArrayStatus
Pgm Setup,
Erase Setup,
OTP Setup,
Pgm in Erase Susp Setup,
EFP Setup,
EFP Busy,
V erify B u sy
Lock/CR Setup,
Lock/CR Setup in Erase Susp
OTP Busy
Ready,
Pgm Busy,
Pgm Suspend,
Erase Busy,
Erase Suspend,
Pgm In Erase Susp Busy,
P gm S u sp In E ra se S u sp
Intel® Wireless Flash Memory (W 18)
Appendix A Write State Machine States
100 Preliminary Datasheet
2. Illega l commands are those not defined in the command set.
3. All pa r ti ti ons default to Rea d Array mode at po wer-up. A Read Arr ay command issued to a busy part ition results in
underm ined data wh en a partition addr ess is read.
4. Both cycles of 2 cycl es co mmands sh ould be iss ued to the same par tition ad dress . If the y are i ssued t o dif fere nt p artit ions,
the seco nd write de termi n es th e ac t ive par tit i o n. Both par t itio ns wi ll ou t put st atus i nfor m atio n when re ad.
5. If the WSM is a ctive, both cycles of a 2 cycle command are ignored. This differs from previ ous Intel devices.
6. The Clear Stat us command clear s Status Register error bits except when t he WSM is running (Pgm Busy, Erase Busy,
Pgm Busy In Er ase Suspend, OT P Busy, EFP mo des) or suspended (Er ase Suspend, Pgm Suspend, Pgm Suspend In
Erase S uspend).
7. EFP wri te s ar e allowe d only when Status Register bit SR.0 = 0. EFP is busy if Block Addr ess = address at EFP Confirm
comm and. Any other comm ands are treated as data.
8. The "cur rent state" is th at of the WS M , not the partition.
9. Confirm comm ands (Lock Block, Unlock Block, Lock-down Block, Conf iguration Regi st er ) per form the operati on and then
mo ve t o t he Re ad y Stat e.
10. In Erase suspend, the onl y valid two cycle commands are "Program W or d", "Lock/Unlock/Lockdown B lo ck", and " CR
Wri te". Both cycles of other two cyc le com man ds ("OE M CAM pr ogra m & con firm ", "Prog ram OTP & confir m", "EFP Se tup
& confirm " , "Erase setup & confirm " ) will be ignored. In Progr am suspend or Pro gram suspend i n Er ase suspend, both
cycles of al l tw o cycl e commands will be ign or ed.
Intel® Wireless Flash Memory (W 18)
Appendix B Common Flash Interface (CFI)
Preliminary Datasheet 101
Appendix B Common Flash Interface (CFI)
This appendix defines the data structure or “database” returned by the Common Flash Interface
(CFI) Query command. System software should parse this structure to gain critical information
such as block size, density, x8/x16, and electrical specifications. Once this information has been
obtained, the software will know which command sets to use to enable flash writes, block erases,
and otherwise control the flash component. The Query is part of an overall specification for
multiple command set and control interface descriptions called Common Flash Interface, or CFI.
B.1 Query Structure Output
The Query database allows system software to obtain information for controlling the flash device.
This section describes the device’s CFI-compliant interface that allows access to Query data.
Query data are presented on the lowest-order data outputs (DQ0-7) only. The numerical offset
value is the address relative to the maximum bus width supported by the device. On this family of
devices, the Query table device starting address is a 10h, which is a word address for x16 devices.
For a word-wide (x16) device, the first two Query-structure bytes, ASCII “Q” and “R,” appear on
the low byte at word addresses 10h and 11h. This CFI-compliant device outputs 00h data on upper
bytes. The device outputs ASCII “Q” in the low byte (DQ0-7) and 00h in the high byte (DQ8-15).
At Query addresses containing two or more bytes of information, the least significant data byte is
presented at the lower address, and the most significant data byte is presented at the higher address.
In all of the following tables, addresses and data are represented in hexadecimal notation, so the
“h” suffix has been dropped. In addition, since the upper byte of word-wide devices is always
“00h,” the leading “00” has been dropped from the table notation and only the lower byte value is
shown. Any x16 device outputs can be assumed to have 00h on the upper byte in this mode.
Table 38. Summary of Query Strucutre Output as a Function of Device and Mode
Device Hex
Offset Hex
Code ASCII
Value
Device Ad dr esses
00010 51 “Q”
00011 52 “R”
00012 59 “Y”
Intel® Wireless Flash Memory (W 18)
Appendix B Common Flash Interface (CFI)
102 Preliminary Datasheet
B.2 Query Structure Overview
The Query command causes the flash component to display the Common Flash Interface (CFI)
Query structure or “database.” The structure sub-sections and address locations are summarized
below.
Table 40. Query Structure
Notes:
1. Refer to the Q uery S truct ure Output sect ion and of fset 28h for the detaile d definiti on of offset address as
a func tion of de vice bus width and m ode.
2. BA = Block Address beginning location ( i.e., 08000h is b lock 1’s beginning loca ti on when the block size
is 32K-word).
3. Of fset 15 def ines “P” which po ints to the Pri m ar y Intel-specif ic Extended Query Table.
B.3 Block Status Register
The Block Status Register indicates whether an erase operation completed successfully or whether
a given block is locked or can be accessed for flash program/erase operations.
Table 39. Example of Query Structure Output of x16 and x8 Devices
Wo rd Addressing Byte Addressing
Offs et Hex C ode Value Offset Hex Code Value
AX - A0D16 - D0AX - A0D7 - D0
00010h 0051 “Q” 00010h 51 “Q”
00011h 0052 “R” 00011h 52 “R”
00012h 0059 “Y” 00012h 59 “Y”
00013h P IDLO P rVendo r 00013h P IDLO P r Vendor
00014h P IDHI ID # 00014h P IDLO ID #
00015h PLO P rVendor 00015h P IDHI ID #
00016h PHI TblAdr 00016h ... ...
00017h A IDLO AltVendor 00017h ... ...
00018h A IDHI ID # 00018h ... ...
Offset Sub-Section Name Descri
p
tion(1)
00000h Manufacturer Code
00001h Device Code
(
BA+2
)
h(2) Block Status re
g
ister Block-s
p
ecific information
00004-Fh Reserved Reserved for vendor-specific information
00010h CFI query identification string Command set ID and vendor data offset
0001B h System interface infor m ation Device timing & voltage inform ation
00027h Devi ce geometry def inition Flash device layout
P(3) Prim ary Intel-specific Extended Query Table Vendor-defined additional inf ormation specific
to the Prim ary Vendor Algorit hm
Intel® Wireless Flash Memory (W 18)
Appendix B Common Flash Interface (CFI)
Preliminary Datasheet 103
Block E ra se Status (BSR.1 ) a ll ows sy st em so ftw ar e t o det er min e the su cc ess of th e las t b loc k er as e
operation. BSR.1 can be used just after power-up to verify that the VCC supply was not
accidentally removed during an erase operation.
Table 41. B lock Status Register
Notes:
1. BA = Block Address b eginning location (i.e., 08000h is block 1’s be ginning locat io n when the bl ock size
is 32K-word).
B.4 CFI Query Identification String
The Identification String provides verification that the component supports the Common Flash
Interface specification. It also indicates the specification version and supported vendor-specified
command set(s).
Offset Length Description
A
dd.
V
alue
(BA+2)h
(1)
1 Block Lock Status Register BA+2 --00 or --01
BA+2 (bi t 0): 0 or 1
BA+2 (bi t 1): 0 or 1
BSR 2–7: Reserved for future use BA+2 (bit 2–7): 0
BSR.0 Block lock status
0 = Unlocked
1 = Locked
BSR.1 Bl o ck lock- down stat us
0 = Not locked down
1 = Locked down
Intel® Wireless Flash Memory (W 18)
Appendix B Common Flash Interface (CFI)
104 Preliminary Datasheet
Table 43. System Interface Information
Table 42. CFI Identification
Offset Length Description Addr. Hex
Code Value
10h 3 Query-unique ASCII string “QRY” 10:
11:
12:
--51
--52
--59
“Q”
“R”
“Y”
13h 2 Primary vendor com mand set and con t ro l in t er face ID code.
16-bit I D code f or ve nd or- s pecif ic al gori t hms . 13:
14: --03
--00 —
15h 2 Extended Query Ta ble primary algorithm address 15:
16: --39
--00 —
17h 2 Alternate vendor command set and control interface ID code.
0000h means no second vendor-specified algorithm exists. 17:
18: --00
--00 —
19h 2 Secondary al gor ithm Ext ended Query Table address.
0000 h m eans none exists. 19:
1A: --00
--00 —
Offset Length Description Add. Hex
Code Value
1Bh 1 1B: --17 1.7V
1Ch 1 1C: --19 1.9V
1Dh 1 1D: --B4 11.4V
1Eh 1 1E: --C6 12.6V
1Fh 1 “n” such that t
yp
ical sin
g
le word
p
ro
g
ram time-out = 2n
µ
-sec 1F: --04 16µs
20h 1 “n” such that t
yp
ic al max. buffer write time -out = 2n
µ
-sec 20: --00 NA
21h 1 “n” such that t
yp
ical bl ock eras e ti m e-out = 2n m-sec 21: --0A 1s
22h 1 “n” such that t
yp
ical full chi
p
erase time-out = 2nm-sec 22: --00 NA
23h 1 “n” such that maximum word
p
ro
g
ram time-out = 2n ti mes t
yp
ical 23: --04 256µs
24h 1 “ n” such that maximum buff er write ti m e-out = 2ntimes t
yp
ical 24: --00 NA
25h 1 “ n” such that maximum block eras e tim e-out = 2ntimes t
yp
ical 25: --03 8s
26h 1 “n” such that maximum chi
p
eras e tim e-out = 2n time s t
yp
ical 26: --00 NA
VCC l ogic supply minimum program/erase vol tage
bits 0–3 BCD 100 mV
bits 4–7 BCD volts
VCC l ogic supply m aximum program/er ase vol tage
bits 0–3 BCD 100 mV
bits 4–7 BCD volts
VPP [program m ing] supply minimu m program /er ase voltage
bits 0–3 BCD 100 mV
bits 4–7 HEX volts
VPP [program m ing] supply maximum program/eras e volt age
bits 0–3 BCD 100 mV
bits 4–7 HEX volts
Intel® Wireless Flash Memory (W 18)
Appendix B Common Flash Interface (CFI)
Preliminary Datasheet 105
B.5 Device Geometry Definition
Table 44. Device Geometry Definition
Offset Length Description Code
27h 1“n” such that device size = 2
n
in num ber o f b
y
tes 27:
See table below
76543210
28h 2 — — — — x64 x32 x16 x8 28: --01 x16
15 14 13 12 11 10 9 8
————————29:--00
2Ah 2“n ” s uc h t h at m ax i m u m number o f b
y
tes in write buffer = 2
n
2A: --00 0
2B: --00
2Ch 1 2C:
2Dh 4 Erase Bloc k R egion 1 Information 2D:
bits 0–15 = y , y + 1 = num ber of ident ical-siz e er ase blocks 2E:
bits 16–31 = z , re gion erase b lock ( s) siz e are z x 256 byt e s 2F :
30:
31h 4 Erase B l oc k R egi on 2 I nfor m at ion 31:
bits 0–15 = y , y + 1 = num ber of ident ical-siz e er ase blocks 32:
bits 16–31 = z , re gion erase b lock ( s) siz e are z x 256 byt e s 33:
34:
35h 4 Reserv ed for f ut ure er ase block region inf o rm ati on 35:
36:
37:
38:
See table below
See table below
See table below
See table below
Num ber o f era se block reg ions (x) withi n device:
1. x = 0 means no era se blocking; the device eras es i n bulk
2. x s pecifies th e number of device re gi ons w it h on e or
mo re contiguous sam e-s ize eras e blocks .
3. S
y
mmetricall
y
block ed
p
artit ions have one blo c ki n
g
re
g
ion
Flash device i nter f ac e c ode ass i gnm e nt :
"n" s uc h that n+ 1 s pecifie s t he bit fiel d t ha t rep resents th e f lash
device width ca
p
abilities as descri bed in t h e t able:
Address 32 Mbit
–
B
–
T
–
B
–
T
–
B
–
T
27: --16 --16 --17 --17 --18 --18
28: --01 --01 --01 --01 --01 --01
29: --00 --00 --00 --00 --00 --00
2A: --00 --00 --00 --00 --00 --00
2B: --00 --00 --00 --00 --00 --00
2C: --02 --02 --02 --02 --02 --02
2D: --07 --3E --07 --7E --07 --FE
2E: --00 --00 --00 --00 --00 --00
2F: --20 --00 --20 --00 --20 --00
30: --00 --01 --00 --01 --00 --01
31: --3E --07 --7E --07 --FE --07
32: --00 --00 --00 --00 --00 --00
33: --00 --20 --00 --20 --00 --20
34: --01 --00 --01 --00 --01 --00
35: --00 --00 --00 --00 --00 --00
36: --00 --00 --00 --00 --00 --00
37: --00 --00 --00 --00 --00 --00
38: --00 --00 --00 --00 --00 --00
64 Mbit 128 Mbit
Intel® Wireless Flash Memory (W 18)
Appendix B Common Flash Interface (CFI)
106 Preliminary Datasheet
B.6 Intel-Specific Extended Query Table
Table 45. Primary Vendor-Specific Extended Query
Offset(1) Len
g
th Description Hex
P = 39h (Optional flash features and commands)
A
dd. Code
V
alue
(P+0)h 3 Primary extended query table 39: --50 "P"
(P+1)h Unique ASCII string “PRI“ 3A: --52 "R"
(P+2)h 3B: --49 "I"
(P+3)h 1 Major version number, ASCII 3C: --31 "1"
(P+4)h 1 Minor version number, ASCII 3D: --33 "3"
(P+5)h 4 Optional feature and command support (1=yes, 0=no) 3E: --E6
(P+6)h bits 10–31 are reserved; undefined bits are “0.” If bit 31 is 3F: --03
(P+7)h “1” then another 31 bit field of Optional features follows at 40: --00
(P+8)h the end of the bit–30 field. 41: --00
bit 0 Chip erase supported bit 0 = 0 No
bit 1 Suspend erase supported bit 1 = 1 Yes
bit 2 Suspend program supported bit 2 = 1 Yes
bit 3 Legacy lock/unlock supported bit 3 = 0 No
bit 4 Queued erase supported bit 4 = 0 No
bit 5 Instant individual block locking supported bit 5 = 1 Yes
bit 6 Protection bits supported bit 6 = 1 Yes
bit 7 Pagemode read supported bit 7 = 1 Yes
bit 8 Synchronous read supported bit 8 = 1 Yes
bit 9 Simultaneous operations supported bit 9 = 1 Yes
(P+9)h 1 42: --01
bit 0 Pro
g
ram su
pp
orted after erase sus
p
end bit 0 = 1 Yes
(P+A)h 2 Block status r egister mask 43: --03
(P+B)h bits 2–15 are Reserved; undefined bits are “0” 44: --00
bit 0 Block Lock-Bit Status register active bit 0 = 1 Yes
bit 1 Block Lock-Down Bit Status active bit 1 = 1 Yes
(P+C)h 1 45: --18 1.8V
(P+D)h 1 46: --C0 12.0V
Supported functions after suspend: read Array, Status, Query
Other supported operations are:
bits 1–7 reserved; undefined bits are “0”
VCC logic supply highest performance program/erase voltage
bits 0–3 BCD value in 100 mV
bits 4–7 BCD value in volts
VPP optimum program/erase supply voltage
bits 0–3 BCD value in 100 mV
bits 4–7 HEX value in volts
Intel® Wireless Flash Memory (W 18)
Appendix B Common Flash Interface (CFI)
Preliminary Datasheet 107
Table 47. Burst Read Infor m ation for Non-muxed Device
Table 48. Partition and Erase-bloc k Region Inf orma tion
Table 46. Protection Register Information
Offset
P = 39h Lengt
hDescription
(Optio nal Flash Feat ures and Commands) Add. Hex
Code Value
(P + E)h 1 N umber of Protectui b Register fields i n JEDEC ID spac e.
“00h” indicates that 256 prote ct ion fiel ds ar e avai lable. 47: --01 1
(P + E)h
(P + 10)h
(P + 11)h
(P + 12)h
4
Prot ect ion Field 1: Prot ection Descr iption
This fi eld describes use r -a vai lable One T i m e
Progr ammable (OTP ) Pr ot ection Register byt es, Some
are pr e-programmed with device-unique serial numbers.
Others ar e user - pr ogrammable . Bits are 0-15 poi nt to the
Prot ect io n Register lock byte, the section’s fi r st byt e. The
follo wi ng bytes ar e factory pre-pr ogr ammed and user -
programmable:
•bits 0- 7 = Lock/byt e s JE DEC-plane physic al low add r ess
•bites 8-15 = Lock/bytes JEDEC-plane physical hi gh address
•bits 16-23 = “n” such that 2n = factory pre-programmed bytes
•bits 24-31 = “n” such that 2n = user-programmable bytes
48:
49:
4A:
4B:
--80
--00
--03
--03
80h
00h
8 byte
8 byte
Offset(1) Length Descri
p
tion Hex
P = 39h (Optional flash features and commands) Add. Code
V
alue
(P+13)h 1 4C: --03 8 byte
(P+14)h 1 4D: --04 4
(P+15)h 1 4E: --01 4
(P+16)h 1 Synchronous m ode read capability configuration 2 4F: --02 8
(P+17)h 1 Synchronous m ode read capability configuration 3 50: --03 16
(P+18)h 1 Synchronous m ode read capability confi guration 4 51: --07 Cont
Page Mode Re ad capability
bits 0–7 = “n” such that 2n HEX value represents the num ber of
read-page bytes. See offset 28h for devic e word width to
determine page-mode data output width. 00h indicates no
read
p
a
g
e buffer.
Number of synchronous mode read configuration fi elds that
follow. 00h indicates no burst capability.
Synchronous mode read capability configuration 1
Bits 3–7 = Res erved
bits 0–2 “n” such that 2n+1 HEX val ue rep r esent s t he
maxim um number of continuous synchronous reads when
the device is c onf igure d fo r its maxim um wor d wid th. A value
of 07h indicates that t he device is capable of continuous
linear bursts that will output data until the internal burst
count er reaches the end of the device’s burstabl e address
space. This field’s 3-bit value can be written directly to the
Read C o nfigur ati on R egist er bit s 0–2 i f th e device is
configured f or its maximum word width. See offset 28h for
word width to determine the burst data out
p
ut wid th.
Offset
(1) See table belo w
P = 39h Descri
p
tion
A
ddress
Bottom To
p
(
O
p
tional fla sh f eatures and commands
)
Len Bot Top
(P+19)h (P+19)h 1 52: 52:Number of device hardware-partit ion regi ons within t he device.
x = 0: a single hardware partition device (no fields follow).
x spec if ies the nu mb er of de v i c e par titi on r egio n s cont aining
one or more contiguous erase block regions.
Intel® Wireless Flash Memory (W 18)
Appendix B Common Flash Interface (CFI)
108 Preliminary Datasheet
Table 49. Partition Region 1 Information
Offset
(1) See table belo w
P = 39h Descri
p
tion
A
ddress
Bottom To
p
(
O
p
tional fla sh f eat ures and commands
)
Len Bot Top
(P+1A)h (P+1A)h Number of identical partitions within t he partition region 2 53: 53:
(P+1B)h (P+1B)h 54: 54:
(P+1C)h (P+1C)h 1 55: 55:
(P+1D)h (P+1D)h 1 56: 56:
(P+1E)h (P+1E)h 1 57: 57:
(P+1F)h (P+1F)h 1 58: 58:
(P+20)h (P+20)h P artition Region 1 Erase Block Type 1 Information 4 59: 59:
(P+21)h (P+21)h bits 0–15 = y, y+1 = number of identi cal-size eras e blocks 5A: 5A:
(P+22)h (P+22)h bits 16–31 = z, region erase block(s) size are z x 256 bytes 5B: 5B:
(P+23)h (P+23)h 5C: 5C:
(P+24)h (P+24)h Partit io n 1 (Eras e Bl oc k Typ e 1) 25D:5D:
(P+25)h (P+25)h Minimum block erase cycles x 1000 5E: 5E:
(P+26)h (P+26)h 1 5F: 5F:
(P+27)h (P+27)h 1 60: 60:
(P+28)h P artition Region 1 Erase Block Type 2 Information 4 61:
(P+29)h bits 0–15 = y, y+1 = number of identical-size eras e blocks 62:
(P+2A)h bits 16–31 = z, region erase block(s) size are z x 256 bytes 63:
(P+2B)h (b ottom param e te r device onl y) 64:
(P+2C)h Partition 1
(
Erase block T
yp
e 2
)
265:
(P+2D)h Mini m um block erase cycles x 1000 66:
(P+2E)h 167:
(P+2F)h 168:
Simultaneous program or eras e operati ons allowed in other
partitions while a part i tion in this region is in Program mode
bits 0–3 = num ber of simultaneous Program operations
bits 4–7 = num ber of simultaneous Erase operat ions
Simultaneous program or eras e operati ons allowed in other
partitions while a part i tion in this region is in Erase mode
bits 0–3 = num ber of simultaneous Program operations
bits 4–7 = num ber of simultaneous Erase operat ions
Number of program or erase operations allowed in a partition
bits 0–3 = num ber of simultaneous Program operations
bits 4–7 = num ber of simultaneous Erase operat ions
Partit ion 1 (e r ase bl o ck Type 1) bi ts pe r cell; int e r nal EC C
bits 0–3 = bits per cell in eras e region
bit 4 = reserved for “i nte rnal E CC used” (1=yes, 0=no)
bits 5–7 = reserve for future use
Partition 1 (erase block Type 1) page mode and synchronous
mode capabilities defined i n Table 10.
bit 0 = p age-mode host reads per mi t te d (1=ye s, 0=no)
bit 1 = synchronous host reads perm itt ed (1=yes, 0=no)
bit 2 = synchronous host writes permi t ted (1=yes, 0=no)
bits 3–7 = reserved for future use
Pa r t it ion 1 (E r ase block Ty pe 2) b its p er c ell
bits 0–3 = bits per cell in eras e region
bit 4 = reserved for “i nte rnal E CC used” (1=yes, 0=no)
bits 5–7 = reserve for future use
Partition 1 (Erase block Type 2) pagemode and synchronous
mode capabilities defined i n Table 10
bit 0 = p age-mode host reads per mi t te d (1=ye s, 0=no)
bit 1 = synchronous host reads perm itt ed (1=yes, 0=no)
bit 2 = synchronous host writes permi t ted (1=yes, 0=no)
bits 3–7 = reserved for future use
Types of erase block regions in this Partition Region.
x = 0 = no erase blocking; the Partition Region erases in bulk
x = number of erase bl ock regions w/ contiguous same-size
eras e blocks. Symm etrically blocked parti tions have one
blocking region. Partition size = (Type 1 blocks)x(Type 1
block sizes) + (Type 2 blocks)x ( Type 2 blo ck sizes) +…+
(Type n blocks)x(Type n bl ock sizes)
Intel® Wireless Flash Memory (W 18)
Appendix B Common Flash Interface (CFI)
Preliminary Datasheet 109
Notes:
1. The varia ble P is a pointer which is de fi ned at CFI off set 15h.
2. TPD - Top parameter device; BPD - Bot tom parameter devi ce.
3. Partition: Each part it i on is 4-Mbit in size. It can contain m ain blocks O R a combinati on of both main and
parameter blocks.
4. Partition Region: Symm etrical par ti tions form a partit ion regi on. There are two partition regions: A
contains all the p artiti ons that are made up of main blocks only; B contains th e partition made up of the
p arameter and the m ain blocks.
Table 50. Partition and Erase B l oc k Region Information
Address 32 Mbit
–
B
–
T
–
B
–
T
–
B
–
T
52: --02 --02 --02 --02 --02 --02
53: --01 --07 --01 --0F --01 --1F
54: --00 --00 --00 --00 --00 --00
55: --11 --11 --11 --11 --11 --11
56: --00 --00 --00 --00 --00 --00
57: --00 --00 --00 --00 --00 --00
58: --02 --01 --02 --01 --02 --01
59: --07 --07 --07 --07 --07 --07
5A: --00 --00 --00 --00 --00 --00
5B: --20 --00 --20 --00 --20 --00
5C: --00 --01 --00 --01 --00 --01
5D: --64 --64 --64 --64 --64 --64
5E: --00 --00 --00 --00 --00 --00
5F: --01 --01 --01 --01 --01 --01
60: --03 --03 --03 --03 --03 --03
61: --06 --01 --06 --01 --06 --01
62: --00 --00 --00 --00 --00 --00
63: --00 --11 --00 --11 --00 --11
64: --01 --00 --01 --00 --01 --00
65: --64 --00 --64 --00 --64 --00
66: --00 --02 --00 --02 --00 --02
67: --01 --06 --01 --06 --01 --06
68: --03 --00 --03 --00 --03 --00
69: --07 --00 --0F --00 --1F --00
6A: --00 --01 --00 --01 --00 --01
6B: --11 --64 --11 --64 --11 --64
6C: --00 --00 --00 --00 --00 --00
6D: --00 --01 --00 --01 --00 --01
6E: --01 --03 --01 --03 --01 --03
6F: --07 --07 --07 --07 --07 --07
70: --00 --00 --00 --00 --00 --00
71: --00 --20 --00 --20 --00 --20
72: --01 --00 --01 --00 --01 --00
73: --64 --64 --64 --64 --64 --64
74: --00 --00 --00 --00 --00 --00
75: --01 --01 --01 --01 --01 --01
76: --03 --03 --03 --03 --03 --03
64Mbit 128Mbit
Intel® Wireless Flash Memory (W 18)
Appendix C Ordering Information
110 Preliminary Datasheet
Appendix C Ordering Information
Figure 43. VF BGA Orderin g Information
Figure 44. SCSP Ordering Information
Package:
GE = V F B GA, Lead ed
PH = VF BGA, Pb-free
Pro duct Li ne Desi g nator :
f or all Int el F l ash Product s
Device Densi t y:
320 = 32M bi t
640 = 64M bi t
128 = 128M bi t
Pr oduct Famil y:
W 18 = Intel
®
Wireless Flash
Memory
Par a m e t er Loc ati on :
T = Top Param et er
B = Bottom Parameter
Process Identifier:
C = 180 nm
D = 130 nm
E = 90 nm
Access S p ee d (n s)
(60,80)
G E 2 8 F 6 4 0 W 1 8 T E 6 0
Package:
RD = S CS P, Le aded
PF = SCSP, Pb-Free
Product Line:
48F = F las h Only
Fl ash Densi t y :
0 = No die
3 = 12 8 M b it
Product Fa m i ly Des i gnat or:
W = Intel
®
Wireless F las h M emory
Voltage:
Y = 1.8 V ol t I /O
Bal l out I ndi ca t or :
Q= QUAD+
Para m et er Location:
T = Top Parameter
B = Bottom Paramet er
Device Details:
0 = I nit ial V ersion
Flash 1 & 2
Flash 3 & 4
Fl ash 1
Fl ash 2
Fl ash 3
Fl ash 4
R D 4 8 F 3 0 0 0 W 0 Y B Q 0
