5962-89571022X - Hewlett-Packard / Agilent

1-524

GND

Hermetically Sealed,

Very High Speed,

Logic Gate Optocouplers

Technical Data

Features

• Dual Marked with Device

Part Number and DESC

Drawing Number

• Manufactured and Tested on

a MIL-PRF-38534 Certified

Line

• QML-38534, Class H and K

• Three Hermetically Sealed

Package Configurations

• Performance Guaranteed

over -55°C to +125°C

• High Speed: 40 M bit/s

• High Common Mode

Rejection 500 V/µs

Guaranteed

• 1500 Vdc Withstand Test

Voltage

• Active (Totem Pole) Outputs

• Three Stage Output Available

• High Radiation Immunity

• HCPL-2400/30 Function

Compatibility

• Reliability Data

• Compatible with TTL, STTL,

LSTTL, and HCMOS Logic

Families

Applications

• Military and Space

• High Reliability Systems

• Transportation, Medical, and

Life Critical Systems

• Isolation of High Speed

Logic Systems

Each channel contains an AlGaAs

light emitting diode which is

optically coupled to an integrated

high gain photon detector. This

combination results in very high

HCPL-540X*

5962-89570

HCPL-543X

Functional Diagram

Multiple Channel Devices

Available

Single Channel DIP

Input Enable Output

On (H) L L

Off (L) L H

On (H) H Z

Off (L) H Z

Truth Tables

(Positive Logic)

Multichannel Devices

Input Output

On (H) H

Off (L) L

HCPL-643X

5962-89571

*See matrix for available extensions.

• Computer-Peripheral

Interfaces

• Switching Power Supplies

• Isolated Bus Driver

(Networking Applications)-

(5400/1 Only)

• Pulse Transformer

Replacement

• Ground Loop Elimination

• Harsh Industrial

Environments

• High Speed Disk Drive I/O

• Digital Isolation for A/D,

D/A Conversion

Description

These units are single and dual

channel, hermetically sealed

optocouplers. The products are

capable of operation and storage

over the full military temperature

range and can be purchased as

either standard product or with

full MIL-PRF-38534 Class Level

H or K testing or from the

appropriate DESC Drawing. All

devices are manufactured and

tested on a MIL-PRF-38534

certified line and are included in

the DESC Qualified Manufac-

turers List QML-38534 for Hybrid

Microcircuits.

CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to

prevent damage and/or degradation which may be induced by ESD.

5965-3004E

1-525

Selection Guide–Package Styles and Lead Configuration Options

Package 8 Pin DIP 8 Pin DIP 20 Pad LCCC

Lead Style Through Hole Through Hole Surface Mount

Channels 1 2 2

Common Channel None VCC, GND None

Wiring

HP Part # & Options

Commercial HCPL-5400 HCPL-5430 HCPL-6430

MIL-PRF-38534, Class H HCPL-5401 HCPL-5431 HCPL-6431

MIL-PRF-38534, Class K HCPL-540K HCPL-543K HCPL-643K

Standard Lead Finish Gold Plate Gold Plate Solder Pads

Solder Dipped Option #200 Option #200

Butt Cut/Gold Plate Option #100 Option #100

Gull Wing/Soldered Option #300 Option #300

SMD Part #

Prescript for all below 5962- 5962- 5962-

Either Gold or Solder 8957001PX 8957101PX 89571022X

Gold Plate 8957001PC 8957101PC

Solder Dipped 8957001PA 8957101PA 89571022A

Butt Cut/Gold Plate 8957001YC 8957101YC

Butt Cut/Soldered 8957001YA 8957101YA

Gull Wing/Soldered 8957001XA 8957101XA

data rate capability. The detector

has a threshold with hysteresis,

which typically provides 0.25 mA

of differential mode noise

immunity and minimizes the

potential for output signal

chatter. The detector in the single

channel units has a three state

output stage which eliminates the

need for a pull-up resistor and

allows for direct drive of a data

bus.

All units are compatible with TTL,

STTL, LSTTL, and HCMOS logic

families. The 35 ns pulse width

distortion specification guaran-

tees a 10 MBd signaling rate at

+125°C with 35% pulse width

distortion. Figures 13 through 16

show recommended circuits for

reducing pulse width distortion

and optimizing the signal rate of

the product. Package styles for

these parts are 8 pin DIP through

hole (case outlines P), and

leadless ceramic chip carrier

(case outline 2). Devices may be

purchased with a variety of lead

bend and plating options. See

Selection Guide Table for details.

Standard Military Drawing (SMD)

parts are available for each

package and lead style.

Because the same electrical die

(emitters and detectors) are used

for each channel of each device

listed in this data sheet, absolute

maximum ratings, recommended

operating conditions, electrical

specifications, and performance

characteristics shown in the

figures are similar for all parts.

Occasional exceptions exist due

to package variations and limita-

tions and are as noted. Addition-

ally, the same package assembly

processes and materials are used

in all devices. These similarities

give justification for the use of

data obtained from one part to

represent other part’s perform-

ance for die related reliability and

certain limited radiation test

results.

1-526

GND

Functional Diagrams

8 Pin DIP 8 Pin DIP 20 Pad LCCC

Through Hole Through Hole Surface Mount

1 Channel 2 Channels 2 Channels

Note: All DIP devices have common VCC and ground. LCCC (leadless ceramic chip carrier) package has isolated channels with

separate VCC and ground connections.

Outline Drawings

GND

CC2

CC1

GND

20 Terminal LCCC Surface Mount, 2 Channels

8.70 (0.342)

9.10 (0.358)

4.95 (0.195)

5.21 (0.205)

1.78 (0.070)

2.03 (0.080) 1.02 (0.040) (3 PLCS)

4.95 (0.195)

5.21 (0.205)

8.70 (0.342)

9.10 (0.358)

1.78 (0.070)

2.03 (0.080)

0.51 (0.020)

0.64

(0.025)

(20 PLCS)

1.52 (0.060)

2.03 (0.080)

METALIZED

CASTILLATIONS (20 PLCS)

2.16 (0.085)

TERMINAL 1 IDENTIFIER

NOTE: DIMENSIONS IN MILLIMETERS (INCHES).

SOLDER THICKNESS 0.127 (0.005) MAX.

1.14 (0.045)

1.40 (0.055)



3.81 (0.150)

MIN.

4.32 (0.170)

MAX.

9.40 (0.370)

9.91 (0.390)

0.51 (0.020)

MAX.

2.29 (0.090)

2.79 (0.110)

0.51 (0.020)

MIN.

0.76 (0.030)

1.27 (0.050)

8.13 (0.320)

MAX.

7.36 (0.290)

7.87 (0.310)

0.20 (0.008)

0.33 (0.013)

7.16 (0.282)

7.57 (0.298)

NOTE: DIMENSIONS IN MILLIMETERS (INCHES).

8 Pin DIP Through Hole, 1 and 2 Channel

1-527









0.51 (0.020)

MIN.

5.57 (0.180)

MAX.

0.51 (0.020)

MAX.

2.29 (0.090)

2.79 (0.110)

1.40 (0.055)

1.65 (0.065) 9.65 (0.380)

9.91 (0.390)

5° MAX.

5.57 (0.180)

MAX.

0.20 (0.008)

0.33 (0.013)

NOTE: DIMENSIONS IN MILLIMETERS (INCHES).

Leadless Device MarkingLeaded Device Marking

Hermetic Optocoupler Options

Option Description

100 Surface mountable hermetic optocoupler with leads trimmed for butt joint assembly. This

option is available on commercial and hi-rel product in 8 pin DIP (see drawings below for

details).

200 Lead finish is solder dipped rather than gold plated. This option is available on commercial

and hi-rel product in 8 pin DIP. DESC Drawing part numbers contain provisions for lead

finish. All leadless chip carrier devices are delivered with solder dipped terminals as a

standard feature.

300 Surface mountable hermetic optocoupler with leads cut and bent for gull wing assembly. This

option is available on commercial and hi-rel product in 8 pin DIP (see drawings below for

details). This option has solder dipped leads.







1.14 (0.045)

1.40 (0.055)

4.32 (0.170)

MAX.

0.51 (0.020)

MAX.

2.29 (0.090)

2.79 (0.110)

0.51 (0.020)

MIN.

7.36 (0.290)

7.87 (0.310)

0.20 (0.008)

0.33 (0.013)

NOTE: DIMENSIONS IN MILLIMETERS (INCHES).

COMPLIANCE INDICATOR,*

DATE CODE, SUFFIX (IF NEEDED)

HP QYYWWZ

XXXXXX

XXXXXXX

XXX USA

* 50434 COUNTRY OF MFR.

HP FSCN*

HP LOGO

DESC SMD*

PIN ONE/

ESD IDENT

HP P/N

DESC SMD*

* QUALIFIED PARTS ONLY

COMPLIANCE INDICATOR,*

DATE CODE, SUFFIX (IF NEEDED)

HP QYYWWZ

XXXXXX

* XXXX

XXXXXX

USA 50434 DESC SMD*

HP FSCN*

HP LOGO

COUNTRY OF MFR.

HP P/N

PIN ONE/

ESD IDENT DESC SMD*

* QUALIFIED PARTS ONLY

1-528

Absolute Maximum Ratings

(No derating required up to +125°C)

Storage Temperature Range, TS.................................. -65°C to +150°C

Operating Temperature, TA......................................... -55°C to +125°C

Case Temperature, TC................................................................+170°C

Junction Temperature, TJ..........................................................+175°C

Lead Solder Temperature .............................................. 260°C for 10 s

Average Forward Current, IF AVG (each channel) ........................ 10 mA

Peak Input Current, IF PK (each channel) ............................... 20 mA[1]

Reverse Input Voltage, VR (each channel) ....................................... 3 V

Supply Voltage, VCC ............................................. 0.0 V min., 7.0 V max.

Average Output Current, IO............................ -25 mA min., 25 mA max.

(each channel)

Output Voltage, VO (each channel) .....................-0.5 V min., 10 V max.

Output Power Dissipation, PO (each channel) ........................... 130 mW

Package Power Dissipation, PD (each channel)......................... 200 mW

Single Channel Product Only

Three State Enable Voltage, VE...........................-0.5 V min., 10 V max.

Recommended Operating Conditions

Parameter Symbol Min. Max. Units

Input Current (High) IF(ON) 610 mA

Supply Voltage, Output VCC 4.75 5.25 V

Input Voltage (Low) VF(OFF) – 0.7 V

Fan Out (Each Channel) N – 5 TTL Loads

Single Channel Product Only

High Level Enable Voltage VEH 2.0 VCC V

Low Level Enable Voltage VEL 0 0.8 V

Note enable pin 7. An external 0.01 µF to 0.1 µF bypass capacitor must be connected

between VCC and ground for each package type.

ESD Classification

(MIL-STD-883, Method 3015)

HCPL-5400/01 .................................................................. (∆∆), Class 2

HCPL-5430/31 and HCPL-6430/31 ................................. (Dot), Class 3

CATHODE

8 Pin Ceramic DIP Single Channel Schematic

ANODE

1-529

Electrical Characteristics

TA = -55°C to +125°C, 4.5 V ≤ VCC ≤ 5.25 V, 6 mA ≤ IF(ON) ≤ 10 mA, 0 V ≤ VF(OFF) ≤ 0.7 V,

unless otherwise specified.

Limits

Parameter Sym. Test Conditions Subgroups Min. Typ.* Max. Units Fig. Notes

Low Level Output Voltage VOL IOL = 8.0 mA (5 TTL Loads) 1, 2, 3 0.3 0.5 V 1 9

High Level Output Voltage V

OH IOH = -4.0 mA 1, 2, 3 2.4 V 2 9

Output Leakage Current IOHH VO = 5.25 V, VF = 0.7 V 1, 2, 3 100 µA9

Logic High Single ICCH VCC = 5.25 V, VE = 0 V 1, 2, 3 17 26 mA

Channel (Single Channel Only)

Dual Channel 34 52 13

Logic Low Single ICCL 1, 2, 3 19 26 mA

Channel

Dual Channel 38 52 13

Input Forward Voltage VFIF = 10 mA 1, 2, 3 1.0 1.35 1.85 V 4 9

Input Reverse Break- VRIR = 10 µA 1, 2, 3 3.0 4.8 V 9

down Voltage

Input-Output Insulation II-O VI-O = 1500 Vdc, RH = 45%, 1 1.0 µA 2, 3

Leakage Current t = 5 s

Propagation Delay Time tPHL 9, 10, 11 33 60 ns 5, 4, 9

Logic Low Output 6, 7

Propagation Delay Time tPLH 9, 10, 11 30 60 ns 5, 4, 9

Logic High Output 6, 7

Pulse Width PWD 9, 10, 11 3 35 ns 5, 4, 9

Distortion 6, 7

Logic High Common |CMH|V

CM = 50 VP-P, IF = 0 mA 9, 10, 11 500 3000 V/µs 11 5, 9,

Mode Transient Immunity 11

Logic Low Common |CML|V

CM = 50 VP-P, IF = 6 mA 9, 10, 11 500 3000 V/µs 11 5, 9,

Mode Transient Immunity 11

Single Channel Product Only

Limits

Parameter Sym. Test Conditions Subgroups Min. Typ.* Max. Units Fig. Notes

Logic High Enable VEH 1, 2, 3 2.0 V

Voltage

Logic Low Enable VEL 1, 2, 3 0.8 V

Voltage

Logic High Enable IEH VE = 2.4 V 1, 2, 3 20 µA

VE = 5.25 V 1, 2, 3 100

Logic Low Enable IEL VE = 0.4 V 1, 2, 3 -0.28 -0.4 mA

Current

High Impedance State ICCZ VCC = 5.25 V, 1, 2, 3 22 28 mA

Supply Current VE = 5.25 V

High Impedance State IOZL VO = 0.4 V, VE = 2 V 1, 2, 3 -20 µA

IOZH VO = 2.4 V, VE = 2 V 20

VO = 5.25 V, VE = 2 V 100

*All typical values are at VCC = 5 V, T

A = 25°C, IF = 8 mA except where noted.

Group A[10]

Current

Output Current

Group A[10]

Supply

Current

Supply

Current

1-530

Parameter Symbol Typ. Units Test Conditions Fig. Notes

Input Current Hysteresis IHYS 0.25 mA VCC = 5 V 3

Input Diode Temperature ∆VF-1.11 mV/°CI

= 10 mA 4

Coefficient ∆TA

Resistance (Input-Output) RI-O 1012 ΩVI-O = 500 V 2

Capacitance (Input-Output) CI-O 0.6 pF f = 1 MHz, VI-O = 0 V 2

Logic Low Short Circuit IOSL 65 mA VO = VCC = 5.25 V, 6, 9

Output Current IF = 10 mA

Logic High Short Circuit IOSH -50 mA VCC = 5.25 V, IF = 0 mA, 6, 9

Output Current VO = GND

Output Rise Time (10-90%) tr15 ns 5

Output Fall Time (90-10%) tf10 ns 5

Propagation Delay Skew tPSK 30 ns 10 12

Power Supply Noise Immunity PSNI 0.5 VP-P 48 Hz ≤ fac ≤ 50 MHz 7

Typical Characteristics

All typical values are at TA = 25°C, VCC = 5 V, IF = 8 mA, unless otherwise specified.

Single Channel Product Only

Parameter Symbol Typ. Units Test Conditions Fig. Notes

Input Capacitance CIN 15 pF f = 1 MHz, VF = 0 V,

Pins 2 and 3

Output Enable Time to Logic High tPZH 15 ns 8, 9

Output Enable Time to Logic Low tPZL 30 ns 8, 9

Output Disable Time from Logic High tPHZ 20 ns 8, 9

Output Disable Time from Logic Low tPLZ 15 ns 8, 9

Dual and Quad Channel Product Only

Input Capacitance CIN 15 pF f = 1 MHz, VO = 0 V

Input-Input Leakage Current II-I 0.5 nA RH = 45%, VI-I = 500 Vdc 8

Input-Input Resistance RI-I 1012 ΩVI-I = 500 V 8

Input-Input Capacitance CI-I 1.3 pF f = 1 MHz, VF = 0 V 8

1-531

Notes:

1. Not to exceed 5% duty factor, not to exceed 50 µsec pulse width.

2. All devices are considered two-terminal devices: measured between all input leads or terminals shorted together and all output leads

or terminals shorted together.

3. This is a momentary withstand test, not an operating condition.

4. tPHL propagation delay is measured from the 50% point on the rising edge of the input current pulse to the 1.5 V point on the falling

edge of the output pulse. The tPLH propagation delay is measured from the 50% point on the falling edge of the input current pulse to

the 1.5 V point on the rising edge of the output pulse. Pulse Width Distortion, PWD = |tPHL - tPLH|.

5. CML is the maximum slew rate of the common mode voltage that can be sustained with the output voltage in the logic low state

(VO(MAX) < 0.8 V). CMH is the maximum slew rate of the common mode voltage that can be sustained with the output voltage in the

logic high state (VO(MIN) > 2.0 V).

6. Duration of output short circuit time not to exceed 10 ms.

7. Power Supply Noise Immunity is the peak to peak amplitude of the ac ripple voltage on the VCC line that the device will withstand and

still remain in the desired logic state. For desired logic high state, VOH(MIN) > 2.0 V, and for desired logic low state, VOL(MAX) < 0.8 V.

8. Measured between adjacent input pairs shorted together for each multichannel device.

9. Each channel.

10. Standard parts receive 100% testing at 25°C (Subgroups 1 and 9). SMD and hi-rel parts receive 100% testing at 25, 125, and –55°C

(Subgroups 1 and 9, 2 and 10, 3 and 11, respectively).

11. Parameters are tested as part of device initial characterization and after design and process changes. Parameters are guaranteed to

limits specified for all lots not specifically tested.

12. Propagation delay skew is defined as the difference between the minimum and maximum propagation delays for any given group of

optocouplers with the same part number that are all switching at the same time under the same operating conditions.

13. The HCPL-6430 and HCPL-6431 dual channel parts function as two independent single channel units. Use the single channel

parameter limits.

Figure 1. Typical Logic Low Output

Voltage vs. Logic Low Output Current. Figure 2. Typical Logic High Output

Voltage vs. Logic High Output Current.

Figure 3. Typical Output Voltage vs.

Input Forward Current. Figure 4. Typical Diode Input Forward

Current Characteristic.

1-532

Figure 8. Test Circuit for tPHZ, tPZH, tPLZ, and tPZL. (Single Channel Product Only).

Figure 5. Test Circuit for tPLH, tPHL, tr, and tf.

GND

5.0 V

D.U.T. 1.3 KΩ

INPUT

MONITORING

NODE

PULSE GEN.

= t

f =

5 ns

f = 500 kHz

25 % DUTY

CYCLE

30 pF

THE PROBE AND JIG CAPACITANCES

ARE REPRESENTED BY C

AND C

2.

ALL DIODES ARE 1N4150 OR EQUIVALENT.

O

OUTPUT

MONITORING

NODE

2.5 KΩ

C1

15 pF

100 Ω

0.1 µF

GND

5.0 V

D.U.T.

1.3 KΩ

PULSE

GENERATOR

= 50 Ω

= t

f =

5 ns



C1

30 pF

INPUT V



MONITORING

NODE

2.5 KΩD

0.1 µF

Figure 6. Typical Propagation Delay

vs. Ambient Temperature. Figure 7. Typical Propagation Delay

vs. Input Forward Current.

1-533

Figure 9. Typical Enable Propagation

Delay vs. Ambient Temperature.

(Single Channel Product Only).

Figure 11. Test Diagram for Common Mode

Transient Immunity and Typical Waveforms.

VFF

GND

VCC

VCM

+–

PULSE GEN.

BD.U.T.

OUTPUT VO

MONITORING

NODE

VCC = 5.0 V

† CL

15 pF

–

A0.1 µF*

Figure 10. Propagation Delay Skew,

tPSK, Waveform.

Figure 12. Operating Circuit for Burn-In and Steady State

Life Tests.

GND

D.U.T.*

* FOR SINGLE CHANNEL UNITS,

GROUND ENABLE PIN.

CONDITIONS: I

= 10 mA

= 5.25 V

+–

= 25 mA

0.01 µF

= +125 °C

2.1 V 100 Ω TYP.

100 Ω

= 3.0 V

tPSK

←→

1-534

MIL-PRF-38534 Class H,

Class K, and DESC SMD

Test Program

Hewlett-Packard’s Hi-Rel Opto-

couplers are in compliance with

MIL-PRF-38534 Classes H and K.

Class H devices are also in

compliance with DESC drawings

5962-89570, and 5962-89571.

Testing consists of 100% screen-

ing and quality conformance

inspection to MIL-PRF-38534.

Data Rate and Pulse-

Width Distortion

Definitions

Propagation delay is a figure of

merit which describes the finite

amount of time required for a

system to translate information

from input to output when

shifting logic levels. Propagation

delay from low to high (tPLH)

specifies the amount of time

required for a system’s output to

change from a Logic 0 to a Logic

1, when given a stimulus at the

input. Propagation delay from

high to low (tPHL) specifies the

amount of time required for a

system’s output to change from a

Logic 1 to a Logic 0, when given

a stimulus at the input (see

Figure 5).

When tPLH and tPHL differ in

value, pulse width distortion

results. Pulse width distortion is

defined as |tPHL -t

PLH| and

determines the maximum data

rate capability of a distortion-

limited system. Maximum pulse

width distortion on the order of

25-35% is typically used when

specifying the maximum data rate

capabilities of systems. The exact

figure depends on the particular

application (RS-232, PCM, T-1,

etc.).

These high performance opto-

couplers offer the advantages of

specified propagation delay (tPLH,

tPHL), and pulse width distortion

(|tPLH -t PHL|) over temperature

and power supply voltage ranges.

Figure 13. Recommended HCPL-5400 Interface Circuit.

GND

HCPL-5400

226 Ω

CC1

= +5 V

TTL

LSTTL

STTL

HCMOS

TOTEM

POLE

OUTPUT GATE

(e.g. 54AS1000)

DATA

OUT

DATA

1GND 2

0.1 µF

274 Ω

30 pF

GND 1

Y = A

CC2

= 5 V

Applications

1-535

GND

HCPL-5400

464 Ω

CC1

= +5 V

TTL

LSTTL

STTL

OPEN

COLLECTOR

OUTPUT

GATE

(e.g. 54S05)

DATA

OUT

DATA

1GND 2

0.1 µF

GND 1

Y = A

CC2

= 5 V

STTL

Figure 14. Alternative HCPL-5400 Interface Circuit.

Figure 15. Recommended HCPL-5430 and HCPL-6430 Interface Circuit.

Figure 16. Alternative HCPL-5430 and HCPL-6430 Interface Circuit.

GND

HCPL-5430

464 Ω

CC1

= +5 V

TTL

LSTTL

HCMOS

STTL

STTL OPEN COLLECTOR

OUTPUT GATE

(e.g. 54AS05)

DATA

OUT Y

DATA

IN A

GND 2

0.1 µF

GND 1 Y = A

CC2

= +5 V

TTL

LSTTL

HCMOS

STTL

DATA

OUT Y

DATA

IN A

464 Ω

GND

HCPL-5430

226 Ω

CC1

= 5 V

TOTEM POLE

OUTPUT GATE

(e.g. 54AS1000)

DATA

OUT Y

DATA

IN A

GND 2

0.1 µF

30 pF

GND 1 Y = A

CC2

= +5 V

TTL

LSTTL

STTL

HCMOS

DATA

OUT Y

226 Ω30 pF

274 Ω

DATA

IN A

TTL

LSTTL

STTL

HCMOS