Data Sheet
©2009 CADEKA Microcircuits LLC www.cadeka.com
Am pl ify the Human Experience
CDK1308 Ultra Low Power, 20/40/65/80MSPS, 10-bit ADCs Rev 1A
CDK1308
Ultra Low Power, 20/40/65/80MSPS,
10-bit Analog-to-Digital Converters (ADCs)
FEATURES
n
10-bit resolution
n
20/40/65/80MSPS max sampling rate
n
Ultra-Low Power Dissipation:
15/25/38/46mW
n
61.6dB SNR at 80MSPS and 8MHz FIN
n
Internal reference circuitry
n
1.8V core supply voltage
n
1.7 – 3.6V I/O supply voltage
n
Parallel CMOS output
n
40-pin QFN package
n
Pin compatible with CDK1307
APPLICATIONS
n Medical Imaging
n Portable Test Equipment
n Digital Oscilloscopes
n IF Communication
n Video Conferencing
n Video Distribution
General Description
The CDK1308 is a high performance ultra low power analog-to-digital
converter (ADC). The ADC employs internal reference circuitry, a CMOS
control interface and CMOS output data, and is based on a proprietary
structure. Digital error correction is employed to ensure no missing codes in
the complete full scale range.
Two idle modes with fast startup times exist. The entire chip can either be
put in Standby Mode or Power Down mode. The two modes are optimized to
allow the user to select the mode resulting in the smallest possible energy
consumption during idle mode and startup.
The CDK1308 has a highly linear THA optimized for frequencies up to Nyquist.
The differential clock interface is optimized for low jitter clock sources and
supports LVDS, LVPECL, sine wave, and CMOS clock inputs.
Functional Block Diagram
Ordering Information
Part Number Speed Package Pb-Free RoHS Compliant Operating Temperature Range Packaging Method
CDK1308AILP40 20MSPS QFN-40 Yes Yes -40°C to +85°C Tray
CDK1308BILP40 40MSPS QFN-40 Yes Yes -40°C to +85°C Tray
CDK1308CILP40 65MSPS QFN-40 Yes Yes -40°C to +85°C Tray
CDK1308DILP40 80MSPS QFN-40 Yes Yes -40°C to +85°C Tray
Moisture sensitivity level for all parts is MSL-2A.
10
©2009 CADEKA Microcircuits LLC www.cadeka.com 2
Data Sheet
CDK1308 Ultra Low Power, 20/40/65/80MSPS, 10-bit ADCs Rev 1A
Pin Assignments
Pin No. Pin Name Description
0VSS Ground connection for all power domains. Exposed pad
1, 11, 16 DVDD Digital and I/O-ring pre driver supply voltage, 1.8V
2CM_EXT Common Mode voltage output
3, 4, 7 AVDD Analog supply voltage, 1.8V
5, 6 IP, IN Analog input (non-inverting, inverting)
8 DVDDCLK Clock circuitry supply voltage, 1.8V
9CLKP Clock input, non-inverting (format: LVDS, LVPECL, CMOS/TTL, Sine Wave)
10 CLKN Clock input, inverting. For CMOS input on CLKP, connect CLKN to ground
12 CLK_EXT_EN CLK_EXT signal enabled when low (zero). Tristate when high.
13 DFRMT Data format selection. 0: Offset Binary, 1: Two's Complement
14 PD_N Full chip Power Down mode when Low. All digital outputs reset to zero. After chip power up
always apply Power Down mode before using Active Mode to reset chip.
15 OE_N Output Enable. Tristate when high
17, 18, 25,
26, 36, 37
OVDD I/O ring post-driver supply voltage. Voltage range 1.7 to 3.6V
19 NC
20 NC
21 NC
22 D_0 Output Data (LSB)
Pin Conguration
QFN-40
CDK1308
QFN-40
2
CM_EXT
4
AVDD
3
AVDD
1
DVDD
6
IN
8
DVDDCLK
7
AVDD
10
CLKN
9
CLKP
5
IP
29
D_3
27
CLK_EXT
28
D_2
30
D_4
25
OVDD
23
D_1
24
ORNG
21
NC
22
D_0
26
OVDD
12
CLK_EXT_EN
14
PD_N
13
DFRMT
11
DVDD
16
DVDD
18
OVDD
17
OVDD
20
NC
19
NC
15
OE_N
39
CM_EXTBC_0
37
OVDD
38
CM_EXTBC_1
40
SLP_N
35
D_9
33
D_7
34
D_8
31
D_5
32
D_6
36
OVDD
©2009 CADEKA Microcircuits LLC www.cadeka.com 3
Data Sheet
CDK1308 Ultra Low Power, 20/40/65/80MSPS, 10-bit ADCs Rev 1A
Pin No. Pin Name Description
23 D_1 Output Data
24 ORNG Out of Range ag. High when input signal is out of range
27 CLK_EXT Output clock signal for data synchronization. CMOS levels
28 D_2 Output Data
29 D_3 Output Data
30 D_4 Output Data
31 D_5 Output Data
32 D_6 Output Data
33 D_7 Output Data
34 D_8 Output Data
35 D_9 Output Data (MSB)
38, 39 CM_EXTBC_1,
CM_EXTBC_0
Bias control bits for the buffer driving pin CM_EXT
00: OFF 01: 50μA
10: 500μA 11: 1mA
40 SLP_N Sleep Mode when low
Pin Assignments
(Continued)
©2009 CADEKA Microcircuits LLC www.cadeka.com 4
Data Sheet
CDK1308 Ultra Low Power, 20/40/65/80MSPS, 10-bit ADCs Rev 1A
Absolute Maximum Ratings
The safety of the device is not guaranteed when it is operated above the “Absolute Maximum Ratings”. The device
should not be operated at these “absolute” limits. Adhere to the “Recommended Operating Conditions” for proper device
function. The information contained in the Electrical Characteristics tables and Typical Performance plots reect the
operating conditions noted on the tables and plots.
Parameter Min Max Unit
AVDD -0.3 +2.3 V
DVDD -0.3 +2.3 V
AVSS, DVSSCK, DVSS, OVSS -0.3 +0.3 V
OVDD -0.3 +3.9 V
CLKP, CLKN -0.3 +3.9 V
Analog inputs and outpts (IPx, INx) -0.3 +2.3 V
Digital inputs -0.3 +3.9 V
Digital outputs -0.3 +3.9 V
Reliability Information
Parameter Min Typ Max Unit
Storage Temperature Range -60 +150 °C
Lead Temperature (Soldering, 10s) J-STD-20
ESD Protection
Product QFN-40
Human Body Model (HBM) 2kV
Recommended Operating Conditions
Parameter Min Typ Max Unit
Operating Temperature Range -40 +85 °C
©2009 CADEKA Microcircuits LLC www.cadeka.com 5
Data Sheet
CDK1308 Ultra Low Power, 20/40/65/80MSPS, 10-bit ADCs Rev 1A
Electrical Characteristics
(AVDD = 1.8V, DVDD = 1.8V, DVDDCLK = 1.8V, OVDD = 2.5V, 20/40/65/80MSPS clock, 50% clock duty cycle,
-1dBFS 8MHz input signal, unless otherwise noted)
Symbol Parameter Conditions Min Typ Max Units
DC Accuracy
No Missing Codes Guaranteed
Offset Error Midscale offset 1 LSB
Gain Error Full scale range deviation from typical -6 6 %FS
DNL Differential Non-Linearity ±0.15 LSB
INL Integral Non-Linearity ±0.2 LSB
V
CMO
Common Mode Voltage Output VAVDD/2 V
Analog Input
V
CMI
Input Common Mode Analog input common mode voltage V
CM
-0.1 VCM +0.2 V
V
FSR
Full Scale Range Differential input voltage range 2.0 Vpp
Input Capacitance Differential input capacitance 2.0 pF
Bandwidth Input bandwidth, full power 500 MHz
Power Supply
AVDD,
DVDD Core Supply Voltage Supply voltage to all 1.8V domain pins.
See Pin Conguration and Description
1.7 1.8 2.0 V
OVDD I/O Supply Voltage
Output driver supply voltage (OVDD).
Must be higher than or equal to Core Supply
Voltage (V
OVDD
≥ V
DVDD
)
1.7 2.5 3.6 V
©2009 CADEKA Microcircuits LLC www.cadeka.com 6
Data Sheet
CDK1308 Ultra Low Power, 20/40/65/80MSPS, 10-bit ADCs Rev 1A
Electrical Characteristics - CDK1308A
(AVDD = 1.8V, DVDD = 1.8V, DVDDCLK = 1.8V, OVDD = 2.5V, 20MSPS clock, 50% clock duty cycle,
-1dBFS 8MHz input signal, unless otherwise noted)
Symbol Parameter Conditions Min Typ Max Units
Performance
SNR Signal to Noise Ratio
FIN = 2MHz 61.7 dBFS
FIN = 8MHz 60 61.6 dBFS
FIN ≃ FS/2 61.6 dBFS
FIN = 20MHz 61.6 dBFS
SINAD Signal to Noise and Distortion Ratio
FIN = 2MHz 61.7 dBFS
FIN = 8MHz 60 61.6 dBFS
FIN ≃ FS/2 60.5 dBFS
FIN = 20MHz 61.6 dBFS
SFDR Spurious Free Dynamic Range
FIN = 2MHz 80 dBc
FIN = 8MHz 70 81 dBc
FIN ≃ FS/2 70 dBc
FIN = 20MHz 80 dBc
HD2 Second order Harmonic Distortion
FIN = 2MHz -90 dBc
FIN = 8MHz -80 -90 dBc
FIN ≃ FS/2 -90 dBc
FIN = 20MHz -90 dBc
HD3 Third order Harmonic Distortion
FIN = 2MHz -80 dBc
FIN = 8MHz -70 -81 dBc
FIN ≃ FS/2 -70 dBc
FIN = 20MHz -80 dBc
ENOB Effective number of Bits
FIN = 2MHz 10.0 bits
FIN = 8MHz 9.7 9.9 bits
FIN ≃ FS/2 9.8 bits
FIN = 20MHz 9.9 bits
Power Supply
AIDD Analog Supply Current 5.7 mA
DIDD Digital Supply Current Digital core supply 1.0 mA
OIDD Output Driver Supply
2.5V output driver supply, sine wave input,
F
IN
= 1MHz, CLK_EXT enabled
1.7 mA
2.5V output driver supply, sine wave input,
F
IN
= 1MHz, CLK_EXT disabled
1.2 mA
Analog Power Dissipation 10.3 mW
Digital Power Dissipation OVDD = 2.5V, 5pF load on output bits,
F
IN
= 1MHz, CLK_EXT disabled
4.8 mW
Total Power Dissipation OVDD = 2.5V, 5pF load on output bits,
F
IN
= 1MHz, CLK_EXT disabled
15.1 mW
Power Down Dissipation 9.9 μW
Sleep Mode Power Dissipation, Sleep mode 7.7 mW
Clock Inputs
Max. Conversion Rate 20 MSPS
Min. Conversion Rate 15 MSPS
©2009 CADEKA Microcircuits LLC www.cadeka.com 7
Data Sheet
CDK1308 Ultra Low Power, 20/40/65/80MSPS, 10-bit ADCs Rev 1A
Electrical Characteristics - CDK1308B
(AVDD = 1.8V, DVDD = 1.8V, DVDDCLK = 1.8V, OVDD = 2.5V, 40MSPS clock, 50% clock duty cycle,
-1dBFS 8MHz input signal, unless otherwise noted)
Symbol Parameter Conditions Min Typ Max Units
Performance
SNR Signal to Noise Ratio
FIN = 2MHz 61.6 dBFS
FIN = 8MHz 60 61.6 dBFS
FIN ≃ FS/2 61.6 dBFS
FIN = 30MHz 61.5 dBFS
SINAD Signal to Noise and Distortion Ratio
FIN = 2MHz 61.6 dBFS
FIN = 8MHz 60 61.6 dBFS
FIN ≃ FS/2 61.2 dBFS
FIN = 30MHz 61.4 dBFS
SFDR Spurious Free Dynamic Range
FIN = 2MHz 80 dBc
FIN = 8MHz 70 81 dBc
FIN ≃ FS/2 72.0 dBc
FIN = 30MHz 80 dBc
HD2 Second order Harmonic Distortion
FIN = 2MHz -90 dBc
FIN = 8MHz -80 -90 dBc
FIN ≃ FS/2 -85 dBc
FIN = 30MHz -85 dBc
HD3 Third order Harmonic Distortion
FIN = 2MHz -80 dBc
FIN = 8MHz -70 -81 dBc
FIN ≃ FS/2 -72.0 dBc
FIN = 30MHz -80 dBc
ENOB Effective number of Bits
FIN = 2MHz 9.9 bits
FIN = 8MHz 9.7 9.9 bits
FIN ≃ FS/2 9.9 bits
FIN = 30MHz 9.9 bits
Power Supply
AIDD Analog Supply Current 9.3 mA
DIDD Digital Supply Current Digital core supply 1.7 mA
OIDD Output Driver Supply
2.5V output driver supply, sine wave input,
F
IN
= 1MHz, CLK_EXT enabled
3.1 mA
2.5V output driver supply, sine wave input,
F
IN
= 1MHz, CLK_EXT disabled
2.2 mA
Analog Power Dissipation 16.7 mW
Digital Power Dissipation OVDD = 2.5V, 5pF load on output bits,
F
IN
= 1MHz, CLK_EXT disabled
8.6 mW
Total Power Dissipation OVDD = 2.5V, 5pF load on output bits,
F
IN
= 1MHz, CLK_EXT disabled
25.3 mW
Power Down Dissipation 9.7 μW
Sleep Mode Power Dissipation, Sleep mode 11.3 mW
Clock Inputs
Max. Conversion Rate 40 MSPS
Min. Conversion Rate 20 MSPS
©2009 CADEKA Microcircuits LLC www.cadeka.com 8
Data Sheet
CDK1308 Ultra Low Power, 20/40/65/80MSPS, 10-bit ADCs Rev 1A
Electrical Characteristics - CDK1308C
(AVDD = 1.8V, DVDD = 1.8V, DVDDCLK = 1.8V, OVDD = 2.5V, 65MSPS clock, 50% clock duty cycle,
-1dBFS 8MHz input signal, unless otherwise noted)
Symbol Parameter Conditions Min Typ Max Units
Performance
SNR Signal to Noise Ratio
FIN = 8MHz 60 61.6 dBFS
FIN = 20MHz 61.6 dBFS
FIN ≃ FS/2 61.5 dBFS
FIN = 40MHz 61.3 dBFS
SINAD Signal to Noise and Distortion Ratio
FIN = 8MHz 60 61.6 dBFS
FIN = 20MHz 61.6 dBFS
FIN ≃ FS/2 60.4 dBFS
FIN = 40MHz 61.1 dBFS
SFDR Spurious Free Dynamic Range
FIN = 8MHz 70 77 dBc
FIN = 20MHz 77 dBc
FIN ≃ FS/2 70 dBc
FIN = 40MHz 75 dBc
HD2 Second order Harmonic Distortion
FIN = 8MHz -80 -90 dBc
FIN = 20MHz -95 dBc
FIN ≃ FS/2 -85 dBc
FIN = 40MHz -90 dBc
HD3 Third order Harmonic Distortion
FIN = 8MHz -70 -77 dBc
FIN = 20MHz -77 dBc
FIN ≃ FS/2 -70 dBc
FIN = 40MHz -75 dBc
ENOB Effective number of Bits
FIN = 8MHz 9.7 9.9 bits
FIN = 20MHz 9.9 bits
FIN ≃ FS/2 9.7 bits
FIN = 40MHz 9.9 bits
Power Supply
AIDD Analog Supply Current 13.8 mA
DIDD Digital Supply Current Digital core supply 2.6 mA
OIDD Output Driver Supply
2.5V output driver supply, sine wave input,
F
IN
= 1MHz, CLK_EXT enabled
4.9 mA
2.5V output driver supply, sine wave input,
F
IN
= 1MHz, CLK_EXT disabled
3.4 mA
Analog Power Dissipation 24.8 mW
Digital Power Dissipation OVDD = 2.5V, 5pF load on output bits,
F
IN
= 1MHz, CLK_EXT disabled
13.2 mW
Total Power Dissipation OVDD = 2.5V, 5pF load on output bits,
F
IN
= 1MHz, CLK_EXT disabled
38.0 mW
Power Down Dissipation 9.3 μW
Sleep Mode Power Dissipation, Sleep mode 15.7 mW
Clock Inputs
Max. Conversion Rate 65 MSPS
Min. Conversion Rate 40 MSPS
©2009 CADEKA Microcircuits LLC www.cadeka.com 9
Data Sheet
CDK1308 Ultra Low Power, 20/40/65/80MSPS, 10-bit ADCs Rev 1A
Electrical Characteristics - CDK1308D
(AVDD = 1.8V, DVDD = 1.8V, DVDDCLK = 1.8V, OVDD = 2.5V, 80MSPS clock, 50% clock duty cycle,
-1dBFS 8MHz input signal, unless otherwise noted)
Symbol Parameter Conditions Min Typ Max Units
Performance
SNR Signal to Noise Ratio
FIN = 8MHz 60 61.6 dBFS
FIN = 20MHz 61.2 dBFS
FIN = 30MHz 61.3 dBFS
FIN ≃ FS/2 61.3 dBFS
SINAD Signal to Noise and Distortion Ratio
FIN = 8MHz 60 61.3 dBFS
FIN = 20MHz 60.7 dBFS
FIN = 30MHz 61.0 dBFS
FIN ≃ FS/2 59 dBFS
SFDR Spurious Free Dynamic Range
FIN = 8MHz 70 75 dBc
FIN = 20MHz 75 dBc
FIN = 30MHz 75 dBc
FIN ≃ FS/2 65 dBc
HD2 Second order Harmonic Distortion
FIN = 8MHz -80 -90 dBc
FIN = 20MHz -95.0 dBc
FIN = 30MHz -90 dBc
FIN ≃ FS/2 -80 dBc
HD3 Third order Harmonic Distortion
FIN = 8MHz -70 -75 dBc
FIN = 20MHz -75.0 dBc
FIN = 30MHz -75 dBc
FIN ≃ FS/2 -65 dBc
ENOB Effective number of Bits
FIN = 8MHz 9.7 9.9 bits
FIN = 20MHz 9.8 bits
FIN = 30MHz 9.8 bits
FIN ≃ FS/2 9.5 bits
Power Supply
AIDD Analog Supply Current 16.5 mA
DIDD Digital Supply Current Digital core supply 3.3 mA
OIDD Output Driver Supply
2.5V output driver supply, sine wave input,
F
IN
= 1MHz, CLK_EXT enabled
5.9 mA
2.5V output driver supply, sine wave input,
F
IN
= 1MHz, CLK_EXT disabled
4.1 mA
Analog Power Dissipation 29.7 mW
Digital Power Dissipation OVDD = 2.5V, 5pF load on output bits,
F
IN
= 1MHz, CLK_EXT disabled
16.2 mW
Total Power Dissipation OVDD = 2.5V, 5pF load on output bits,
F
IN
= 1MHz, CLK_EXT disabled
45.9 mW
Power Down Dissipation 9.1 μW
Sleep Mode Power Dissipation, Sleep mode 18.3 mW
Clock Inputs
Max. Conversion Rate 80 MSPS
Min. Conversion Rate 65 MSPS
©2009 CADEKA Microcircuits LLC www.cadeka.com 10
Data Sheet
CDK1308 Ultra Low Power, 20/40/65/80MSPS, 10-bit ADCs Rev 1A
Digital and Timing Electrical Characteristics
(AVDD = 1.8V, DVDD = 1.8V, DVDDCLK = 1.8V, OVDD = 2.5V, 20/40/65/80MSPS clock, 50% clock duty cycle,
-1 dBFS input signal, 5pF capacitive load, unless otherwise noted)
Symbol Parameter Conditions Min Typ Max Units
Clock Inputs
Duty Cycle 20 80 % high
Compliance CMOS, LVDS, LVPECL, Sine Wave
Input Range
Differential input swing
Differential input swing, sine wave clock input
Input Common Mode Voltage
Keep voltages within ground and voltage of OVDD
0.3
VOVDD -0.3
V
Input Capacitance Differential 2 pF
Timing
TPD Start Up Time from Power Down From Power Down Mode to Active Mode 900 clk cycles
TSLP Start Up Time from Sleep From Sleep Mode to Active Mode 20 clk cycles
TOVR Out Of Range Recovery Time 1 clk cycles
TAP Aperture Delay 0.8 ns
εRMS Aperture Jitter <0.5 ps
TLAT Pipeline Delay 12 clk cycles
TDOutput Delay 5pF load on output bits (see timing diagram) 3 10 ns
TDC Output Delay Relative to CLK_EXT See timing diagram 1 6 ns
Logic Inputs
VIH High Level Input Voltage
VOVDD ≥ 3.0V 2 V
VOVDD = 1.7V – 3.0V
0.8 • VOVDD
V
VIL Low Level Input Voltage
VOVDD ≥ 3.0V 0 0.8 V
VOVDD = 1.7V – 3.0V 0
0.2 • VOVDD
V
IIH High Level Input Leakage Current -10 10 μA
IIL Low Level Input Leakage Current -10 10 μA
CIInput Capacitance 3 pF
Logic Outputs
VOH High Level Output Voltage
VOVDD -0.1
V
VOL Low Level Output Voltage 0.1 V
CLMax Capacitive Load
Post-driver supply voltage equal to pre-driver
supply voltage VOVDD = VOCVDD
5 pF
Post-driver supply voltage above 2.25V (1) 10 pF
Note:
(1) The outputs will be functional with higher loads. However, it is recommended to keep the load on output data bits as low as possible to keep dynamic currents
and resulting switching noise at a minimum.
400 mVpp
1.6 Vpp
©2009 CADEKA Microcircuits LLC www.cadeka.com 11
Data Sheet
CDK1308 Ultra Low Power, 20/40/65/80MSPS, 10-bit ADCs Rev 1A
Recommended Usage
Analog Input
The analog inputs to the CDK1308 is a switched capacitor
track-and-hold amplier optimized for differential opera-
tion. Operation at common mode voltages at mid supply
is recommended even if performance will be good for the
ranges specied. The CM_EXT pin provides a voltage suit-
able as common mode voltage reference. The internal
buffer for the CM_EXT voltage can be switched off, and
driving capabilities can be changed by using the CM_EXT-
BC control input.
Figure 2 shows a simplied drawing of the input net-
work. The signal source must have sufciently low output
impedance to charge the sampling capacitors within one
clock cycle. A small external resistor (e.g. 22Ω) in series
with each input is recommended as it helps reducing tran-
sient currents and dampens ringing behavior. A small dif-
ferential shunt capacitor at the chip side of the resistors
may be used to provide dynamic charging currents and
may improve performance. The resistors form a low pass
lter with the capacitor, and values must therefore be de-
termined by requirements for the application.
Figure 2. Input Conguration
DC-Coupling
Figure 3 shows a recommended conguration for DC-
coupling. Note that the common mode input voltage must
be controlled according to specied values. Preferably, the
CM_EXT output should be used as a reference to set the
common mode voltage.
The input amplier could be inside a companion chip or
it could be a dedicated amplier. Several suitable single
ended to differential driver ampliers exist in the market.
The system designer should make sure the specications
of the selected amplier is adequate for the total system,
and that driving capabilities comply with the CDK1308
input specications.
Figure 3. DC-Coupled Input
Detailed conguration and usage instructions must be
found in the documentation of the selected driver, and
the values given in Figure 3 must be varied according to
the recommendations for the driver.
AC-Coupling
A signal transformer or series capacitors can be used
to make an AC-coupled input network. Figure 4 shows
CLK_EXT
N-13
N+1
N+2
N+3 N+4
N+5
N
Figure 1. Timing Diagram
33pF
43Ω
43Ω
©2009 CADEKA Microcircuits LLC www.cadeka.com 12
Data Sheet
CDK1308 Ultra Low Power, 20/40/65/80MSPS, 10-bit ADCs Rev 1A
a recommended conguration using a transformer. Make
sure that a transformer with sufcient linearity is selected,
and that the bandwidth of the transformer is appropriate.
The bandwidth should exceed the sampling rate of the
ADC with at least a factor of 10. It is also important to
keep phase mismatch between the differential ADC inputs
small for good HD2 performance. This type of transformer
coupled input is the preferred conguration for high fre-
quency signals as most differential ampliers do not have
adequate performance at high frequencies. If the input
signal is traveling a long physical distance from the signal
source to the transformer (for example a long cable), kick-
backs from the ADC will also travel along this distance. If
these kick-backs are not terminated properly at the source
side, they are reected and will add to the input signal at
the ADC input. This could reduce the ADC performance.
To avoid this effect, the source must effectively terminate
the ADC kick-backs, or the traveling distance should be
very short. If this problem could not be avoided, the cir-
cuit in Figure 6 can be used.
Figure 4. Transformer-Coupled Input
Figure 5 shows AC-coupling using capacitors. Resistors
from the CM_EXT output, RCM, should be used to bias the
differential input signals to the correct voltage. The series
capacitor, CI, form the high-pass pole with these resistors,
and the values must therefore be determined based on
the requirement to the high-pass cut-off frequency.
Figure 5. AC-Coupled Input
Note that startup time from Sleep Mode and Power Down
Mode will be affected by this lter as the time required
to charge the series capacitors is dependent on the lter
cut-off frequency.
If the input signal has a long traveling distance, and the kick-
backs from the ADC not are effectively terminated at the
signal source, the input network of Figure 6 can be used.
The conguration is designed to attenuate the kickback
from the ADC and to provide an input impedance that looks
as resistive as possible for frequencies below Nyquist.
Values of the series inductor will however depend on board
design and conversion rate. In some instances a shunt
capacitor in parallel with the termination resistor (e.g. 33pF)
may improve ADC performance further. This capacitor
attenuate the ADC kick-back even more, and minimize the
kicks traveling towards the source. However, the imped-
ance match seen into the transformer becomes worse.
Figure 6. Alternative Input Network
Clock Input And Jitter Considerations
Typically high-speed ADCs use both clock edges to gener-
ate internal timing signals. In the CDK1308 only the rising
edge of the clock is used. Hence, input clock duty cycles
between 20% and 80% is acceptable.
The input clock can be supplied in a variety of formats.
The clock pins are AC-coupled internally, and hence a wide
common mode voltage range is accepted. Differential
clock sources as LVDS, LVPECL or differential sine wave
can be connected directly to the input pins. For CMOS
inputs, the CLKN pin should be connected to ground, and
the CMOS clock signal should be connected to CLKP. For
differential sine wave clock input the amplitude must be
at least ±800mVpp.
33Ω
33Ω
RT
47Ω
pF
Ω
Ω
pF
120nH
120nH
33Ω
33Ω
RT
68Ω 220Ω
optional
1:1
©2009 CADEKA Microcircuits LLC www.cadeka.com 13
Data Sheet
CDK1308 Ultra Low Power, 20/40/65/80MSPS, 10-bit ADCs Rev 1A
The quality of the input clock is extremely important for
high-speed, high-resolution ADCs. The contribution to SNR
from clock jitter with a full scale signal at a given frequency
is shown in the equation below:
SNRjitter = 20 • log (2 • π • FIN • εt)
where FIN is the signal frequency, and εt is the total rms
jitter measured in seconds. The rms jitter is the total of all
jitter sources including the clock generation circuitry, clock
distribution and internal ADC circuitry.
For applications where jitter may limit the obtainable per-
formance, it is of utmost importance to limit the clock
jitter. This can be obtained by using precise and stable
clock references (e.g. crystal oscillators with good jitter
specications) and make sure the clock distribution is
well controlled. It might be advantageous to use analog
power and ground planes to ensure low noise on the sup-
plies to all circuitry in the clock distribution. It is of utmost
importance to avoid crosstalk between the ADC output bits
and the clock and between the analog input signal and
the clock since such crosstalk often results in harmonic
distortion.
The jitter performance is improved with reduced rise and
fall times of the input clock. Hence, optimum jitter per-
formance is obtained with LVDS or LVPECL clock with fast
edges. CMOS and sine wave clock inputs will result in
slightly degraded jitter performance.
If the clock is generated by other circuitry, it should be re-
timed with a low jitter master clock as the last operation
before it is applied to the ADC clock input.
Digital Outputs
Digital output data are presented on parallel CMOS form.
The voltage on the OVDD pin set the levels of the CMOS
outputs. The output drivers are dimensioned to drive a
wide range of loads for OVDD above 2.25V, but it is rec-
ommended to minimize the load to ensure as low transient
switching currents and resulting noise as possible. In ap-
plications with a large fanout or large capacitive loads, it
is recommended to add external buffers located close to
the ADC chip.
The timing is described in the Timing Diagram section.
Note that the load or equivalent delay on CK_EXT always
should be lower than the load on data outputs to ensure
sufcient timing margins.
The digital outputs can be set in tristate mode by setting
the OE_N signal high.
The CDK1308 employs digital offset correction. This means
that the output code will be 4096 with shorted inputs.
However, small mismatches in parasitics at the input
can cause this to alter slightly. The offset correction also
results in possible loss of codes at the edges of the full
scale range. With no offset correction, the ADC would clip
in one end before the other, in practice resulting in code
loss at the opposite end. With the output being centered
digitally, the output will clip, and the out of range ags will
be set, before max code is reached. When out of range
ags are set, the code is forced to all ones for over-range
and all zeros for under-range.
Data Format Selection
The output data are presented on offset binary form
when DFRMT is low (connect to OVSS). Setting DFRMT
high (connect to OVDD) results in 2’s complement output
format. Details are shown in Table 1 below.
Table 1: Data Format Description for 2Vpp Full Scale Range
Differential Input Voltage (IP - IN) Output data: D_9 : D_0
(DFRMT = 0, offset binary)
Output Data: D_9 : D_0
(DFRMT = 1, 2’s complement)
1.0 V 11 1111 1111 01 1111 1111
+0.24mV 10 0000 0000 00 0000 0000
-0.24mV 01 1111 1111 11 1111 1111
-1.0V 00 0000 0000 10 0000 0000
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Data Sheet
CDK1308 Ultra Low Power, 20/40/65/80MSPS, 10-bit ADCs Rev 1A
Am pl ify the Human Experience
Mechanical Dimensions
QFN-40 Package
NOTE:
Package dimensions in millimeter unless otherwise noted.
Symbol Min Typ Max Min Typ Max
A – – 0.035 – – 0.9
A1 0.001 0.0004 0.002 0.00 0.01 0.05
A2 – 0.023 0.028 – 0.65 0.7
A3 0.008 REF 0.2 REF
b 0.008 0.010 0.013 0.2 0.25 0.32
D 0.236 BSC 6.00 BSC
D1 0.226 BSC 5.75 BSC
D2 0.156 0.162 0.167 3.95 4.10 4.25
L 0.012 0.016 0.020 0.3 0.4 0.5
e 0.020 BSC 0.50 BSC
θ1 0° – 12° 0° – 12°
F 0.008 – – 0.2 – –
G 0.0096 0.0168 0.024 0.24 0.42 0.6
R 0.004 0.008 – 0.1 0.2 –
Inches Millimeters
Pin 1 ID - Dia. 0.5
(Top Side) Pin 1 ID - Dia. R
Pin 0 Exposed Pad
F
G
A
A3
A1
A2
θ
1
L
b
e
1.14
0.45
D
D2
D D2 D1
Reference Voltages
The reference voltages are internally generated and buff-
ered based on a bandgap voltage reference. No external
decoupling is necessary, and the reference voltages are
not available externally. This simplies usage of the ADC
since two extremely sensitive pins, otherwise needed, are
removed from the interface.
Operational Modes
The operational modes are controlled with the PD_N and
SLP_N pins. If PD_N is set low, all other control pins are
overridden and the chip is set in Power Down mode. In
this mode all circuitry is completely turned off and the in-
ternal clock is disabled. Hence, only leakage current con-
tributes to the Power Down Dissipation. The startup time
from this mode is longer than for Sleep Mode as all refer-
ences need to settle to their nal values before normal
operation can resume.
The SLP_N signal can be used to set the full chip in Sleep
Mode. In this mode internal clocking is disabled, but some
low bandwidth circuitry is kept on to allow for a short
startup time. However, Sleep Mode represents a signi-
cant reduction in supply current, and it can be used to
save power even for short idle periods.
The input clock should be kept running in all idle modes.
However, even lower power dissipation is possible in Power
Down mode if the input clock is stopped. In this case it is
important to start the input clock prior to enabling active mode.